以太网接口芯片
rtl8139c以太网接口芯片
RTL8139C(L) Preliminary REALTEK 3.3V SINGLE CHIP FAST ETHERNET CONTROLLERWITH POWER MANAGEMENTRTL8139C(L)1.Features:l128 pins QFP/LQFPl Integrated Fast Ethernet MAC, Physical chip and transceiver in one chipl10 Mb/s and 100 Mb/s operationl Supports 10 Mb/s and 100 Mb/s N-way Auto-negotiation operationl PCI local bus single-chip Fast Ethernet controller²Compliant to PCI Revision 2.2²Supports PCI clock 16.75MHz-40MHz²Supports PCI target fast back-to-backtransaction²Provides PCI bus master data transfers and PCI memory space or I/O spacemapped data transfers of RTL8139C(L)'soperational registers²Supports PCI VPD (Vital Product Data)²Supports ACPI, PCI power management l Supports CardBus. The CIS can be stored in 93C56 or expansion ROMl Supports up to 128K bytes Boot ROMinterface for both EPROM and Flash memory l Supports 25MHz crystal or 25MHz OSC as the internal clock source. The frequency deviation of either crystal or OSC must be within 50 PPM. l Compliant to PC99 standardl Supports Wake-On-LAN function and remote wake-up (Magic Packet*, LinkChg andMicrosoft® wake-up frame)l Supports 4 Wake-On-LAN (WOL) signals (active high, active low, positive pulse, andnegative pulse)l Supports auxiliary power-on internal reset, to be ready for remote wake-up when main power still remains offl Supports auxiliary power auto-detect, and sets the related capability of power managementregisters in PCI configuration space.l Includes a programmable, PCI burst size and early tx/rx threshold.l Supports a 32-bit general-purpose timer with the external PCI clock as clock source, toRTL8139C(L) Preliminarygenerate timer-interruptl Contains two large (2Kbyte) independent receive and transmit FIFO’sl Advanced power saving mode when LAN function or wakeup function is not usedl Uses 93C46 (64*16-bit EEPROM) or 93C56 (128*16-bit EEPROM) to store resourceconfiguration, ID parameter, and VPD data.The 93C56 can also be used to store the CISdata structure for CardBus application.l Supports LED pins for various network activity indicationsl Supports digital and analog loopback capability on both portsl Half/Full duplex capabilityl Supports Full Duplex Flow Control (IEEE 802.3x)l 3.3V power supply with 5V tolerant I/Os.* Third-party brands and names are the property of their respective owners..N ote: The number of QFP package is RTL8139C. For the LQFP package, the number is RTL8139CL.RTL8139C(L) Preliminary 2.General DescriptionT he Realtek RTL8139C(L) is a highly integrated and cost-effective single-chip Fast Ethernet controller that provides 32-bit performance, PCI bus master capability, and full compliance with IEEE 802.3u 100Base-T specifications and IEEE 802.3x Full Duplex Flow Control. It also supports Advanced Configuration Power management Interface (ACPI), PCI power management for modern operating systems that is capable of Operating System Directed Power Management (OSPM) to achieve the most efficient power management. The RTL8139CL is suitable for the applications of CardBus or mobile with built-in network controller. The CIS data can be stored in either 93C56 EEPROM or expansion ROM.B esides the ACPI feature, the RTL8139C(L) also supports remote wake-up (including AMD Magic Packet*, LinkChg, and Microsoft® wake-up frame) in both ACPI and APM environments. Especially, the RTL8139C(L) is capable of performing internal reset whenever there is (auxiliary) power applied to. Once the auxiliary power is on whereas the main power still remains off, the RTL8139C(L) is ready and is waiting for the Magic Packet* or Link Change to wake the system up. Also, the LWAKE pin provides 4 different output signals including active high, active low, positive pulse, and negative pulse. The versatility of the RTL8139C(L) LWAKE pin satisfies all kinds of motherboards with Wake-On-LAN (WOL) function. The RTL8139C(L) also supports Analog Auto-Power-down, that is, the analog part of the RTL8139C(L) can be shut down temporarily according to the user’s requirement or when the RTL8139C(L) is in power down states with the wakeup function disabled. Besides, when the analog part is shut down and the IsolateB pin is low (i.e. the main power is off), then both the analog and digital parts stop functioning and the RTL8139C(L) will achieve the most power saving and consume extremely minor power. The RTL8139C(L) also support aux. power auto-detect function, and will auto-configure related bits of their own PCI power management registers in PCI configuration space.T he PCI Vital Product Data (VPD) is also supported to provide the information that uniquely identifies hardware (i.e., the RTL8139C(L) LAN card). The information may consist of part number, serial number, and other detailed information, and so on.RTL8139C(L) PreliminaryF or sake of cost-down, the RTL8139C(L) is capable of applying 25MHz crystal as its internal clock source. And you also can use 25MHz OSC.T he RTL8139C(L) keeps network maintenance cost low and eliminates usage barriers. It is the easiest way to upgrade a network from 10 to 100Mbps. It also supports full-duplex operation, making possible 200Mbps of bandwidth at no additional cost. To improve compatibility with other brands’ products, the RTL8139C(L) is also capable of receiving packets with InterFrameGap no less than 40 Bit-Time. The RTL8139C(L) is highly integrated and requires no “glue” logic or external memory. It includes an interface for a boot ROM and can be used in diskless workstations, providing maximum network security and ease of management.RTL8139C(L) Preliminary 3.Pin AssignmentRTL8139C(L) Preliminary4.Pin Descriptions4.1 POWER MANAGEMENT/ISOLATION INTERFACESymbol Type Pin No DescriptionPMEB (PME#)O/D76Power Management Event: Open drain, active low. Used by theRTL8139C(L) to request a change in its current power managementstate and/or to indicate that a power management event has occurred.ISOLATEB (ISOLATE#)I95Isolate pin: Active low. Used to isolate RTL8139C(L) from the PCI bus.The RTL8139C(L) does not drive its PCI outputs (excluding PME#)and does not sample its PCI input (including RST# and PCICLK) aslong as Isolate pin is asserted.LWAKE/ CSTSCHG O83LAN WAKE-UP signal (When CardB_En=0, bit2 Config3): Thissignal is used to inform motherboard to execute wake-up process. Themotherboard must support Wake-On-LAN (WOL). There are 4 choicesof output, including active high, active low, positive pulse, and negativepulse, that may be asserted from the LWAKE pin. Please refer toLWACT bit in CONFIG1 register and LWPTN bit in CONFIG4register for the setting of this output signal. The default output is anactive high signal. Once there is a PME event having come in, theLWAKE and PMEB assert at the same time when the LWPME (bit4,CONFIG4) is set to 0. If the LWPME is set to 1, the LWAKE assertsonly when the PMEB asserts and the ISOLATEB is low.CSTSCHG signal (When CardB_En=1, bit2 Config3): This signal isused in CardBus application only and is used to inform motherboard toexecute wake-up process whenever there is PME event occurs. This isalways an active high signal, the setting of LWACT (bit 4, Config1),LWPTN (bit2, Config4), and LWPME (bit4, Config4) means nothingin this case.This pin is a 3.3V signaling output pin.4.2 PCI INTERFACESymbol Type Pin No DescriptionAD31-0T/S120-123, 125-128, 4-6,8-11, 13, 26-29, 31-34,37-39, 41-45PCI address and data multiplexed pins.C/BE3-0T/S2, 14, 24, 36PCI bus command and byte enables multiplexed pins.CLK I116Clock provides timing for all transactions on PCI and is input to PCIdevice.CLKRUNB I/O75Clock Run: This signal is used by RTL8139C(L) to request starting (orspeeding up) the clock, CLK. CLKRUNB also indicates the clockstatus. For RTL8139C(L), CLKRUNB is an open drain output and alsoan input. The RTL8139C(L) requests the central resource to start, speedup, or maintain the interface clock by the assertion of CLKRUNB. Forthe host system, it is an S/T/S signal. The host system (central resource)is responsible for maintaining CLKRUNB asserted, and for driving ithigh to the negated (deasserted) state.DEVSELB S/T/S19Device Select: The RTL8139C(L) asserts this signal low when itrecognizes its target address after FRAMEB is asserted. As a busmaster, the RTL8139C(L) samples this signal to insure that a PCI targetRTL8139C(L) Preliminaryrecognizes the destination address for the data transfer.FRAMEB S/T/S15Cycle Frame is driven by the current master to indicate the beginningand duration of an access. FRAMEB is asserted to indicate a bustransaction is beginning. While FRAMEB is asserted, data transferscontinue. When FRAMEB is deasserted, the transaction is in the finaldata phase.GNTB I117Grant: This signal is asserted low to indicate to the RTL8139C(L) thatthe central arbiter has granted the ownership of the bus to theRTL8139C(L).REQB T/S118Request: The RTL8139C(L) will assert this signal low to request theownership of the bus to the central arbiter.IDSEL I3Initialization Device Select is used as a chip-select during configurationread and write transactions.INTAB O/D114INTAB is used to request an interrupt.IRDYB S/T/S16Initiator Ready indicates the initiating agent’s ability to complete thecurrent data phase of the transaction.TRDYB S/T/S17Target Ready indicates the target agent’s ability to complete the currentphase of the transaction.PAR T/S23Parity is even parity across AD31-0 and C/BE3-0.PERRB S/T/S21Parity Error: When the RTL8139C(L) is the bus master and a parityerror is detected, the RTL8139C(L) asserts both SERR bit in ISR andConfiguration Space command bit 8 (SERRB enable). Next, itcompletes the current data burst transaction, then stops operation andresets itself. After the host clears the system error, the RTL8139C(L)continues its operation.When the RTL8139C(L) is the bus target and a parity error is detected,the RTL8139C(L) asserts this PERRB pin.SERRB O/D22System Error: If an address parity error is detected and ConfigurationSpace Status register bit 15 (detected parity error) is enabled,RTL8139C(L) asserts both SERRB pin and bit 14 of Status register inConfiguration Space.STOPB S/T/S20Stop: Indicates the current target is requesting the master to stop thecurrent transaction.RSTB I115Reset: When RSTB is asserted low, the RTL8139C(L) performsinternal system hardware reset. RSTB must be held for a minimum of120 ns periods.4.3 FLASH/EEPROM INTERFACESymbol Type Pin No DescriptionMA16-3 MA8OI/O70-63, 61, 60, 57, 53-5161Boot PROM address bus: These pins are used to access up to 128k-byteflash memory or EPROM.Output pin as part of Boot PROM(or Flash) address bus after PCI reset.Input pin as Aux. Power detect pin to detect if Aux. Power exists or not,when initial power-on or PCI reset is asserted. Besides connecting thispin to Boot PROM, it should be pulled high to the Aux. Power via aresistor to detect Aux. power. If this pin is not pulled high to Aux.Power, the RTL8139C(L) assumes there is no Aux. power exists. Tosupport wakeup from ACPI D3cold or APM power-down, this pin mustbe pulled high to aux. power via a resistor.MA6/9356SEL I/O57When this pin is pulled high with a 10K£[resistor, the 93C56RTL8139C(L) PreliminaryEEPROM is used to store the resource data and CIS for theRTL8139C(L). The RTL8139C(L) latches the status of this pin atpower-up to determine what EEPROM(93C46 or 93C56) is used,afterwards, this pin is used as MA6.MA2/EESK O49The MA2-0 pins are switched to EESK, EEDI, EEDO in 93C46(93C56) programming or auto-load mode.MA1/EEDI O48MA0/EEDO O, I47EECS O5093C46 (93C56) chip selectMD0-7I/O108, 107, 105-100Boot PROM data busROMCSB O110ROM Chip Select: This is the chip select signal of the Boot PROM. OEB O88Output Enable: This enables the output buffer of the Boot PROM orFlash memory during a read operation.WEB O89Write Enable: This signal strobes data into the Flash memory during awrite cycle.4.4 POWER PINSSymbol Type Pin No DescriptionVDD P1, 12, 25, 35, 46, 58,+3.3V59, 77, 90, 96, 106,109, 119GroundGND P7, 18, 30, 40, 55, 56,62, 74, 80, 85, 93, 111,112, 113, 1244.5 LED INTERFACESymbol Type Pin No DescriptionLED0, 1, 2O99, 98, 97LED pinsLEDS1-000011011LED0TX/RX TX/RX TX TXLED1LINK100LINK10/100LINK10/100LINK100LED2LINK10FULL RX LINK10During power down mode, the LED’s are OFF.RTL8139C(L) Preliminary4.6 ATTACHMENT UNIT INTERFACESymbol Type Pin No DescriptionTXD+ TXD-OO9291100/10BASE-T transmit (Tx) data.RXIN+ RXIN-II8786100/10BASE-T receive (Rx) data.X1I7925 MHz crystal/OSC. input.X2O78Crystal feedback output. This output is used in crystal connection only.It must be left open when X1 is driven with an external 25 MHzoscillator.4.7 TEST AND THE OTHER PINSSymbol Type Pin No DescriptionRTT2-3TEST81, 82Chip test pins.RTSET I/O84This pin must pull low by 1.8KΩ resistor.NC-54, 71, 72, 73, 94Reserved5.Register DescriptionsT he RTL8139C(L) provides the following set of operational registers mapped into PCI memory space or I/O space.O ffset R/W T ag D escription0000h R/W I DR0I D Register 0, The ID register0-5 are only permitted to read/write by4-bye access.0001h R/W I DR1I D Register 10002h R/W I DR2I D Register 20003h R/W I DR3I D Register 30004h R/W I DR4I D Register 40005h R/W I DR5I D Register 50006h-0007h--R eserved0008h R/W M AR0M ulticast Register 0, The MAR register0-7 are only permitted toread/write by 4-bye access.0009h R/W M AR1M ulticast Register 1000Ah R/W M AR2M ulticast Register 2000Bh R/W M AR3M ulticast Register 3000Ch R/W M AR4M ulticast Register 4000Dh R/W M AR5M ulticast Register 5000Eh R/W M AR6M ulticast Register 6000Fh R/W M AR7M ulticast Register 70010h-0013h R/W T SD0T ransmit Status of Descriptor 00014h-0017h R/W T SD1T ransmit Status of Descriptor 10018h-001Bh R/W T SD2T ransmit Status of Descriptor 2001Ch-001Fh R/W T SD3T ransmit Status of Descriptor 30020h-0023h R/W T SAD0T ransmit Start Address of Descriptor00024h-0027h R/W T SAD1T ransmit Start Address of Descriptor1RTL8139C(L) Preliminary 0028h-002Bh R/W T SAD2T ransmit Start Address of Descriptor2002Ch-002Fh R/W T SAD3T ransmit Start Address of Descriptor30030h-0033h R/W R BSTART R eceive (Rx) Buffer Start Address0034h-0035h R E RBCR E arly Receive (Rx) Byte Count Register0036h R E RSR E arly Rx Status Register0037h R/W C R C ommand Register0038h-0039h R/W C APR C urrent Address of Packet Read003Ah-003Bh R C BR C urrent Buffer Address: The initial value is 0000h. It reflects totalreceived byte-count in the rx buffer.003Ch-003Dh R/W I MR I nterrupt Mask Register003Eh-003Fh R/W I SR I nterrupt Status Register0040h-0043h R/W T CR T ransmit (Tx) Configuration Register0044h-0047h R/W R CR R eceive (Rx) Configuration Register0048h-004Bh R/W T CTR T imer CounT Register: This register contains a 32-bit general-purpose timer. Writing any value to this 32-bit register will reset theoriginal timer and begin to count from zero.004Ch-004Fh R/W M PC M issed Packet Counter: Indicates the number of packets discarded dueto rx FIFO overflow. It is a 24-bit counter. After s/w reset, MPC iscleared. Only the lower 3 bytes are valid.W hen written any value, MPC will be reset also.0050h R/W9346CR93C46 (93C56) Command Register0051h R/W C ONFIG0C onfiguration Register 00052h R/W C ONFIG1C onfiguration Register 10053H--R eserved0054h-0057h R /W T imerInt T imer Interrupt Register. Once having written a nonzero value to thisregister, the Timeout bit of ISR register will be set whenever theTCTR reaches to this value. The Timeout bit will never be set as longas TimerInt register is zero.0058h R/W M SR M edia Status Register0059h R/W C ONFIG3C onfiguration register 3005Ah R/W C ONFIG4C onfiguration register 4005Bh--R eserved005Ch-005Dh R/W M ULINT M ultiple Interrupt Select005Eh R R ERID P CI Revision ID = 10h.005Fh--R eserved.0060h-0061h R T SAD T ransmit Status of All Descriptors0062h-0063h R/W B MCR B asic Mode Control Register0064h-0065h R B MSR B asic Mode Status Register0066h-0067h R/W A NAR A uto-Negotiation Advertisement Register0068h-0069h R A NLPAR A uto-Negotiation Link Partner Register006Ah-006Bh R A NER A uto-Negotiation Expansion Register006Ch-006Dh R D IS D isconnect Counter006Eh-006Fh R F CSC F alse Carrier Sense Counter0070h-0071h R/W N WAYTR N-way Test Register0072h-0073h R R EC R X_ER Counter0074h-0075h R/W C SCR C S Configuration Register0076-0077h--R eserved.0078h-007Bh R/W P HY1_PARM P HY parameter 1007Ch-007Fh R/W T W_PARM T wister parameter0080h R/W P HY2_PARM P HY parameter 20081-0083h--R eservedRTL8139C(L) Preliminary0084h R/W C RC0P ower Management CRC register0 for wakeup frame00085h R/W C RC1P ower Management CRC register1 for wakeup frame10086h R/W C RC2P ower Management CRC register2 for wakeup frame20087h R/W C RC3P ower Management CRC register3 for wakeup frame30088h R/W C RC4P ower Management CRC register4 for wakeup frame40089h R/W C RC5P ower Management CRC register5 for wakeup frame5008Ah R/W C RC6P ower Management CRC register6 for wakeup frame6008Bh R/W C RC7P ower Management CRC register7 for wakeup frame7008Ch–0093h R/W W akeup0P ower Management wakeup frame0 (64bit)0094h–009Bh R/W W akeup1P ower Management wakeup frame1 (64bit)009Ch–00A3h R/W W akeup2P ower Management wakeup frame2 (64bit)00A4h–00ABh R/W W akeup3P ower Management wakeup frame3 (64bit)00ACh–00B3h R/W W akeup4P ower Management wakeup frame4 (64bit)00B4h–00BBh R/W W akeup5P ower Management wakeup frame5 (64bit)00BCh–00C3h R/W W akeup6P ower Management wakeup frame6 (64bit)00C4h–00CBh R/W W akeup7P ower Management wakeup frame7 (64bit)00CCh R/W L SBCRC0L SB of the mask byte of wakeup frame0 within offset 12 to 7500CDh R/W L SBCRC1L SB of the mask byte of wakeup frame1 within offset 12 to 7500CEh R/W L SBCRC2L SB of the mask byte of wakeup frame2 within offset 12 to 7500CFh R/W L SBCRC3L SB of the mask byte of wakeup frame3 within offset 12 to 7500D0h R/W L SBCRC4L SB of the mask byte of wakeup frame4 within offset 12 to 7500D1h R/W L SBCRC5L SB of the mask byte of wakeup frame5 within offset 12 to 7500D2h R/W L SBCRC6L SB of the mask byte of wakeup frame6 within offset 12 to 7500D3h R/W L SBCRC7L SB of the mask byte of wakeup frame7 within offset 12 to 7500D4h-00D7h R/W F LASH F lash memory read/write register00D8h R/W C onfig5C onfiguration register 500D9h-00EFh--R eserved00F0h-00F3h R/W F ER F unction Event Register (Cardbus only)00F4h-00F7h R/W F EMR F unction Event Mask Register (CardBus only)00F8h-00FBh R F PSR F unction Present State Register (CardBus only)00FCh-00FFh W F FER F unction Force Event Register (CardBus only)5.1 Receive Status Register in Rx packet headerB it R/W S ymbol D escription15R M AR M ulticast Address Received: Set to 1 indicates that a multicast packet isreceived.14R P AM P hysical Address Matched: Set to 1 indicates that the destinationaddress of this packet matches the value written in ID registers.13R B AR B roadcast Address Received: Set to 1 indicates that a broadcast packetis received. BAR, MAR bit will not be set simultaneously.12-6--R eserved5R I SE I nvalid Symbol Error: (100BASE-TX only) An invalid symbol wasencountered during the reception of this packet if this bit set to 1.4R R UNT R unt Packet Received: Set to 1 indicates that the received packet lengthis smaller than 64 bytes ( i.e. media header + data + CRC < 64 bytes ) 3R L ONG L ong Packet: Set to 1 indicates that the size of the received packetexceeds 4k bytes.2R C RC C RC Error: When set, indicates that a CRC error occurred on thereceived packet.RTL8139C(L) Preliminary 1R F AE F rame Alignment Error: When set, indicates that a frame alignmenterror occurred on this received packet.0R R OK R eceive OK: When set, indicates that a good packet is received.5.2 Transmit Status Register (TSD0-3)(Offset 0010h-001Fh, R/W) T he read-only bits (CRS, TABT, OWC, CDH, NCC3-0, TOK, TUN) will be cleared by RTL8139C(L) when the Transmit Byte Count (bit12-0) in the corresponding Tx descriptor is written. It is not affected when software writes to these bits. These registers are only permitted to write by double-word access. After software reset, all bits except OWN bit are reset to “0”.B it R/W S ymbol D escription31R C RS C arrier Sense Lost: Set to 1 when the carrier is lost during transmittinga packet.30R T ABT T ransmit Abort: Set to 1 if the transmission of a packet was aborted.This bit is read only, writing to this bit is not affected.29R O WC O ut of Window Collision: Set to 1 if the RTL8139C(L) encountered an"out of window" collision during the transmission of a packet.28R C DH C D Heart Beat: The same as RTL8139(A/B).T his bit is cleared in the 100 Mbps mode.27-24R N CC3-0N umber of Collision Count: Indicates that the number of collisionsencountered during the transmission of a packet.23-22--R eserved21-16R/W E RTXTH5-0E arly Tx Threshold: Specifies the threshold level in the Tx FIFO tobegin the transmission. When the byte count of the data in the Tx FIFOreaches this level, (or the FIFO contains at least one complete packet)the RTL8139C(L) will transmit this packet.000000 = 8 bytesT hese fields count from 000001 to 111111 in unit of 32 bytes.T his threshold must be avoided from exceeding 2K byte.15R T OK T ransmit OK: Set to 1 indicates that the transmission of a packet wascompleted successfully and no transmit underrun occurs.14R T UN T ransmit FIFO Underrun: Set to 1 if the Tx FIFO was exhausted duringthe transmission of a packet. The RTL8139C(L) can re-transfer data ifthe Tx FIFO underruns and can also transmit the packet to the wiresuccessfully even though the Tx FIFO underruns. That is, whenTSD<TUN>=1, TSD<TOK>=0 and ISR<TOK>=1 (or ISR<TER>=1).13R/W O WN O WN: The RTL8139C(L) sets this bit to 1 when the Tx DMA operationof this descriptor was completed. The driver must set this bit to 0 whenthe Transmit Byte Count (bit0-12) is written. The default value is 1.12-0R/W S IZE D escriptor Size: The total size in bytes of the data in this descriptor. Ifthe packet length is more than 1792 byte (0700h), the Tx queue will beinvalid, i.e. the next descriptor will be written only after the OWN bit ofthat long packet's descriptor has been set.5.3 ERSR: Early Rx Status Register (Offset 0036h, R)B it R/W S ymbol D escription7-4--R eserved3R E RGood E arly Rx Good packet: This bit is set whenever a packet is completelyRTL8139C(L) Preliminaryreceived and the packet is good. This bit is cleared when writing 1 to it, 2R E RBad E arly Rx Bad packet: This bit is set whenever a packet is completelyreceived and the packet is bad. Writing 1 will clear this bit.1R E ROVW E arly Rx OverWrite: This bit is set when the RTL8139C(L)'s localaddress pointer is equal to CAPR. In the early mode, this is differentfrom buffer overflow. It happens that the RTL8139C(L) detected an Rxerror and wanted to fill another packet data from the beginning addressof that error packet. Writing 1 will clear this bit.0R E ROK E arly Rx OK: The power-on value is 0. It is set when the Rx byte countof the arriving packet exceeds the Rx threshold. After the whole packetis received, the RTL8139C(L) will set ROK or RER in ISR and clearthis bit simultaneously. Setting this bit will invoke a ROK interrupt.5.4 Command Register (Offset 0037h, R/W)B it R/W S ymbol D escription7-5--R eserved4R/W R ST R eset: Setting to 1 forces the RTL8139C(L) to a software reset statewhich disables the transmitter and receiver, reinitializes the FIFOs,resets the system buffer pointer to the initial value (Tx buffer is atTSAD0, Rx buffer is empty). The values of IDR0-5 and MAR0-7 andPCI configuration space will have no changes. This bit is 1 during thereset operation, and is cleared to 0 by the RTL8139C(L) when the resetoperation is complete.3R/W R E R eceiver Enable2R/W T E T ransmitter Enable1--R eserved0R B UFE B uffer Empty: Rx Buffer Empty. There is no packet stored in the Rxbuffer ring.5.5 Interrupt Mask Register (Offset 003Ch-003Dh, R/W)B it R/W S ymbol D escription15R/W S ERR S ystem Error Interrupt: 1 => Enable, 0 => Disable.14R/W T imeOut T ime Out Interrupt: 1 => Enable, 0 => Disable.13R/W L enChg C able Length Change Interrupt: 1 => Enable, 0 => Disable.12-7--R eserved6R/W F OVW R x FIFO Overflow Interrupt: 1 => Enable, 0 => Disable.5R/W P UN/LinkChg P acket Underrun/Link Change Interrupt: 1 => Enable, 0 => Disable.4R/W R XOVW R x Buffer Overflow Interrupt: 1 => Enable, 0 => Disable.3R/W T ER T ransmit Error Interrupt: 1 => Enable, 0 => Disable.2R/W T OK T ransmit OK Interrupt: 1 => Enable, 0 => Disable.1R/W R ER R eceive Error Interrupt: 1 => Enable, 0 => Disable.0R/W R OK R eceive OK Interrupt: 1 => Enable, 0 => Disable.5.6 Interrupt Status Register (Offset 003Eh-003Fh, R/W)B it R/W S ymbol D escriptionRTL8139C(L) Preliminary 15R/W S ERR S ystem Error: Set to 1 when the RTL8139C(L) signals a system error onthe PCI bus.14R/W T imeOut T ime Out: Set to 1 when the TCTR register reaches to the value of theTimerInt register.13R/W L enChg C able Length Change: Cable length is changed after Receiver isenabled.12 - 7--R eserved6R/W F OVW R x FIFO Overflow5R/W P UN/LinkChg P acket Underrun/Link Change: Set to 1 when CAPR is written but Rxbuffer is empty, or when link status is changed.4R/W R XOVW R x Buffer Overflow: Set when receive (Rx) buffer ring storageresources have been exhausted.3R/W T ER T ransmit (Tx) Error: Indicates that a packet transmission was aborted,due to excessive collisions, according to the TXRR's setting 2R/W T OK T ransmit (Tx) OK: Indicates that a packet transmission is completedsuccessfully.1R/W R ER R eceive (Rx) Error: Indicates that a packet has either CRC error orframe alignment error (FAE). The collided frame will not be recognizedas CRC error if the length of this frame is shorter than 16 byte.0R/W R OK R eceive (Rx) OK: In normal mode, indicates the successful completionof a packet reception. In early mode, indicates that the Rx byte count ofthe arriving packet exceeds the early Rx threshold.5.7 Transmit Configuration Register (Offset 0040h-0043h, R/W)B it R/W S ymbol D escription31--R eservedHardware Version ID:30-26R HWVERIDB it30B it29B it28B it27B it26B it23R TL8139110000R TL8139A111000R TL8139A-G111001R TL8139B111100R TL8130111110R TL8139C111010R eserved A ll other combination25-24R/W I FG1, 0I nterframe Gap Time: This field allows the user to adjust the interframegap time below the standard: 9.6us for 10Mbps, 960 ns for 100Mbps.The time can be programmed from 9.6 us to 8.4 us (10Mbps) and 960nsto 840ns (100Mbps). Note that any value other than zero will violate theIEEE 802.3 standard.T he formula for the inter frame gap is:10 Mbps8.4us + 0.4(IFG(1:0)) us100 Mbps840ns + 40(IFG(1:0)) ns 23R8139A-G RTL8139A rev.G ID = 1. For others, this bit is 0.22-19--Reserved。
网络接口MII和PHY芯片
网络接口MII和PHYPHY指物理层，OSI的最底层。
一般指与外部信号接口的芯片。
以太网PHY芯片网络中最基础的部件是什么?不是交换机也不是路由器，而是小小的不起眼但又无处不在的网卡。
如果在5年前，或许网卡与您无关，但在如今这网络的时代，无论是上网冲浪还是联网玩游戏，都离不开网卡，更何况，就算您不食人间烟火，多数主板上也会为您集成一块板载网卡。
所以，对于想迈入网络之门的读者而言，先认识网卡，会让您在进行各种网络应用时更得心应手。
一、网卡的主要特点网卡(Network Interface Card，简称NIC)，也称网络适配器，是电脑与局域网相互连接的设备。
无论是普通电脑还是高端服务器，只要连接到局域网，就都需要安装一块网卡。
如果有必要，一台电脑也可以同时安装两块或多块网卡。
电脑之间在进行相互通讯时，数据不是以流而是以帧的方式进行传输的。
我们可以把帧看做是一种数据包，在数据包中不仅包含有数据信息，而且还包含有数据的发送地、接收地信息和数据的校验信息。
一块网卡包括OSI模型的两个层——物理层和数据链路层。
物理层定义了数据传送与接收所需要的电与光信号、线路状态、时钟基准、数据编码和电路等，并向数据链路层设备提供标准接口。
数据链路层则提供寻址机构、数据帧的构建、数据差错检查、传送控制、向网络层提供标准的数据接口等功能。
网卡的功能主要有两个:一是将电脑的数据封装为帧，并通过网线(对无线网络来说就是电磁波)将数据发送到网络上去;二是接收网络上其它设备传过来的帧，并将帧重新组合成数据，发送到所在的电脑中。
网卡能接收所有在网络上传输的信号，但正常情况下只接受发送到该电脑的帧和广播帧，将其余的帧丢弃。
然后，传送到系统CPU做进一步处理。
当电脑发送数据时，网卡等待合适的时间将分组插入到数据流中。
接收系统通知电脑消息是否完整地到达，如果出现问题，将要求对方重新发送。
二、图解网卡以最常见的PCI接口的网卡为例，一块网卡主要由PCB线路板、主芯片、数据汞、金手指(总线插槽接口)、BOOTROM、EEPROM、晶振、RJ45接口、指示灯、固定片等等，以及一些二极管、电阻电容等组成。
常用接口芯片及应用
常用接口芯片及应用1. 介绍接口芯片是计算机系统中用于连接各个设备和外部接口的重要组件。
它们可以实现设备之间的数据传输和通信，并且支持各种不同的接口标准和协议。
在现代电子产品中，常用接口芯片被广泛应用于各个领域，如计算机、通信、汽车、工业控制等。
本文将介绍一些常用的接口芯片以及它们的应用。
2. USB接口芯片USB（Universal Serial Bus）是一种常用的计算机接口标准，用于连接外部设备和计算机主机。
USB接口芯片通常包括USB控制器和USB PHY（Physical Layer）两部分。
USB控制器负责处理USB协议的逻辑层，而USB PHY负责处理USB物理层的电信号转换。
USB接口芯片的应用非常广泛，如打印机、扫描仪、摄像头、音频设备等。
3. Ethernet接口芯片Ethernet（以太网）是一种用于局域网（LAN）的常用接口标准。
Ethernet接口芯片通常包括MAC（Media Access Control）子层和物理层接口部分。
它们可以支持不同的以太网速度和传输介质，如10/100/1000 Mbps和光纤、双绞线等。
Ethernet接口芯片的应用非常广泛，如网络交换机、路由器、网络存储设备等。
4. HDMI接口芯片HDMI（High-Definition Multimedia Interface）是一种用于高清视频和音频传输的接口标准。
HDMI接口芯片通常包括HDMI控制器和HDMI PHY两部分。
HDMI控制器负责处理HDMI协议的逻辑层，而HDMI PHY负责处理HDMI物理层的电信号转换。
HDMI接口芯片广泛应用于高清电视、投影仪、显示器等设备。
5. SPI接口芯片SPI（Serial Peripheral Interface）是一种用于外围设备和微控制器之间的串行通信接口。
SPI接口芯片通常包括SPI控制器和SPI PHY两部分。
SPI控制器负责处理SPI协议的逻辑层，而SPI PHY负责处理SPI物理层的电信号转换。
以太网接口芯片CH395与ENC28J60对比
单片机联网芯片CH395与ENC28J60对比目前较成熟的单片机联网方案有CH395和ENC28J60，都是被常用到的芯片，这两种芯片分别为片上自带TCP/IP协议栈和未带TCP/IP协议栈，其中ENC28J60片上不带TCP/IP协议栈成本略低而CH395为内置TCP/IP协议栈芯片（仅需消耗较少单片机资源），其单片机命令操作方式让用户实际使用起来更方便。
CH395 ENC28J60生产厂家WCH沁恒MicrochipTCP/IP实现方式内置（基本不消耗单片机RAM和Flash资源）无（单片机端加载，消耗单片机RAM 和FLASH资源）PHY 10M/100M自适应（支持直连和交叉线）10MMAC 有有接口串口/并口/SPI(30MHZ) SPI（最高10MHZ）RAM 24K 8KSocket 8个，独立通道互不影响可分配多个，但Socket增多会导致MCU效率大幅降低工作电压 1.8V/3.3V 3.45V工作电流10M BASE-T：80ma100M BASE-T：150ma10M BASE-T:250ma时钟30MHZ 25MHZApp例程官方库，规范、可移植性强（wch官网可直接下载）第三方库，可移植性差，稳定性不确定开发周期有网络基础的一周内可完成周期较长实测ping返回速率平均0ms 平均2ms实测SPI方式网络通讯速率10Mbps 0.3Mbps实测并口方式万国通讯速率12.5Mbps 无操作方式命令操作，简单方便寄存器操作工作温度范围工业级：-40 - 85度工业级：-40 - 85度芯片封装LQFP64M SPDIP/SSOP/SOIC/QFN288路GPIO（用于扩展单片机IO）无附加功能：4K EEPROM 无1、硬件参数对比（1）ENC28J60芯片结构方面，结构比较简单，通过内置MAC+PHY芯片来实现简单的以太网物理层连接，用户需要自己创建或市场上的第三方库方能实现应用层的设计； PHY芯片方面，内置了一块10M BASE-T芯片，基本可以满足目前通信需要；接口方面，采用最高10MHz的SPI接口；缓存方面，ENC28J60仅提供8KB内部收发缓存，在目前处理大量数据要求的背景下显得捉襟见肘。
网口扫盲三：以太网芯片MAC和PHY的关系
⽹⼝扫盲三：以太⽹芯⽚MAC和PHY的关系问:如何实现单⽚以太⽹微控制器?答:诀窍是将微控制器、以太⽹媒体接⼊控制器(MAC)和物理接⼝收发器(PHY)整合进同⼀芯⽚,这样能去掉许多外接元器件.这种⽅案可使MAC和PHY实现很好的匹配,同时还可减⼩引脚数、缩⼩芯⽚⾯积.单⽚以太⽹微控制器还降低了功耗,特别是在采⽤掉电模式的情况下.问:以太⽹MAC是什么?答:MAC即Media Access Control,即媒体访问控制⼦层协议.该协议位于OSI七层协议中数据链路层的下半部分,主要负责控制与连接物理层的物理介质.在发送数据的时候,MAC协议可以事先判断是否可以发送数据,如果可以发送将给数据加上⼀些控制信息,最终将数据以及控制信息以规定的格式发送到物理层;在接收数据的时候,MAC协议⾸先判断输⼊的信息并是否发⽣传输错误,如果没有错误,则去掉控制信息发送⾄LLC 层.该层协议是以太⽹MAC由IEEE-802.3以太⽹标准定义.最新的MAC同时⽀持10Mbps和100Mbps两种速率.以太⽹数据链路层其实包含MAC(介质访问控制)⼦层和LLC(逻辑链路控制)⼦层.⼀块以太⽹卡MAC芯⽚的作⽤不但要实现MAC⼦层和LLC⼦层的功能,还要提供符合规范的PCI界⾯以实现和主机的数据交换.MAC从PCI总线收到IP数据包(或者其他⽹络层协议的数据包)后,将之拆分并重新打包成最⼤1518Byte,最⼩64Byte的帧.这个帧⾥⾯包括了⽬标MAC地址、⾃⼰的源MAC地址和数据包⾥⾯的协议类型(⽐如IP数据包的类型⽤80表⽰).最后还有⼀个DWORD(4Byte)的CRC码.可是⽬标的MAC地址是哪⾥来的呢?这牵扯到⼀个ARP协议(介乎于⽹络层和数据链路层的⼀个协议).第⼀次传送某个⽬的IP地址的数据的时候,先会发出⼀个ARP包,其MAC的⽬标地址是⼴播地址,⾥⾯说到：”谁是xxx.xxx.xxx.xxx这个IP地址的主⼈？”因为是⼴播包,所有这个局域⽹的主机都收到了这个ARP请求.收到请求的主机将这个IP地址和⾃⼰的相⽐较,如果不相同就不予理会,如果相同就发出ARP响应包.这个IP地址的主机收到这个ARP请求包后回复的ARP响应⾥说到:”我是这个IP地址的主⼈”.这个包⾥⾯就包括了他的MAC地址.以后的给这个IP地址的帧的⽬标MAC地址就被确定了.(其它的协议如IPX/SPX也有相应的协议完成这些操作.)IP地址和MAC地址之间的关联关系保存在主机系统⾥⾯,叫做ARP表,由驱动程序和操作系统完成.在Microsoft的系统⾥⾯可以⽤arp-a的命令查看ARP表.收到数据帧的时候也是⼀样,做完CRC以后,如果没有CRC效验错误,就把帧头去掉,把数据包拿出来通过标准的借⼝传递给驱动和上层的协议客栈,最终正确的达到我们的应⽤程序.还有⼀些控制帧,例如流控帧也需要MAC直接识别并执⾏相应的⾏为.以太⽹MAC芯⽚的⼀端接计算机PCI总线,另外⼀端就接到PHY芯⽚上,它们之间是通过MII接⼝链接的.问:什么是MII?答:MII即媒体独⽴接⼝,它是IEEE-802.3定义的以太⽹⾏业标准."媒体独⽴"表明在不对MAC硬件重新设计或替换的情况下,任何类型的PHY设备都可以正常⼯作.它包括⼀个数据接⼝,以及⼀个MAC和PHY之间的管理接⼝.数据接⼝包括分别⽤于发送器和接收器的两条独⽴信道.每条信道都有⾃⼰的数据,时钟和控制信号.MII数据接⼝总共需要16个信号,包括TX_ER,TXD<3:0>,TX_EN,TX_CLK, COL,RXD<3:0>,RX_EX,RX_CLK,CRS,RX_DV等.MII以4位半字节⽅式传送数据双向传输,时钟速率25MHz.其⼯作速率可达100Mb/s;MII管理接⼝是个双信号接⼝,⼀个是时钟信号,另⼀个是数据信号.通过管理接⼝,上层能监视和控制PHY.其管理是使⽤SMI(Serial Management Interface)总线通过读写PHY的寄存器来完成的.PHY⾥⾯的部分寄存器是IEEE定义的,这样PHY把⾃⼰的⽬前的状态反映到寄存器⾥⾯,MAC通过SMI总线不断的读取PHY的状态寄存器以得知⽬前PHY的状态,例如连接速度,双⼯的能⼒等.当然也可以通过SMI设置PHY的寄存器达到控制的⽬的,例如流控的打开关闭,⾃协商模式还是强制模式等.不论是物理连接的MII总线和SMI总线还是PHY的状态寄存器和控制寄存器都是有IEEE的规范的,因此不同公司的MAC和PHY⼀样可以协调⼯作.当然为了配合不同公司的PHY的⾃⼰特有的⼀些功能,驱动需要做相应的修改.MII⽀持10Mbps和100Mbps的操作,⼀个接⼝由14根线组成,它的⽀持还是⽐较灵活的,但是有⼀个缺点是因为它⼀个端⼝⽤的信号线太多,如果⼀个8端⼝的交换机要⽤到112根线,16端⼝就要⽤到224根线,到32端⼝的话就要⽤到448根线,⼀般按照这个接⼝做交换机,是不太现实的,所以现代的交换机的制作都会⽤到其它的⼀些从MII简化出来的标准,⽐如RMII,SMII,GMII等.RMII是简化的MII接⼝,在数据的收发上它⽐MII接⼝少了⼀倍的信号线,所以它⼀般要求是50MHz的总线时钟.RMII⼀般⽤在多端⼝的交换机,它不是每个端⼝安排收,发两个时钟,⽽是所有的数据端⼝公⽤⼀个时钟⽤于所有端⼝的收发,这⾥就节省了不少的端⼝数⽬.RMII的⼀个端⼝要求7个数据线,⽐MII少了⼀倍,所以交换机能够接⼊多⼀倍数据的端⼝.和MII⼀样,RMII⽀持10Mbps和100Mbps的总线接⼝速度.SMII是由思科提出的⼀种媒体接⼝,它有⽐RMII更少的信号线数⽬,S表⽰串⾏的意思.因为它只⽤⼀根信号线传送发送数据,⼀根信号线传输接受数据,所以为了满⾜100Mbps的总线接⼝速度的需求,它的时钟频率就达到了125MHz,为什么⽤125MHz,是因为数据线⾥⾯会传送⼀些控制信息.SMII⼀个端⼝仅⽤4根信号线完成100Mbps的传输,⽐起RMII差不多⼜少了⼀倍的信号线.SMII在⼯业界的⽀持⼒度是很⾼的.同理,所有端⼝的数据收发都公⽤同⼀个外部的125MHz时钟.GMII是千兆⽹的MII接⼝,这个也有相应的RGMII接⼝,表⽰简化了的GMII接⼝.MII总线在IEEE802.3中规定的MII总线是⼀种⽤于将不同类型的PHY与相同⽹络控制器(MAC)相连接的通⽤总线.⽹络控制器可以⽤同样的硬件接⼝与任何PHY .GMII(Gigabit MII)GMII采⽤8位接⼝数据,⼯作时钟125MHz,因此传输速率可达1000Mbps.同时兼容MII所规定的10/100 Mbps⼯作⽅式.GMII接⼝数据结构符合IEEE以太⽹标准.该接⼝定义见IEEE 802.3-2000.发送器:GTXCLK——吉⽐特TX..信号的时钟信号(125MHz)TXCLK——10/100Mbps信号时钟TXD[7..0]——被发送数据TXEN——发送器使能信号TXER——发送器错误(⽤于破坏⼀个数据包)注:在千兆速率下,向PHY提供GTXCLK信号,TXD,TXEN,TXER信号与此时钟信号同步.否则,在10/100Mbps速率下,PHY提供TXCLK时钟信号,其它信号与此信号同步.其⼯作频率为25MHz(100M⽹络)或2.5MHz(10M⽹络).接收器:RXCLK——接收时钟信号(从收到的数据中提取,因此与GTXCLK⽆关联)RXD[7..0]——接收数据RXDV——接收数据有效指⽰RXER——接收数据出错指⽰COL——冲突检测(仅⽤于半双⼯状态)管理配置MDC——配置接⼝时钟MDIO——配置接⼝I/O管理配置接⼝控制PHY的特性.该接⼝有32个寄存器地址,每个地址16位.其中前16个已经在"IEEE 802.3,2000-22.2.4 Management Functions"中规定了⽤途,其余的则由各器件⾃⼰指定.RMII(Reduced Media Independant Interface)简化媒体独⽴接⼝是标准的以太⽹接⼝之⼀,⽐MII有更少的I/O传输.RMII⼝是⽤两根线来传输数据的,MII⼝是⽤4根线来传输数据的,GMII是⽤8根线来传输数据的.MII/RMII只是⼀种接⼝,对于10Mbps线速,MII的时钟速率是2.5MHz就可以了,RMII则需要5MHz;对于100Mbps线速,MII需要的时钟速率是25MHz,RMII则是50MHz.MII/RMII⽤于传输以太⽹包,在MII/RMII接⼝是4/2bit的,在以太⽹的PHY⾥需要做串并转换,编解码等才能在双绞线和光纤上进⾏传输,其帧格式遵循IEEE 802.3(10M)/IEEE 802.3u(100M)/IEEE 802.1q(VLAN).以太⽹帧的格式为:前导符+开始位+⽬的mac地址+源mac地址+类型/长度+数据+padding(optional)+32bitCRC如果有vlan,则要在类型/长度后⾯加上2个字节的vlan tag,其中12bit来表⽰vlan id,另外4bit表⽰数据的优先级!问:以太⽹PHY是什么?答:PHY是物理接⼝收发器,它实现物理层.IEEE-802.3标准定义了以太⽹PHY.包括MII/GMII(介质独⽴接⼝)⼦层,PCS(物理编码⼦层),PMA(物理介质附加)⼦层,PMD(物理介质相关)⼦层,MDI⼦层.它符合IEEE-802.3k中⽤于10BaseT(第14条)和100BaseTX(第24条和第25条)的规范.PHY在发送数据的时候,收到MAC过来的数据(对PHY来说,没有帧的概念,对它来说,都是数据⽽不管什么地址,数据还是CRC.对于100BaseTX 因为使⽤4B/5B编码,每4bit就增加1bit的检错码),然后把并⾏数据转化为串⾏流数据,再按照物理层的编码规则把数据编码,再变为模拟信号把数据送出去.收数据时的流程反之.PHY还有个重要的功能就是实现CSMA/CD的部分功能.它可以检测到⽹络上是否有数据在传送,如果有数据在传送中就等待,⼀旦检测到⽹络空闲,再等待⼀个随机时间后将送数据出去.如果两个碰巧同时送出了数据,那样必将造成冲突,这时候,冲突检测机构可以检测到冲突,然后各等待⼀个随机的时间重新发送数据.这个随机时间很有讲究的,并不是⼀个常数,在不同的时刻计算出来的随机时间都是不同的,⽽且有多重算法来应付出现概率很低的同两台主机之间的第⼆次冲突.许多⽹友在接⼊Internt宽带时,喜欢使⽤”抢线”强的⽹卡,就是因为不同的PHY碰撞后计算随机时间的⽅法设计上不同,使得有些⽹卡⽐较”占便宜”.不过,抢线只对⼴播域的⽹络⽽⾔的,对于交换⽹络和ADSL这样点到点连接到局端设备的接⼊⽅式没什么意义.⽽且”抢线”也只是相对⽽⾔的,不会有质的变化.现在交换机的普及使得交换⽹络的普及,使得冲突域⽹络少了很多,极⼤地提⾼了⽹络的带宽.但是如果⽤HUB,或者共享带宽接⼊Internet的时候还是属于冲突域⽹络,有冲突碰撞的.交换机和HUB最⼤的区别就是:⼀个是构建点到点⽹络的局域⽹交换设备,⼀个是构建冲突域⽹络的局域⽹互连设备.除此之外PHY还提供了和对端设备连接的重要功能并通过LED灯显⽰出⾃⼰⽬前的连接的状态和⼯作状态让我们知道.当我们给⽹卡接⼊⽹线的时候,PHY不断发出的脉冲信号检测到对端有设备,它们通过标准的”语⾔”交流,互相协商并却定连接速度、双⼯模式、是否采⽤流控等.通常情况下,协商的结果是两个设备中能同时⽀持的最⼤速度和最好的双⼯模式.这个技术被称为AutoNegotiation或者NWAY,它们是⼀个意思–⾃动协商.具体传输过程为,发送数据时,⽹卡⾸先侦听介质上是否有载波(载波由电压指⽰),如果有,则认为其他站点正在传送信息,继续侦听介质.⼀旦通信介质在⼀定时间段内(称为帧间缝隙IFG=9.6微秒)是安静的,即没有被其他站点占⽤,则开始进⾏帧数据发送,同时继续侦听通信介质,以检测冲突.在发送数据期间,如果检测到冲突,则⽴即停⽌该次发送,并向介质发送⼀个“阻塞”信号,告知其他站点已经发⽣冲突,从⽽丢弃那些可能⼀直在接收的受到损坏的帧数据,并等待⼀段随机时间(CSMA/CD确定等待时间的算法是⼆进制指数退避算法).在等待⼀段随机时间后,再进⾏新的发送.如果重传多次后(⼤于16次)仍发⽣冲突,就放弃发送.接收时,⽹卡浏览介质上传输的每个帧,如果其长度⼩于64字节,则认为是冲突碎⽚.如果接收到的帧不是冲突碎⽚且⽬的地址是本地地址,则对帧进⾏完整性校验,如果帧长度⼤于1518字节(称为超长帧,可能由错误的LAN驱动程序或⼲扰造成)或未能通过CRC校验,则认为该帧发⽣了畸变.通过校验的帧被认为是有效的,⽹卡将它接收下来进⾏本地处理.问:造成以太⽹MAC和PHY单⽚整合难度⾼的原因是什么?答:PHY整合了⼤量模拟硬件,⽽MAC是典型的全数字器件.芯⽚⾯积及模拟/数字混合架构是为什么先将MAC集成进微控制器⽽将PHY留在⽚外的原因.更灵活、密度更⾼的芯⽚技术已经可以实现MAC和PHY的单芯⽚整合.问: ⽹卡上除RJ-45接⼝外,还需要其它元件吗?答:PHY和MAC是⽹卡的主要组成部分,⽹卡⼀般⽤RJ-45插⼝,10M⽹卡的RJ-45插⼝也只⽤了1,2,3,6四根针,⽽100M或1000M⽹卡的则是⼋根针都是全的.除此以外,还需要其它元件,因为虽然PHY提供绝⼤多数模拟⽀持,但在⼀个典型实现中,仍需外接6,7只分⽴元件及⼀个局域⽹绝缘模块.绝缘模块⼀般采⽤⼀个1：1的变压器.这些部件的主要功能是为了保护PHY免遭由于电⽓失误⽽引起的损坏.另外,⼀颗CMOS制程的芯⽚⼯作的时候产⽣的信号电平总是⼤于0V的(这取决于芯⽚的制程和设计需求),但是这样的信号送到100⽶甚⾄更长的地⽅会有很⼤的直流分量的损失.⽽且如果外部⽹线直接和芯⽚相连的话,电磁感应(打雷)和静电,很容易造成芯⽚的损坏.再就是设备接地⽅法不同,电⽹环境不同会导致双⽅的0V电平不⼀致,这样信号从A传到B,由于A设备的0V电平和B点的0V电平不⼀样,这样会导致很⼤的电流从电势⾼的设备流向电势低的设备.为了解决以上问题Transformer(隔离变压器)这个器件就应运⽽⽣.它把PHY送出来的差分信号⽤差模耦合的线圈耦合滤波以增强信号,并且通过电磁场的转换耦合到连接⽹线的另外⼀端.这样不但使⽹线和PHY之间没有物理上的连接⽽换传递了信号,隔断了信号中的直流分量,还可以在不同0V电平的设备中传送数据.隔离变压器本⾝就是设计为耐2KV~3KV的电压的.也起到了防雷感应(我个⼈认为这⾥⽤防雷击不合适)保护的作⽤.有些朋友的⽹络设备在雷⾬天⽓时容易被烧坏,⼤都是PCB设计不合理造成的,⽽且⼤都烧毁了设备的接⼝,很少有芯⽚被烧毁的,就是隔离变压器起到了保护作⽤.隔离变压器本⾝是个被动元件,只是把PHY的信号耦合了到⽹线上,并没有起到功率放⼤的作⽤.那么⼀张⽹卡信号的传输的最长距离是谁决定的呢?⼀张⽹卡的传输最⼤距离和与对端设备连接的兼容性主要是PHY决定的.但是可以将信号送的超过100⽶的PHY其输出的功率也⽐较⼤,更容易产⽣EMI的问题.这时候就需要合适的Transformer与之配合.作PHY的⽼⼤公司Marvell的PHY,常常可以传送180~200⽶的距离,远远超过IEEE的100⽶的标准.RJ-45的接头实现了⽹卡和⽹线的连接.它⾥⾯有8个铜⽚可以和⽹线中的4对双绞(8根)线对应连接.其中100M的⽹络中1,2是传送数据的,3,6是接收数据的.1,2之间是⼀对差分信号,也就是说它们的波形⼀样,但是相位相差180度,同⼀时刻的电压幅度互为正负.这样的信号可以传递的更远,抗⼲扰能⼒强.同样的,3,6也⼀样是差分信号.⽹线中的8根线,每两根扭在⼀起成为⼀对.我们制作⽹线的时候,⼀定要注意要让1,2在其中的⼀对,3,6在⼀对.否则长距离情况下使⽤这根⽹线的时候会导致⽆法连接或连接很不稳定.现在新的PHY⽀持AUTO MDI-X功能(也需要Transformer⽀持).它可以实现RJ-45接⼝的1,2上的传送信号线和3,6上的接收信号线的功能⾃动互相交换.有的PHY甚⾄⽀持⼀对线中的正信号和负信号的功能⾃动交换.这样我们就不必为了到底连接某个设备需要使⽤直通⽹线还是交叉⽹线⽽费⼼了.这项技术已经被⼴泛的应⽤在交换机和SOHO路由器上.在1000Basd-T⽹络中,其中最普遍的⼀种传输⽅式是使⽤⽹线中所有的4对双绞线,其中增加了4,5和7,8来共同传送接收数据.由于1000Based-T⽹络的规范包含了AUTOMDI-X功能,因此不能严格确定它们的传出或接收的关系,要看双⽅的具体的协商结果.⼀⽚⽹卡主要功能的实现就基本上是上⾯这些器件了.其他的,还有⼀颗EEPROM芯⽚,通常是⼀颗93C46.⾥⾯记录了⽹卡芯⽚的供应商ID,⼦系统供应商ID,⽹卡的MAC地址,⽹卡的⼀些配置,如SMI 总线上PHY的地址,BOOTROM的容量,是否启⽤BOOTROM引导系统等东西.很多⽹卡上还有BOOTROM这个东西.它是⽤于⽆盘⼯作站引导操作系统的.既然⽆盘,⼀些引导⽤必需⽤到的程序和协议栈就放到⾥⾯了,例如RPL,PXE等.实际上它就是⼀个标准的PCI ROM.所以才会有⼀些硬盘写保护卡可以通过烧写⽹卡的BootRom来实现.其实PCI设备的ROM是可以放到主板BIOS⾥⾯的.启动电脑的时候⼀样可以检测到这个ROM并且正确识别它是什么设备的.AGP在配置上和PCI很多地⽅⼀样,所以很多显卡的BIOS也可以放到主板BIOS⾥⾯.这就是为什么板载的⽹卡我们从来没有看到过BOOTROM的原因.最后就是电源部分了.⼤多数⽹卡现在都使⽤3.3V或更低的电压.有的是双电压的.因此需要电源转换电路.⽽且⽹卡为了实现Wake on line功能,必须保证全部的PHY和MAC的极少⼀部分始终处于有电的状态,这需要把主板上的5V Standby电压转换为PHY⼯作电压的电路.在主机开机后,PHY的⼯作电压应该被从5V转出来的电压替代以节省5V Standby的消耗.(许多劣质⽹卡没有这么做).有Wake on line功能的⽹卡⼀般还有⼀个WOL的接⼝.那是因为PCI2.1以前没有PCI设备唤醒主机的功能,所以需要着⼀根线通过主板上的WOL的接⼝连到南桥⾥⾯以实现WOL的功能.新的主板合⽹卡⼀般⽀持PCI2.2/2.3,扩展了PME#信号功能,不需要那个接⼝⽽通过PCI总线就可以实现唤醒功能.我们现在来看两个图MAC和PHY分开的以太⽹卡MAC和PHY集成在⼀颗芯⽚的以太⽹卡上图中各部件为:①RJ-45接⼝②Transformer(隔离变压器)③PHY芯⽚④MAC芯⽚⑤EEPROM⑥BOOTROM插槽⑦WOL接头⑧晶振⑨电压转换芯⽚⑩LED指⽰灯⽹卡的功能主要有两个:⼀是将电脑的数据封装为帧,并通过⽹线(对⽆线⽹络来说就是电磁波)将数据发送到⽹络上去;⼆是接收⽹络上其它设备传过来的帧,并将帧重新组合成数据,发送到所在的电脑中.⽹卡能接收所有在⽹络上传输的信号,但正常情况下只接受发送到该电脑的帧和⼴播帧,将其余的帧丢弃.然后,传送到系统CPU做进⼀步处理.当电脑发送数据时,⽹卡等待合适的时间将分组插⼊到数据流中.接收系统通知电脑消息是否完整地到达,如果出现问题,将要求对⽅重新发送.问:10BaseT和100BaseTX PHY实现⽅式不同的原因何在?答:两种实现的分组描述本质上是⼀样的,但两者的信令机制完全不同.其⽬的是阻⽌⼀种硬件实现容易地处理两种速度.10BaseT采⽤曼彻斯特编码,100BaseTX采⽤4B/5B编码.问:什么是曼彻斯特编码?答:曼彻斯特编码⼜称曼彻斯特相位编码,它通过相位变化来实现每个位(图2).通常,⽤⼀个时钟周期中部的上升沿表⽰“1”,下降沿表⽰“0”.周期末端的相位变化可忽略不计,但有时⼜可能需要将这种相位变化计算在内,这取决于前⼀位的值.问:什么是4B/5B编码?答:4B/5B编码是⼀种块编码⽅式.它将⼀个4位的块编码成⼀个5位的块.这就使5位块内永远⾄少包含2个“1”转换,所以在⼀个5位块内总能进⾏时钟同步.该⽅法需要25%的额外开销.问:⽹卡的MAC和PHY间的关系?答:⽹卡⼯作在osi的最后两层,物理层和数据链路层,物理层定义了数据传送与接收所需要的电与光信号、线路状态、时钟基准、数据编码和电路等,并向数据链路层设备提供标准接⼝.物理层的芯⽚称之为PHY.数据链路层则提供寻址机构、数据帧的构建、数据差错检查、传送控制、向⽹络层提供标准的数据接⼝等功能.以太⽹卡中数据链路层的芯⽚称之为MAC控制器.很多⽹卡的这两个部分是做到⼀起的.他们之间的关系是pci总线接mac总线,mac接phy,phy接⽹线(当然也不是直接接上的,还有⼀个变压装置).PHY和MAC之间是如何传送数据和相互沟通的.通过IEEE定义的标准的MII/GigaMII(Media Independed Interfade,介质独⽴界⾯)界⾯连接MAC和PHY.这个界⾯是IEEE定义的.MII界⾯传递了⽹络的所有数据和数据的控制.ETHERNET的接⼝实质是MAC通过MII总线控制PHY的过程.问:⽹线上传输的是模拟信号还是数字信号?答:是模拟信号.因为它传出和接收是采⽤的模拟的技术.虽然它传送的信息是数字的(并不是传送的信息是数字的信号就可以叫做数字信号).简单的例⼦:我们知道电话是模拟信号,但是当我们拨号上⽹的时候,电话线⾥传送的是数字信息,但信号本⾝依旧是模拟的.然⽽ADSL同样是通过电话线传送的,却是数字信号.这取决于它传出和接受采⽤的技术.问:若操作系统没有加载⽹卡驱动,⽹卡虽然在系统设备树上,但⽹卡接⼝创建不了,那⽹卡实际能不能接收到数据?答:这⾥⾯有很多细节, 我根据Intel⽹卡的Spec⼤概写了写, 想尽量写的通俗⼀些,所以没有刻意⽤Spec⾥的术语,另外本⽂虽然讲的是MAC/PHY,但光⼝卡的(SERDES)也是类似的.1. PCI设备做reset以后进⼊D0uninitialized(⾮初始化的D0状态, 参考PCI电源管理规范),此时⽹卡的MAC和DMA都不⼯作,PHY是⼯作在⼀个特殊的低电源状态的;2. 操作系统创建设备树时,初始化这个设备,PCI命令寄存器的 Memory Access Enable or the I/O Access Enable bit会被enable, 这就是D0active.此时PHY/MAC就使能了;3. PHY被使能应该就可以接收物理链路上的数据了,否则不能收到FLP/NLP, PHY就不能建⽴物理连接.但这类包⼀般是流量间歇发送的;4. 驱动程序⼀般要通过寄存器来控制PHY, ⽐如⾃动协商speed/duplex, 查询物理链路的状态Link up/down;5. MAC被使能后, 如果没有驱动设置控制寄存器的⼀个位(CTRL.SLU )的话, MAC和PHY是不能通讯的, 就是说MAC不知道PHY的link已经ready, 所以收不到任何数据的.这位设置以后, PHY完成⾃协商, ⽹卡才会有个Link change的中断,知道物理连接已经Link UP了;6. 即使Link已经UP, MAC还需要enable接收器的⼀个位(RCTL.RXEN ),包才可以被接收进来,如果⽹卡被reset,这位是0,意味着所有的包都会被直接drop掉,不会存⼊⽹卡的 FIFO.⽼⽹卡在驱动退出前利⽤这位关掉接收.Intel的最新千兆⽹卡发送接收队列的动态配置就是依靠这个位的,重新配置的过程⼀定要关掉流量;7. ⽆论驱动加载与否, 发⽣reset后,⽹卡EEPOM⾥的mac地址会写⼊⽹卡的MAC地址过滤寄存器, 驱动可以去修改这个寄存器,现代⽹卡通常⽀持很多MAC地址,也就是说,MAC地址是可以被软件设置的.例如,Intel的千兆⽹卡就⽀持16个单播 MAC地址,但只有1个是存在EEPROM⾥的,其它是软件声称和设置的;8. 但如果驱动没有加载,⽹卡已经在设备树上,操作系统完成了步骤1-2的初始化,此时⽹卡的PHY应该是⼯作的,但因为没有⼈设置控制位(CTRL.SLU)来让MAC和PHY建⽴联系,所以MAC是不收包的.这个控制位在reset时会再设置成0;9. PHY可以被软件设置加电和断电, 断电状态除了接收管理命令以外,不会接收数据.另外,PHY还能⼯作在Smart Power Down模式下,linkdown就进⼊省电状态;10. 有些多⼝⽹卡,多个⽹⼝共享⼀个PHY, 所以BIOS⾥设置disbale了某个⽹⼝, 也未必会把PHY的电源关掉,反过来,也要⼩⼼地关掉PHY的电源;11. 要详细了解PHY,最终还是要熟悉IEEE以太⽹的相关协议.。
以太网协议栈管理芯片CH392用户手册说明书
以太网协议栈芯片CH392版本：v1.0 1、概述CH392是以太网协议栈管理芯片，用于单片机系统进行以太网通讯。
CH392芯片自带10M 以太网介质传输层（MAC ）和物理层(PHY)，完全兼容IEEE802.3协议，内置了IP 、DHCP 、ARP 、ICMP 、IGMP 、UDP 、TCP 等以太网协议栈固件。
单片机系统可以方便的通过CH392芯片进行网络通讯。
CH392支持两种通讯接口： SPI 接口或者异步串口，单片机/DSP/MCU/MPU 等控制器可以通过上述任何一种通讯接口控制CH392芯片进行以太网通讯。
下图为CH392的应用框图。
2、特点● 内部自带以太网介质传输层（MAC ）和物理层(PHY)。
● 支持10M ，全双工/半双工自适应，兼容802.3 协议。
● 支持MDI/MDIX 线路自动转换。
● 内置TCP/IP 协议簇，支持IPv4、DHCP 、ARP 、ICMP 、IGMP 、UDP 、TCP 协议。
● 提供4个独立的Socket 对，可以同时进行数据收发。
● 提供最高8MHz 速度的SPI 设备接口，支持连接到单片机的SPI 串行总线。
● 提供最高921600bps 速度的异步串口，支持连接到单片机的串行口，支持通讯波特率动态调整。
● 内置4KB RAM ，可用于以太网数据收发，每个Socket 收发缓冲区可以自由配置。
● 提供QFN28封装。
INT本地端 控制器 单片机 DSP MCU MPU 等 SPI设备 接口 异步 串口 SCS SCK MOSI=> SDI MISO <= SDO SPI 总线 TXD => RXD RXD <= TXD 串口UART 10M PHY交换机 PC路由器 等网络设备 TXP TXN RXPRXN 以太网信号IPARP ICMP IGMP UDP TCP DHCP MAC3、封装芯片型号芯片封装名称描述CH392F QFN28 QFN封装；28脚；本体4x4mm 4、引脚CH392F 引脚号引脚名称类型引脚说明0 GND 电源芯片接地端3,4,22 VCC 电源内部电源，需外接0.1uF退耦电容5 VDD 电源 3.3V工作电压输入，外接2.2uF退耦电容6 RXD 输入异步串口数据输入，内置上拉电阻7 TXD 输出异步串口数据输出，内置上拉电阻8 RXP 以太网信号以太网RXP信号9 RXN 以太网信号以太网RXN信号10 TXP 以太网信号以太网TXP信号11 TXN 以太网信号以太网TXN信号12 INT 输出中断信号输出，低电平有效14 ACT 输出以太网连接通讯指示灯驱动引脚15 LINK 输出PHY连接指示引脚，低有效16 RSTI 输入外部复位输入，低电平有效18 XO 输出晶体振荡的反相输出端，需要外接32MHz晶振19 XI 输入晶体振荡的输入端，需要外接32MHz晶振20 VREF 电源内部模拟电路电源节点，需外接 1uF 退耦电容23 SEL 输入通讯接口选择引脚，内置上拉，高电平选择串口，低电平选择SPI25 SDO 输出SPI数据输出26 SDI 输入SPI数据输入27 SCK 输入SPI时钟输入28 SCS 输入SPI片选输入1,2,13,17,21,24NC NC 保留管脚，悬空5、命令本手册中的数据，后缀B为二进制数，后缀H为十六进制数，否则为十进制数。
rtl8304mb原理
rtl8304mb原理
RTL8304MB是一款以太网交换芯片，具有高性能和可靠性。
该芯片采用了先进的技术和设计，以满足各种网络交换需求。
RTL8304MB采用了高集成度的设计，可以支持多个以太网接口和各种网络协议。
它具有4个10/100Mbps以太网接口，可以连接多个网络设备，如计算机、路由器和交换机等。
同时，它还支持各种网络协议，如IEEE 802.3、IEEE 802.1q和IEEE 802.1p等，以实现高效的数据传输和管理。
RTL8304MB具有优秀的性能特点。
它采用了高性能的交换引擎，可以实现高速的数据传输和处理。
同时，它还支持流量控制和拥塞控制等功能，以保证网络的稳定和可靠性。
此外，RTL8304MB还具有多种数据包处理技术，如VLAN和QoS等，以提供灵活的网络管理和服务质量保障。
RTL8304MB还具有丰富的安全功能。
它支持MAC地址过滤、端口隔离和访问控制列表等功能，可以有效地保护网络的安全。
另外，RTL8304MB还支持网络监控和故障检测功能，可以及时发现和解决网络问题，保证网络的稳定和可靠性。
总的来说，RTL8304MB是一款功能强大、性能优越的以太网交换芯片。
它具有高集成度、高性能和丰富的安全功能，可以满足各种网络交换需求。
无论是家庭网络还是企业网络，都可以通过使用
RTL8304MB来实现高效可靠的数据传输和管理。
这款芯片的应用广泛，已经成为许多网络设备的首选芯片。
未来，随着网络技术的不断发展，RTL8304MB还将不断升级和改进，以满足更高的网络需求。
以太网phy芯片
以太网phy芯片以太网PHY芯片是一种广泛应用于以太网接口的集成电路芯片，用于在计算机和网络设备之间传输数据。
以太网PHY芯片通常由物理层接口、传输媒介接口、时钟管理和自适应均衡和等化器等模块组成。
以太网PHY芯片可以支持不同速度的以太网接口，如10 Mbps、100 Mbps和1000 Mbps（即千兆以太网）。
它通过采用不同的调制解调器和编码技术来实现不同的速度，以满足不同类型的网络需求。
以太网PHY芯片的物理层接口负责将数据从高层协议传输到物理媒介上。
它通过生成和解析电压和电流信号，实现数据的传输和接收。
物理层接口还负责检测和纠正传输中的错误，以保证数据的准确性和完整性。
传输媒介接口是以太网PHY芯片连接到物理媒介（如双绞线、光纤等）的接口。
它根据不同的媒介类型提供不同的连接方式和电气特性，以适应不同环境下的网络需求。
时钟管理模块是以太网PHY芯片中的一个重要组成部分，用于生成和同步数据传输的时钟信号。
时钟信号是保证数据传输的同步和准确性的关键因素。
时钟管理模块可以提供内部时钟源或接收外部时钟源，并通过锁相环（PLL）技术调整时钟频率和相位来保证数据传输的稳定性。
自适应均衡和等化器模块是以太网PHY芯片中的另一个重要组成部分，用于对传输中的信号进行均衡和补偿，以减小信号损失和抖动，提高数据传输的可靠性。
自适应均衡和等化器模块根据接收到的信号特性自动调整均衡和补偿参数，以适应不同长度和质量的传输线路。
除了上述基本模块，以太网PHY芯片还可以包含一些其他功能，如电源管理、噪声抑制、故障检测和诊断等。
这些功能可以提供更高级的性能和功能，以满足不同网络设备的需求。
总的来说，以太网PHY芯片是一种集成电路芯片，用于实现不同速度和不同介质的以太网接口。
它通过物理层接口、传输媒介接口、时钟管理和自适应均衡和等化器等模块实现数据的传输和接收，以及网络的连接和管理。
随着以太网技术的发展和应用范围的扩大，以太网PHY芯片的功能和性能将会进一步提升，以满足不断变化的网络需求。
usb转以太网芯片
usb转以太网芯片USB转以太网芯片，顾名思义就是一种将USB接口转换为以太网接口的芯片。
它能够在计算机或其他设备上提供以太网连接的功能。
这样，用户就可以通过USB接口来连接到以太网，并享受到高速稳定的网络连接。
USB转以太网芯片通常采用Ethernet Controller的形式，具有一系列的特性和功能，包括：1. 支持千兆以太网速率（1000 Mbps），以满足高速网络传输的需求。
2. 具备自适应和自动协商功能，能够自动识别实际的网络速率，并调整以保证最佳的网络连接质量。
3. 支持全双工通信，即可以同时进行发送和接收数据，提高了数据传输效率。
4. 提供大容量的数据缓存，以应对高速网络传输中的数据冲击。
5. 支持高级的网络特性，如IPv4和IPv6协议、VLAN（虚拟局域网）等。
6. 集成了MAC（媒体访问控制）和PHY（物理层）功能，能够直接与网络传输介质（如网线）进行通信。
7. 具备低功耗设计，以减少对设备电池的消耗，延长使用时间。
8. 通过USB接口供电，不需要额外的电源供应，方便携带和使用。
9. 兼容主流的操作系统，包括Windows、MAC OS和Linux等。
10. 提供丰富的软件支持和驱动程序，方便用户进行安装和配置。
USB转以太网芯片在许多应用领域都具有广泛的应用。
以下是一些常见的应用场景：1. 笔记本电脑和台式电脑：在某些情况下，计算机可能没有内置的以太网接口或者内置的以太网接口不能满足用户的需求。
用户可以通过连接USB转以太网芯片，来实现高速的有线网络连接。
2. 游戏主机和电视盒子：某些游戏主机和电视盒子可能只提供无线网络连接。
但对于一些需要更稳定和更快的网络连接的情况，用户可以通过使用USB转以太网芯片，来实现有线网络连接。
3. 嵌入式系统和物联网设备：在一些特殊的嵌入式系统和物联网设备中，无线网络连接可能不太可靠或者不能满足特定的需求。
通过使用USB转以太网芯片，可以为这些设备提供可靠且高速的有线网络连接。
以太网芯片的工作原理
以太网芯片的工作原理以太网芯片是计算机网络设备中的重要组成部分，负责将数据包传输到以太网上。
它的工作原理涉及到以下几个方面：1.数据编码：以太网将每个数据包划分为多个帧，每个帧由一系列比特组成。
以太网芯片会将数据从计算机的处理器传送到物理介质上，并对数据进行编码处理。
编码和解码过程使用的是物理层规范，如 Manchester 编码或4B/5B编码等。
2.数据传输：以太网芯片会将编码后的数据通过物理介质传输。
物理介质可以是铜缆、光纤或无线电波等。
传输过程中，以太网芯片会按照以太网协议的规范将数据帧发送出去。
发送过程中，会使用载波侦听多路访问（CSMA/CD）技术来协调多个设备之间的访问冲突和碰撞。
3.数据接收：当以太网芯片接收到一个数据帧时，它会进行数据的提取和解码。
首先，芯片会检查数据帧的前导码，并与预设的前导码进行比较，用于同步数据的接收。
之后，芯片会将数据进行解码，还原成原始的比特序列。
4.地址识别：每个以太网芯片都有一个唯一的物理地址，称为MAC 地址。
芯片在接收到数据帧后，会提取出帧头中的目标地址和源地址进行比较，以确定数据是否是发送给本机的。
如果目标地址与本机的 MAC 地址匹配，芯片将接受数据；否则，将忽略数据。
5.数据处理：一旦数据被接受，以太网芯片将数据传输到计算机的内存中，供处理器或操作系统使用。
这些数据可以被上层协议处理，如传输层协议 TCP 或 UDP。
总结起来，以太网芯片的工作原理可以概括为：数据编码、数据传输、数据接收、地址识别和数据处理。
通过这些步骤，以太网芯片实现了快速、可靠的数据传输和通信。
以太网PHY芯片之MIIMDIO接口详解
以太⽹PHY芯⽚之MIIMDIO接⼝详解本⽂主要分析MII/RMII/SMII，以及GMII/RGMII/SGMII接⼝的信号定义，及相关知识，同时本⽂也对RJ-45接⼝进⾏了总结，分析了在10/100模式下和1000M模式下的设计⽅法。
MII接⼝提供了MAC与PHY之间、PHY与STA(Station Management)之间的互联技术，该接⼝⽀持10Mb/s与100Mb/s的数据传输速率，数据传输的位宽为4位。
提到MII，就有可能涉及到RS，PLS，STA等名词术语，下⾯讲⼀下他们之间对应的关系。
所谓RS即Reconciliation sublayer，它的主要功能主要是提供⼀种MII和MAC/PLS之间的信号映射机制。
它们(RS与MII)之间的关系如下图：MII接⼝的Management Interface可同时控制多个PHY，802.3协议最多⽀持32个PHY，但有⼀定的限制：要符合协议要求的connector特性。
所谓Management Interface，即MDC信号和MDIO信号。
前⾯已经讲过RS与PLS的关系，以及MII接⼝连接的对象。
它们是通过MII接⼝进⾏连接的，⽰意图如下图。
由图可知，MII的Management Interface是与STA（Station Management）相连的。
接⼝⽀持10Mb/s以及100Mb/s，且在两种⼯作模式下所有的功能以及时序关系都是⼀致的，唯⼀不同的是时钟的频率问题。
802.3要求PHY 不⼀定⼀定要⽀持这两种速率，但⼀定要描述，通过Management Interface反馈给MAC。
下⾯将详细介绍MII接⼝的信号定义，时序特性等。
由于MII接⼝有MAC和PHY模式，因此，将会根据这两种不同的模式进⾏分析，同时还会对RMII/SMII进⾏介绍。
MII接⼝可分为MAC模式和PHY模式，⼀般说来MAC和PHY对接，但是MAC和MAC也是可以对接的。
以太网接口芯片W5500与ENC28J60对比
以太网接口芯片W5500与ENC28J60对比目前较为成熟的单片机接入以太网方案：W5100和ENC28J60，都是被常常使用到的芯片，这两种方案也可以说是硬件协议栈和软件协议栈的典型代表，都经得住市场考验。
除了在传统单片机的以太网接入中被广泛使用，也能看到他们在开源硬件的以太网扩展以及物联网应用等方面发挥的重要作用。
W5500是WIZnet最新的以太网芯片，这里就拿W5500来做比较。
表1为W5500与ENC28J60基本参数对比表。
表1 W5500于ENC28J60基本参数对比1、硬件参数对比（1）ENC28J60芯片结构方面，结构比较简单，通过内置MAC+PHY芯片来实现简单的以太网物理层连接，用户需要自己创建或市场上的第三方库方能实现应用层的设计；PHY芯片方面，内置了一块10M BASE-T 芯片，基本可以满足目前通信需要；接口方面，采用最高10MHz的SPI接口；缓存方面，ENC28J60仅提供8KB内部收发缓存，在目前处理大量数据要求的背景下显得捉襟见肘。
（2）W5500芯片结构方面，内部由TCP/IP协议栈+MAC+PHY构成，拥有非常完善的官方应用库，极大缩短开发周期，可以完美实现以太网接入要求；PHY芯片方面，10M/100M BASE-T自适应芯片让W5500表现更为出色；接口方面，W5500采用新的高效SPI协议支持80MHz速率；缓存方面，W5500内置32KB收发缓存，用户可以同时使用8个硬件Socket独立通信，且各个Socket之间互不影响。
2、TCP/IP协议栈ENC28J60采用的是传统的软协议操作，需要主控MCU不断的响应中断，这在很大程度上占用了MCU的资源来跑软协议栈。
经过测试发现，随着需要响应的事件增多，MCU的处理效率直线下降，会严重影响通信质量。
W5500采用的是最新的TOE（TCP卸载引擎）技术，不同于传统的软协议栈，通过内置TCP/IP硬件协议栈也就是硬件逻辑电路，在W5500芯片内完成TCP/IP握手请求，基本上不占用MCU内部资源，能够极大地提高MCU工作效率。
比较常用的以太网物理层接口芯片---AC101
PRELIMINARY DATA SHEETI AC101AC101-DS01-R¥¥¥¥¥16215 Alton Parkway •P .O. Box 57013•Irvine, CA 92619-7013•Phone: 949-450-8700•Fax: 949-450-871006/04/01AC101QF/TF Ultra Low Power 10/100Ethernet TransceiverFigure 1:Functional Block Diagram GENERAL DESCRIPTIONFEATURES The AC101QF/TF is a highly integrated, 3.3V, low power,10BASE-T/100BASE-TX/FX, Ethernet transceiver implement-ed in 0.35 µm CMOS technology. Multiple modes of operation,including normal operation, test mode and power saving mode,are available through either hardware or software control.Features include MAC interfaces, encoder/decoders (EN-DECs), Scrambler/Descrambler, and Auto-Negotiation (ANeg)with support for parallel detection. The transmitter includes adual-speed clock synthesizer that only needs one external clocksource (crystal or clock oscillator). The chip has built-in waveshaping driver circuit for both 10 Mbps and 100 Mbps, eliminat-ing the need for an external hybrid filter. The receiver has anadaptive equalizer/DC restoration circuit for accurate clock anddata recovery for the 100BASE-TX signal. It also provides anon-chip low pass filer/Squelch circuit for the 10BASE-T signal.MAC interfaces to support 10/100 MII, 100M only SymbolMode, 10M only Symbol Mode and 10M only 7 wire interfaceare included.The AC101TF and the AC101QF are the same product in differ-ent packages.•MII MAC connection - 5 Volt tolerant and 2.5 Volt capable •10/100 TX/FX -Full-duplex or half-duplex -FEFI on 100FX •Two packages: 80TQFP and 100PQFP •Industrial temperature: -40°C to +85°C •Very low power – TYP < 280 mW (Total)-Cable Detect mode – TYP < 40 mW (Total)-Power Down mode – TYP < 3.3 mW (T otal)-Selectable TX drivers for 1:1 or 1.25:1 transformers for additional power reduction • 3.3 Volt .35 micron CMOS •Fully compliant with -IEEE 802.3/802.3u -MII •Baseline Wander Compensation •Multi-Function LED outputs •Legacy 10BASE-T 7 wire interface •100M Symbol Mode/10M Symbol Mode •Cable length indicator•Reverse polarity detection and correction with register bitindication – automatic or forced•8 programmable interrupts•Diagnostic registers 10T X 10R X 100R X 100T X 20 M H zC o n tro l/S ta tu s 25 M H z X T L P /N C K IN T E S T [3:0]L ED D riv e rsR XF L P M u x A u to -N e g o tia tio n10B A S E -T P L L C lk G e n T e s t/L E D C o n tro l M II S e ria l M a n a g e m e n tIn te rfa c e a n d R e g is te rs M II D a taIn te rfa c eP H Y A D [4:0]P M A o C lk R e c o v o L in k M o n o S ig n a l De t T P _P M D o M L T -3o B L W o S tre a m M A Co rR IC In te rfa c e P C S o F ra m e r o C a rrie r C ip h e r D e te c t o 4B /5B MII S e ria l M g m tIn te rfa c e T X O P /T X O N R X IP /R X IN F X T P /F X T N F X R P /F X R NRevision HistoryRevision Date Change DescriptionAC101-DS00-R5/22/01Initial release.AC101-DS01-R Changed signal names: FX_DIS, FXRP/FXRN, FXTP/FXTN, RXIP/RX-IN, and TXOP/TXON.Altima Communications, Inc.A Wholly Owned Subsidiary ofBroadcom CorporationP.O. Box 5701316215 Alton ParkwayIrvine, CA 92619-7013© 2001 by Altima Communications, Inc.All rights reservedPrinted in the U.S.A.Broadcom®, the pulse logo, and QAMLink are registered trademarks of Broadcom Corporation and/or its subsidiaries in the United States and certain other countries. All other trademarks are the property of their respective owners.Preliminary Data Sheet I AC101 06/04/01T ABLE OF C ONTENTSSection 1: Functional Description (1)Overview (1)MAC Interface (1)Media Independent Interface (MII) (1)Serial Management Interface (SMI) (1)Interrupts (2)Carrier Sense/RX_DV (2)7-Wire Serial Interface (2)PCS Bypass (3)100 Mbps PCS Bypass (3)10 Mbps PCS Bypass (3)Media Interface (3)10BASE-T Interface (3)Transmit Function (3)Receive Function (3)Link Monitor (3)100BASE-TX Interface (3)Transmit Function (4)Parallel to Serial, NRZ to NRZI, and MLT3 Conversion (4)Receive Function (4)Baseline Wander Compensation (5)Clock/Data Recovery (5)Decoder/De-scrambler (5)Link Monitor (5)100BASE-FX Interface (6)Transmit Function (6)Receive Function (6)Link Monitor (6)Far-End-Fault-Insertion (FEFI) (6)10BASE-T/100BASE-TX/FX Interface (6)Multi-Mode Transmit Driver (6)Adaptive Equalizer (7)BroadcomDocument AC101-DS01-R¥¥¥¥¥Page iiiI AC101Preliminary Data SheetT ABLE OF C ONTENTS06/04/01 PLL Clock Synthesizer (7)Jabber and SQE (Heartbeat) (7)Reverse Polarity Detection and Correction (7)Hardware Configuration (7)Software Configuration (7)LED Outputs (7)Auto-Negotiation (8)Parallel Detection (9)Diagnostics (9)Loopback Operation (9)Cable Length Indicator (9)Reset and Power (10)Clock Input (10)Section 2: Signal Definitions and Pin Assignments (11)Pin Descriptions (11)PHY Address Pins (11)MDI (Media Dependent Interface) Pins (11)MII (Media Independent Interface) 100 PCS Bypass Pins (12)10 Mbps PCS Bypass Pins (13)10 Mbps 7-Wire Interface Pins (13)Special/Test Pins (14)Control and Status Pins (14)LED Indicators Pins (16)Power and Ground Pins (17)No Connect Pins (18)Technology Selections (18)Advanced LED Selections (19)Section 3: Pinout Diagrams (21)AC101QF Pinout Diagram (21)AC101TF Pinout Diagram (22)Section 4: Register Descriptions (23)Register Summary (23)MII-Specified Registers (24)BroadcomPage iv Document AC101-DS01-R¥¥¥¥¥Preliminary Data Sheet I AC101 06/04/01T ABLE OF C ONTENTSRegister 0: Control Register (24)Register 1: Status Register (25)Register 2: PHY Identifier 1 Register (26)Register 3: PHY Identifier 2 Register (26)Register 4: Auto-Negotiation Advertisement Register (26)Register 5: Auto-Negotiation Link Partner Ability Register (27)Register 6: Auto-Negotiation Expansion Register (28)Register 7: Auto-Negotiation Next Page Transmit Register (28)Altima-Specified Registers (29)Register 16: Polarity and Interrupt Level Register (29)Register 17: Interrupt Control/Status Register (30)Register 18: Diagnostic Register (30)Register 19: Power/Loopback Register (31)Register 20: Cable Measurement Register (31)Register 21: Mode Control Register (32)Register 24: Receive Error Counter Register (33)4B/5B Code-Group Table (33)SMI Read/Write Sequence (34)Section 5: Electrical Characteristics (35)Operating Range (35)Total Power Consumption (35)TTL I/O Characteristics (35)REFCLK and XTAL Pin Characteristics (36)I/O Characteristics – LED/CFG Pin Characteristics (36)100BASE-TX Transceiver Characteristics (36)10BASE-T Transceiver Characteristics (37)100BASE-FX Transceiver Characteristics (37)10BASE-T Link Integrity Timing Characteristics (38)Section 6: Timing and AC Characteristics (39)Digital Timing Characteristics (39)Power on Reset Timing (39)Management Data Interface Timing (39)100BASE-TX/FX MII Transmit System Timing (40)100BASE-TX/FX MII Receive System Timing (41)BroadcomDocument AC101-DS01-R¥¥¥¥¥Page vI AC101Preliminary Data SheetT ABLE OF C ONTENTS06/04/01 10BASE-T MII Transmit System Timing (42)10BASE-T MII Receive System Timing (44)10BASE-T 7-Wire Transmit System Timing (45)10BASE-T 7-Wire Receive System Timing (46)10BASE-T 7-Wire Collision Timing (46)Recommended Board Circuitry (47)TX Application Termination (47)FX Application Termination (48)Power and Ground Filtering for AC101QF (49)Power and Ground Filtering for AC101TF (50)Section 7: Mechanical Information (51)Package Dimensions for AC101QF (100 pin PQFP) (51)Package Dimensions for AC101TF (80 pin TQFP) (52)BroadcomPage vi Document AC101-DS01-R¥¥¥¥¥Preliminary Data Sheet I AC101 06/04/01L IST OF F IGURESFigure 1:Functional Block Diagram (i)Figure 2:Multifunction LED Pin Connection (19)Figure 3:Dual-color LED Indicator for Link, Duplex, and Activity Status (20)Figure 4:AC101QF Pinout Diagram (21)Figure 5:AC101TF Pinout Diagram (22)Figure 6:Power-on Reset Timing (39)Figure 7:Management Data Interface Timing (40)Figure 8:100BASE-TX/FX MII Transmit Timing (41)Figure 9:100BASE-TX/FX MII Receive Timing (42)Figure 10:10BASE-T MII Transmit Timing (43)Figure 11:10BASE-T MII Receive Timing (44)Figure 12:10BASE-T 7-WireTransmit Timing (45)Figure 13:10BASE-T 7-Wire Receive Timing (46)Figure 14:10BASE-T 7-Wire Collision Timing (47)Figure 15:TX Application Termination Circuit (47)Figure 16:FX Application Termination Circuit (48)Figure 17:Power and Ground Filtering for the AC101QF (49)Figure 18:Power and Ground Filtering for the AC101TF (50)Figure 19:Package Dimensions for AC101QF (100 pin PQFP) (51)Figure 20:Package Dimensions for AC101TF (80 pin TQFP) (52)BroadcomDocument AC101-DS01-R¥¥¥¥¥Page viiI AC101Preliminary Data SheetL IST OF F IGURES06/04/01BroadcomPage viii Document AC101-DS01-R¥¥¥¥¥Preliminary Data Sheet I AC101 06/04/01L IST OF T ABLESTable 1:PHY Address Pins (11)Table 2:MDI (Media Dependent) Pins (11)Table 3:MII (Media Independent Interface) 100 PCS Bypass Pins (12)Table 4:10 Mbps PCS Bypass Pins (13)Table 5:10 Mbps 7-Wire Interface Pins (13)Table 6:Special/Test Pins (14)Table 7:Control and Status Pins (14)Table 8:LED Indicator Pins (16)Table 9:Power and Ground Pins (17)Table 10:No Connect Pins (18)Table 11:Technology Solutions (18)Table 12:Advanced LED Selections (19)Table 13:Register Summary (23)Table 14:Register 0: Control Register (24)Table 15:Register 1: Status Register (25)Table 16:Register 2: PHY Identifier 1 Register (26)Table 17:Register 3: PHY Identifier 2 Register (26)Table 18:Register 4: Auto-Negotiation Advertisement Register (26)Table 19:Register 5: Auto-Negotiation Link Partner Ability Register (27)Table 20:Register 6: Auto-Negotiation Expansion Register (28)Table 21:Register 7: Auto-Negotiation Next Page Transmit Register (28)Table 22:Register 16: Polarity and Interrupt Level Register (29)Table 23:Register 17: Interrupt Control/Status Register (30)Table 24:Register 18: Diagnostic Register (30)Table 25:Register 19: Power/Loopback Register (31)Table 26:Register 20: Cable Measurement Register (31)Table 27:Register 21: Mode Control Register (32)Table 28:Register 24: Receive Error Counter Register (33)Table 29:4B/5B Code-Group Table (33)Table 30:SMI Read/Write Sequence (34)Table 31:Total Power Consumption (35)Table 32:TTL I/O Characteristics (35)BroadcomDocument AC101-DS01-R¥¥¥¥¥Page ixI AC101Preliminary Data SheetL IST OF T ABLES06/04/01 Table 33:REFCLK and XTAL Pin Characteristics (36)Table 34:I/O Characteristics – LED/CFG Pin Characteristics (36)Table 35:100BASE-TX Transceiver Characteristics (36)Table 36:10BASE-T Transceiver Characteristics (37)Table 37:100BASE-FX Transceiver Characteristics (37)Table 39:Power On Reset Timing (39)Table 40:Management Data Interface Timing (39)Table 41:100BASE-TX/FX MII Transmit System Timing (40)Table 42:100BASE-TX/FX MII Receive System Timing (41)Table 43:10BASE-T MII Transmit System Timing (42)Table 44:10BASE-T MII Receive System Timing (44)Table 45:10BASE-T 7-Wire Transmit System Timing (45)Table 46:10BASE-T 7-Wire Receive System Timing (46)Table 47:10BASE-T 7-Wire Collision Timing (46)Table 48:Quad Flat Pack Outline: 20 x 14 mm (51)Table 49:Quad Flat Pack Outline: 12 x 12 mm (52)BroadcomPage x Document AC101-DS01-R¥¥¥¥¥06/04/01Section1:Functional DescriptionO VERVIEWThe AC101TF/QF PHYsical layer device (PHY) integrates the 100BASE-X and 10BASE-T functions in a single chip that is used in Fast Ethernet 10/100 Mbps applications. The 100BASE-X section consists of physical coding sublayer (PCS), phys-ical media attachment (PMA), and physical media dependent (PMD) functions and the 10BASE-T section consists of Manchester encoder/decoder (ENDEC) and transceiver functions. The device performs the following functions:•4B/5B•MLT3•NRZI•Manchester Encoding and Decoding•Clock and Data Recovery•Stream Cipher Scrambling/De-Scrambling•Adaptive Equalization•Line Transmission•Carrier Sense•Link Integrity Monitor•Auto-Negotiation (ANeg)•MII MAC connectivity•MII Management FunctionIt also provides an IEEE802.3u compatible Media Independent Interface (MII) to communicate with an Ethernet Media Ac-cess Controller (MAC). Selection of 10 or 100 Mbps operation is based on the settings of internal Serial Management Inter-face registers or determined by the on-chip ANeg logic. The device can operate in 10 or 100 Mbps with full-duplex or half-duplex mode.MAC I NTERFACEM EDIA I NDEPENDENT I NTERFACE (MII)The Media Independent Interface (MII) is an 18 wire MAC/PHY interface (see ”MII (Media Independent Interface) 100 PCS Bypass Pins” on page 12) described in 802.3u. The purpose of the interface is to allow MAC layer devices to attach to a variety of Physical Layer devices through a common interface. MII operates at either 100 Mbps or 10 Mbps, dependant on the speed of the Physical Layer. With clocks running at either 25 MHz or 2.5 MHz, 4 bit data is clocked between the MAC and PHY, synchronous with Enable and Error signals.At the time of PLL lock on an incoming signal from the wire interface, the PHY will generate RX_CLK at either 2.5 MHz for 10 Mbps or 25 MHz for 100 Mpbs.On receipt of valid data from the wire interface, RX_DV will go active signaling to the MAC that the valid data will be present-ed on the RXD[3:0] pins at the speed of the RX_CLK.On transmission of data from the MAC, TX_EN is presented to the PHY indicating the presence of valid data on TXD[3:0]. TXD[3:0] are sampled by the PHY synchronous to TX_CLK during the time that TX_EN is valid.Serial Management Interface (SMI)The PHY’s internal registers are accessible only through the MII 2-wire Serial Management Interface (SMI. see ”MII (Media06/04/01Independent Interface) 100 PCS Bypass Pins” on page 12). MDC is a clock input to the PHY which is used to latch in or out data and instructions for the PHY. The clock can run at any speed from DC to 25 MHz. MDIO is a bi-directional connection used to write instructions to, write data to, or read data from the PHY. Each data bit is latched either in or out on the rising edge of MDC. MDC is not required to maintain any speed or duty cycle, provided no half cycle is less than 20ns and that data is presented synchronous to MDC.MDC/MDIO are a common signal pair to all PHYs on a design. Therefore, each PHY needs to have its own unique Physical Address. The Physical Address of the PHY is set using the pins defined as PHYAD[4:0] (see ”PHY Address Pins” on page 11). These input signals are strapped externally and sampled as reset is negated. At idle, the PHY is responsible to pull MDIO line to a high state. Therefore, a 1.5K Ohms resistor is required to connect MDIO line to Vcc. The PHYAD can be reprogrammed via software. A detailed definition of the Serial Management registers follows.At the beginning of a read or write cycle, the MAC will send a continuous 32 bits of one at the MDC clock rate to indicate preamble. A zero and a one will follow to indicate start of frame. A read OP code is a one and a zero, while a write OP code is a zero and a one. These will be followed by 5 bits to indicate PHY address and 5 bits to indicate register address. Then 2 bits follow to allow for turn around time. For read operation, the first bit will be high impedance. Neither the PHY nor the station will assert this bit. During the second bit time, the PHY will assert this bit to a zero. For write operation, the station will drive a one for the first bit time, and a zero for the second bit time. The 16 bits data field is then presented. The first bit that is transmitted is bit 15 of the register content.InterruptsThe INTR pin (see ”MII (Media Independent Interface) 100 PCS Bypass Pins” on page 12) on the PHY will be asserted when-ever one of 8 selectable interrupt events occur. Assertion state is programmable to either high or low through the INTR_LEVL register bit (see ”Register 16: Polarity and Interrupt Level Register” on page 29). Selection is made by setting the appropriate bit in the upper half of the Interrupt Control/Status register (see ”Register 17: Interrupt Control/Status Register” on page 30). When the INTR bit goes active, the MAC interface is required to read the Interrupt Control/Status register to determine which event caused the interrupt. The Status bits are read only and clear on read. When INTR is not asserted, the pin is held in a high impedance state.Carrier Sense/RX_DVCarrier sense is asserted asynchronously on the CRS pins as soon as activity is detected on the receive data stream. RX_DV is asserted as soon as a valid SSD (Start-of-Stream Delimiter) is detected. Carrier sense and RX_DV are de-assert-ed synchronously upon detection of a valid end of stream delimiter or two consecutive idle code groups in the receive data stream. However, if the carrier sense is asserted and a valid SSD is not detected immediately, RX_ER is asserted instead of RX_DV. See ”MII (Media Independent Interface) 100 PCS Bypass Pins” on page 12.)In 10BASE-T mode, CRS is asserted asynchronously when the valid preamble and data activity is detected on the RXIP and RXIN pins.In the half-duplex mode, the CRS is activated during the transmit and receiving of data. In the full-duplex mode, the CRS is activated during data reception only.7-W IRE S ERIAL I NTERFACETo allow the PHY to run in legacy 10 Mbps only designs, the 7-wire serial interface, referred to as General Purpose Serial Interface (GPSI, see ”10 Mbps 7-Wire Interface Pins” on page 13) has been included. GPSI is an industry standard interface which has been implemented in many micro-controllers and micro-processors, as well as the majority of the 10 Mpbs MACs.The interface consists of 10 Mbps transmit and receive clocks, 10 Mbps serial transmit and receive data, transmit enable, receive enable and collision.When running the GPSI mode, the PHY must be forced to 10 Mbps only mode through hardware configuration.The 10BASE-T 7-wire interface is enabled when the GPIO[0] (see ”Control and Status Pins” on page 14) is pull low by 1 KΩduring reset.06/04/01PCS B YPASSThe AC101TF/QF is put into PCS bypass mode when the PCSBP pin is pull high (see ”Control and Status Pins” on page 14).100 Mbps PCS BypassIn MII designs, the encoding/decoding functions are performed in the PHY, thereby allowing 4-bit data exchange. Certain designs, however, require MAC/PHY data transfer to be in the form of 5-bit symbols. By selecting PCS Bypass mode of op-eration, the PHY will present data to, and accept data from the MAC layer as 5-bit symbols. In PCS Bypass mode the RX_ER and TX_ER pins are used as the RXD4 and TXD4 (see ”MII (Media Independent Interface) 100 PCS Bypass Pins” on page 12).10 Mbps PCS BypassWhen using PCS Bypass at 10 Mbps, the standard MAC/PHY interface is no longer valid. Differential drivers and receivers carry data serially between the MAC and PHY (see ”10 Mbps PCS Bypass Pins” on page 13).M EDIA I NTERFACEThe AC101TF/QF can be media-configured using any of the following three methods:•Hardware configuration: see ”Control and Status Pins” on page 14.•Software configuration: see ”Register 21: Mode Control Register” on page 32.•Auto-Negotiation (ANeg): see ”Control and Status Pins” on page 14 and ”MII-Specified Registers” on page 24.10BASE-T I NTERFACEWhen configured to run in 10BASE-T mode, either through hardware configuration, software configuration, or ANeg, the PHY will support all the features and parameters of the industry standards.Transmit FunctionIf the MII interface is used, Parallel to Serial logic is used to convert the 4-bit data into the serial stream. If the 7-Wire interface is used (see ”10 Mbps 7-Wire Interface Pins” on page 13), the serial data goes directly to the Manchester encoder where it is synthesized through the output waveshaping driver. The waveshaper reduces any EMI emission by filtering out the har-monics, therefore eliminating the need for an external filter.Receive FunctionThe received signal passes through a low-pass filter, which filters out the noise from the cable, board, and transformer. This eliminates the need for a 10BASE-T external filter. A Manchester decoder converts the incoming serial stream. If the 7-wire 10BASE-T interface is enabled (see ”10 Mbps 7-Wire Interface Pins” on page 13), the decoded serial data is presented to the MAC. If the MII interface is used (see ”MII (Media Independent Interface) 100 PCS Bypass Pins” on page 12), Serial to Parallel logic is used to generate the 4-bit data.Link MonitorThe 10-BASE-T link-pulse detection circuit will constantly monitor the RXIP/RXIN pins (see ”MDI (Media Dependent Inter-face) Pins” on page 11) for the presence of valid link pulses. In the absence of valid link pules, the Link Status bit will be cleared and the Link LED will de-assert.100BASE-TX I NTERFACEWhen configured to run in 100BASE-TX mode, either through hardware configuration, software configuration, or ANeg, the PHY will support all the features and parameters of the industry standards.06/04/01Transmit FunctionIn 100BASE-TX mode, the PHY transmit function converts synchronous 4-bit data nibbles from the MII to a pair of 125 Mbps differential serial data streams. The serial data is transmitted over network twisted pair cables via an isolation transformer. Data conversion includes 4B/5B encoding, scrambling, parallel to serial, NRZ to NRZI, and MLT-3 encoding. The entire op-eration is synchronous to 25 MHz and 125 MHz clock. Both clocks are generated by an on-chip PLL clock synthesizer that is locked on to an external 25 MHz clock source.The transmit data, in 4-bit nibbles at 25 MHz rate, is transmitted from the MAC to the PHY via the MII TXD[3:0] signals. The 4B/5B encoder replaces the first two nibbles of the preamble from the MAC frame with a /J/K/ code-group pair Start-of-Stream Delimiter (SSD), following the onset of TX_EN signal. The 4B/5B encoder appends a /T/R/ code-group pair End-of-Stream Delimiter (ESD) to the end of transmission in place of the first two IDLE code-groups that follow the negation of the TX_EN signal. The encapsulated data stream is converted from 4-bit nibbles to 5-bit code-groups. During the inter-packet gap, when there is no data present, a continuous stream of IDLE code-groups are transmitted. When TX_ER is asserted while TX_EN is active, the Transmit Error code-group /H/ is substituted for the translated 5B code word. The 4B/5B encoding is bypassed when Reg. 21.1 is set to “1”, or the PCSBP pin is strapped high. See ”MII (Media Independent Interface) 100 PCS Bypass Pins” on page 12.In 100BASE-TX mode, the 5-bit transmit data stream is scrambled as defined by the TP-PMD Stream Cipher function in order to reduce radiated emissions on the twisted pair cable. The scrambler encodes a plain text NRZ bit stream using a key stream periodic sequence of 2047 bits generated by the recursive linear function:X[n] = X[n-11] + X[n-9] (modulo 2)The scrambler reduces peak emissions by randomly spreading the signal energy over the transmitted frequency range, thus eliminating peaks at any single frequency. For repeater applications, where all ports transmit the same data simultaneously, signal energy is spread further by using a non-repeating sequence for each PHY (i.e., the scrambled seed is unique for each different PHY based on the PHY address).When Dis_Scrm (see ”Register 21: Mode Control Register” on page 32) is set to “0” the data scrambling function is disabled, the 5-bit data stream is clocked directly to the device’s PMA sublayer.Parallel to Serial, NRZ to NRZI, and MLT3 ConversionThe 5-bit NRZ data is clocked into PHY’s shift register with a 25 MHz clock and clocked out with a 125 MHz clock to convert it into a serial bit stream. The serial data is converted from NRZ to NRZI format, which produces a transition on Logic 1 and no transition on Logic 0. To further reduce EMI emissions, the NRZI data is converted to an MLT-3 signal. The conversion offers a 3dB to 6dB reduction in EMI emissions. This allows system designers to meet the FCC Class B limit. Whenever there is a transition occurring in NRZI data, there is a corresponding transition occurring in the MLT-3 data. For NRZI data, it changes the count up/down direction after every single transition. For MLT-3 data, it changes the count up/down direction after every two transitions. The NRZI to MLT-3 data conversion is implemented without reference to the bit timing or clock information. The conversion requires detecting the transitions of the incoming NRZI data and setting the count up/down di-rection for the MLT-3 data. Asserting FX_SEL high will disable this encoding.The slew rate of the transmitted MLT-3 signal can be controlled to reduce EMI emissions. The MLT-3 signal after the mag-netic has a typical rise/fall time of approximately 4 ns, which is within the target range specified in the ANSI TP- PMD stan-dard. This is guaranteed with either 1:1 or 1.25:1 transformer.Receive FunctionThe 100BASE-TX receive path functions as the inverse of the transmit path. The receive path includes a receiver with adap-tive equalization and DC restoration in the front end. It also includes a MLT-3 to NRZI converter, 125 MHz data and clock recovery, NRZI/NRZ conversion, Serial-to-Parallel conversion, de-scrambler, and 5B/4B decoder. The receiver circuit starts with a DC bias for the differential RX+/- inputs, followed with a low-pass filter to filter out high frequency noise from the trans-mission channel media. An energy detect circuit is also added to determine whether there is any signal energy on the media. This is useful in the power-saving mode. The amplification ratio and slicer’s threshold is set by the on-chip bandgap refer-ence.06/04/01Baseline Wander CompensationThe 100BASE-TX data stream is not always DC balanced. The transformer blocks the DC components of the incoming sig-nal, thus the DC offset of the differential receive inputs can drift. The shifting of the signal level, coupled with non-zero rise and fall times of the serial stream can cause pulse-width distortion. This creates jitter and possible increase in the bit error rates. Therefore, a DC restoration circuit is needed to compensate for the attenuation of the DC component. This PHY im-plements a patent-pending DC restoration circuit. Unlike the traditional implementation, the circuit does not need the feed-back information from the slicer or the clock recovery circuit. This design simplifies the circuit design and eliminates any random/systematic offset on the receive path. In the 10BaseT and the 100BASE-FX modes, the baseline wander correction circuit is not required, and therefore is disabled.Clock/Data RecoveryThe equalized MLT-3 signal passes through the slicer circuit, and gets converted to NRZI format. The PHY uses a propri-etary mixed-signal phase locked loop (PLL) to extract clock information from the incoming NRZI data. The extracted clock is used to re-time the data stream and set the data boundaries. The transmit clock is locked to the 25 MHz clock input while the receive clock is locked to the incoming data streams. When initial lock is achieved, the PLL switches to the data stream, extracts the 125 MHz clock, and uses it for the bit framing for the recovered data. The recovered 125 MHz clock is also used to generate the 25 MHz RX_CLK signal. The PLL requires no external components for its operation and has high noise im-munity and low jitter. It provides fast phase alignment and locks to data in one transition. Its data/clock acquisition time after power-on is less than 60 transitions. The PLL can maintain lock on run-lengths of up to 60 data bits in the absence of signal transitions. When no valid data is present, i.e. when the SD is de-asserted, the PLL will switch and lock on to TX_CLK. This provides a continuously running RX_CLK. At the PCS interface, the 5 bit data RXD[4:0] is synchronized to the 25 MHz RX_CLK. See ”MII (Media Independent Interface) 100 PCS Bypass Pins” on page 12.Decoder/De-scramblerThe de-scrambler detects the state of the transmit Linear Feedback Shift Register (LFSR) by looking for a sequence repre-senting consecutive idle codes. The de-scrambler acquires lock on the data stream by recognizing IDLE bursts of 30 or more bits and locks its frequency to its de-ciphering LFSR.Once lock is acquired, the device can operate with an inter-packet-gap (IPG) as low as 40 nS. However, before lock is ac-quired, the de-scrambler needs a minimum of 270 nS of consecutive idles in between packets in order to acquire lock.The de-ciphering logic also tracks the number of consecutive errors received while the RX_DV (see ”MII (Media Independent Interface) 100 PCS Bypass Pins” on page 12) is asserted. Once the error counter exceeds its limit currently set to 64 con-secutive errors, the logic assumes that the lock has been lost, and the de-cipher circuit resets itself. The process of regaining lock will start again.Stream cipher de-scrambler is not used in the 100BASE-FX and the 10BASE-T modes.Link MonitorSignal level is detected through a squelch detection circuitry. A signal detect (SD) circuit allows the equalizer to assert high whenever the peak detector detects a post-equalized signal with peak to ground voltage greater than 400 mV. This is ap-proximately 40% of a normal signal voltage level. In addition, the energy level must be sustained for longer than 2~3 µS in order for the signal detect signal to stay on. The SD gets de-asserted approximately 1~2 µs after the energy level drops consistently below 300 mV from peak to ground.The link signal is forced low during a local loopback operation (Loopback register bit is set) and forced to high when a remote loopback is taking place (EN_RPBK is set, see ”Register 21: Mode Control Register” on page 32).In forced 100BASE-TX mode, when a cable is unplugged or no valid signal is detected on the receive pair, the link monitor enters in the “link fail” state and NLP's are transmitted. When a valid signal is detected for a minimum period of time, the link monitor enters Link Pass State and transmits MLT-3 signal.。
以太网芯片
以太网芯片以太网芯片（Ethernet Chip）是一种集成电路芯片，用于在计算机网络中传输数据。
在以太网通信中，以太网芯片充当网络适配器的角色，负责从计算机系统中发送和接收以太网数据包。
以太网芯片的主要功能包括物理层和数据链路层协议的实现，以及数据包的发送和接收。
在物理层，以太网芯片通过调制解调器和光纤收发器等外部设备，将数字信号转换为模拟或光学信号，以便在物理介质上进行传输。
同时，它还负责接收来自物理介质的信号，并将其转换为数字信号，以供计算机系统进行处理。
在数据链路层，以太网芯片处理数据包的封装和解封装。
它通过添加以太网帧的头部和尾部，将数据转换为以太网数据包，以便在网络中传输。
同时，它还负责校验和处理数据包的错误或丢失。
除了物理和数据链路层的实现，以太网芯片还具有一些额外的功能和特性，以提高网络传输的性能和稳定性。
例如，它可以支持全双工通信，允许同时发送和接收数据，减少网络延迟和冲突。
此外，它还可以支持虚拟局域网(VLAN)和流量控制等功能，为网络管理和优化提供便利。
以太网芯片的性能主要取决于其处理能力和传输速度。
处理能力通常由芯片的内部处理器和内存大小决定。
较高的处理能力可以提供更高的网络吞吐量和稳定性，以处理更大量的数据。
传输速度则是以太网芯片的另一个重要指标，常用的传输速度包括10Mbps、100Mbps和1Gbps等。
以太网芯片被广泛应用于各种计算机设备和网络设备中，如个人电脑、服务器、路由器和交换机等。
它可以通过PCI、PCI Express、USB等接口与计算机系统连接，提供网络连接和传输功能。
总结来说，以太网芯片是一种关键的网络适配器芯片，负责实现物理层和数据链路层协议，并提供高速和稳定的网络连接。
它在计算机网络中起到了至关重要的作用，推动了互联网的发展和普及。
以太网转串口芯片
以太网转串口芯片以太网转串口芯片是一种用于将以太网信号转换为串口信号的芯片。
以太网是一种广泛应用于局域网和广域网的通信协议，而串口则是一种用于设备之间的通信的通用接口标准。
以太网转串口芯片的作用就是将以太网信号转换为串口信号，用于串口设备与以太网之间的通信传输。
以太网转串口芯片通常包含一个以太网接口和一个或多个串口接口。
以太网接口用于与以太网连接，通过以太网协议与其他设备进行通信。
串口接口用于与串口设备连接，通过串口协议与串口设备进行通信。
以太网转串口芯片还包含了处理数据传输的控制逻辑电路和数据缓存等功能。
以太网转串口芯片的主要功能包括数据的接收和发送。
当以太网接收到数据后，以太网转串口芯片会对数据进行处理，然后通过串口接口发送给串口设备。
当串口设备发送数据时，以太网转串口芯片会接收到数据，并根据串口协议将数据转换为以太网协议格式，然后通过以太网接口发送给其他设备。
以太网转串口芯片还具有传输速率的调节等功能。
由于以太网和串口的速率可调节，以太网转串口芯片可以根据实际需求来调整数据传输的速率，以保证数据的传输稳定性和可靠性。
此外，以太网转串口芯片还支持多种串口协议和以太网协议，可以适应不同的通信环境和设备。
以太网转串口芯片的应用范围非常广泛。
它可以用于工业自动化系统、网络设备管理、远程监控等领域。
在工业自动化系统中，以太网转串口芯片可以将传感器、执行器等串口设备与以太网连接起来，实现对设备的远程管理和控制。
在网络设备管理中，以太网转串口芯片可以将路由器、交换机等设备的串口接口与以太网连接，用于远程管理和维护设备。
随着物联网的发展，越来越多的设备需要通过以太网进行通信。
但是仍然有许多设备只支持串口接口，无法直接与以太网通信。
以太网转串口芯片的出现，可以有效地解决这个问题，实现不同设备之间的互联互通。
以太网转串口芯片的发展，将为物联网的发展提供更多的可能性和便利性。
单片网络接口芯片W5100的原理与应用
单片网络接口芯片W5100的原理与应用W5100是一种单片以太网控制器，它支持10/100Mbps以太网传输速度，并且集成了TCP/IP协议栈。
这种芯片被广泛应用于嵌入式以太网应用中，包括IoT设备、网关、传感器、自动化设备等。
W5100的工作原理是将数据包从以太网物理层转换成网络层的数据包，然后在协议栈中处理数据包，最终将它们传输到应用层。
使用W5100时，可以直接连接到以太网，并使用通信接口进行通信。
W5100芯片具有许多应用，例如：①IoT设备-使用W5100将IoT设备连接到互联网，并使用TCP/IP协议进行远程监测和控制。
②网关-使用W5100将不同的网络连接到一起，如：以太网、Wi-Fi、电视线、同轴电缆等，以便在室内和室外传输数据。
③传感器-使用W5100将传感器连接到以太网，并将数据传输到云中进行分析和处理。
④智能家居系统-使用W5100将家庭设备连接到互联网，并使用TCP/IP协议进行远程监测和控制。
W5100芯片具有许多优点，在嵌入式应用中体现得淋漓尽致。
首先，它具有低成本、高性能、可靠性高等特点。
其次，它可以使用标准的API进行编程，易于开发，且有广泛的开发人员社区支持。
第三，它可以同时处理几个连接，支持多通道数据传输，因此使得并发连接成为可能。
此外，它还支持硬件加速和流控制，可以在高负荷情况下保持网络性能的稳定。
总体来说，W5100芯片是嵌入式以太网应用的理想选择。
其高性能、低成本、易于使用和广泛的应用范围使得它在IoT、直播、视频会议和其他嵌入式应用中得到了广泛的应用。
ar8033用法 -回复
ar8033用法-回复AR8033是一款常用的以太网物理层接口芯片，广泛应用于网络设备和嵌入式系统中。
本文将一步一步回答有关AR8033的用法，以帮助读者更好地了解和使用这款芯片。
第一步：介绍AR8033芯片AR8033芯片是由德州仪器公司（Texas Instruments）推出的一款集成式以太网物理层接口（PHY）芯片。
它采用了低功耗设计，适用于各类网络设备，如路由器、交换机、无线接入点等。
AR8033支持IEEE 802.3标准，可实现10/100/1000Mbps自适应速率，并提供全双工和半双工通讯模式。
第二步：AR8033的引脚功能AR8033芯片共有48个引脚，其中包括用于数据传输和控制的引脚。
以下是AR8033的主要引脚功能介绍：1. MDIO：这是一个双向串行接口，用于与主控制器进行通信，传输控制和配置数据。
2. MDC：时钟引脚，用于控制MDIO的数据传输速率。
3. TX0/RX0：这是第一个以太网通道的发送和接收引脚。
4. TX1/RX1：这是第二个以太网通道的发送和接收引脚。
5. LED0/LED1：这些引脚用于连接到LED指示灯，以显示网络连接状态。
以上只是AR8033芯片部分引脚的功能介绍，其他引脚的功能可根据具体需求进行配置和使用。
第三步：使用AR8033的基本步骤下面是使用AR8033芯片的基本步骤：1. 连接电源：将AR8033芯片的VCC引脚与正电源连接，将GND引脚与地线连接，确保芯片正常工作。
2. 连接MDIO和MDC引脚：将AR8033的MDIO引脚连接到主控制器的MDIO引脚，将MDC引脚连接到主控制器的MDC引脚，以实现数据传输和控制。
3. 连接以太网通道：将AR8033的TX0/RX0引脚与第一个以太网通道的发送和接收引脚相连，将TX1/RX1引脚与第二个以太网通道的发送和接收引脚相连。
4. 连接LED指示灯：将AR8033的LED0/LED1引脚连接到LED指示灯，以显示网络连接状态。
51单片机驱动W5100以太网接口芯片
51单⽚机驱动W5100以太⽹接⼝芯⽚51单⽚机驱动W5100以太⽹接⼝芯⽚****************************************************************************** * @file W5100.c* 本⽂件包括5个部分：* 1. W5100初始化* 2. W5100的Socket初始化* 3. Socket连接* 如果Socket设置为TCP服务器模式，则调⽤Socket_Listen()函数,W5100处于侦听状态，直到远程客户端与它连接。
* 如果Socket设置为TCP客户端模式，则调⽤Socket_Connect()函数，* 每调⽤⼀次Socket_Connect(s)函数，产⽣⼀次连接，* 如果连接不成功，则产⽣超时中断，然后可以再调⽤该函数进⾏连接。
* 如果Socket设置为UDP模式,则调⽤Socket_UDP函数* 4. Socket数据接收和发送* 5. W5100中断处理** 置W5100为服务器模式的调⽤过程：W5100_Init()-->Socket_Init(s)-->Socket_Listen(s)，设置过程即完成，等待客户端的连接。
* 置W5100为客户端模式的调⽤过程：W5100_Init()-->Socket_Init(s)-->Socket_Connect(s)，设置过程即完成，并与远程服务器连接。
* 置W5100为UDP模式的调⽤过程：W5100_Init()-->Socket_Init(s)-->Socket_UDP(s)，设置过程即完成，可以与远程主机UDP通信。
** W5100产⽣的连接成功、终⽌连接、接收数据、发送数据、超时等事件，都可以从中断状态中获得。
****************************************************************************** */#include"W5100.h" /* 定义W5100的寄存器地址、状态*/#include"REG51.h"typedef unsigned char SOCKET;sbit SPI_CS= P1^0;sbit SPI_SCK= P1^1;sbit SPI_SO= P1^2;sbit SPI_SI= P1^3;sbit SPI_EN= P1^4;sbit KEY= P1^5;/* 端⼝数据缓冲区*/unsigned char Rx_Buffer[20]; /* 端⼝接收数据缓冲区*/unsigned char Tx_Buffer[20]; /* 端⼝发送数据缓冲区*//* ⽹络参数寄存器*/unsigned char Gateway_IP[4]={192,168,2,254}; /* Gateway IP Address */unsigned char Sub_Mask[4]={255,255,255,0}; /* Subnet Mask */unsigned char Phy_Addr[6]={0x00,0x08,0xDC,0x01,0x02,0x03}; /* Physical Address */ unsigned char IP_Addr[4]= {192,168,2,1}; /* Loacal IP Address */unsigned char S0_Port[2]={0x13,0x88}; /* Socket0 Port number 5000 */unsigned char S0_DIP[4]={192,168,2,43}; /* Socket0 Destination IP Address */ unsigned char S0_DPort[2]={0x13,0x88}; /* Socket0 Destination Port number 5000*/ unsigned char S0_State=0; /* Socket0 state recorder */unsigned char S0_Data; /* Socket0 receive data and transmit OK */unsigned char W5100_Interrupt;/* UDP Destionation IP address and Port number */unsigned char UDP_DIPR[4];unsigned char UDP_DPORT[2];void Delay(unsigned int x){unsigned int i;for(i=0;iSPI_EN=1;}}unsigned char SPI_ReadByte(void){unsigned char i,rByte=0;for(i=0;i<8;i++){rByte<<=1;rByte|=SPI_SO;SPI_SCK=0;Delay(10);SPI_SCK=1;SPI_SCK=0;}return rByte;}void SPI_SendByte(unsigned char dt){unsigned char i;for(i=0;i<8;i++){if((dt<{SPI_SI=1;}else{SPI_SI=0;}SPI_SCK=0;Delay(10);SPI_SCK=1;SPI_SCK=0;}}unsigned char Read_W5100(unsigned short addr){unsigned char i;/* 置W5100的CS为低电平*/SPI_CS=0;/* 发送读命令*/SPI_SendByte(0x0f);/* 发送地址*/SPI_SendByte(addr/256);SPI_SendByte(addr);/* 读取数据*/i=SPI_ReadByte();/* 置W5100的CS为⾼电平*/SPI_CS=1;return i;}void Write_W5100(unsigned short addr, unsigned char dat) {/* 置W5100的CS为低电平*/SPI_CS=0;Delay(100);/* 发送写命令*/SPI_SendByte(0xf0);/* 发送地址*/SPI_SendByte(addr/256);SPI_SendByte(addr);/* 写⼊数据*/SPI_SendByte(dat);Delay(100);/* 置W5100的CS为⾼电平*/SPI_CS=1;}void W5100_Init(void){unsigned char i;SPI_EN=1;SPI_SCK=0;SPI_CS=1;SPI_SO=1;Write_W5100(W5100_MODE,MODE_RST); /*软复位W5100*/ Delay(100);///Write_W5100(W5100_MODE,0); /*软复位W5100*/Delay(100); /*延时100ms，⾃⼰定义该函数*//*设置⽹关(Gateway)的IP地址，4字节*//*使⽤⽹关可以使通信突破⼦⽹的局限，通过⽹关可以访问到其它⼦⽹或进⼊Internet*/ for(i=0;i<4;i++)Write_W5100(W5100_GAR+i,Gateway_IP); /*Gateway_IP为4字节unsigned char数组,⾃⼰定义*/for(i=0;i<4;i++)Gateway_IP=Read_W5100(W5100_GAR+i);/*设置⼦⽹掩码(MASK)值，4字节。
网络接口芯片（和芯润德）
⽹络接⼝芯⽚（和芯润德）⽹络接⼝芯⽚⽹络接⼝芯⽚，顾名思义，就是和⽹络相关的⼀种接⼝芯⽚！⽹络接⼝芯⽚有很多种⽐如：传统的PCI接⼝，SPI接⼝，USB接⼝，MII接⼝，RMII 接⼝，GMII接⼝，RGMII接⼝！和芯润德科技是国内唯⼀⼀家做⽹络接⼝芯⽚的IC设计公司，公司的⽹络接⼝芯⽚，主要有USB.1.1接⼝的以太⽹控制芯⽚SR9700，USB2.0接⼝的以太⽹控制芯⽚SR9800及MII接⼝，RMII接⼝的⽹络控制芯⽚SR8201F,SR8201G说个题外话：现在的⽹络安全存在很⼤的隐忧，棱镜门事件还没告⼀段落，国内各⼤政府机关，银⾏，部队也都⼈⼼惶惶~ 弱弱的问⼀下，⽤国产⽹络IC会不会更安全啊~！不过⽤国内⽹络芯⽚设计公司的IC，⾄少⽹络接⼝IC部分，是可以放⼼的！接下来接单介绍⼀下这⼏款⽹络接⼝芯⽚1.SR9700SR9700是⼀个⾼集成度、低功耗、单芯⽚USB接⼝以太⽹控制电路。
SR9700内部集成USB收发器、以太⽹PHY模块、以太⽹MAC模块、内存控制模块。
SR9700完全兼容IEEE802.3u协议，并⽀持IEEE 802.3x 流量控制协议。
SR9700⽀持USB接⼝以太⽹适配器和CD-ROM复合设备，通过外接SPI Flash可实现USB 接⼝以太⽹适配器⾃带驱动程序功能。
外接SPI Flash内也可存放除驱动程序之外的其他应⽤功能软件程序。
功能还是蛮强⼤的~2.SR9800功能更加强⼤！3.SR8201GSR8201G是⼀款RMII接⼝的以太⽹控制芯⽚，主要⽤于机顶盒，⽹络摄像机，OTT盒⼦这些设备，他的⼀些规格参数和美国,中国台湾的⽹络IC设计公司的IC基本⼀致，这都说明⼤陆的⽹络IC设计公司的这些⽅⾯的技术已经发展接近甚⾄等同于美国和中国台湾。
●Supports IEEE 802.3az-2010 (EEE)Conforms to USB 12Mbps Specification, Version 2.0●100Base-TX IEEE 802.3u Compliant●10Base-T IEEE 802.3 Compliant●Supports MII mode●Supports RMII mode●Full/half duplex operation●Twisted pair or fiber mode output●Supports Auto-Negotiation●Supports power down mode●Supports Link Down Power Saving●Supports auto MDIX●Supports Interrupt function●Supports Wake-On-LAN (WOL)●Automatic Polarity Correction●Provide two network status LEDs●Supports 25MHz external crystal or OSC●Supports 50MHz external OSC Clock input for RMII●Provides 50MHz clock source for MAC●Single-Supply 3.3V CMOS technology with On-chip 1.8V regulator ●Small Package:。
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
以太网接口芯片
以太网接口芯片是指用于以太网通信的接口芯片，主要功能是实现数据的传输和接收。
本文将对以太网接口芯片进行详细的介绍。
以太网接口芯片是计算机网络中最常用的接口类型之一，它用来连接计算机与以太网之间的物理层和数据链路层。
以太网接口芯片通常包括发送器和接收器两个主要部分。
发送器是以太网接口芯片中的一个重要组成部分，主要功能是将计算机中的数据转换成电信号发送到网络中。
发送器通常包括物理层接口电路、调制解调器、编码解码器等功能模块。
物理层接口电路主要负责将计算机中的二进制数据转换成电信号，调制解调器主要用来将数字信号转换成模拟信号，编码解码器用来对信号进行编码和解码。
接收器是以太网接口芯片中的另一个重要组成部分，主要功能是接收网络中的数据并将其转换成计算机可以识别的格式。
接收器通常包括物理层接口电路、解调器、解码器等功能模块。
物理层接口电路主要负责将接收到的电信号转换成计算机中的数字数据，解调器主要用来将模拟信号转换成数字信号，解码器用来对信号进行解码。
除了发送器和接收器，以太网接口芯片还包括一些辅助功能模块，例如MAC（媒体访问控制）子层和PHY（物理层）子层。
MAC子层主要负责控制数据的传输、接收和发送的顺序等功能，而PHY子层主要负责处理物理层的数据传输和接收。
以太网接口芯片使用的是IEEE802.3协议标准，该标准定义了
以太网的物理特性、数据传输方式和数据格式等。
以太网接口芯片通常支持多种不同传输速率，例如10Mbps、100Mbps和
1Gbps等。
随着技术的不断发展，以太网接口芯片的传输速率
也在不断提高。
以太网接口芯片广泛应用于各种计算机设备和网络设备中，例如个人电脑、服务器、路由器、交换机等。
它们在计算机网络中扮演着重要的角色，能够实现高效、可靠的数据传输。
总的来说，以太网接口芯片是计算机网络中最常用的接口类型之一，它通过发送器和接收器实现数据的传输和接收。
以太网接口芯片使用的是IEEE802.3协议标准，支持多种不同传输速率。
它广泛应用于各种计算机设备和网络设备中，是实现高效、可靠数据传输的关键。