FPGA可编程逻辑器件芯片EP3SL340F1517I4N中文规格书

(4) —
1100
(4) — 1100
(4) —
800
(4) — 800
Mbps
Stratix III Device Handbook, Volume 2
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics
ROM 1P, 8K × 1, 4K × 2, or 2K × 4
ROM 1P, 1K × 9, 512 × 18, or 256 × 36
ROM 2P, 8K × 1, 4K × 2, or 2K × 4
ROM 2P, 1K × 9, or 512 × 18
Min Pulse Width (Clock High Time)
345
250
240
180
330
240
330
240
415
270
330
250
I3 VCCL= 1.1 V 345 385 345 385 470 345 345 380 380
380
300
370
370
430
370
I4 VCCL= 1.1 V 315 375 315 375 440 315 315 345 345
Table 1–25. True and Emulated LVDS Specifications for Stratix III Devices (Note 1), (2) (Part 1 of 3)
C2
Symbol
Conditions
C3, I3
C4, I4
C4L, I4L
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
(4) — (4)
(4) — (4)
Mbps
SERDES factor J = 1, Uses SDR (4) — (4) Register
(4) — (4)
(4) — (4)
(4) — (4)
Mbps
LVDS_E_3R -fHSDR (data rate)
SERDES factor J = 4 to 10
Min Pulse Width (Clock Low Time)
ALUTs
TriMatrix Memory
C2 (6)
VCCL = 1.1 V
C3
VCCL = 1.1 V
C4
VCCL = 1.1 V
C4L
VCCL = VCCL = 1.1 V 0.9 V
I3
VCCL= 1.1 V
I4
VCCL= 1.1 V
Table 1–21. DSP Block Performance Specifications for Stratix III Devices (Note 1)
Mode
99-bit multiplier (a, c, e, g) (2) 99-bit multiplier (b, d, f, h) (2) 1212-bit multiplier (a, e) (3) 1212-bit multiplier (b, d, f, h) (3) 1818-bit multiplier 3636-bit multiplier Double mode 1818-bit multiply adder 1818-bit multiply adder 1818-bit multiply adder with loop back 1818-bit multiply adder with loop back (4) 1818-bit multiply accumulator 1818-bit multiply adder with chainout Input Cascade Independent output of four 1818 bit multiplier 36-bit shift (32 bit data)
True dual-port, 8K × 1, 4K × 2, or 2K × 4 with read-during-write option set to Old Data
True dual-port, 1K × 9 or 512 × 18 with read-during-write option set to Old Data
Transmitter
SERDES factor J = 3 to 10 (8)
(4) —
1600
(4) — 1250
(4) —
1250
(4) — 1250
Mbps
fHSDR (data rate)
SERDES factor
J = 2, Uses
(4) — (4)
DDR Register
(4) — (4)
Stratix III Device Handbook, Volume 2
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics
TriMatrix Memory Block Specifications Table 1–22 lists the Stratix III TriMatrix Memory Block specifications.
Number of Multipliers
1 1 1 1 1 1 1 2 4 2
2 4
4
4 1
C2 (5) VCCL = 1.1 V 440 500 440 500 600 440 440 490 490
490
390
475
475
550
475
C3 VCCL = 1.1 V 365 410 365 410 495 365 365 405 405
I4L
VCCL= Unit 0.9 V
0
1
600 500 450 450 340 475 450 320 MHz
0
1
600 500 450 450 340 475 450 320 MHz
0
1
600 500 450 450 370 475 450 350 MHz
0
1
600 500 450 450 340 475 450 320 MHz
Periphery Performance
This section describes periphery performance, including high-speed I/O and external memory interface.
I/O performance supports several system interfacing, such as the LVDS high-speed I/O interface, external memory interface, and the PCI/PCI-X bus interface. For example, Stratix III devices I/O configured with voltage referenced I/O standards can achieve up to the stated system interfacing speed as indicated in “External Memory Interface Specifications” on page 1–25. General-purpose I/O standards such as 3.3, 3.0, 2.5, 1.8, or 1.5 LVTTL/LVCMOS are capable of typical 167 MHz and 1.2 LVCMOS at 100MHz interfacing frequency with 10pF load.
1 Actual achievable frequency depends on design- and system-specific factors. You must perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
0
1
550 465 390 390 245 440 390 230 MHz
0
1
575 485 405 405 255 460 405 230 MHz
0
1
565 475 395 395 245 450 395 220 MHz
High-Speed I/O Specifications Refer to the “Glossary” on page 1–326 for the definitions of the high-speed timing specifications.
Table 1–25 lists the true and emulated LVDS specifications for Stratix III devices.
Unit
fHSCLK_in (input clock
Clock boost
frequency)—True factor W = 1 to 40 5 — 800
Differential I/O
(3)
Standards
5 — 717
5 — 717
5 — 717 MHz
fHSCLK_in (input clock
405
320
390
390
455
390
C4 VCCL = 1.1 V 315 375 315 375 440 315 315 345 345
345
300
330
330
415
330
C4L
VCCL = 1.1 V
315 375 315 375 440 315 315 345 345
VCCL = 0.9 V
240 270 240 270 320 220 220 250 250
Simple dual-port, 1K × 9, 512 × 18, 256 × 36 with read-during-write option set to Old Data
True dual-port, 8K × 1
True dual-port, 4K × 2 or 2K × 4
True dual-port, 1K × 9 or 512 × 18
Simple dual-port 16 20 ROM 64 × 10
ROM 32 × 20
Single-port 8K × 1
Single-port 4K × 2 or 2K × 4
Single-port 1K × 9, 512 × 18, or 256 × 36
Simple dual-port, 8K × 1
345
300
330
330
415
330
I4L VCCL= Unit 0.9 V 225 MHz 250 MHz 225 MHz 250 MHz 300 MHz 205 MHz 205 MHz 235 MHz 235 MHz
235 MHz
135 MHz
225 MHz
225 MHz
250 MHz
235 MHz
Table 1–22. TriMatrix Memory Block Performance Specifications for Stratix III Devices (Note 1) (Part 1 of 3)
Memory Block Type
Mode
MLAB M9K (2)
Single port 16 × 10
Simple dual-port, 4K × 2 or 2K × 4
Simple dual-port, 1K × 9, 512 × 18, or 256 × 36
Simple dual-port, 8K × 1, 4K × 2 or 2K × 4 with read-during-write option set to Old Data
Clock boost
frequency)—Single factor W = 1 to 40 5 — 800
Ended I/O
(3)
Standards (9)
5 — 717
Baidu Nhomakorabea
5 — 717
5 — 717 MHz
fHSCLK_out (output clock
frequency)
—
5 — 800 (7) 5 — 717 (7) 5 — 717 (7) 5 — 717 (7) MHz