LPC1765原理图

合集下载

夏普摄像头CCD板机原理图LR386032

75
4.7K 0.1uF BLC MIR WB2 WB1 1K 470 470 1K BLK ADCLP OBCP
CCDIN VCON AVSS2 AVSS2 AVDD2 AVDD2 VRP VRN NC AVDD4 NC
ADJUSTMENT
EEPSL DATA CLK EEPFL
10K 10K
0.1uF RESET
RESET
22K
1uH
1 M/R 2 SUB 3 GND
10 10
Vcc Vo
5 4
ADCK SCK SDATA D9 D8 D7 D6 D5 D4
0.1uF
PST598JN
SCK SDATA CSN
ADCLP BLK OBCP
1 2
0.1uF 4 3 xtal-osc
Reference
The schematic diagrams are merely intended for illustrating typical applications. Therefor verify the bias voltage of IC's by specifications and we take no responsibility for any problem as may result form the use of those schematic diagrams as well as those problems related to industrial properties and other rights.
POFD
+
VIDEO OUT
VL VH
FV4 FV3 FV2 FV1
100

LPC1765中文资料

1.General descriptionThe LPC1768/66/65/64 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.The LPC1768/66/65/64 operate at CPU frequencies of up to 100 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.The peripheral complement of the LPC1768/66/65/64 includes up to 512 kB of ﬂash memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG interface,8-channel general purpose DMA controller,4UARTs,2CAN channels,2SSP controllers,SPI interface, 3 I 2C-bus interfaces, 2-input plus 2-output I 2S-bus interface, 8-channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, 4 general purpose timers, 6-output general purpose PWM, ultra-low power Real-Time Clock (RTC)with separate battery supply, and up to 70 general purpose I/O pins.The LPC1768/66/65/64 are pin-compatible to the 100-pin LPC236x ARM7-based microcontroller series.2.FeaturesI ARM Cortex-M3 processor, running at frequencies of up to 100 MHz. A Memory Protection Unit (MPU) supporting eight regions is included.I ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).I Up to 512kB on-chip ﬂash programming memory.Enhanced ﬂash memory accelerator enables high-speed 100 MHz operation with zero wait states.I In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.I On-chip SRAM includes:N 32/16kB of SRAM on the CPU with local code/data bus for high-performance CPU access.N Two/one 16 kB SRAM blocks with separate access paths for higher throughput.These SRAM blocks may be used for Ethernet (LPC1768/66/64 only), USB, and DMA memory, as well as for general purpose CPU instruction and data storage.LPC1768/66/65/6432-bit ARM Cortex-M3microcontroller;up to 512kB ﬂash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CANRev. 02 — 11 February 2009Objective data sheetI Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayermatrix that can be used with the SSP, I2S-bus, UART, the Analog-to-Digital andDigital-to-Analog converter peripherals, timer match signals, and formemory-to-memory transfers.I Multilayer AHB matrix interconnect provides a separate bus for each AHB master.AHBmasters include the CPU, General Purpose DMA controller, Ethernet MAC(LPC1768/66/64 only), and the USB interface. This interconnect providescommunication with no arbitration delays.I Split APB bus allows high throughput with few stalls between the CPU and DMA.I Serial interfaces:N Ethernet MAC with RMII interface and dedicated DMA controller (LPC1768/66/64 only).N USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device,Host,and OTG functions.The LPC1764includes a device controller only.N Four UARTs with fractional baud rate generation,internal FIFO,DMA support,and RS-485 support. One UART has modem control I/O, and one UART has IrDAsupport.N CAN 2.0B controller with two channels.N SPI controller with synchronous, serial, full duplex communication and programmable data length.N T wo SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller.N T wo I2C-bus interfaces supporting fast mode with a data rate of 400 kbits/s with multiple address recognition and monitor mode.N One I2C-bus interface supporting full I2C-bus speciﬁcation and fast mode plus witha data rate of 1 Mbit/s with multiple address recognition and monitor mode.N On the LPC1768/66/65only,I2S(Inter-IC Sound)interface for digital audio input or output, with fractional rate control. The I2S-bus interface can be used with theGPDMA. The I2S-bus interface supports 3-wire and 4-wire data transmit andreceive as well as master clock input/output.I Other peripherals:N70General Purpose I/O(GPIO)pins with conﬁgurable pull-up/down resistors and a new, conﬁgurable open-drain operating mode.N12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins, conversion rates up to1MHz,and multiple result registers.The12-bit ADC can be used with the GPDMA controller.N10-bit Digital-to-Analog Converter(DAC)with dedicated conversion timer and DMA support (LPC1768/66/65 only).N Four general purpose timers/counters, with a total of eight capture inputs and ten compare outputs. Each timer block has an external count input and DMA support.N One motor control PWM with support for three-phase motor control.N Quadrature encoder interface that can monitor one external quadrature encoder.N One standard PWM/timer block with external count input.N RTC with a separate power domain and dedicated RTC oscillator. The RTC block includes 64 bytes of battery-powered backup registers.N Watchdog Timer (WDT) resets the microcontroller within a reasonable amount of time if it enters an erroneous state.N System tick timer, including an external clock input option.N Repetitive interrupt timer provides programmable and repeating timed interrupts.N Each peripheral has its own clock divider for further power savings.I Standard JT AG test/debug interface for compatibility with existing tools. Serial WireDebug and Serial Wire Trace Port options.I Emulation trace module enables non-intrusive, high-speed real-time tracing ofinstruction execution.I Integrated PMU(Power Management Unit)automatically adjusts internal regulators tominimize power consumption during Sleep, Deep sleep, Power-down, and Deeppower-down modes.I Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.I Single 3.3V power supply (2.4V to 3.6V).I Four external interrupt inputs conﬁgurable as edge/level sensitive. All pins on PORT0and PORT2 can be used as edge sensitive interrupt sources.I Non-maskable Interrupt (NMI) input.I Clock output function that can reﬂect the main oscillator clock, IRC clock, RTC clock,CPU clock, and the USB clock.I The Wakeup Interrupt Controller (WIC) allows the CPU to automatically wake up fromany priority interrupt that can occur while the clocks are stopped in deep sleep,Power-down, and Deep power-down modes.I Processor wake-up from Power-down mode via interrupts from various peripherals.I Brownout detect with separate threshold for interrupt and forced reset.I Power-On Reset (POR).I Crystal oscillator with an operating range of 1MHz to 25MHz.I4MHz internal RC oscillator trimmed to1%accuracy that can optionally be used as a system clock.I PLL allows CPU operation up to the maximum CPU rate without the need for ahigh-frequency crystal. May be run from the main oscillator, the internal RC oscillator,or the RTC oscillator.I USB PLL for added ﬂexibility.I Code Read Protection (CRP) with different security levels.I Available as 100-pin LQFP package (14× 14× 1.4 mm).3.ApplicationsI eMeteringI LightingI Industrial networkingI Alarm systemsI White goodsI Motor control4.Ordering information4.1Ordering optionsTable 1.Ordering informationType numberPackage NameDescriptionVersion LPC1768FBD100LQFP100plastic low proﬁle quad ﬂat package; 100 leads; body 14× 14× 1.4 mm SOT407-1LPC1766FBD100LQFP100plastic low proﬁle quad ﬂat package; 100 leads; body 14× 14× 1.4 mm SOT407-1LPC1765FBD100LQFP100plastic low proﬁle quad ﬂat package; 100 leads; body 14× 14× 1.4 mm SOT407-1LPC1764FBD100LQFP100plastic low proﬁle quad ﬂat package; 100 leads; body 14× 14× 1.4 mmSOT407-1Table 2.Ordering optionsType number Flash Total SRAM Ethernet USB CAN I 2S DAC Package Sampling LPC1768FBD100512 kB 64 kB yes Device/Host/OTG 2yes yes 100 pins Q2 2009LPC1766FBD100256 kB 64 kB yes Device/Host/OTG 2yes yes 100 pins Q1 2009LPC1765FBD100256 kB 64 kB no Device/Host/OTG 2yes yes 100 pins Q1 2009LPC1764FBD100128 kB32 kByesDevice only2nono100 pinsQ1 20095.Block diagramGrey-shaded blocks represent peripherals with connection to the GPDMA.Fig 1.Block diagramSRAM 32/64 kBARM CORTEX-M3TEST/DEBUG INTERFACE E M U L A T I O N T R A C E M O D U L EFLASHACCELERATOR FLASH 512/256/128 kBDMACONTROLLERETHERNET CONTROLLER WITH DMA (2)USB HOST/DEVICE/OTG CONTROLLER WITH DMA (3)I-code bus D-code bus system busAHB TO APB BRIDGE 0HIGH-SPEEDGPIOAHB TO APB BRIDGE 1CLOCK GENERATION,POWER CONTROL,SYSTEM FUNCTIONSXTAL1XTAL2RESETclocks and controls JT AG interfacedebug portUSB PHYSSP0UART2/3I2S (1)I2C2RI TIMER TIMER2/3EXTERNAL INTERRUPTS SYSTEM CONTROL MOTOR CONTROL PWMQUADRATURE ENCODERSSP1UART0/1CAN1/2I2C0/1SPI0TIMER 0/1WDTPWM112-bit ADC PIN CONNECTGPIO INTERRUPT CONTROLRTCBACKUP REGISTERS 32 kHz OSCILLATORAPB slave group 1APB slave group 0DAC (1)RTC POWER DOMAINLPC1768/66/65/64mastermastermaster 002aad944slaveslave slaveslaveslaveROMslaveMULTILAYER AHB MATRIXP0 to P4SDA2SCL2SCK0SSEL0MISO0MOSI0SCK1SSEL1MISO1MOSI1RXD2/3TXD2/3PHA, PHB INDEXEINT[3:0]AOUT MC0A/B MC1A/B MC2A/B MCFB1/2MCABORT 4 × MAT22 × MAT32 × CAP22 × CAP33 × I2SRX 3 × I2STX TX_MCLK RX_MCLK RTCX1RTCX2VBATPWM1[7:0]2 × MAT0/12 × CAP0/1RD1/2TD1/2SDA0/1SCL0/1AD0[7:0]SCK/SSEL MOSI/MISO 8 × UART1RXD0/TXD0P0, P2PCAP1[1:0]RMII pins USB pinsCLKOUTM P U(1)LPC1768/66/65 only (2)LPC1768/66/64 only(3)LPC1764 USB device only6.Pinning information6.1Pinning6.2Pin descriptionFig 2.Pin conﬁguration LQFP100 packageLPC176xFBD1007526501007651125002aad945Table 3.Pin descriptionSymbol PinType DescriptionP0[0] to P0[31]I/OPort 0:Port 0is a 32-bit I/O port with individual direction controls for each bit.The operation of port 0pins depends upon the pin function selected via the pin connect block. Pins 12, 13, 14, and 31 of this port are not available.P0[0]/RD1/TXD3/SDA146[1]I/O P0[0] —General purpose digital input/output pin.I RD1 —CAN1 receiver input.O TXD3 —Transmitter output for UART3.I/OSDA1 —I 2C1 data input/output (this is not an I 2C-bus compliant open-drain pin).P0[1]/TD1/RXD3/SCL147[1]I/O P0[1] —General purpose digital input/output pin.O TD1 —CAN1 transmitter output.I RXD3 —Receiver input for UART3.I/OSCL1 —I 2C1 clock input/output (this is not an I 2C-bus compliant open-drain pin).P0[2]/TXD0/AD0[7]98[2]I/O P0[2] —General purpose digital input/output pin.O TXD0 —Transmitter output for UART0.IAD0[7] —A/D converter 0, input 7.P0[3]/RXD0/AD0[6]99[2]I/O P0[3] —General purpose digital input/output pin.I RXD0 —Receiver input for UART0.IAD0[6] —A/D converter 0, input 6.P0[4]/I2SRX_CLK/RD2/CAP2[0]81[1]I/O P0[4] —General purpose digital input/output pin.I/OI2SRX_CLK —Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I 2S-bus speciﬁcation .(LPC1768/66/65 only).I RD2 —CAN2 receiver input.ICAP2[0] —Capture input for Timer 2, channel 0.P0[5]/I2SRX_WS/ TD2/CAP2[1]80[1]I/O P0[5] —General purpose digital input/output pin.I/O I2SRX_WS —Receive Word Select.It is driven by the master and received by the slave.Corresponds to the signal WS in the I2S-bus speciﬁcation.(LPC1768/66/65only).O TD2 —CAN2 transmitter output.I CAP2[1] —Capture input for Timer2, channel 1.P0[6]/I2SRX_SDA/ SSEL1/MA T2[0]79[1]I/O P0[6] —General purpose digital input/output pin.I/O I2SRX_SDA —Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus speciﬁcation.(LPC1768/66/65 only).I/O SSEL1 —Slave Select for SSP1.O MAT2[0] —Match output for Timer2, channel 0.P0[7]/I2STX_CLK/ SCK1/MA T2[1]78[1]I/O P0[7] —General purpose digital input/output pin.I/O I2STX_CLK —Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus speciﬁcation.(LPC1768/66/65 only)I/O SCK1 —Serial Clock for SSP1.O MAT2[1] —Match output for Timer2, channel 1.P0[8]/I2STX_WS/ MISO1/MA T2[2]77[1]I/O P0[8] —General purpose digital input/output pin.I/O I2STX_WS —Transmit Word Select.It is driven by the master and received by the slave.Corresponds to the signal WS in the I2S-bus speciﬁcation.(LPC1768/66/65only).I/O MISO1 —Master In Slave Out for SSP1.O MAT2[2] —Match output for Timer2, channel 2.P0[9]/I2STX_SDA/ MOSI1/MA T2[3]76[1]I/O P0[9] —General purpose digital input/output pin.I/O I2STX_SDA —Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus speciﬁcation.(LPC1768/66/65 only).I/O MOSI1 —Master Out Slave In for SSP1.O MAT2[3] —Match output for Timer2, channel 3.P0[10]/TXD2/ SDA2/MA T3[0]48[1]I/O P0[10] —General purpose digital input/output pin.O TXD2 —Transmitter output for UART2.I/O SDA2 —I2C2 data input/output (this is not an open-drain pin).O MAT3[0] —Match output for Timer3, channel 0.P0[11]/RXD2/ SCL2/MAT3[1]49[1]I/O P0[11] —General purpose digital input/output pin.I RXD2 —Receiver input for UART2.I/O SCL2 —I2C2 clock input/output (this is not an open-drain pin).O MAT3[1] —Match output for Timer3, channel 1.P0[15]/TXD1/ SCK0/SCK 62[1]I/O P0[15] —General purpose digital input/output pin.O TXD1 —Transmitter output for UART1.I/O SCK0 —Serial clock for SSP0.I/O SCK —Serial clock for SPI.Table 3.Pin description …continuedSymbol Pin Type DescriptionP0[16]/RXD1/ SSEL0/SSEL 63[1]I/O P0[16] —General purpose digital input/output pin.I RXD1 —Receiver input for UART1.I/O SSEL0 —Slave Select for SSP0.I/O SSEL —Slave Select for SPI.P0[17]/CTS1/ MISO0/MISO 61[1]I/O P0[17] —General purpose digital input/output pin.I CTS1 —Clear to Send input for UART1.I/O MISO0 —Master In Slave Out for SSP0.I/O MISO —Master In Slave Out for SPI.P0[18]/DCD1/ MOSI0/MOSI 60[1]I/O P0[18] —General purpose digital input/output pin.I DCD1 —Data Carrier Detect input for UART1.I/O MOSI0 —Master Out Slave In for SSP0.I/O MOSI —Master Out Slave In for SPI.P0[19]/DSR1/ SDA159[1]I/O P0[19] —General purpose digital input/output pin.I DSR1 —Data Set Ready input for UART1.I/O SDA1 —I2C1 data input/output (this is not an I2C-bus compliant open-drain pin).P0[20]/DTR1/SCL158[1]I/O P0[20] —General purpose digital input/output pin.O DTR1 —Data Terminal Ready output for UART1.I/O SCL1 —I2C1 clock input/output (this is not an I2C-bus compliant open-drain pin). P0[21]/RI1/RD157[1]I/O P0[21] —General purpose digital input/output pin.I RI1 —Ring Indicator input for UART1.I RD1 —CAN1 receiver input.P0[22]/RTS1/TD156[1]I/O P0[22] —General purpose digital input/output pin.O RTS1 —Request to Send output for UART1.O TD1 —CAN1 transmitter output.P0[23]/AD0[0]/ I2SRX_CLK/ CAP3[0]9[2]I/O P0[23] —General purpose digital input/output pin.I AD0[0] —A/D converter 0, input 0.I/O I2SRX_CLK —Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus speciﬁcation.(LPC1768/66/65 only).I CAP3[0] —Capture input for Timer3, channel 0.P0[24]/AD0[1]/ I2SRX_WS/ CAP3[1]8[2]I/O P0[24] —General purpose digital input/output pin.I AD0[1] —A/D converter 0, input 1.I/O I2SRX_WS —Receive Word Select.It is driven by the master and received by the slave.Corresponds to the signal WS in the I2S-bus speciﬁcation.(LPC1768/66/65only).I CAP3[1] —Capture input for Timer3, channel 1.P0[25]/AD0[2]/ I2SRX_SDA/ TXD37[2]I/O P0[25] —General purpose digital input/output pin.I AD0[2] —A/D converter 0, input 2.I/O I2SRX_SDA —Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus speciﬁcation.(LPC1768/66/65 only).O TXD3 —Transmitter output for UART3.Table 3.Pin description …continuedSymbol Pin Type DescriptionP0[26]/AD0[3]/ AOUT/RXD36[3]I/O P0[26] —General purpose digital input/output pin.I AD0[3] —A/D converter 0, input 3.O AOUT —DAC output (LPC1768/66/65 only).I RXD3 —Receiver input for UART3.P0[27]/SDA0/ USB_SDA 25[4]I/O P0[27] —General purpose digital input/output pin. Output is open-drain.I/O SDA0 —I2C0 data input/output. Open-drain output (for I2C-bus compliance).I/O USB_SDA —USB port I2C serial data (OTG transceiver, LPC1768/66/65 only).(LPC1768/66/65 only).P0[28]/SCL0/ USB_SCL 24[4]I/O P0[28] —General purpose digital input/output pin. Output is open-drain.I/O SCL0 —I2C0 clock input/output. Open-drain output (for I2C-bus compliance).I/O USB_SCL —USB port I2C serial clock (OTG transceiver, LPC1768/66/65 only).P0[29]/USB_D+29[5]I/O P0[29] —General purpose digital input/output pin.I/O USB_D+ —USB bidirectional D+ line.P0[30]/USB_D−30[5]I/O P0[30] —General purpose digital input/output pin.I/O USB_D− —USB bidirectional D− line.P1[0] to P1[31]I/O Port1:Port1is a32-bit I/O port with individual direction controls for each bit.Theoperation of port1pins depends upon the pin function selected via the pin connectblock. Pins 2, 3, 5, 6, 7, 11, 12, and 13 of this port are not available.P1[0]/ ENET_TXD095[1]I/O P1[0] —General purpose digital input/output pin.O ENET_TXD0 —Ethernet transmit data 0. (LPC1768/66/64 only).P1[1]/ ENET_TXD194[1]I/O P1[1] —General purpose digital input/output pin.O ENET_TXD1 —Ethernet transmit data 1. (LPC1768/66/64 only).P1[4]/ENET_TX_EN 93[1]I/O P1[4] —General purpose digital input/output pin.O ENET_TX_EN —Ethernet transmit data enable. (LPC1768/66/64 only).P1[8]/ ENET_CRS 92[1]I/O P1[8] —General purpose digital input/output pin.I ENET_CRS —Ethernet carrier sense. (LPC1768/66/64 only).P1[9]/ENET_RXD091[1]I/O P1[9] —General purpose digital input/output pin.I ENET_RXD0 —Ethernet receive data. (LPC1768/66/64 only).P1[10]/ ENET_RXD190[1]I/O P1[10] —General purpose digital input/output pin.I ENET_RXD1 —Ethernet receive data. (LPC1768/66/64 only).P1[14]/ENET_RX_ER 89[1]I/O P1[14] —General purpose digital input/output pin.I ENET_RX_ER —Ethernet receive error. (LPC1768/66/64 only).P1[15]/ENET_REF_CLK 88[1]I/O P1[15] —General purpose digital input/output pin.I ENET_REF_CLK —Ethernet reference clock. (LPC1768/66/64 only).P1[16]/ ENET_MDC 87[1]I/O P1[16] —General purpose digital input/output pin.O ENET_MDC —Ethernet MIIM clock (LPC1768/66/64 only).P1[17]/ ENET_MDIO 86[1]I/O P1[17] —General purpose digital input/output pin.I/O ENET_MDIO —Ethernet MIIM data input and output. (LPC1768/66/64 only).Table 3.Pin description …continuedSymbol Pin Type DescriptionP1[18]/USB_UP_LED/ PWM1[1]/ CAP1[0]32[1]I/O P1[18] —General purpose digital input/output pin.O USB_UP_LED —USB GoodLink LED indicator. It is LOW when device is conﬁgured (non-control endpoints enabled). It is HIGH when the device is notconﬁgured or during global suspend.O PWM1[1] —Pulse Width Modulator 1, channel 1 output.I CAP1[0] —Capture input for Timer1, channel 0.P1[19]/MC0A/ USB_PPWR CAP1[1]33[1]I/O P1[19] —General purpose digital input/output pin.O MC0A —Motor control PWM channel 0, output A.O USB_PPWR —Port Power enable signal for USB port (LPC1768/66/65 only).I CAP1[1] —Capture input for Timer1, channel 1.P1[20]/MCFB0/ PWM1[2]/SCK034[1]I/O P1[20] —General purpose digital input/output pin.I MCFB0 —Motor control PWM channel 0, feedback input. Also QuadratureEncoder Interface PHA input.O PWM1[2] —Pulse Width Modulator 1, channel 2 output.I/O SCK0 —Serial clock for SSP0.P1[21]/MCABORT/ PWM1[3]/SSEL035[1]I/O P1[21] —General purpose digital input/output pin.O MCABORT —Motor control PWM, emergency abort.O PWM1[3] —Pulse Width Modulator 1, channel 3 output.I/O SSEL0 —Slave Select for SSP0.P1[22]/MC0B/ USB_PWRD/ MA T1[0]36[1]I/O P1[22] —General purpose digital input/output pin.O MC0B —Motor control PWM channel 0, output B.I USB_PWRD —Power Status for USB port (host power switch, LPC1768/66/65only).O MAT1[0] —Match output for Timer1, channel 0.P1[23]/MCFB1/ PWM1[4]/MISO037[1]I/O P1[23] —General purpose digital input/output pin.I MCFB1 —Motor control PWM channel 1, feedback input. Also QuadratureEncoder Interface PHB input.O PWM1[4] —Pulse Width Modulator 1, channel 4 output.I/O MISO0 —Master In Slave Out for SSP0.P1[24]/MCFB2/ PWM1[5]/MOSI038[1]I/O P1[24] —General purpose digital input/output pin.I MCFB2 —Motor control PWM channel 2, feedback input. Also QuadratureEncoder Interface INDEX input.O PWM1[5] —Pulse Width Modulator 1, channel 5 output.I/O MOSI0 —Master Out Slave in for SSP0.P1[25]/MC1A/ MA T1[1]39[1]I/O P1[25] —General purpose digital input/output pin.O MC1A —Motor control PWM channel 1, output A.O MAT1[1] —Match output for Timer1, channel 1.P1[26]/MC1B/ PWM1[6]/CAP0[0]40[1]I/O P1[26] —General purpose digital input/output pin.O MC1B —Motor control PWM channel 1, output B.O PWM1[6] —Pulse Width Modulator 1, channel 6 output.I CAP0[0] —Capture input for Timer0, channel 0.Table 3.Pin description …continuedSymbol Pin Type DescriptionP1[27]/CLKOUT /USB_OVRCR/ CAP0[1]43[1]I/O P1[27] —General purpose digital input/output pin.O CLKOUT —Clock output pin.I USB_OVRCR —USB port Over-Current status. (LPC1768/66/65 only).I CAP0[1] —Capture input for Timer0, channel 1.P1[28]/MC2A 1[0]/MA T0[0]44[1]I/O P1[28] —General purpose digital input/output pin.O MC2A —Motor control PWM channel 2, output A.I PCAP1[0] —Capture input for PWM1, channel 0.O MAT0[0] —Match output for Timer0, channel 0.P1[29]/MC2B/ PCAP1[1]/ MA T0[1]45[1]I/O P1[29] —General purpose digital input/output pin.O MC2B —Motor control PWM channel 2, output B.I PCAP1[1] —Capture input for PWM1, channel 1.O MAT0[1] —Match output for Timer0, channel 0.P1[30]/V BUS/ AD0[4]21[2]I/O P1[30] —General purpose digital input/output pin.I V BUS —Monitors the presence of USB bus power.Note: This signal must be HIGH for USB reset to occur.I AD0[4] —A/D converter 0, input 4.P1[31]/SCK1/ AD0[5]20[2]I/O P1[31] —General purpose digital input/output pin.I/O SCK1 —Serial Clock for SSP1.I AD0[5] —A/D converter 0, input 5.P2[0] to P2[31]I/O Port2:Port2is a32-bit I/O port with individual direction controls for each bit.Theoperation of port2pins depends upon the pin function selected via the pin connectblock. Pins 14 through 31 of this port are not available.P2[0]/PWM1[1]/ TXD175[1]I/O P2[0] —General purpose digital input/output pin.O PWM1[1] —Pulse Width Modulator 1, channel 1 output.O TXD1 —Transmitter output for UART1.P2[1]/PWM1[2]/ RXD174[1]I/O P2[1] —General purpose digital input/output pin.O PWM1[2] —Pulse Width Modulator 1, channel 2 output.I RXD1 —Receiver input for UART1.P2[2]/PWM1[3]/ CTS1/ TRACEDA T A[3]73[1]I/O P2[2] —General purpose digital input/output pin.O PWM1[3] —Pulse Width Modulator 1, channel 3 output.I CTS1 —Clear to Send input for UART1.O TRACEDATA[3] —T race data, bit 3.P2[3]/PWM1[4]/ DCD1/ TRACEDA T A[2]70[1]I/O P2[3] —General purpose digital input/output pin.O PWM1[4] —Pulse Width Modulator 1, channel 4 output.I DCD1 —Data Carrier Detect input for UART1.O TRACEDATA[2] —T race data, bit 2.P2[4]/PWM1[5]/ DSR1/ TRACEDA T A[1]69[1]I/O P2[4] —General purpose digital input/output pin.O PWM1[5] —Pulse Width Modulator 1, channel 5 output.I DSR1 —Data Set Ready input for UART1.O TRACEDATA[1] —T race data, bit 1.Table 3.Pin description …continuedSymbol Pin Type DescriptionP2[5]/PWM1[6]/ DTR1/ TRACEDA T A[0]68[1]I/O P2[5] —General purpose digital input/output pin.O PWM1[6] —Pulse Width Modulator 1, channel 6 output.O DTR1 —Data Terminal Ready output for UART1.O TRACEDATA[0] —T race data, bit 0.P2[6]/PCAP1[0]/ RI1/TRACECLK 67[1]I/O P2[6] —General purpose digital input/output pin.I PCAP1[0] —Capture input for PWM1, channel 0.I RI1 —Ring Indicator input for UART1.O TRACECLK —Trace Clock.P2[7]/RD2/ RTS166[1]I/O P2[7] —General purpose digital input/output pin.I RD2 —CAN2 receiver input.O RTS1 —Request to Send output for UART1.P2[8]/TD2/ TXD265[1]I/O P2[8] —General purpose digital input/output pin.O TD2 —CAN2 transmitter output.O TXD2 —Transmitter output for UART2.P2[9]/USB_CONNECT/ RXD264[1]I/O P2[9] —General purpose digital input/output pin.O USB_CONNECT —Signal used to switch an external 1.5 kΩ resistor under software control. Used with the SoftConnect USB feature.I RXD2 —Receiver input for UART2.P2[10]/EINT0/NMI53[6]I/O P2[10] —General purpose digital input/output pin.Note: LOW on this pin while RESET is LOW forces on-chip bootloader to takeover control of the part after a reset.I EINT0 —External interrupt 0 input.I NMI —Non-maskable interrupt input.P2[11]/EINT1/ I2STX_CLK 52[6]I/O P2[11] —General purpose digital input/output pin.I EINT1 —External interrupt 1 input.I/O I2STX_CLK —Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus speciﬁcation.(LPC1768/66/65 only).P2[12]/EINT2/ I2STX_WS 51[6]I/O P2[12] —General purpose digital input/output pin.I EINT2 —External interrupt 2 input.I/O I2STX_WS —Transmit Word Select.It is driven by the master and received by the slave.Corresponds to the signal WS in the I2S-bus speciﬁcation.(LPC1768/66/65only).P2[13]/EINT3/ I2STX_SDA 50[6]I/O P2[13] —General purpose digital input/output pin.I EINT3 —External interrupt 3 input.I/O I2STX_SDA —Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus speciﬁcation.(LPC1768/66/65 only).P3[0] to P3[31]I/O Port3:Port3is a32-bit I/O port with individual direction controls for each bit.Theoperation of port3pins depends upon the pin function selected via the pin connectblock. Pins 0 through 24, and 27 through 31 of this port are not available.P3[25]/MA T0[0]/ PWM1[2]27[1]I/O P3[25] —General purpose digital input/output pin.O MAT0[0] —Match output for Timer0, channel 0.O PWM1[2] —Pulse Width Modulator 1, output 2.Table 3.Pin description …continuedSymbol Pin Type DescriptionP3[26]/STCLK/MA T0[1]/PWM1[3]26[1]I/OP3[26] —General purpose digital input/output pin.I STCLK —System tick timer clock input.OMAT0[1] —Match output for Timer 0, channel 1.O PWM1[3] —Pulse Width Modulator 1, output 3.P4[0] to P4[31]I/O Port 4:Port 4is a 32-bit I/O port with individual direction controls for each bit.The operation of port 4pins depends upon the pin function selected via the pin connectblock. Pins 0 through 27, 30, and 31 of this port are not available.P4[28]/RX_MCLK/MA T2[0]/TXD382[1]I/O P4[28] —General purpose digital input/output pin.I RX_MCLK —I 2S receive master clock. (LPC1768/66/65 only).O MAT2[0] —Match output for Timer 2, channel 0.O TXD3 —Transmitter output for UART3.P4[29]/TX_MCLK/MA T2[1]/RXD385[1]I/O P4[29] —General purpose digital input/output pin.I TX_MCLK —I 2S transmit master clock. (LPC1768/66/65 only).O MAT2[1] —Match output for Timer 2, channel 1.I RXD3 —Receiver input for UART3.TDO/SWO 1[1]O TDO —T est Data out for JTAG interface.O SWO —Serial wire trace output.TDI 2[1]I TDI —T est Data in for JTAG interface.TMS/SWDIO 3[1]I TMS —T est Mode Select for JT AG interface.I/O SWDIO —Serial wire debug data input/output.TRST 4[1]I TRST —Test Reset for JTAG interface.TCK/SWDCLK 5[1]I TCK —T est Clock for JTAG interface.I SWDCLK —Serial wire clock.RTCK 100[1]I/O RTCK —JTAG interface control signal.RSTOUT 14O RSTOUT —This is a 3.3 V pin. LOW on this pin indicates LPC1768/66/65/64being in Reset state.RESET 17[7]I External reset input: A LOW on this pin resets the device, causing I/O ports andperipherals to take on their default states, and processor execution to begin ataddress 0. TTL with hysteresis, 5V tolerant.XT AL122[8]I Input to the oscillator circuit and internal clock generator circuits.XTAL223[8]O Output from the oscillator ampliﬁer.RTCX116[8]I Input to the RTC oscillator circuit.RTCX218[8]O Output from the RTC oscillator circuit.V SS 31, 41,55, 72,97, 83[8]I ground: 0V reference.V SSA 11[8]I analog ground:0V reference.This should nominally be the same voltage as V SS ,but should be isolated to minimize noise and error.V DD(3V3)28, 54,71, 96[8]I 3.3V supply voltage: This is the power supply voltage for the I/O ports.V DD(REG)(3V3)42, 84[8]I 3.3V voltage regulator supply voltage:This is the supply voltage for the on-chipvoltage regulator only.Table 3.Pin description …continued Symbol PinType Description。

LPC1764_1765_1766_1767_1768数据手册V02.07

D R A F TD R A F TD R A F T D R D R A F TD R A F T D RA F T D R A F D R A F TD R A F TDRA F T D R AF T D R A F T DD R A F TD R AF T D R A F T D RA F T D RA F T DRA F T D R A1.General descriptionThe LPC1768/67/66/65/64 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.The LPC1768/67/66/65/64 operate at CPU frequencies of up to 100 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.The peripheral complement of the LPC1768/67/66/65/64 includes up to 512 kB of flash memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG interface, 8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers, SPI interface, 3 I 2C-bus interfaces, 2-input plus 2-output I 2S-bus interface, 8-channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, four general purpose timers, 6-output general purpose PWM, ultra-low power Real-Time Clock (RTC) with separate battery supply, and up to 70 general purpose I/O pins.The LPC1768/67/66/65/64 are pin-compatible to the 100-pin LPC236x ARM7-based microcontroller series.2.FeaturesARM Cortex-M3 processor, running at frequencies of up to 100 MHz. A MemoryProtection Unit (MPU) supporting eight regions is included.ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).Up to 512 kB on-chip flash programming memory. Enhanced flash memory acceleratorenables high-speed 100 MHz operation with zero wait states.In-System Programming (ISP) and In-Application Programming (IAP) via on-chipbootloader software. On-chip SRAM includes:32/16 kB of SRAM on the CPU with local code/data bus for high-performance CPU access.Two/one 16 kB SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as for general purpose CPU instruction and data storage.LPC1768/67/66/65/6432-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CANRev. 02.07 — 30 October 2009Product data sheetA F T D R A F AF TDRAF TD R A F T D AF TDRA F T D R A F T DRA F T D R A Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayermatrix that can be used with SSP , I 2S-bus, UART, Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers.Multilayer AHB matrix interconnect provides a separate bus for each AHB master.AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, and the USB interface. This interconnect provides communication with no arbitration delays.Split APB bus allows high throughput with few stalls between the CPU and DMA. Serial interfaces:Ethernet MAC with RMII interface and dedicated DMA controller (LPC1768/67/66/64 only).USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions (LPC1768/66/65 only). The LPC1764 includes a device controller only.Four UARTs with fractional baud rate generation, internal FIFO, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support, and one UART has IrDA support.CAN 2.0B controller with two channels.SPI controller with synchronous, serial, full duplex communication and programmable data length.Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller.Three enhanced I 2C bus interfaces, one with an open-drain output supporting full I 2C specification and Fast mode plus with data rates of 1Mbit/s, two with standard port pins. Enhancements include multiple address recognition and monitor mode. On the LPC1768/67/66/65 only, I 2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I 2S-bus interface can be used with the GPDMA. The I 2S-bus interface supports 3-wire and 4-wire data transmit and receive as well as master clock input/output.Other peripherals:70 (100 pin package) General Purpose I/O (GPIO) pins with configurablepull-up/down resistors. All GPIOs support a new, configurable open-drain operating mode. The GPIO block is accessed through the AHB mulitlayer bus for fast access and located in memory such that it supports Cortex-M3 bit banding and use by the General Purpose DMA Controller.12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins, conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller.10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support (LPC1768/67/66/65 only).Four general purpose timers/counters, with a total of eight capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests.One motor control PWM with support for three-phase motor control.Quadrature encoder interface that can monitor one external quadrature encoder. One standard PWM/timer block with external count input.A F T D R A F AF TDRAF TD R A F T D AF TDRA F T D R A F T DRA F T D R A RTC with a separate power domain and dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers.Watchdog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock.ARM Cortex-M3 system tick timer, including an external clock input option.Repetitive interrupt timer provides programmable and repeating timed interrupts. Each peripheral has its own clock divider for further power savings.Standard JTAG test/debug interface for compatibility with existing tools. Serial Wire Debug and Serial Wire Trace Port options.Emulation trace module enables non-intrusive, high-speed real-time tracing of instruction execution.Integrated PMU (Power Management Unit) automatically adjusts internal regulators to minimize power consumption during Sleep, Deep sleep, Power-down, and Deep power-down modes.Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down. Single 3.3 V power supply (2.4 V to 3.6 V).Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0 and PORT2 can be used as edge sensitive interrupt sources. Non-maskable Interrupt (NMI) input.Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock, CPU clock, and the USB clock.The Wakeup Interrupt Controller (WIC) allows the CPU to automatically wake up from any priority interrupt that can occur while the clocks are stopped in deep sleep, Power-down, and Deep power-down modes.Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt, CAN bus activity, PORT0/2 pin interrupt, and NMI). Brownout detect with separate threshold for interrupt and forced reset. Power-On Reset (POR).Crystal oscillator with an operating range of 1 MHz to 25 MHz.4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock.PLL allows CPU operation up to the maximum CPU rate without the need for ahigh-frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator.USB PLL for added flexibility.Code Read Protection (CRP) with different security levels.Available as 100-pin LQFP package (14 × 14 × 1.4 mm).3.ApplicationseMetering Alarm systems LightingWhite goods Industrial networking Motor controlAF T DR A F AF TDRA F T D R A F TDAF TDR A F T D RA F TD R A F TD R A4.Ordering information4.1Ordering optionsTable 1.Ordering informationType numberPackage NameDescriptionVersionLPC1768FBD100LQFP100plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1LPC1767FBD100LQFP100plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1LPC1766FBD100LQFP100plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1LPC1765FBD100LQFP100plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1LPC1764FBD100LQFP100plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mmSOT407-1Table 2.Ordering optionsType number Flash Total SRAM Ethernet USBCAN I 2S DAC Package LPC1768FBD100512 kB 64 kB yes Device/Host/OTG 2yes yes 100 pins LPC1767FBD100512 kB 64 kB yes nono yes yes 100 pins LPC1766FBD100256 kB 64 kB yes Device/Host/OTG 2yes yes 100 pins LPC1765FBD100256 kB 64 kB no Device/Host/OTG 2yes yes 100 pins LPC1764FBD100128 kB32 kByesDevice only2nono100 pinsAF T DR A F AF TDRA F TA F TDAF TDR A F T T DRA5.Block diagramAF TDR A F AF TDRA F T D R A F T DAF TDR A F T D RA F TTD R A6.Pinning information6.1Pinning6.2Pin descriptionTable 3.Pin descriptionSymbol PinType DescriptionP0[0] to P0[31]I/OPort 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the pin connect block. Pins 12, 13, 14, and 31 of this port are not available.P0[0]/RD1/TXD3/ SDA146[1]I/O P0[0] — General purpose digital input/output pin.I RD1 — CAN1 receiver input. (LPC1768/66/65/64 only). O TXD3 — Transmitter output for UART3.I/OSDA1 — I 2C1 data input/output. (This is not an I 2C-bus compliant open-drain pin).P0[1]/TD1/RXD3/ SCL147[1]I/O P0[1] — General purpose digital input/output pin.O TD1 — CAN1 transmitter output. (LPC1768/66/65/64 only).I RXD3 — Receiver input for UART3.I/OSCL1 — I 2C1 clock input/output. (This is not an I 2C-bus compliant open-drain pin).P0[2]/TXD0/AD0[7]98[2]I/O P0[2] — General purpose digital input/output pin.O TXD0 — Transmitter output for UART0.IAD0[7] — A/D converter 0, input 7.P0[3]/RXD0/AD0[6]99[2]I/O P0[3] — General purpose digital input/output pin.I RXD0 — Receiver input for UART0.IAD0[6] — A/D converter 0, input 6.P0[4]/I2SRX_CLK/ RD2/CAP2[0]81[1]I/O P0[4] — General purpose digital input/output pin.I/OI2SRX_CLK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I 2S-bus specification . (LPC1768/67/66/65 only).I RD2 — CAN2 receiver input. (LPC1768/66/65/64 only). ICAP2[0] — Capture input for Timer 2, channel 0.AF TDR A F AF TDRA F TDRA F T D AF TDR A F T DR A F T D RAF T D R AP0[5]/I2SRX_WS/ TD2/CAP2[1]80[1]I/O P0[5] — General purpose digital input/output pin.I/OI2SRX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I 2S-bus specification . (LPC1768/67/66/65 only).O TD2 — CAN2 transmitter output. (LPC1768/66/65/64 only). ICAP2[1] — Capture input for Timer 2, channel 1.P0[6]/I2SRX_SDA/ SSEL1/MAT2[0]79[1]I/O P0[6] — General purpose digital input/output pin.I/OI2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I 2S-bus specification . (LPC1768/67/66/65 only).I/O SSEL1 — Slave Select for SSP1.OMAT2[0] — Match output for Timer 2, channel 0.P0[7]/I2STX_CLK/ SCK1/MAT2[1]78[1]I/O P0[7] — General purpose digital input/output pin.I/OI2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I 2S-bus specification . (LPC1768/67/66/65 only).I/O SCK1 — Serial Clock for SSP1.OMAT2[1] — Match output for Timer 2, channel 1.P0[8]/I2STX_WS/ MISO1/MAT2[2]77[1]I/O P0[8] — General purpose digital input/output pin.I/OI2STX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I 2S-bus specification . (LPC1768/67/66/65 only).I/O MISO1 — Master In Slave Out for SSP1.OMAT2[2] — Match output for Timer 2, channel 2.P0[9]/I2STX_SDA/ MOSI1/MAT2[3]76[1]I/O P0[9] — General purpose digital input/output pin.I/OI2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I 2S-bus specification . (LPC1768/67/66/65 only).I/O MOSI1 — Master Out Slave In for SSP1.OMAT2[3] — Match output for Timer 2, channel 3.P0[10]/TXD2/ SDA2/MAT3[0]48[1]I/O P0[10] — General purpose digital input/output pin.O TXD2 — Transmitter output for UART2.I/O SDA2 — I 2C2 data input/output (this is not an open-drain pin).OMAT3[0] — Match output for Timer 3, channel 0.P0[11]/RXD2/ SCL2/MAT3[1]49[1]I/O P0[11] — General purpose digital input/output pin.I RXD2 — Receiver input for UART2.I/O SCL2 — I 2C2 clock input/output (this is not an open-drain pin).OMAT3[1] — Match output for Timer 3, channel 1.P0[15]/TXD1/ SCK0/SCK62[1]I/O P0[15] — General purpose digital input/output pin.O TXD1 — Transmitter output for UART1.I/O SCK0 — Serial clock for SSP0.I/OSCK — Serial clock for SPI.Table 3.Pin description …continuedSymbolPin Type DescriptionAF TDR A F AF TDRA F TDRA F T D AF TDR A F T DR A F T D RAF T D R AP0[16]/RXD1/ SSEL0/SSEL63[1]I/O P0[16] — General purpose digital input/output pin.I RXD1 — Receiver input for UART1.I/O SSEL0 — Slave Select for SSP0.I/OSSEL — Slave Select for SPI.P0[17]/CTS1/ MISO0/MISO61[1]I/O P0[17] — General purpose digital input/output pin.I CTS1 — Clear to Send input for UART1.I/O MISO0 — Master In Slave Out for SSP0.I/OMISO — Master In Slave Out for SPI.P0[18]/DCD1/ MOSI0/MOSI60[1]I/O P0[18] — General purpose digital input/output pin.I DCD1 — Data Carrier Detect input for UART1.I/O MOSI0 — Master Out Slave In for SSP0.I/OMOSI — Master Out Slave In for SPI.P0[19]/DSR1/ SDA159[1]I/O P0[19] — General purpose digital input/output pin.I DSR1 — Data Set Ready input for UART1.I/O SDA1 — I 2C1 data input/output (this is not an I 2C-bus compliant open-drain pin).P0[20]/DTR1/SCL158[1]I/O P0[20] — General purpose digital input/output pin.O DTR1 — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal.I/OSCL1 — I 2C1 clock input/output (this is not an I 2C-bus compliant open-drain pin).P0[21]/RI1/RD157[1]I/O P0[21] — General purpose digital input/output pin.I RI1 — Ring Indicator input for UART1.IRD1 — CAN1 receiver input. (LPC1768/66/65/64 only).P0[22]/RTS1/TD156[1]I/O P0[22] — General purpose digital input/output pin.O RTS1 — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal.OTD1 — CAN1 transmitter output. (LPC1768/66/65/64 only). P0[23]/AD0[0]/ I2SRX_CLK/ CAP3[0]9[2]I/O P0[23] — General purpose digital input/output pin.I AD0[0] — A/D converter 0, input 0.I/OI2SRX_CLK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I 2S-bus specification . (LPC1768/67/66/65 only).ICAP3[0] — Capture input for Timer 3, channel 0.P0[24]/AD0[1]/ I2SRX_WS/ CAP3[1]8[2]I/O P0[24] — General purpose digital input/output pin.I AD0[1] — A/D converter 0, input 1.I/OI2SRX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I 2S-bus specification . (LPC1768/67/66/65 only).ICAP3[1] — Capture input for Timer 3, channel 1.Table 3.Pin description …continuedSymbolPin Type DescriptionAF TDR A F AF TDRA F TDRA F T D AF TDR A F T DR A F T D RAF T D R A P0[25]/AD0[2]/ I2SRX_SDA/ TXD37[2]I/O P0[25] — General purpose digital input/output pin.I AD0[2] — A/D converter 0, input 2.I/OI2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I 2S-bus specification . (LPC1768/67/66/65 only).OTXD3 — Transmitter output for UART3.P0[26]/AD0[3]/ AOUT/RXD36[3]I/O P0[26] — General purpose digital input/output pin.I AD0[3] — A/D converter 0, input 3.O AOUT — DAC output (LPC1768/67/66/65 only).IRXD3 — Receiver input for UART3.P0[27]/SDA0/ USB_SDA25[4]I/O P0[27] — General purpose digital input/output pin. Output is open-drain.I/O SDA0 — I 2C0 data input/output. Open-drain output (for I 2C-bus compliance).I/OUSB_SDA — USB port I 2C serial data (OTG transceiver, LPC1768/66/65 only). P0[28]/SCL0/ USB_SCL24[4]I/O P0[28] — General purpose digital input/output pin. Output is open-drain.I/O SCL0 — I 2C0 clock input/output. Open-drain output (for I 2C-bus compliance).I/OUSB_SCL — USB port I 2C serial clock (OTG transceiver, LPC1768/66/65 only).P0[29]/USB_D+29[5]I/O P0[29] — General purpose digital input/output pin.I/O USB_D+ — USB bidirectional D+ line. (LPC1768/66/65/64 only).P0[30]/USB_D −30[5]I/O P0[30] — General purpose digital input/output pin.I/O USB_D − — USB bidirectional D − line. (LPC1768/66/65/64 only).P1[0] to P1[31]I/OPort 1: Port 1 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block. Pins 2, 3, 5, 6, 7, 11, 12, and 13 of this port are not available.P1[0]/ENET_TXD095[1]I/O P1[0] — General purpose digital input/output pin.O ENET_TXD0 — Ethernet transmit data 0. (LPC1768/67/66/64 only).P1[1]/ENET_TXD194[1]I/O P1[1] — General purpose digital input/output pin.O ENET_TXD1 — Ethernet transmit data 1. (LPC1768/67/66/64 only).P1[4]/ENET_TX_EN 93[1]I/O P1[4] — General purpose digital input/output pin.O ENET_TX_EN — Ethernet transmit data enable. (LPC1768/67/66/64 only).P1[8]/ENET_CRS 92[1]I/O P1[8] — General purpose digital input/output pin.I ENET_CRS — Ethernet carrier sense. (LPC1768/67/66/64 only).P1[9]/ENET_RXD091[1]I/O P1[9] — General purpose digital input/output pin.I ENET_RXD0 — Ethernet receive data. (LPC1768/67/66/64 only).P1[10]/ENET_RXD190[1]I/O P1[10] — General purpose digital input/output pin.I ENET_RXD1 — Ethernet receive data. (LPC1768/67/66/64 only).P1[14]/ENET_RX_ER 89[1]I/O P1[14] — General purpose digital input/output pin.I ENET_RX_ER — Ethernet receive error. (LPC1768/67/66/64 only).P1[15]/ENET_REF_CLK 88[1]I/O P1[15] — General purpose digital input/output pin.I ENET_REF_CLK — Ethernet reference clock. (LPC1768/67/66/64 only).P1[16]/ENET_MDC87[1]I/O P1[16] — General purpose digital input/output pin.OENET_MDC — Ethernet MIIM clock (LPC1768/67/66/64 only).Table 3.Pin description …continuedSymbolPin Type DescriptionAF TDR A F AF TDRA F TDRA F T D AF TDR A F T DR A F T D RAF T D R A P1[17]/ENET_MDIO 86[1]I/O P1[17] — General purpose digital input/output pin.I/O ENET_MDIO — Ethernet MIIM data input and output. (LPC1768/67/66/64 only).P1[18]/USB_UP_LED/ PWM1[1]/ CAP1[0]32[1]I/O P1[18] — General purpose digital input/output pin.OUSB_UP_LED — USB GoodLink LED indicator. It is LOW when device is configured (non-control endpoints enabled). It is HIGH when the device is not configured or during global suspend. (LPC1768/66/65/64 only). O PWM1[1] — Pulse Width Modulator 1, channel 1 output.ICAP1[0] — Capture input for Timer 1, channel 0.P1[19]/MCOA0/ USB_PPWR CAP1[1]33[1]I/O P1[19] — General purpose digital input/output pin.O MCOA0 — Motor control PWM channel 0, output A.O USB_PPWR — Port Power enable signal for USB port. (LPC1768/66/65 only).ICAP1[1] — Capture input for Timer 1, channel 1.P1[20]/MCI0/ PWM1[2]/SCK034[1]I/O P1[20] — General purpose digital input/output pin.I MCI0 — Motor control PWM channel 0, input. Also Quadrature Encoder Interface PHA input.O PWM1[2] — Pulse Width Modulator 1, channel 2 output.I/OSCK0 — Serial clock for SSP0.P1[21]/MCABORT/PWM1[3]/ SSEL035[1]I/O P1[21] — General purpose digital input/output pin.O MCABORT — Motor control PWM, LOW-active fast abort.O PWM1[3] — Pulse Width Modulator 1, channel 3 output.I/OSSEL0 — Slave Select for SSP0.P1[22]/MCOB0/ USB_PWRD/ MAT1[0]36[1]I/O P1[22] — General purpose digital input/output pin.O MCOB0 — Motor control PWM channel 0, output B.I USB_PWRD — Power Status for USB port (host power switch, LPC1768/66/65 only).OMAT1[0] — Match output for Timer 1, channel 0.P1[23]/MCI1/ PWM1[4]/MISO037[1]I/O P1[23] — General purpose digital input/output pin.I MCI1 — Motor control PWM channel 1, input. Also Quadrature Encoder Interface PHB input.O PWM1[4] — Pulse Width Modulator 1, channel 4 output.I/OMISO0 — Master In Slave Out for SSP0.P1[24]/MCI2/ PWM1[5]/MOSI038[1]I/O P1[24] — General purpose digital input/output pin.I MCI2 — Motor control PWM channel 2, input. Also Quadrature Encoder Interface INDEX input.O PWM1[5] — Pulse Width Modulator 1, channel 5 output.I/OMOSI0 — Master Out Slave in for SSP0.P1[25]/MCOA1/ MAT1[1]39[1]I/O P1[25] — General purpose digital input/output pin.O MCOA1 — Motor control PWM channel 1, output A.OMAT1[1] — Match output for Timer 1, channel 1.Table 3.Pin description …continuedSymbolPin Type DescriptionAF TDR A F AF TDRA F TDRA F T D AF TDR A F T DR A F T D RAF T D R AP1[26]/MCOB1/ PWM1[6]/CAP0[0]40[1]I/O P1[26] — General purpose digital input/output pin.O MCOB1 — Motor control PWM channel 1, output B.O PWM1[6] — Pulse Width Modulator 1, channel 6 output.ICAP0[0] — Capture input for Timer 0, channel 0.P1[27]/CLKOUT /USB_OVRCR/ CAP0[1]43[1]I/O P1[27] — General purpose digital input/output pin.O CLKOUT — Clock output pin.I USB_OVRCR — USB port Over-Current status. (LPC1768/66/65 only).ICAP0[1] — Capture input for Timer 0, channel 1.P1[28]/MCOA2/ PCAP1[0]/ MAT0[0]44[1]I/O P1[28] — General purpose digital input/output pin.O MCOA2 — Motor control PWM channel 2, output A.I PCAP1[0] — Capture input for PWM1, channel 0.OMAT0[0] — Match output for Timer 0, channel 0.P1[29]/MCOB2/ PCAP1[1]/ MAT0[1]45[1]I/O P1[29] — General purpose digital input/output pin.O MCOB2 — Motor control PWM channel 2, output B.I PCAP1[1] — Capture input for PWM1, channel 1.OMAT0[1] — Match output for Timer 0, channel 1.P1[30]/V BUS / AD0[4]21[2]I/O P1[30] — General purpose digital input/output pin.I V BUS — Monitors the presence of USB bus power. (LPC1768/66/65/64 only). Note: This signal must be HIGH for USB reset to occur.IAD0[4] — A/D converter 0, input 4.P1[31]/SCK1/ AD0[5]20[2]I/O P1[31] — General purpose digital input/output pin.I/O SCK1 — Serial Clock for SSP1.I AD0[5] — A/D converter 0, input 5.P2[0] to P2[31]I/OPort 2: Port 2 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 2 pins depends upon the pin function selected via the pin connect block. Pins 14 through 31 of this port are not available.P2[0]/PWM1[1]/ TXD175[1]I/O P2[0] — General purpose digital input/output pin.O PWM1[1] — Pulse Width Modulator 1, channel 1 output.OTXD1 — Transmitter output for UART1.P2[1]/PWM1[2]/ RXD174[1]I/O P2[1] — General purpose digital input/output pin.O PWM1[2] — Pulse Width Modulator 1, channel 2 output.IRXD1 — Receiver input for UART1.P2[2]/PWM1[3]/ CTS1/TRACEDATA[3]73[1]I/O P2[2] — General purpose digital input/output pin.O PWM1[3] — Pulse Width Modulator 1, channel 3 output.I CTS1 — Clear to Send input for UART1.OTRACEDATA[3] — Trace data, bit 3.P2[3]/PWM1[4]/ DCD1/TRACEDATA[2]70[1]I/O P2[3] — General purpose digital input/output pin.O PWM1[4] — Pulse Width Modulator 1, channel 4 output.I DCD1 — Data Carrier Detect input for UART1.OTRACEDATA[2] — Trace data, bit 2.Table 3.Pin description …continuedSymbolPin Type DescriptionAF TDR A F AF TDRA F TDRA F T D AF TDR A F T DR A F T D RAF T D R AP2[4]/PWM1[5]/ DSR1/TRACEDATA[1]69[1]I/O P2[4] — General purpose digital input/output pin.O PWM1[5] — Pulse Width Modulator 1, channel 5 output.I DSR1 — Data Set Ready input for UART1.OTRACEDATA[1] — Trace data, bit 1.P2[5]/PWM1[6]/ DTR1/TRACEDATA[0]68[1]I/O P2[5] — General purpose digital input/output pin.O PWM1[6] — Pulse Width Modulator 1, channel 6 output.O DTR1 — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal.OTRACEDATA[0] — Trace data, bit 0.P2[6]/PCAP1[0]/ RI1/TRACECLK67[1]I/O P2[6] — General purpose digital input/output pin.I PCAP1[0] — Capture input for PWM1, channel 0.I RI1 — Ring Indicator input for UART1.OTRACECLK — Trace Clock.P2[7]/RD2/ RTS166[1]I/O P2[7] — General purpose digital input/output pin.I RD2 — CAN2 receiver input. (LPC1768/66/65/64 only).ORTS1 — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal.P2[8]/TD2/ TXD265[1]I/O P2[8] — General purpose digital input/output pin.O TD2 — CAN2 transmitter output. (LPC1768/66/65/64 only). OTXD2 — Transmitter output for UART2.P2[9]/USB_CONNECT/ RXD264[1]I/O P2[9] — General purpose digital input/output pin.OUSB_CONNECT — Signal used to switch an external 1.5 k Ω resistor under software control. Used with the SoftConnect USB feature. (LPC1768/66/65/64 only).IRXD2 — Receiver input for UART2.P2[10]/EINT0/NMI53[6]I/OP2[10] — General purpose digital input/output pin.Note: LOW on this pin while RESET is LOW forces on-chip bootloader to take over control of the part after a reset.I EINT0 — External interrupt 0 input.INMI — Non-maskable interrupt input.P2[11]/EINT1/ I2STX_CLK52[6]I/O P2[11] — General purpose digital input/output pin.I EINT1 — External interrupt 1 input.I/OI2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I 2S-bus specification . (LPC1768/67/66/65 only).P2[12]/EINT2/ I2STX_WS51[6]I/O P2[12] — General purpose digital input/output pin.I EINT2 — External interrupt 2 input.I/OI2STX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I 2S-bus specification . (LPC1768/67/66/65 only).Table 3.Pin description …continuedSymbolPin Type DescriptionAF TDR A F AF TDRA F TDRA F T D AF TDR A F T DR A F T D RAF T D R A P2[13]/EINT3/ I2STX_SDA50[6]I/O P2[13] — General purpose digital input/output pin.I EINT3 — External interrupt 3 input.I/OI2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I 2S-bus specification . (LPC1768/67/66/65 only).P3[0] to P3[31]I/OPort 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 3 pins depends upon the pin function selected via the pin connect block. Pins 0 through 24, and 27 through 31 of this port are not available.P3[25]/MAT0[0]/ PWM1[2]27[1]I/O P3[25] — General purpose digital input/output pin.O MAT0[0] — Match output for Timer 0, channel 0.OPWM1[2] — Pulse Width Modulator 1, output 2.P3[26]/STCLK/ MAT0[1]/PWM1[3]26[1]I/O P3[26] — General purpose digital input/output pin.I STCLK — System tick timer clock input.O MAT0[1] — Match output for Timer 0, channel 1.OPWM1[3] — Pulse Width Modulator 1, output 3.P4[0] to P4[31]I/OPort 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 4 pins depends upon the pin function selected via the pin connect block. Pins 0 through 27, 30, and 31 of this port are not available.P4[28]/RX_MCLK/MAT2[0]/TXD382[1]I/O P4[28] — General purpose digital input/output pin.I RX_MCLK — I 2S receive master clock. (LPC1768/67/66/65 only).O MAT2[0] — Match output for Timer 2, channel 0.OTXD3 — Transmitter output for UART3.P4[29]/TX_MCLK/MAT2[1]/RXD385[1]I/O P4[29] — General purpose digital input/output pin.I TX_MCLK — I 2S transmit master clock. (LPC1768/67/66/65 only).O MAT2[1] — Match output for Timer 2, channel 1.IRXD3 — Receiver input for UART3.TDO/SWO 1[1]O TDO — Test Data out for JTAG interface.O SWO — Serial wire trace output.TDI2[1]I TDI — Test Data in for JTAG interface.TMS/SWDIO 3[1]I TMS — Test Mode Select for JTAG interface.I/O SWDIO — Serial wire debug data input/output.TRST 4[1]I TRST — Test Reset for JTAG interface.TCK/SWDCLK 5[1]I TCK — Test Clock for JTAG interface. I SWDCLK — Serial wire clock.RTCK 100[1]I/O RTCK — JTAG interface control signal.RSTOUT 14O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates the microcontroller being in Reset state.RESET17[7]IExternal reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant.XTAL122[8]I Input to the oscillator circuit and internal clock generator circuits.XTAL223[8]O Output from the oscillator amplifier.RTCX116[8]IInput to the RTC oscillator circuit.Table 3.Pin description …continuedSymbolPin Type Description。

lpc176X技术资料

D R A FT
D R A FT D A FT
D R A FT D R A FT D
R
R A FT D R A FT A R
A FT A FT D R D R FT
Rev. 03.01 — 16 December 2009
Product data sheet
A A FT FT D D R A FT D R A R
D
D
NXP Semiconductors
LPC1769/68/67/66/65/64
FT FT FT FT D D D R R R A A A FT FT FT D D D R R R A A FT FT D D
32-bit ARM Cortex-M3 microcontroller
A

Two/one 16 kB SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as for general purpose CPU instruction and data storage. Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with SSP, I2S-bus, UART, Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers. Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, and the USB interface. This interconnect provides communication with no arbitration delays. Split APB bus allows high throughput with few stalls between the CPU and DMA. Serial interfaces: Ethernet MAC with RMII interface and dedicated DMA controller (LPC1769/68/67/66/64 only). USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions (LPC1769/68/66/65 only). The LPC1764 includes a device controller only. Four UARTs with fractional baud rate generation, internal FIFO, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support, and one UART has IrDA support. CAN 2.0B controller with two channels. SPI controller with synchronous, serial, full duplex communication and programmable data length. Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller. Three enhanced I2C bus interfaces, one with an open-drain output supporting full I2C specification and Fast mode plus with data rates of 1 Mbit/s, two with standard port pins. Enhancements include multiple address recognition and monitor mode. On the LPC1769/68/67/66/65 only, I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I2S-bus interface can be used with the GPDMA. The I2S-bus interface supports 3-wire and 4-wire data transmit and receive as well as master clock input/output. Other peripherals: 70 (100 pin package) General Purpose I/O (GPIO) pins with configurable pull-up/down resistors. All GPIOs support a new, configurable open-drain operating mode. The GPIO block is accessed through the AHB mulitlayer bus for fast access and located in memory such that it supports Cortex-M3 bit banding and use by the General Purpose DMA Controller. 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins, conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller. 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support (LPC1769/68/67/66/65 only). Four general purpose timers/counters, with a total of eight capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests. One motor control PWM with support for three-phase motor control.

LPC总线介绍

在NB电路的架构框图中，我们可以看到PCH和EC之间通过LPC总线连接，在MB板上也会看到EC芯片旁边有一个JDEBUG的connector，其也与LPC总线相连，用于主板诊断。

下面将对LPC总线做一些简单介绍，希望能够帮助大家了解LPC的工作原理：1、LPC总线LPC（Low Pin Count）是基于Intel 标准的33 MHz 4 bit 并行总线协议（但目前NB系统中LPC的时钟频率为24MHz，可能是由于CPU平台的不断发展导致的，后面会具体分析），用于代替以前的ISA 总线协议，但两者性能相似，都用于连接南桥和Super I/O芯片、FLASH BIOS、EC等设备（由于目前EC芯片中整合了Super I/O功能，所以我们在NB系统中看不到LPC总线上挂有Super I/O芯片了）。

传统ISA BUS速率大约在7.159~8.33MHz，提供的理论尖峰传输值为16MB/s，但是ISA BUS与传统的PCI BUS的电气特性、信号定义方式迥异，使得南桥芯片、Super I/O芯片浪费很多针脚来做处理，主板的线路设计也显得复杂。

为此，Intel 定义了LPC接口，将以往ISA BUS的地址/数据分离译码，改成类似PCI的地址/数据信号线共享的译码方式，信号线数量大幅降低，工作速率由PCI总线速率同步驱动（时钟同为33MHz），虽然改良过的LPC接口一样维持最大传输值16MB/s，但信号管脚却大幅减少了25~30个，以LPC接口设计的Super I/O芯片、Flash芯片都能享有脚位数减少、体积微缩的好处，主板的设计也可以简化，这也是取名LPC——Low Pin Count的原因。

2、LPC总线的接口管脚LPC总线由7个必选信号和6个可选信号组成，具体如下表所示：MB板上的JDEBUG connector有12pin,没有连接LRESET#信号，只连接了其余的6个必选信号，为主板诊断提供接口，其中CLK_DEBUG由PCH提供，24MHZ：EC与PCH连接的LPC总线中除了包含7个必选信号，还包含SEEIRQ和CLKRUN#信号。

LM016L结构及功能之欧阳德创编

液晶模块简介LM016L的结构及功能LM016L液晶模块采用HD44780控制器，hd44780具有简单而功能较强的指令集，可以实现字符移动，闪烁等功能，LM016L与单片机MCU 通讯可采用8位或4位并行传输两种方式，hd44780控制器由两个8位寄存器，指令寄存器（IR）和数据寄存器（DR）忙标志（BF），显示数RAM（DDRAM），字符发生器ROMA （CGOROM）字符发生器RAM（CGRAM），地址计数器RAM(AC)。

IR用于寄存指令码，只能写入不能读出，DR用于寄存数据，数据由内部操作自动写入DDRAM和CGRAM,或者暂存从DDRAM和CGRAM读出的数据，BF为1时，液晶模块处于内部模式，不响应外部操作指令和接受数据，DDTAM用来存储显示的字符，能存储80个字符码，CGROM由8位字符码生成5*7点阵字符160中和5*10点阵字符32种.8位字符编码和字符的对应关系，可以查看参考文献（30）中的表4.CGRAM是为用户编写特殊字符留用的，它的容量仅64字节，可以自定义8个5*7点阵字符或者4个5*10点阵字符，AC可以存储DDRAM和CGRAM的地址，如果地址码随指令写入IR,则IR 自动把地址码装入AC，同时选择DDRAM或CGRAM但愿，LM016L液晶模块的引脚功能如下表所示：引脚说明1602字符型LCD通常有14条引脚线或16条引脚线的LCD，多出来的2条线是背光电源线VCC(15脚)和地线GND(16脚)，其控制原理与14脚的LCD完全一样，其中：引脚符号功能说明1 VSS 一般接地2 VDD 接电源（+5V）3 V0 液晶显示器对比度调整端，接正电源时对比度最弱，接地电源时对比度最高（对比度过高时会产生“鬼影”，使用时可以通过一个10K的电位器调整对比度）。

4 RS RS为寄存器选择，高电平1时选择数据寄存器、低电平0时选择指令寄存器。

5 R/W R/W为读写信号线，高电平(1)时进行读操作，低电平(0)时进行写操作。

32位MCU开发攻略连载之27：电源电路

32 位MCU 开发攻略连载之27：电源电路
5.5 电源电路
LPC17xx 系列微控制器在电源部分需要五种电压源对其供电，分别为：
1. 内核和外部通路所需的3.3V 电压源VDD(3V3)；
2. 内部稳压器所需的
3.3V 电压源VDD(REG)(3V3)；
3. 模拟部分(诸如片上ADC 以及DAC)所需的3.3V 电压源VDDA；
4. 模数转换器ADC 所需的参考电压源VREFP；
5. 实时时钟RTC 所需的3.3V 电压源VBAT。

由上述分析可见，如果用户对ADC 参考电压源无特殊要求，LPC17xx 系
列微控制器可以统一由3.3V 电平的电压源供电，降低了用户在设计硬件时电
源部分的复杂度，需要注意的是，模拟部分电压源VDDA 可以与VDD(3V3)
由相同的电压源提供，但最好隔离开来以减小电源噪声。

除此之外，用户的
设计中不使用ADC 或者DAC，关于模拟部分电压源的管脚仍需要连接到电
压源上。

现以Linpo-PS-LPC1760 开发板为例，简单介绍一下LPC17xx 系列微控制器电源部分的实现。

如图5.4 所示，开发板使用常用的1117 系列LDO 低压
差线性稳压器将外部5V 电压源降压产生LPC17xx 所需的3.3V 的电压，
EC301 和C302 用于对5V 输入电源的滤波，EC302 和C303 用于对3.3V 输出电流的滤波。

图5.4 LPC17xx 系列微控制器3.3V 电压源原理图
LPC17xx 的RTC 部分电路可参看图5.5，通过两个二极管D101 和D102 实现板上3.3V 电源或者是3.3V 电池对RTC 供电，且电池电源不会与板上。

LPC总线介绍之欧阳育创编

下面将对LPC总线做一些简单介绍，希望能够帮助大家了解LPC的工作原理：2、LPC总线LPC（Low Pin Count）是基于 Intel 标准的33 MHz 4 bit 并行总线协议（但目前NB系统中LPC的时钟频率为24MHz，可能是由于CPU平台的不断发展导致的，后面会具体分析），用于代替以前的 ISA 总线协议，但两者性能相似，都用于连接南桥和Super I/O芯片、FLASH BIOS、EC等设备（由于目前EC芯片中整合了Super I/O功能，所以我们在NB系统中看不到LPC总线上挂有Super I/O芯片了）。

为此，Intel定义了LPC接口，将以往ISA BUS的地址/数据分离译码，改成类似PCI的地址/数据信号线共享的译码方式，信号线数量大幅降低，工作速率由PCI总线速率同步驱动（时钟同为33MHz），虽然改良过的LPC接口一样维持最大传输值16MB/s，但信号管脚却大幅减少了25~30个，以LPC接口设计的Super I/O芯片、Flash芯片都能享有脚位数减少、体积微缩的好处，主板的设计也可以简化，这也是取名LPC——Low Pin Count的原因。

2、LPC总线的接口管脚LPC总线由7个必选信号和6个可选信号组成，具体如下表所示：表 32 LPC总线可选信号列表MB板上的JDEBUG connector有12pin,没有连接LRESET#信号，只连接了其余的6个必选信号，为主板诊断提供接口，其中CLK_DEBUG由PCH提供，24MHZ：EC与PCH连接的LPC总线中除了包含7个必选信号，还包含SEEIRQ和CLKRUN#信号。

LPC简介

Chapter1:LPC17xx Introductory information 第一章：lpc17xx入门资料文档信息信息内容关键词lpc1769，lpc1768，lpc1767，lpc1766，lpc1765，lpc1764，lpc1759，lpc1758，lpc1756，lpc1754，lpc1752，lpc1751，手臂，微，32位，通用串行总线，以太网接口，微控制器，可以，摘要lpc17xx用户手册译结果（英> 中）复制结果双语对照查看恩智浦半导体um10360lpc17xx用户手册修订历史修订日期的描述120100104lpc17xx用户手动修改。

修改：•“草案”状态删除。

•编辑更新和印刷更正各地用户手册。

•lpc1758，lpc1767，和lpc1768已被添加到列表的前盖，订货信息，在1节和4节–，部分的识别号码表32部分–7.11。

•操作的注意在睡眠模式被删除从第4–8.1。

•表8–81，clkout的功能是从描述p1.25。

在部分•以太网章，10节和10节的–16.1–17.2，有人指出在外部物理层必须初始化和物理时钟收到的以太网块前进一步的以太网初始化块。

此外，在10节–17.1，标题下“所有的描述”的句子，-仲裁被删除。

一般的更正确的讨论的主题中添加了2节–5。

•收发器分数波特率发生器是残疾人在波特率的自动模式（参见14节和15节的–14.4.10.1–4.14）。

在第14节•–4.12节和15–4.16，说明价值的动态链接库已登记的更正阅读”价值的动态链接库登记必须大于2”。

•* * * * * * ** * * * * * *运动控制•描述计算的qei章（见26节–4.3），定义为公式的值相加，并说明改进。

描述的位置和指数比较寄存器错误表明，小于，等于，大于比较可以选择。

它变为只显示“等于”。

•说明闪光签名生成已被添加在32节–10。

联系信息更多信息，请访问：销售办公地址，请发送电子邮件到：salesaddresses@ 1。

MEMORY存储芯片LPC1765FBD100中文规格书

LPC122X All information provided in this document is subject to legal disclaimers.© NXP B.V. 2011. All rights reserved.Product data sheet Rev. 2 — 26 August 2011 25 of 61NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontrollerThe system oscillator operates at frequencies of 1MHz to 25MHz. This frequency can beboosted to a higher frequency, up to the maximum CPU operating frequency, by thesystem PLL. The ARM processor clock frequency is referred to as CCLK elsewhere in thisdocument.7.18.1.3Watchdog oscillatorThe watchdog oscillator can be used as a clock source that directly drives the CPU, thewatchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency isprogrammable between 7.8 kHz and 1.7 MHz. The frequency spread over processing andtemperature is ±40 %.7.18.2System PLLThe PLL accepts an input clock frequency in the range of 10MHz to 25MHz. The inputfrequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).The multiplier can be an integer value from 1 to 32. The CCO operates in the range of156MHz to 320MHz, so there is an additional divider in the loop to keep the CCO withinits frequency range while the PLL is providing the desired output frequency. The outputdivider may be set to divide by 2, 4, 8, or 16 to produce the output clock. The PLL outputfrequency must be lower than 100 MHz. Since the minimum output divider value is 2, it isinsured that the PLL output has a 50% duty cycle. The PLL is turned off and bypassedfollowing a chip reset and may be enabled by software. The program must configure andactivate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source.The PLL settling time is 100μs.7.18.3Clock outputThe LPC122x features a clock output function that routes the IRC oscillator, the systemoscillator, the watchdog oscillator, or the main clock to an output pin.7.18.4Wake-up processThe LPC122x begin operation at power-up and when awakened from Deep power-downmode by using the 12MHz IRC oscillator as the clock source. This allows chip operationto resume quickly. If the main oscillator or the PLL is needed by the application, softwarewill need to enable these features and wait for them to stabilize before they are used as aclock source.7.18.5Power controlThe LPC122x support a variety of power control features. There are three special modesof processor power reduction: Sleep mode, Deep-sleep mode, and Deep power-downmode. The CPU clock rate may also be controlled as needed by changing clock sources,reconfiguring PLL values, and/or altering the CPU clock divider value. This allows atrade-off of power versus processing speed based on application requirements. Inaddition, a register is provided for shutting down the clocks to individual on-chipperipherals, allowing fine tuning of power consumption by eliminating all dynamic poweruse in any peripherals that are not required for the application. Selected peripherals havetheir own clock divider which provides even better power control.7.18.5.1Sleep modeWhen Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleepmode does not need any special sequence but re-enabling the clock to the ARM core.LPC122X All information provided in this document is subject to legal disclaimers.© NXP B.V. 2011. All rights reserved.Product data sheet Rev. 2 — 26 August 2011 26 of 61NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontrollerIn Sleep mode, execution of instructions is suspended until either a reset or interruptoccurs. Peripheral functions continue operation during Sleep mode and may generateinterrupts to cause the processor to resume execution. Sleep mode eliminates dynamicpower used by the processor itself, memory systems and related controllers, and internalbuses.7.18.5.2Deep-sleep modeIn Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shutdown. As an exception, the user has the option to keep the watchdog oscillator and theBOD circuit running for self-timed wake-up and BOD protection. Deep-sleep mode allowsfor additional power savings.The GPIO pins PIO0_0 to PIO0_11 (up to 12 pins total) and the RTC match interrupt canserve as a wake-up input to the start logic to wake up the chip from Deep-sleep mode.Unless the watchdog oscillator is selected to run in Deep-sleep mode, the clock sourceshould be switched to IRC before entering Deep-sleep mode, because the IRC can beswitched on and off glitch-free.7.18.5.3Deep power-down modeIn Deep power-down mode, power is shut off to the entire chip with the exception of theReal Time Clock, the four general-purpose registers, and the WAKEUP pin. The LPC122xcan wake up from Deep power-down mode via the WAKEUP pin or the RTC matchinterrupt.When entering Deep power-down mode, an external pull-up resistor is required on the WAKEUP pin to hold it HIGH. The RESET pin must also be held HIGH to prevent it fromfloating while in Deep power-down mode.7.19System control7.19.1Start logicThe start logic connects external pins to corresponding interrupts in the NVIC. Each pinshown in Table 3 as input to the start logic has an individual interrupt in the NVIC interruptvector table. The start logic pins can serve as external interrupt pins when the chip isrunning. In addition, an input signal on the start logic pins can wake up the chip fromDeep-sleep mode when all clocks are shut down.The start logic must be configured in the system configuration block and in the NVICbefore being used.7.19.2Reset Reset has four sources on the LPC122x: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitttrigger input pin. Assertion of chip reset by any source, once the operating voltage attainsa usable level, starts the IRC and initializes the flash controller.When the internal Reset is removed, the processor begins executing at address 0, whichis initially the Reset vector mapped from the boot block. At that point, all of the processorand peripheral registers have been initialized to predetermined values.芯片详细信息Manufacturer Part Number: Pbfree Code Rohs c 。

车载产品介绍

车载设备产品翻译关于我们UCAST有限公司成立于2003年，是一家生产耐用的显示器和移动数据为工业设备制造商和商用车。

我们的产品包括车载GPS设备，车载电脑硬件等，我们还提供售后支持和对销售商和客户的一系列服务，以及嵌入式软件解决方案和项目管理。

UCAST伙伴包括许多全球领先的公司，我们的产品已在北美，欧洲，亚洲和澳大利亚的主要市场。

总之，我们期望与我们的客户实现通过建立稳定，持续，以及智能远程信息处理解决方案的愿望。

UCAST的移动数据终端（MDT）可用于字符和图形。

我们的终端设备是可编程的，可定制的，并能承受冲击，振动，湿度和其他恶劣环境下的工作。

并有很多接口是可以用的包括USB, EIA-232, EIA-422, EIA-485, J1708，以太网和电源以太网。

一个具有可配置的硬件选项终端整条生产线是为我们的客户.我们还可以调整我们的产品，以配合您的需求。

在UCAST，我们努力在每个业务环节精益求精。

我们的领导团队有运作10年的丰富经验和知识。

UCAST的产品在世界各地的使用，我们的使命是提供产品，将充分满足您的需求。

一、MDT彩色液晶GPS显示器系列1、MDT 700处理器： ARM9 400MHz处理器内存： 128MB闪存： 128MB操作系统： WinCE5.0SIM卡插槽 * 2SD卡插槽 * 1无线通讯： GSM / GPRS调制解调器GPS接收机：500ms的热启动，暖启动31秒，冷启动33秒屏幕： 7寸薄膜晶体管液晶显示器、LED背光、触摸面板、分辨率800 * 480USB ：个数：2 USB主机* 1，USB接口* 1输入：通用信号* 6输出：输出数2 信号* 1 、继电器* 1串行接口方式：RS232 * 5电源：车辆动态控制系统支持10V – 36V的输入消耗功率：车辆动态控制系统支持 <800mA的典型12V直流工作温度：-20℃至70℃[实验室测试]存储温度：-20℃至85℃湿度： 5-90％电源保护：反向电流，过压，过滤外型尺寸： 198 * 142 * 36（长*宽*高）（单位：毫米）原文：/ProductShow_D30_New.htm2、MDT 710处理器： ARM9 400MHz处理器内存： 256MB闪存： 128MB操作系统： WinCE 6.0SIM卡插槽 * 2SD卡插槽 * 1无线通讯： GSM / GPRS调制解调器 ,WCDMA网络 (可选)EVDO网络 (可选)GPS接收机：500ms的热启动，暖启动31秒，冷启动33秒屏幕： 7寸薄膜晶体管液晶显示器、LED背光、触摸面板、800 * 480分辨率USB ：个数：2 USB主机* 1，USB接口* 1输入：通用信号* 6输出：输出数2 信号* 1 、继电器* 1串行接口方式：RS232 * 5电源：车辆动态控制系统支持10V – 36V的输入消耗功率：车辆动态控制系统支持 <800mA的典型12V直流工作温度：-20℃至70℃[实验室测试]存储温度：-20℃至85℃湿度： 5-90％电源保护：反向电流，过压，过滤外型尺寸： 198 * 142 * 36（长*宽*高）（毫米）原文：/ProductShow_D33(710)_New.htm3、MDT 8001、MDU（信息解码器）和MCU（控制器）分离设计示意图2、MDU硬件特征液晶触摸屏： 7寸、800*480像素，触摸屏处理器： ARM7 LPC2103 72MHz 处理器图像传感器：自动背光调整亮度控制： 32级亮度、用户可调节背光控制光学手指导航：最小现有鼠标按钮麦克风* 2：语音识别和VOIP（可选）、语音电话喇叭* 2：系统音频和免提电话功能耳机插孔：戴在头上的耳机或听筒指示灯* 4：通过API显示系统控制状态灯罩：减少阳光的反射屏幕按钮：短按可开启/关闭屏幕、按住6秒重新启动系统复位按钮（隐藏）：硬件复位整个系统（包括MCU和MDU）键* 6： 4个功能侧键3、MCU硬件特征处理器： 400MHz ARM9内存： 128MB的闪存： 128MB的操作系统： WinCE5.0SIM卡插槽 * 2SD卡插槽 * 1无线通讯： GSM/GPRSWCDMA（可选）EVDO（可选）GPS接收机：500ms的热启动，暖启动31秒，冷启动33秒USB * 2： USB主机和USB接口输入：通用信号*6输出* 2：信号* 1 、继电器* 1串行接口方式：RS232 * 4电源：车辆动态控制系统支持10V – 36V的输入功耗：车辆动态控制系统支持 <1000mA的典型12V直流工作温度： -20℃至70℃[实验室测试]存储温度： -20℃至85℃湿度： 5-90％电源保护：反向电流，过压，过滤外型尺寸： 175 * 80 * 38（长*宽*高）（单位：毫米）原文：/ProductShow_D32Gs(720)_New.htm 4、MDT 8101、MDU（信息解码器）和MCU（控制器）分离设计示意图2、MDU硬件特征液晶触摸屏：7寸、800*480像素，触摸屏处理器：ARM7 LPC2103 72MHz 处理器图像传感器：自动背光调整亮度控制：32级亮度、用户可调节背光控制光学手指导航：最小现有鼠标按钮麦克风* 2：语音识别和VOIP（可选）、语音电话喇叭* 2：系统音频和免提电话功能耳机插孔：戴在头上的耳机或听筒指示灯* 4：通过API显示系统控制状态灯罩：减少阳光的反射屏幕按钮：短按可开启/关闭屏幕、按住6秒重新启动系统复位按钮（隐藏）：硬件复位整个系统（包括MCU和MDU）键* 4： 4个功能侧键3、MCU硬件特征处理器：667MHz ARM11内存：128MB的闪存：128MB的2D和3D图像：内置二维和三维的硬件加速器H264、MPEG4: 支持硬件压缩内部SIM卡插槽 * 2SD卡插槽 * 1无线(wifi)：可选蓝牙：可选无线通讯：GSM/GPRSWCDMA（可选）EVDO（可选）GPS接收机：500ms的热启动，暖启动31秒，冷启动33秒USB * 2：USB主机和USB接口* 1输入：通用信号*6输出* 2：信号* 1 、继电器* 1串行接口方式：RS232 * 7电源：车辆动态控制系统支持10V – 36V的输入功耗：车辆动态控制系统支持 <1000mA的典型12V直流工作温度：-20℃至70℃[实验室测试]存储温度：-20℃至85℃湿度： 5-90％电源保护：反向电流，过压，过滤原文：/ProductShow_D35Gs(750)_New.htm二、MDT的单色液晶显示器系列1、MDT 500处理器： ARM7 72MHz内部SIM插槽 * 1无线通讯： GSM / GPRS调制解调器Gps接收机：暖启动20秒，冷启动120秒屏幕： 192 * 64像素的单色液晶屏、240 * 64像素的单色液晶显示屏（可选）输入：通用信号* 9输出：输出（继电器）* 2串行接口方式：RS232 * 3电源：车辆动态控制系统支持8V – 32V的输入消耗功率：车辆动态控制系统支持 <250mA的典型12V直流工作温度： -20℃至70℃[实验室测试]存储温度： -20℃至85℃湿度： 5-90％电源保护：反向电流，过压，过滤产品概述：最便宜的调度设备、最便捷的安装原文：/ProductShow_MDT520_New.htm 2、MDT 510处理器： ARM7 72MHz内存： 4M内部SIM插槽 * 1无线通讯： GSM / GPRS调制解调器GPS接收机：暖启动20秒，冷启动120秒屏幕： 192 * 64像素的单色液晶屏输入：通用信号* 6输出：输出（继电器）* 1串行接口方式：RS232 * 2电源：车辆动态控制系统支持8V – 32V的输入消耗功率：车辆动态控制系统支持 <250mA的典型12V直流工作温度： -20℃至70℃[实验室测试]存储温度： -20℃至85℃湿度： 5-90％电源保护：反向电流，过压，过滤产品概述：最便宜的调度设备、最便捷的安装原文：/ProductShow_MDT520_S_New.htm三、数字视频录像机系列1、DVR 600处理器： Hi3512操作系统：嵌入式Linux操作系统系统资源： 4路实时CIF视频视频标准： PAL，NTSC图像压缩标准：H.264音频压缩： ADPCM录像方式：手动，定时，报警，移动侦测影片查询：时间检索，事件检索，检索途径备份方法： USB备份视频输入： 4路BNC(BNC:高频线接插器)视频输出： 1路BNC音频输入： 4路BNC音频输出： 1路BNC显示器质量：PAL 720 * 576（D1）; NTSC 720 * 480（D1）播放质量： PAL 352 * 288（CIF）; NTSC 352 * 240（CIF）图像控制：6齿轮可调运动检测：可用照片显示：单画面，四画面视频速度：PAL：25帧每秒（可调）; NTSC：30帧每秒（可调）视频保护：硬盘，SD卡本地回放：1路，4路回放报警输入：4个开关量存储接口：USB接口* 1，SD接口* 1点火信号：（Ignition Signal） * 1电源：直流6V-36V的原文：/ProductShow_DVR600_New.htm 2、DVR 620处理器： Hi3512操作系统：嵌入式Linux操作系统语音功能：语音合成无线通讯：GSM/GPRS调制解调器GPS接收机：500MS热启动，暖启动31秒，冷启动33秒NFC技术：近场通讯读卡器系统资源：4路实时CIF视频视频标准： PAL，NTSC图像压缩标准：H.264音频压缩： ADPCM录像方式：手动，定时，报警，移动侦测影片查询：时间检索，事件检索，检索途径备份方法：USB备份视频输入：4路BNC(BNC:高频线接插器)视频输出：1路BNC音频输入：4路BNC音频输出：1路BNC显示器质量：PAL 720 * 576（D1）; NTSC 720 * 480（D1）播放质量：PAL 352 * 288（CIF）; NTSC 352 * 240（CIF）图像控制：6齿轮可调运动检测：可用照片显示：单画面，四画面视频速度：PAL：25帧每秒（可调）; NTSC：30帧每秒（可调）视频保护：硬盘，SD卡本地回放：1路，4路回放报警输入：4个开关量存储接口：USB接口* 1，SD接口* 1点火信号 * 1电源：直流6V-36V的原文：/ProductShow_DVR620_New.htm四、车辆数据追踪系列1、TK 300硬件特征：处理器： ARM7 72MHz内部SIM插槽* 1无线通讯：GSM / GPRS调制解调器GPS接收机：暖启动20秒，120秒冷启动输入：通用信号* 6输出：输出（继电器）* 1串行接口方式：RS232 * 2电源：+8V - 32V输入直流消耗功率：<100mA 12V直流工作温度：-20℃至70℃[实验室测试]存储温度：-20℃至85℃湿度：5-90％电源保护：反向电流，过压，过滤软件特征：定时或者定距离报告车辆信号信息给back-end system报告超速信息给back-end system报告行车路线给back-end system通过OTA或者串口进行升级。

LPCXpresso--用户手册

LPCXpresso 用户手册V1.01、绪论LPCXpresso是来自NXP的一款新的、低成本开发平台。

其软件部分包括增强型IDE开发环境、GNU C编译器、连接器、库函数、增强型GDB调试器。

硬件部分包括LPCXpresso开发板，该开发板包含两部分：LPC –Link调试接口板、LPC ARM微控制器目标板。

LPCXpresso是一个中断对终端解决方案，它可以帮助嵌入式工程师完成从产品的初始评估到最终产品的所有工作。

LPCXpresso IDE是由Code Red Technologies公司开发的基于流行的Eclipse开发平台并且支持LPC系列器件。

它是一个符合行业标准的GNU工具链，它的优化C库函数提供给工程师各种所需的开发工具，使得工程师能够获得快速，廉价的高质量软件解决方案。

C编程环境具有专业特色：语句/关键字颜色设置、源程序格式设置、展开/收缩功能、离线/在线帮助、自动项目管理。

LPCXpresso目标板由NXP、Code Red Technologies、Embedded Artists 共同合作开发。

板载集成的JTAG调试器（LPC-Link），不用再另外配置单独的JTAG调试器。

核心半部分提供了多种接口和I/O驱动方式，可以方便地进行功能扩展。

板载LPC-Link调试器提供高速USB转JTAG/SWD接口连接到IDE开发软件，并且还可以作为调试器连接到其他的目标板进行调试。

用户还可以从Code Red Technologies 购买Red ProbeJTAG适配器在LPCXpresso IDE上进行开发。

LPCXpresso支持下列LPC器件：LPC11XX：全系列LPC13XX：全系列LPC17XX：LPC1751，LPC1752，LPC1754，LPC1756，LPC1758，LPC1764，LPC1765，LPC1766，LPC1767，LPC1768LPC2XXX：LPC2109，LPC2134，LPC2142，LPC2362LPC3XXX：LPC31301.1 LPCXpresso IDELPCXpresso IDE是一个针对LPC微控制器的高度集成的软件开发环境，它包含要求快速、廉价方式软件解决方案所需要的所有工具。

全套LPC中文数据手册（精品）.pdf

地址：广州市天河北路689号光大银行大厦12楼F4网址：第一章概述用户手手册册R R e e v v 0000..0044L P C 1700系列微控制器销售与服务网络广州周立功单片机发展有限公司地址：广州市天河北路689号光大银行大厦12楼F4 邮编：510630 电话：(020)38730972 38730976 38730916 38730917 38730977 传真：(020)38730925网址：广州专卖店地址：广州市天河区新赛格电子城203-204室电话：(020)87578634 87569917传真：(020)87578842南京周立功地址：南京市珠江路280号珠江大厦2006室电话：(025)83613221 83613271 83603500 传真：(025)83613271北京周立功地址：北京市海淀区知春路113号银网中心A座1207-1208室（中发电子市场斜对面）电话：(010)62536178 62536179 82628073传真：(010)82614433 重庆周立功地址：重庆市石桥铺科园一路二号大西洋国际大厦（赛格电子市场）1611室电话：(023)68796438 68796439传真：(023)68796439杭州周立功地址：杭州市天目山路217号江南电子大厦502室电话：(0571)89719480 89719481 8971948289719483 89719448 89719485传真：(0571)89719494 成都周立功地址：成都市一环路南二段1号数码同人港401室（磨子桥立交西北角）电话：(028)85439836 85437446传真：(028) 85437896深圳周立功地址：深圳市深南中路 2070号电子科技大厦C座4楼D室电话：(0755)83781788（5线）传真：(0755)83793285 武汉周立功地址：武汉市洪山区广埠屯珞瑜路158号12128室（华中电脑数码市场）电话：(027)87168497 87168297 87168397传真：(027)87163755上海周立功地址：上海市北京东路668号科技京城东座7E室电话：(021)53083452 53083453 53083496传真：(021)53083491西安办事处地址：西安市长安北路54号太平洋大厦1201室电话：(029)87881296 83063000 87881295传真：(029)87880865目录第1章概述 (1)1.1 简介 (1)1.2 特性 (1)1.3 应用 (3)1.4 订购信息 (3)1.4.1 器件选项汇总 (3)1.5 简化方框图 (4)1.6 结构概述 (4)Cortex-M3处理器 (5)1.7 ARM1.7.1 Cortex-M3配置选项 (5)1.8 片上Flash存储器系统 (5)1.9 片上静态RAM (6)1.10 方框图 (7)第1章概述1.1 简介LPC1700系列Cortex-M3微控制器用于处理要求高度集成和低功耗的嵌入式应用。

(整理)电脑主板原理图

1.主板上的英文字母都代表什么1.L----电感.电感线圈2.C----电容.3.BC---贴片电容4.R----电阻5.9231 芯片-----脉宽6.74 门电路-----它在主板南桥旁边7.PQ----场效应管8.VT 、Q、V----三级管9.VD 、D---二级管10.RN----排阻11. ZD----稳压二极管12.W-----电位器13.IC---稳压块14.IC 、N、U----集成电路15.X 、Y、G、Z----晶振16.S-----开关17.CM----频率发生器(一般在晶振14.31818 旁边)2. 计算机开机原理开机原理：插上ATX 电源后，有一个静态5V 电压送到南桥,为南桥里面的ATX 开机电路提供工作条件（ATX 电源的开机电路是集成南桥里面的），南桥里面的ATX 开机电路将开始工作，会送一个电压给晶体，晶体起振工作，产生振荡，发出波形。

同时ATX 开机电路会送出一个开机电压到主板的开机针帽的一个脚，针帽的另一个脚接地。

当打开开机开关时，开机针帽的两个脚接通，而使南桥送出开机电压对地短路，拉低南桥送出的开机电压，而使南桥里的开机电路导通，拉低静态5V 电压，使其变为0 电位。

使电源开始工作，从而达到开机目的。

（ATX 电源里还有一个稳压部分，它需要静态5V 变为0 电位才能工作）。

3. 主板时钟电路工作原理时钟电路工作原理：3.5 电源经过二极管和电感进入分频器后，分频器开始工作，和晶体一起产生振荡，在晶体的两脚均可以看到波形。

晶体的两脚之间的阻值在450---700 欧之间。

在它的两脚各有1V 左右的电压，由分频器提供。

晶体两脚常生的频率总和是14.318M 。

总频（OSC ）在分频器出来后送到PCI 槽的B16 脚和ISA 的B30 脚。

这两脚叫OSC 测试脚。

也有的还送到南桥，目的是使南桥的频率更加稳定。

在总频OSC 线上还电容。

总频线的对地阻值在450---700 欧之间，总频时钟波形幅度一定要大于2V 电平。

LPC1700_um_12

地址：广州市天河北路689号光大银行大厦12楼F4 网址：第1122章 U S B 主机控制器用户手手册册R R e e v v 0000..0044L P C 1700系列微控制器销售与服务网络广州周立功单片机发展有限公司地址：广州市天河北路689号光大银行大厦12楼F4 邮编：510630 电话：(020)38730972 38730976 38730916 38730917 38730977 传真：(020)38730925网址：广州专卖店地址：广州市天河区新赛格电子城203-204室电话：(020)87578634 87569917传真：(020)87578842南京周立功地址：南京市珠江路280号珠江大厦2006室电话：(025)83613221 83613271 83603500 传真：(025)83613271北京周立功地址：北京市海淀区知春路113号银网中心A座1207-1208室（中发电子市场斜对面）电话：(010)62536178 62536179 82628073传真：(010)82614433 重庆周立功地址：重庆市石桥铺科园一路二号大西洋国际大厦（赛格电子市场）1611室电话：(023)68796438 68796439传真：(023)68796439杭州周立功地址：杭州市天目山路217号江南电子大厦502室电话：(0571)89719480 89719481 8971948289719483 89719448 89719485传真：(0571)89719494 成都周立功地址：成都市一环路南二段1号数码同人港401室（磨子桥立交西北角）电话：(028)85439836 85437446传真：(028) 85437896深圳周立功地址：深圳市深南中路 2070号电子科技大厦C座4楼D室电话：(0755)83781788（5线）传真：(0755)83793285 武汉周立功地址：武汉市洪山区广埠屯珞瑜路158号12128室（华中电脑数码市场）电话：(027)87168497 87168297 87168397传真：(027)87163755上海周立功地址：上海市北京东路668号科技京城东座7E室电话：(021)53083452 53083453 53083496传真：(021)53083491西安办事处地址：西安市长安北路54号太平洋大厦1201室电话：(029)87881296 83063000 87881295传真：(029)87880865目录第12章 USB设备控制器 (1)12.1 如何阅读本章 (1)12.2 基本配置 (1)12.3 简介 (1)12.3.1 特性 (1)12.3.2 结构 (2)12.4 接口 (2)12.4.1 管脚描述 (2)12.4.2 软件接口 (3)第12章USB设备控制器12.1 如何阅读本章本章描述了LPC1768、LPC1766、LPC1765、LPC1758、LPC1756和LPC1754可以使用的USB主机控制器。

机器人原理图-V1.0

G41_POWER-V1 G41_POWER-V1.0.Sch GSM_VCC 232C_EN_1 232_VCC_1 GPS_EN GPS_VCC CAR_GND GND 3.3V V_CAR VCC GSM_EN CAR_BAT_CHK V_CAR_IN +5V PT_MOT-5V_CTRL LCD_BLA_VCC LCD_BLA_CTRL PT_Heat-5V_CTRL IC_CARD_VCC IC_CARD_VCC_CTRL 232C_EN_2 232_VCC_2 SD_VCC PT_MOT-5V PT_Heat-5V SD_EN-L GSM_VCC 232C_EN_1 232_VCC_1 GPS_EN GPS_VCC CAR_GND GND 3.3V V_CAR VCC GSM_EN CAR_BAT_CHK V_CAR_IN +5V PT_MOT-5V_CTRL LCD_BLA_VCC LCD_BLA_CTRL PT_Heat-5V_CTRL IC_CARD_VCC IC_CARD_VCC_CTRL 232C_EN_2 232_VCC_2 SD_VCC PT_MOT-5V PT_Heat-5V SD_EN-L DOORN_IN SPEED_IN CAN_RX CAN_TX SOS_IN CTRL_OIL_OUT L_TURN_IN SPARE_IN R_TURN_IN BEAM_IN 3.3V +5V GND V_CAR ACC_IN 232_TX3 232_RX3 SPK2P SPK2N MIC2P MIC2N CAR_GND V_CAR_IN 232_TX0 232_RX0 232_VCC_1 BRACK_IN 485-A 485-B SPAREN_IN 34119-CTRL 232_VCC_2

1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。