MCP7383XEV-DIBC;中文规格书,Datasheet资料

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3933中文资料

Data Sheet 26301.100†The A3933SEQ is a three-phase MOSFET controller for use with bipolar brushless dc motors. It drives all n-channel external power FETs, allowing system cost savings and minimizing r (DS)on power loss.The high-side drive block is implemented with bootstrap capacitors at each output to provide the floating positive supply for the gate drive.The high-side circuitry also employs a unique “intelligent” FETmonitoring circuit that ensures the gate voltages are at the proper levels before turn-on and during the ON cycle. This device is targeted for applications with motor supplies from 12 V to 28 V.Internal fixed off-time PWM current-control circuitry can be used to regulate the maximum load current to a desired value. The peak load-current limit is set by the user’s selection of an input reference voltage and external sensing resistor. The fixed off-time pulse duration is set by a user-selected external RC timing network.A power-loss braking circuit brakes the motor on an under-voltage condition. The device is configured to either coast or dynamically brake the motor when this occurs.The A3933SEQ is supplied in a 32-lead rectangular (9 x 7) plasticchip carrier (quad pack) for minimum-area, surface-mount applica-tions.3933FEATURES AND BENEFITSI Drives External N-Channel FETs I Intelligent High-Side Gate DriveI Selectable Coast or Dynamic Brake on Power Down I Adjustable Dead Time for Cross-Conduction Protection I Selectable Fast or Slow Current-Decay Modes I Internal PWM Peak Current Control I Reset/Coast InputI 120° Hall Commutation with Internal Pullup I Internal 5-V RegulatorI Low-Side Synchronous Rectification I Direction ControlI PWM Speed-Control Input I Fault-Diagnostic Output IUnder-Voltage ProtectionTHREE-PHASE POWER MOSFET CONTROLLER115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-********THREE-PHASE POWER MOSFET CONTROLLERCopyright © 1999, Allegro MicroSystems, Inc.Functional Block DiagramRECOMMENDED OPERATING CONDITIONSSupply Voltage, V BB ...................................... 15 V to 28 Vor, if V BB = V CCOUT ................................... 12 V ±10%Logic Input Voltage Range, V IN .............. -0.3 V to +4.8 V Sense Voltage Range, V SENSE ........................ -1 V to +1 V RC Resistance.......................................... 10 k Ω to 100 k ΩPWM Frequency, f PWM ....................... 20 kHz to 100 kHzLOW-SIDE Dwg. FP-045V 1 OF 3 HIGH-SIDE DRIVERSTO 1 OF 3MOTOR PHASES TO LCAP3933THREE-PHASE POWER MOSFET CONTROLLERELECTRICAL SPECIFICATIONS at T A = 25°C, V BB = V CCOUT = 12 V, C load = 1000 pF, C boot = 0.047 µF (unless noted otherwise).LimitsParameterSymbolConditionsMinTypMaxUnitsSupply CurrentQuiescent Current I BB RESET low, f PWM = 40 kHz –1619mA RESET high–1517mA Reference Voltage V LCAP4.755.0 5.25V Ref. Volt. Load Regulation ∆V LCAP(∆ILCAP)I LCAP = 0 to -2 mA –1025mV Output VoltageV CCOUTV BB = 28 V10.81213.2V Output Voltage Regulation∆V CCOUT(∆ICCOUT)V BB = 28 V, I CCOUT = 0 to -10 mA––25mV Digital Logic LevelsLogic Input Voltage V IH 2.0––V V IL ––0.8V Logic Input CurrentI IH V IH = 2 V –<1.010µA I ILV IL = 0.8 V-70–-130µA Gate DriveLow-Side Output Voltage V GLxH 9.510.511.5V V GLxL I GLx = 1 mA––0.30V High-Side Output Voltage V GHxH 9.010.511.5V V GHxL I GHx = 1 mA ––0.25V Low-Side Output t rGLx 1 V to 8 V –50–ns Switching Time t fGLx 8 V to 1 V –40–ns High-Side Output t rGHx 1 V to 8 V –100–ns Switching Time t fGHx 8 V to 1 V –100–ns DEAD Timet DEADI DEAD = 10 µA –3000–ns (Source OFF to Sink ON)I DEAD = 215 µA –180–nsContinued —NOTES: 1.Typical Data is for design information only.2.Negative current is defined as coming out of (sourcing) the specified device terminal.115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-50003933THREE-PHASE POWER MOSFET CONTROLLERELECTRICAL SPECIFICATIONS at T A = 25°C, V BB = V CCOUT = 12 V, C load = 0.001 µF, C boot = 0.047 µF (unless noted otherwise), continued.LimitsParameterSymbolConditions MinTypMaxUnitsBootstrap CapacitorBootstrap Charge Current I Cx 50100150mA Bootstrap Output Voltage V Cx Reference Sx9.510.511.5V Leakage CurrentI Cx High side switched high, Sx = V BB–1520µA Current LimitOffset Voltage V io –0±5.0mV Input bias current I SENSE ––-1.0µA RC Charge Current I RC 8509451040µA RC Voltage Threshold V RCL 1.0 1.1 1.2V V RCH 2.73.0 3.2V PWM frequency Rangef PWM Operating 20–100kHz Protection CircuitryUndervoltage Threshold UVLO Increasing V BB 9.710.210.7V Decreasing V BB 9.35–10.35V Boot-Strap Capacitor Volt.V CxSx V BB = 12 V 9.5––V High-Side Gate-Source Volt.V GHxSx – 6.3–V Fault Output VoltageV FAULT I O = 1 mA––0.8V Brake FunctionBrake Cap. Supply Current I BRKCAP V BB = 8 V, BRKSEL ≥ 2 V –30–µA Low-Side Gate VoltageV GLxHV BB = 0, BRKCAP = 8 V–6.6–VNOTES: 1.Typical Data is for design information only.2.Negative current is defined as coming out of (sourcing) the specified device terminal.3933THREE-PHASE POWER MOSFET CONTROLLERTerminalName1PGND 2RESET 3GLC 4SC 5GHC 6CC 7GLB 8SB 9GHB 10CB 11GLA 12SA 13GHA 14CA 15V CCOUT 16LCAP 17FAULT 18MODE 19V BB 20H121H322H223DIR 24BRAKE 25BRKCAP 26BRKSEL 27PWM 28RC 29SENSE 30REF 31DEAD 32AGNDRESET — A logic input used to enable the device, internally pulled up to V LCAP (+5 V). A logic HIGH will disable the device and force all gate drivers to 0 V, coasting the motor. A logic LOW allows the gate drive to follow commutation logic.This input overrides BRAKE.GLA/GLB/GLC — Low-side, gate-drive outputs for external NMOS drivers. External series-gate resistors (as close aspossible to the NMOS gate) can be used to control the slew rate seen at the power-driver gate, thereby controlling the di/dt and dv/dt of the SA/SB/SC outputs. Each output is designed and specified to drive a 1000 pF load with a rise time of 50 ns.SA/SB/SC — Directly connected to the motor, these terminals sense the voltages switched across the load. These terminals are also connected to the negative side of the bootstrap capaci-tors and are the negative supply connections for the floating high-side drive.GHA/GHB/GHC — High-side, gate-drive outputs for external NMOS drivers. External series-gate resistors (as close aspossible to the NMOS gate) can be used to control the slew rate seen at the power-driver gate, thereby controlling the di/dt and dv/dt of the SA/SB/SC outputs. Each output is designed and specified to drive a 1000 pF load with a rise time of 100 ns.CA/CB/CC — High-side connections for the bootstrap capaci-tors, positive supply for high-side gate drive. The bootstrap capacitor is charged to approximately V CCOUT when theassociated output SA/SB/SC terminal is low. When the output swings high, the voltage on this terminal rises with the output to provide the boosted gate voltage needed for n-channel power FETs.Terminal Descriptionscontinued next page115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-50003933THREE-PHASE POWER MOSFET CONTROLLERFAULT — Open-drain output to indicate fault condition; will go active high for any of the following:1 – invalid HALL input code,2 – high-side, gate-source voltage less than 7 V,3 – bootstrap capacitor not sufficiently charged, or4 – under-voltage condition detected at V CCOUT .The fault state for gate-source and bootstrap monitors are cleared at each commutation. If the motor has stalled, then the fault can only be cleared by toggling the RESET terminal or power-up sequence.MODE — A logic input to set current-decay method, internally pulled up to V LCAP (+5 V). When in slow-decay mode (logic HIGH), only the high-side FET is switched open during a PWM OFF cycle. The fast-decay mode (logic LOW) switches both the source and sink FETs.H1/H2/H3 — Hall-sensor inputs; internally pulled up to V LCAP (+5 V). Configured for 120° electrical spacing.DIR — A logic input to reverse rotation, see commutation logic table. Internally pulled up to V LCAP (+5 V).BRAKE — A logic input to short out the motor windings for a braking function. A logic HIGH will turn ON the low-side FETs, turn OFF the high-side FETs. Internally pulled up to V LCAP (+5 V). The braking torque applied will depend on the speed.BRKCAP — Connection for reservoir capacitor. This terminal is used to provide a positive power supply for the sink-drive outputs for a power-down condition. This will allow predict-able braking, if desired. A blocking diode to V CCOUT is re-quired. A 4.7 µF capacitor will provide 6.5 V gate drive for 300 ms. If a power-down braking option is not needed(BRKSEL = LOW) then this terminal should be tied to V CCOUT .BRKSEL — A logic input to enable/disable braking on power-down condition. Internally pulled up to V LCAP (+5 V). If held low, the motor will coast on a power-down condition.PWM — Speed control input, internally pulled up to V LCAP(+5 V). A logic LOW turns OFF all drivers, a logic HIGH will turn ON selected drivers as determined by H1/H2/H3 input logic. Holding the terminal high allows speed/torque control solely by the current-limit circuit via REF analog voltage command.RC — An analog input used to set the fixed off time with an external resistor (R T ) and capacitor (C T ). The t blank time is controlled by the value of the external capacitor (see Applica-tions Information). As a rule, the fixed off time should not be less than 10 µs. The resistor should be in the range of 10 k Ω to 100 k Ω.SENSE — An analog input to the current-limit comparator.A voltage representing load current appears on this terminal during ON time, when it reaches REF voltage, the comparator trips and load current decays for the fixed off-time interval.Voltage transients seen at this terminal when the drivers turn ON are ignored for time t blank .REF — An analog input to the current-limit comparator.Voltage applied here sets the peak load current.I peak = V REF /R S .V CCOUT — A regulated 12 V output; supply for low-side gate drive and bootstrap capacitor charge circuits. It is good practice to connect a decoupling capacitor from this terminal to AGND,as close to the device terminals as possible. The terminal should be shorted to V BB for 12 V applications.V BB — The A3933 supply voltage. It is good practice toconnect a decoupling capacitor from this terminal to AGND, as close to the device terminals as possible. This terminal should be shorted to V CCOUT for 12 V applications.LCAP — Connection for decoupling capacitor for the internal 5 V reference. This terminal can source no more than 2 mA.DEAD — An analog input. A resistor between DEAD and LCAP is selected to adjust turn-off to turn-on time. This delay is needed to prevent shoot-through in the external power FETs.The allowable resistor range is 20 k Ω to 430 k Ω, whichconverts to deadtime of 210 ns to 2.1 µs, using the following equation:t DEAD = (6.75 x 10-12 x R DEAD ) + (75 x 10-9).AGND — The low-level (analog) reference point for the A3933.PGND — The reference point for all low-side gate drivers.Terminal Descriptions (cont’d)3933 THREE-PHASE POWER MOSFET CONTROLLER Commutation Truth TableLogic Inputs Driver OutputsH1H2H3DIR GLA GLB GLC GHA GHB GHC SA SB SCH L H H L L H H L L H Z L H L L H L L H L H L Z H L H H L H H L L L H L L H Z L H L H H L L L L H L Z H L H H H L H L L L H Z L H L L H H L H L H L L H L Z H L H L H L L L L H L Z H H L L L L H L L L H Z L H H H L L L H L H L L H L Z L H L L L L H H L L H Z L L H H L L L H L H L Z H L L L H L H L L L H L L H ZInput LogicMODE PWM RESET Mode OperationL L L Fast decay PWM chop mode, current decayL H L Fast decay Peak current limit, selected drivers ONH L L Slow decay PWM chop mode. current decayH H L Slow decay Peak current limit, selected drivers ONX X H Coast All gate drive outputs OFF, clear fault logicBrake ControlBRAKE BRKSEL Normal Operation Under Voltage or Power Loss ConditionL L Normal run mode Coast, all gate drive outputs OFFL H Normal run mode Dynamic brake, all sink gate drives ONH L Dynamic brake, all sink gate drives ON Coast, all gate drive outputs OFFH H Dynamic brake, all sink gate drives ON Dynamic brake, all sink gate drives ONL = Low Level, H = High Level, X = Don’t Care, Z = High Impedance115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-50003933THREE-PHASE POWER MOSFET CONTROLLERApplications Informationbootstrap capacitor. When the bootstrap capacitor has been properly charged, the high side is turned back ON. The circuit will allow three faults of this type within one commutation cycle before signaling a fault and coast the motor (all gate outputs go low).2)Bootstrap Monitor. The bootstrap capacitor is charged whenever a sink-side MOSFET is ON, Sx output goes low, and the load current recirculates. This happens constantly during normal operation. A 60 µs timer is started at the beginning of this cycle and the capacitor is charged with typically 100 mA.The bootstrap capacitor voltage is clamped at approximately 87% of V CCOUT . If the capacitor is not charged to the clamp voltage in 60 µs, a fault is signaled and the motor will coast.3)Undervoltage. The internal V CCOUT regulator supplies the low-side gate driver and the bootstrap charge current. It is critical to ensure that the voltages are at a proper level before enabling any of the outputs. The undervoltage circuit is active during power up and will force a motor coast condition until V CCOUT is greater than approximately 10 V.4)Hall Invalid. Illegal codes for the HALL inputs (000 or 111) will force a fault and coast the motor.Faults are cleared at the beginning of each commutation. If a stalled motor results from a fault, the fault can only be cleared by toggling the RESET terminal or by a power-up sequence.Current Control. Internal fixed off-time PWM circuitry is implemented to limit load current to a desired value. The external sense resistor combined with the applied analog voltage to REF terminal will set the peak current level approximatelyI TRIP ≈ V REF /R S .After the peak level is reached, the sense comparator trips and the load current will decay for a fixed off time.An external resistor (R T ) and capacitor (C T ) are used to set the fixed off-time period (t off = R T x C T ). The t off should be in the range of 10 µs to 50 µs. Longer values for t off can result in audible noise problems.Torque control can be implemented by varying the REF input voltage as long as the PWM input stays high. If direct control of the torque/current is desired by PWM input, a voltage can be applied to the REF input to set an absolute maximum current limit.Bootstrap Capacitor Selection. The high-side bootstrap circuit operates on a charge-transfer principle. The gate charge (Q g ) specification of the external power MOSFET must betaken into consideration. The bootstrap capacitor must be large enough to turn on the MOSFET without losing significant gate voltage. If the bootstrap capacitor is too large, it would take too long to charge up during the off portion of the PWM cycle. The capacitor value must be selected with both of these constraints in mind.1)Minimum bootstrap capacitor value to transfer charge. The charge on the bootstrap capacitor should be 20x greater than the gate charge (Q g ) of the power MOSFET.Example: For Q g = 0.025 µC, selectC boot = 20 x Q g /10.5 V = 0.047 µF.Check for maximum V g drop at turn on: dq = C boot x dV g , where Q g = dq.dV g = dq/C boot = 0.025 µC/0.047 µF = 532 mV.2)Calculate minimum PWM “OFF” cycle with C boot = 0.047 µF.dt = r o x C boot x ln(0.036/[Q g /C boot + 0.036])where r o = 20 ohms, the equivalent internal series resistance of the bootstrap capacitor monitor circuit.The sink-side MOSFET will be held OFF for this minimum time such that the bootstrap capacitor can be recharged independently of the PWM input frequency.The above equation is valid for PWM cycles after the bootstrap capacitor has been charged once. For the first cycle after a motor phase commutates from Hi-Z to GHx ON, or during the first charging cycle at power-up, the circuit will ignore PWM signals until it has been charged.The time required to charge up at power up and at commutation change is approximately:t = C boot x 7 V/0.1 AProtection Circuitry. The A3933 will protect the external MOSFETs by shutting down the gate drive if any of the following conditions are detected:1)Gate Source Monitor (high side only). The voltage on the GHx terminals must stay 7 V higher than the source. If this voltage droops below the threshold, the high side turns OFF,and the low-side gate will turn ON in an attempt to recharge the3933 THREE-PHASE POWER MOSFET CONTROLLER Applications Information (cont’d)PWM Blank. The capacitor (C T) also serves as the means to set the blank time duration. After the off time expires, the selected gates are turned back ON. At this time, large current transients can occur during the reverse recovery time (t rr) of the intrinsic body diodes of the external MOSFETs. To prevent the current-sense comparator from thinking the current spikes are a real overcurrent event, the comparator is blanked:t blank = 1.9 x C T/(1 mA-2/R T)The user must ensure that C T is large enough to cover the current-spike duration.Load Current Recirculation. If MODE has been set for slow decay, the high-side (source) driver will turn OFF forcing the current to recirculate through the pair of sink MOSFETs. If MODE has been selected for fast decay, both the selected high-and low-side gates are turned OFF, which will force the current to recirculate through one sink MOSFET and the high-side clamp diode. Synchronous rectification (only on the low side) allows current to flow through the MOSFET, rather than the clamp diode, during the decay time. This will minimize power loss during the off period. It is important to take into account that, when switching, the intrinsic diodes will conduct during the adjustable deadtime.Braking. The A3933 will dynamically brake by forcing all sink-side MOSFETs ON. This will effectively short out the BEMF. During braking, the load current can be approximated by:I BRAKE = V BEMF/R LPower Loss Brake. The BRKCAP and BRKSEL terminals provide a power-down braking option. By applying a logic level to input BRKSEL, the system can control if the motor is dynamically braked or is allowed to coast during an undervoltage event. The reservoir capacitor on the BRKCAP terminal provides the power to hold the sink-side gates ON after supply voltage is lost. A logic high on BRKSEL will brake the motor, a logic low and it will coast.Layout. Careful consideration must be given to PCB layout when designing high-frequency, fast-switching, high-current circuits.1)The analog ground (AGND), the power ground (PGND), and the high-current return of the external MOSFETs (the negative side of the sense resistor) should return separately to the negative side of the motor supply filtering capacitor. This will minimize the effect of switching noise on the device logic and analog reference.2)Minimize stray inductances by using short, wide copper runs at the drain and source terminals of all power MOSFETs. This includes motor lead connections, the input power buss, and the common source of the low-side power MOSFETs. This will minimize voltages induced by fast switching of large load currents.3)Kelvin connect the SENSE terminal PC trace to the positive side of the sense resistor.115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-50003933THREE-PHASE POWER MOSFET CONTROLLERDimensions in Inches(controlling dimensions)Dwg. MA-006-32 in5NOTES: 1. Lead spacing tolerance is non-cumulative.2. Exact body and lead configuration at vendor’s option within limits shown3933THREE-PHASE POWER MOSFET CONTROLLERDimensions in Millimeters(for reference only)Dwg. MA-006-32 mm5201413NOTES: 1. Lead spacing tolerance is non-cumulative.2. Exact body and lead configuration at vendor’s option within limits shownThe products described here are manufactured under one or more U.S.patents or U.S. patents pending.Allegro MicroSystems, Inc. reserves the right to make, from time totime, such departures from the detail specifications as may be required topermit improvements in the performance, reliability, or manufacturabilityof its products. Before placing an order, the user is cautioned to verify thatthe information being relied upon is current.Allegro products are not authorized for use as critical components inlife-support devices or systems without express written approval.The information included herein is believed to be accurate and reliable.However, Allegro MicroSystems, Inc. assumes no responsibility for its use;nor for any infringement of patents or other rights of third parties whichmay result from its use.115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-********THREE-PHASE POWER MOSFET CONTROLLERMOTOR DRIVERS FunctionOutput Ratings*Part Number †INTEGRATED CIRCUITS FOR BRUSHLESS DC MOTORS3-Phase Power MOSFET Controller —28 V 39333-Phase Power MOSFET Controller —50 V 39323-Phase Power MOSFET Controller —50 V 76002-Phase Hall-Effect Sensor/Driver 400 mA 26 V 3626Bidirectional 3-Phase Back-EMF Controller/Driver ±600 mA 14 V 89062-Phase Hall-Effect Sensor/Driver 900 mA 14 V 36253-Phase Back-EMF Controller/Driver ±900 mA 14 V 8902–A3-Phase Controller/Drivers ±2.0 A 45 V 2936 & 2936-120INTEGRATED BRIDGE DRIVERS FOR DC AND BIPOLAR STEPPER MOTORSDual Full Bridge with Protection & Diagnostics ±500 mA 30 V 3976PWM Current-Controlled Dual Full Bridge ±650 mA 30 V 3966PWM Current-Controlled Dual Full Bridge ±650 mA 30 V 3968PWM Current-Controlled Dual Full Bridge ±750 mA 45 V 2916PWM Current-Controlled Dual Full Bridge ±750 mA 45 V 2919PWM Current-Controlled Dual Full Bridge ±750 mA 45 V 6219PWM Current-Controlled Dual Full Bridge ±800 mA 33 V 3964PWM Current-Controlled Full Bridge ±1.3 A 50 V 3953PWM Current-Controlled Dual Full Bridge ±1.5 A 45 V 2917PWM Current-Controlled Dual Full Bridge ±1.5 A 45 V 2918PWM Current-Controlled Microstepping Full Bridge ±1.5 A 50 V 3955PWM Current-Controlled Microstepping Full Bridge ±1.5 A 50 V 3957PWM Current-Controlled Dual DMOS Full Bridge ±1.5 A 50 V 3972Dual Full-Bridge Driver ±2.0 A 50 V 2998PWM Current-Controlled Full Bridge ±2.0 A 50 V 3952DMOS Full Bridge PWM Driver ±2.0 A 50 V 3958Dual DMOS Full Bridge ±2.5 A 50 V 3971UNIPOLAR STEPPER MOTOR & OTHER DRIVERSVoice-Coil Motor Driver ±500 mA 6 V 8932–A Voice-Coil Motor Driver ±800 mA 16 V 8958Unipolar Stepper-Motor Quad Drivers 1 A 46 V 7024 & 7029Unipolar Microstepper-Motor Quad Driver 1.2 A 46 V 7042Unipolar Stepper-Motor Translator/Driver 1.25 A 50 V 5804Unipolar Stepper-Motor Quad Driver 1.8 A 50 V 2540Unipolar Stepper-Motor Quad Driver 1.8 A 50 V 2544Unipolar Stepper-Motor Quad Driver 3 A 46 V 7026Unipolar Microstepper-Motor Quad Driver 3 A 46 V 7044*Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits or over-current protection voltage limits. Negative current is defined as coming out of (sourcing) the output.†Complete part number includes additional characters to indicate operating temperature range and package style.Also, see 3175, 3177, 3235, and 3275 Hall-effect sensors for use with brushless dc motors.。

ZSSC3135AA2T中文资料(ZMDI)中文数据手册「EasyDatasheet - 矽搜」

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数据表
修订1.00 2011 /月
ZSSC3135
传感器信号调理器,用于压阻式桥传感器
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ZSSC3135
传感器信号调理器,用于压阻式桥传感器
简要描述 ;简介
所述ZSSC3135是ZSSC313x成员 CMOS产品系列集成电路专为汽车/工业传感器应用系统蒸发散.所有家人都非常适合highly-
2电路描述....................................................................................................................................... 11 2.1.信号流........................................................................................................................................... 11 2.2.应用模式................................................................................................................................ 12 2.3.模拟前端（AFE） ....................................................................................................................... 12 2.3.1.可编程增益放大器（PGA）............................................ ................................................. 12 2.3.2.偏移补偿..................................................................................................................... 13 2.3.3.测量周期....................................................................................................................... 13 2.3.4.模拟 - 数字转换器............................................................................................................ 15 2.4.温度测量.................................................................................................................. 16 2.5.系统控制和调节计算............................................. ......................................... 16 2.5.1.操作Modes............................................................................................................................ 16 2.5.2.启动阶段................................................................................................................................ 16 2.5.3.空调计算................................................................................................................ 17 2.6.模拟输出AOUT ............................................................................................................................ 17 2.7.串行数字接口.......................................................................................................................... 18 2.8.故障防护护功能,看门狗和错误检测........................................... .................................... 18 2.9.高电压,反向极性防护护和短路防护护......................................... ...................... 18

MCP73871中文文档

18, 19 2 6
CE
IN
IN
IN
OUT
系统负载
7 STAT2 8 3 STAT1 LBO SEL PROG2 TE CE
单节锂离子电池
低低低低
高 4 高高高 9 17
PROG3
12 RPROG3
VSS 10, 11, EP
DS22090A_CN 第 2 页
2009 Microchip Technology Inc.
2009 MicrochiБайду номын сангаас Technology Inc.
DS22090A_CN 第 1 页
MCP73871
封装类型
MCP73871 20 引脚 QFN VBAT_SENSE 15 VBAT 外露的金属焊盘 VSS 14 VBAT 13 PROG1 12 PROG3 11 VSS 6 PG 7 STAT2 8 STAT1 / LBO 9 TE 10 VSS
VREG + 0.25V VREG + 0.17V — 4.121 4.221 4.372 4.422 +0.5 +0.75 0.20 0.18 — — 110 1100 100 500
V V mV V V V % % %/V % dB dB mA mA mA mA
VDD=[VREG( 典型值 )+1V] IOUT=10 mA TA=-5°C 至 +55°C TA= +25°C TA= -5°C 至 +55°C VDD=[VREG( 典型值 )+1V] 至 6V IOUT=10 mA IOUT=10 mA 至 150 mA VDD= [VREG( 典型值 )+1V] IOUT=10 mA， 1 kHz IOUT=10 mA， 10 kHz PROG1 = 10 kΩ PROG1 = 1 kΩ， TA=-5°C 至 +55°C， SEL = 高 PROG2 = 低， SEL = 低，（注 2） PROG2 = 高， SEL = 低，（注 2） TA= -5°C 至 +55°C

7383-G1C3-ATVA中文资料

元器件交易网EVERLIGHT ELECTRONICS CO.,LTD.Technical Data Sheet 7383/G1C3-ATVA/X/MSFeatures˙Popular T-1 3/4 diameter package. ˙Choice of various viewing angles. ˙Available on tape and reel. ˙Reliable and robust. ˙ESD-withstand voltage: up to 4KV. ˙The product itself will remain within RoHS compliant version. ˙UV resistant epoxyDescriptions˙The series is specially designed for applications requiring higher brightness. ˙The LED lamps are available with different colors, intensities, epoxy colors, etc. ˙Superior performance in outdoor environmentApplications˙Color Graphic Signs ˙Message boards ˙Variable message signs (VMS) ˙Commercial outdoor advertisingDevice Selection GuideLED Part No.7383/G1C3-ATVA/MS 7383/G1C3-ATVA/P/MSChip Mterial InGaN InGaNEmitted Color Super Green Super GreenLens Color Water Clear Water ClearStopper No YesEverlight Electronics Co., Ltd. Device Number : DLE-738-037http\\: Prepared date:05-26-2006Rev :1Page: 1 of 8Prepared : Grace Shen元器件交易网EVERLIGHT ELECTRONICS CO.,LTD.Technical Data Sheet 7383/G1C3-ATVA/X/MSPackage DimensionsStopper type No Stopper typeNotes: ˙All dimensions are in millimeters, tolerance is 0.25mm except being specified. ˙Lead spacing is measured where the lead emerges from the package. ˙Protruded resin under flange is 1.5mm Max LED.Everlight Electronics Co., Ltd. Device Number : DLE-738-037http\\: Prepared date:05-26-2006Rev :1Page: 2 of 8Prepared : Grace Shen元器件交易网EVERLIGHT ELECTRONICS CO.,LTD.Technical Data Sheet 7383/G1C3-ATVA/X/MSAbsolute Maximum Ratings (Ta=25℃)Parameter Forward Current Pulse Forward Current*1 Operating Temperature Storage Temperature Electrostatic Discharge*2Symbol IF IFP Topr Tstg ESD Tsol Pd Iz VRRating 30 100 -40 ~ +85 -40 ~ +100 4K 260 ±5 120 100 5Units mA mA ℃ ℃ V ℃ mW mA VSoldering Temperature Power Dissipation Zener Reverse Current Reverse VoltageNotes: *1:IFP Conditions--Pulse Width≦10msec and Duty≦1/10. *2:Soldering time≦5 seconds.Electro-Optical Characteristics (Ta=25℃)Parameter Forward Voltage Zener Reverse Voltage Luminous Intensity Viewing Angle Peak Wavelength Dominant Wavelength Spectrum Radiation Bandwidth Reverse Current Symbol VF Vz IV 2θ1/2 λp λd Δλ IR Condition IF=20mA IZ=5mA IF=20mA IF=20mA IF=20mA IF=20mA IF=20mA VR=5V Min. 2.8 5.2 7150 ----524 --Typ. ---30 518 528 35 -Max. 3.6 -14250 ----532 -50 Units V V mcd deg nm nm nm μAEverlight Electronics Co., Ltd. Device Number : DLE-738-037http\\: Prepared date:05-26-2006Rev :1Page: 3 of 8Prepared : Grace Shen元器件交易网EVERLIGHT ELECTRONICS CO.,LTD.Technical Data Sheet 7383/G1C3-ATVA/X/MSRank Combination (IF=20mA)Rank Luminous Intensity T 7150~9000 U 9000~11250 V 11250~14250Unit: :mcd*Measurement Uncertainty of Luminous Intensity: ±15%Rank Forward Voltage0 2.8~3.01 3.0~3.22 3.2~3.43 3.4~3.6Unit:V*Measurement Uncertainty of Forward Voltage: ±0.1VRank Dominant Wavelength12Unit:nm524~528 528~532 *Measurement Uncertainty of Dominant Wavelength ±1.0nm*The quantity ratio of the ranks is decided by EVERLIGHT.Everlight Electronics Co., Ltd. Device Number : DLE-738-037http\\: Prepared date:05-26-2006Rev :1Page: 4 of 8Prepared : Grace Shen元器件交易网EVERLIGHT ELECTRONICS CO.,LTD.Technical Data Sheet 7383/G1C3-ATVA/X/MSTypical Electro-Optical Characteristics CurvesEverlight Electronics Co., Ltd. Device Number : DLE-738-037http\\: Prepared date:05-26-2006Rev :1Page: 5 of 8Prepared : Grace Shen元器件交易网EVERLIGHT ELECTRONICS CO.,LTD.Technical Data Sheet 7383/G1C3-ATVA/X/MSPacking Quantity Specification1.500PCS/1Bag，5Bags/1Box 2.10Boxes/1CartonLabel Form SpecificationEVERLIGHT CPN: P/N: 7383/G1C3-ATVA/X/MS QTY： CAT: HUE: LOT NO： REF: MADE IN TAIWAN CPN: Customer’s Production Number P/N : Production Number QTY: Packing Quantity CAT: Ranks of Luminous Intensity and Forward Voltage HUE: Ranks of Dominant Wavelength REF: Reference LOT No: Lot Number MADE IN TAIWAN: Production PlaceEverlight Electronics Co., Ltd. Device Number : DLE-738-037http\\: Prepared date:05-26-2006Rev :1Page: 6 of 8Prepared : Grace Shen元器件交易网EVERLIGHT ELECTRONICS CO.,LTD.Technical Data Sheet 7383/G1C3-ATVA/X/MSNotes 1. Above specification may be changed without notice. EVERLIGHT will reserve authority on material change for above specification. 2. When using this product, please observe the absolute maximum ratings and the instructions for using outlined in these specification sheets. EVERLIGHT assumes no responsibility for any damage resulting from use of the product which does not comply with the absolute maximum ratings and the instructions included in these specification sheets. 3. These specification sheets include materials protected under copyright of EVERLIGHT corporation. Please don’t reproduce or cause anyone to reproduce them without EVERLIGHT’s consent. 4. Below the zener reference voltage Vz, all the current flows through LED and as the voltage rises to Vz, the zener diode “breakdown." If the voltage tries to rise above Vz current flows through the zener branch to keep the voltage at exactly Vz. 5. When the LED is connected using serial circuit, if either piece of LED is no light up but current can’t flow through causing others to light down. In new design, the LED is parallel with zener diode. if either piece of LED is no light up but current can flow through causing others to light up.Everlight Electronics Co., Ltd. Device Number : DLE-738-037http\\: Prepared date:05-26-2006Rev :1Page: 7 of 8Prepared : Grace Shen元器件交易网EVERLIGHT ELECTRONICS CO.,LTD.Technical Data Sheet 7383/G1C3-ATVA/X/MS6. Soldering ConditionCareful attention should be paid during soldering. When soldering, leave more then 3mm from solder joint to case, and soldering beyond the base of the tie bar is recommended. Avoiding applying any stress to the lead frame while the LEDs are at high temperature particularly when soldering. Recommended soldering conditions: Hand Soldering Temp. at tip of iron Soldering time Distance 400℃ Max. (30W Max.) 3 sec Max. 3mm Min.(From solder joint to case) Preheat temp. Bath temp. Bath time. Distance DIP Soldering 100℃ Max. (60 sec Max.) 265 Max. 5 sec Max. 3mm Min.EVERLIGHT ELECTRONICS CO., LTD. Office: No 25, Lane 76, Sec 3, Chung Yang Rd, Tucheng, Taipei 236, Taiwan, R.O.CTel: 886-2-2267-2000, 2267-9936 Fax: 886-2267-6244, 2267-6189, 2267-6306 http:\\Everlight Electronics Co., Ltd. Device Number : DLE-738-037http\\: Prepared date:05-26-2006Rev :1Page: 8 of 8Prepared : Grace Shen。

TDA7385,E-TDA7385,TDA7385H, 规格书,Datasheet 资料

This is information on a product in full production.July 2012Doc ID 8160 Rev 51/17TDA73854 x 42 W quad bridge car radio amplifierDatasheet − production dataFeatures■High output power capability:– 4 x 42 W / 4 Ω max.– 4 x 23 W / 4 Ω @ 14.4 V , 1 kHz, 10 %■Clipping detector ■Low distortion ■Low output noise ■Standby function ■Mute function■Automute at min. supply voltage detection ■Diagnostics facility for: –Clipping–Out to GND short –Out to V S short –Thermal shutdown■Low external component count:–Internally fixed gain (26 dB)–No external compensation –No bootstrap capacitors■Protections:–Output short circuit to GND, to V S , across the load–Very inductive loads–Overrating chip temperature with soft thermal limiter–Load dump voltage –Fortuitous open GND–ESDDescriptionThe TDA7385 is an AB class audio poweramplifier, packaged in Flexiwatt 25 and designed for high end car radio applications.Based on a fully complementary PNP/NPN configuration, the TDA7385 allows a rail to rail output voltage swing with no need of bootstrap capacitors. The extremely reduced boundary components count allows very compact sets.The on-board clipping detector simplifies gain compression operations. The fault diagnostics makes it possible to detect mistakes during car-radio assembly and wiring in the car.Table 1.Device summaryOrder code Package Packing TDA7385Flexiwatt25Tube E-TDA7385(1)1.Device in ECOPACK® package (see Section 4: Package information on page 15).Flexiwatt25TubeContents TDA7385Contents1Block and pin connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.1Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.2Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.3Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.4PCB and component layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.5Electrical characteristic curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.1Biasing and SVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.2Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.3Standby and muting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.4Diagnostics facility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.5Stability and layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162/17Doc ID 8160 Rev 5TDA7385List of tables List of tablesTable 1.Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2.Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3.Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 4.Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 5.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Doc ID 8160 Rev 53/17List of figures TDA7385 List of figuresFigure 1.Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2.Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3.Standard test and application circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure ponents and top copper layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 5.Bottom copper layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6.Quiescent current vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 7.Quiescent output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 8.Output power vs. supply voltage (4Ω). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 9.Distortion vs. output power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 10.Distortion vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 11.Supply voltage rejection vs. frequency by varying C6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 12.Output noise vs. source resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 13.Power dissipation and efficiency vs. output power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 14.Input/output biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 15.Diagnostics circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 16.Clipping detection waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 17.Diagnostics waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 18.Fault detection circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 19.Flexiwatt25 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4/17Doc ID 8160 Rev 5TDA7385Block and pin connection diagrams 1 Block and pin connection diagramsDoc ID 8160 Rev 55/17Electrical specifications TDA73856/17Doc ID 8160 Rev 52 Electrical specifications2.1Absolute maximum ratings2.2 Thermal data2.3 Electrical characteristicsV S = 14.4 V; f = 1 kHz; R g = 600 Ω; R L = 4 Ω;T amb = 25 °C; Refer to the test and applicationdiagram (Figure 3), unless otherwise specified.Table 2.Absolute maximum ratingsSymbol ParameterValue Unit V S Operating supply voltage 18V V S (DC)DC supply voltage28V V S (pk)Peak supply voltage (t = 50 ms)50V I O Output peak current:Repetitive (duty cycle 10 % at f = 10 Hz)Non repetitive (t = 100 µs) 4.55.5A A P tot Power dissipation, (T case = 70 °C)80W T j Junction temperature 150°C T stgStorage temperature– 55 to 150°CTable 3.Thermal dataSymbol ParameterValue Unit R th j-caseThermal resistance junction-to-casemax.1°C/WTable 4.Electrical characteristicsSymbol ParameterTest conditionMin.Typ.Max.Unit I q1Quiescent current --180300mA V OS Output offset voltage ---100mV G vVoltage gain-252627dBP oOutput power THD = 10%THD = 1%THD = 10%; V S = 13.2 V THD = 1%; V S = 13.2 V 2116.5171423192016-WP o max.Max. output power (1)V S = 14.4 V 3335-W V S = 15.2 V -42-W THDDistortionP o = 4 W-0.040.3%TDA7385Electrical specificationsDoc ID 8160 Rev 57/17e No Output noise"A" WeightedBw = 20 Hz to 20 kHz -5065-150μV μV SVR Supply voltage rejection f = 100 Hz 5065-dB f cl Low cut-off frequency --20-Hz f ch High cut-off frequency -75-kHz R i Input impedance -70100-k ΩC T Cross talk f = 1 kHz 5070-dB I SB Standby current consumptionVs tandby =0 V --15µA V SB out Standby out threshold voltage(Amp: on)3.5--V V SB IN Standby in threshold voltage (Amp: off)-- 1.5V A M Mute attenuationV O = 1Vrms 8090-dB V M out Mute out threshold voltage (Amp: play) 3.5--V V M in Mute in threshold voltage (Amp: mute)-- 1.5V I m (L)Muting pin currentV MUTE = 1.5V (source current)51016μA I CDOFF Clipping detector "off" outputaverage currentTHD = 1% (1)-100-μA I CDONClipping detector "on" outputaverage currentTHD = 10% (1)100240350μA1.Diagnostics output pulled-up to 5 V with 10 k Ω series resistor.Table 4.Electrical characteristics (continued)Symbol ParameterTest conditionMin.Typ.Max.UnitElectrical specifications TDA73858/17Doc ID 8160 Rev 52.4 PCB and component layoutReferred to Figure 3: Standard test and application circuit .Figure 4.Components and top copper layerFigure 5.Bottom copper layerTDA7385Electrical specificationsDoc ID 8160 Rev 59/172.5Electrical characteristic curvesFigure 6.Quiescent current vs. supplyFigure 7.Quiescent output voltage vs. Figure 8.Output power vs. supply voltageFigure 9.Distortion vs. output powerFigure 10.Distortion vs. frequencyFigure 11.Supply voltage rejection vs.Electrical specifications TDA7385 Figure 12.Output noise vs. source resistance Figure 13.Power dissipation and efficiency10/17Doc ID 8160 Rev 5TDA7385Application hintsDoc ID 8160 Rev 511/173 Application hintsReferred to the circuit of Figure 3.3.1 Biasing and SVRAs shown by Figure 14, all the TDA7385’s main sections, such as Inputs, Outputs AND AC-GND (pin 16) are internally biased at half supply voltage level (Vs/2), which is derived fromthe Supply Voltage Rejection (SVR) block. In this way no current flows through the internal feedback network. The AC-GND is common to all the 4 amplifiers and represents the connection point of all the inverting inputs.Both individual inputs and AC-GND are connected to Vs/2 (SVR) by means of 100 k Ω resistors.To ensure proper operation and high supply voltage rejection, it is of fundamentalimportance to provide a good impedance matching between Inputs and AC-GROUND terminations. This implies that C 1, C 2, C 3, C 4, C 5 capacitors have to carry the same nominal value and their tolerance should never exceed ± 10 %.Besides its contribution to the ripple rejection, the SVR capacitor governs the turn ON/OFF time sequence and, consequently, plays an essential role in the pop optimization during ON/OFF transients. To conveniently serve both needs, its minimum recommended value is 10µF .3.2 Input stageThe TDA7385’s inputs are ground-compatible and can stand very high input signals(± 8 Vpk) without any performances degradation.If the standard value for the input capacitors (0.1 µF) is adopted, the low frequency cut-off will amount to 16 Hz.Application hints TDA738512/17Doc ID 8160 Rev 53.3 Standby and mutingStandby and muting facilities are both CMOS-compatible. If unused, a straight connection toVs of their respective pins would be admissible. Conventional low-power transistors can be employed to drive muting and stand-by pins in absence of true CMOS ports ormicroprocessors. R-C cells have always to be used in order to smooth down the transitions for preventing any audible transient noises.Since a DC current of about 10 µA normally flows out of pin 22, the maximum allowable muting-series resistance (R 2) is 70 k Ω, which is sufficiently high to permit a muting capacitor reasonably small (about 1µF).If R 2 is higher than recommended, the involved risk will be that the voltage at pin 22 may rise to above the 1.5 V threshold voltage and the device will consequently fail to turn OFF when the mute line is brought down.About the stand-by, the time constant to be assigned in order to obtain a virtually pop-free transition has to be slower than 2.5V/ms.3.4 Diagnostics facilityThe TDA7385 is equipped with a diagnostics circuitry able to detect the following events:●Clipping in the output stage●overheating (thermal shut-down proximity)●Output misconnections (OUT -GND and OUT -V S shorts)Diagnostics information is available across an open collector output located at pin 25(Figure 15) through a current sinking whenever at least one of the above events is recognized.Among them, the Clipping Detector acts in a way to output a signal as soon as one or more power transistors start being saturated.As a result, the clipping-related signal at pin 25 takes the form of pulses, which are perfectly synchronized with each single clipping event in the music program and reflect the same duration time (Figure 16). Applications making use of this facility usually operate afiltering/integration of the pulses train through passive R-C networks and realize a volume (or tone bass) stepping down in association with microprocessor-driven audioprocessors. The maximum load that pin 25 can sustain is 1 k Ω.Due to its operating principles, the clipping detector has to be viewed mainly as a power-dependent feature rather than frequency-dependent. This means that clipping state will be immediately signaled out whenever a fixed power level is reached, regardless of the audioTDA7385Application hints frequency. In other words, this feature offers the means to counteract the extremely sound-damaging effects of clipping, caused by a sudden increase of odd order harmonics andappearance of serious inter-modulation phenomena.Another possible kind of distortion control could be the setting of a maximum allowable THDlimit (e.g. 0.5%) over the entire audio frequency range. Besides offering no practicaladvantages, this procedure cannot be much accurate, as the non-clipping distortion is likelyto vary over frequency.In case of Overheating, pin 25 will signal out the junction temperature proximity to thethermal shut-down threshold. This will typically start about 2°C before the thermal shut-down threshold is reached.As various kind of diagnostics information is available at pin 25 (clipping, shorts andoverheating), it may be necessary to operate some distinctions on order to treat each eventseparately. This could be achieved by taking into account the intrinsically different timing ofthe diagnostics output under each circumstance.In fact, clipping will produce pulses normally much shorter than those present under faultyconditions. An example of circuit able to distinguish between the two occurrences is shownby Figure18.3.5 Stability and layout considerationsIf properly layouted and hooked to standard car-radio speakers, the TDA7385 will beintrinsically stable with no need of external compensations such as output R-C cells. Due tothe high number of channels involved, this translates into a very remarkable componentssaving if compared to similar devices on the market.To simplify pc-board layout designs, each amplifier stage has its own power groundexternally accessible (pins 2,8,18,24) and one supply voltage pin for each couple of them.Even more important, this makes it possible to achieve the highest possible degree ofseparation among the channels, with remarkable benefits in terms of cross-talk anddistortion features.About the layout grounding, it is particularly important to connect the AC-GND capacitor (C5)to the signal GND, as close as possible to the audio inputs ground: this will guarantee highrejection of any common mode spurious signals.The SVR capacitor (C6) has also to be connected to the signal GND.Supply filtering elements (C7, C8) have naturally to be connected to the power-ground andlocated as close as possible to the Vs pins.Doc ID 8160 Rev 513/17Application hints TDA7385 Pin 1, which is mechanically attached to the device’s tab, needs to be tied to the cleanestpower ground point in the pc-board, which is generally near the supply filtering capacitors.14/17Doc ID 8160 Rev 5TDA7385Package informationDoc ID 8160 Rev 515/174 Package informationIn order to meet environmental requirements, ST offers these devices in different grades ofECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: .ECOPACK ® is an ST trademark.Revision history TDA738516/17Doc ID 8160 Rev 55 Revision historyTable 5.Document revision historyDate RevisionChanges10-Mar-20011Initial release.13-Nov-20082Document reformatted.Added Features on page 1.Updated Table 4: Electrical characteristics on page 6.Updated Section 4: Package information on page 15.09-Jan-20123Modified Features on page 1;Updated Table 4: Electrical characteristics .14-Jun-20124Updated Features on page 1;Updated Table 4: Electrical characteristics .26-Jul-20125Updated Figure 17: Diagnostics waveforms on page 14.TDA7385Please Read Carefully:Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.All ST products are sold pursuant to ST’s terms and conditions of sale.Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.UNL ESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SAL E ST DISCL AIMS ANY EXPRESS OR IMPL IED WARRANTY WITH RESPECT TO THE USE AND/OR SAL E OF ST PRODUCTS INCL UDING WITHOUT L IMITATION IMPL IED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNL ESS EXPRESSL Y APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.ST and the ST logo are trademarks or registered trademarks of ST in various countries.Information in this document supersedes and replaces all information previously supplied.The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.© 2012 STMicroelectronics - All rights reservedSTMicroelectronics group of companiesAustralia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of AmericaDoc ID 8160 Rev 517/17。

IRF7389TRPBF;IRF7389PBF;中文规格书,Datasheet资料

Min. Typ. Max. Units
Conditions
N-Ch 30 P-Ch -30
V
VGS = 0V, ID = 250µA VGS = 0V, ID = -250µA
N-Ch P-Ch
0.022 0.022
V/°C
Reference to 25°C, ID = 1mA Reference to 25°C, ID = -1mA
IDSS
IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
P-Ch -2.5 A
N-Ch 30
ISM
Pulsed Source Current (Body Diode)
P-Ch -30
VSD
Diode Forward Voltage
N-Ch 0.78 1.0 P-Ch -0.78 -1.0
V
TJ = 25°C, IS = 1.7A, VGS = 0V TJ = 25°C, IS = -1.7A, VGS = 0V

PIC下载地址

PIC18F87J10系列（128K字节Flash）中文数据手册：
/downloads/en/DeviceDoc/39663b_cn.pdf
PIC16F627A/628A/648A中文数据手册：
/downloads/en/DeviceDoc/40044d_cn.pdf
Section 17. 10-Bit A/D Converter
/downloads/en/DeviceDoc/39705a_cn.pdf
Section 19. Comparator Module
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Section 7. Reset
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MCP2515 SPI接口的CAN控制器中文数据手册

FAN7384MX;FAN7384M;中文规格书,Datasheet资料

Symbol
VS VB VHO VDD VIN VCSC VFO dVS/dt PD(2)(3)(4) JA TJ TS Notes:
Parameter
High-side offset voltage VS High-side floating supply voltage VB High-side floating output voltage Low-side and logic-fixed supply voltage Logic input voltage (HIN, LIN, SD) Current sense input voltage Fault output voltage Allowable offset voltage slew rate Power dissipation Thermal resistance, junction-to-ambient Junction temperature Storage temperature
14-SOP
Applications
Motor Inverter Driver Normal Half-Bridge and Full-Bridge Driver Switching Mode Power Supply
1
Ordering Information
Operating Temperature Range
FAN7384 — Half-Bridge Gate-Drive IC
Pin Configuration
LIN SD HIN VDD FO CSC GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VB HO VS NC NC LO VSL

TDA7385中文资料

2/12
25
D94AU117B
Max.
Value 1
Unit °C/W
元器件交易网
TDA7385
ELECTRICAL CHARACTERISTICS (VS = 14.4V; f = 1KHz; Rg = 600Ω; RL = 4Ω; Tamb = 25°C; Refer to the Test and application circuit (fig.1), unless otherwise specified.)
The on-board clipping detector simplifies gain
compression operations. The fault diagnostics makes it possible to detect mistakes during CarRadio assembly and wiring in the car.
30
W
33
35
W
0.04 0.3
%
50
µV
65
150
µV
50
65
dB
20
Hz
75
KHz
70
100
KΩ
50
70
dB
100
µA
3.5
V
1.5
V8090dB3.5V
1.5
V
5
10
16
µA
100
µA
100 240 350
µA
(*) Saturated square wave output. (**) Diagnostics output pulled-up to 5V with 10KΩ series resistor.

MAX738AEWE中文资料

__________________General DescriptionThe MAX730A/MAX738A/MAX744A are 5V-output CMOS, step-down switching regulators. The MAX738A/MAX744A accept inputs from 6V to 16V and deliver 750mA. The MAX744A guarantees 500mA load capa-bility for inputs above 6V and has tighter oscillator fre-quency limits for low-noise (radio) applications. The MAX730A accepts inputs between 5.2V and 11V and delivers 450mA for inputs above 6V. Typical efficien-cies are 85% to 96%. Quiescent supply current is 1.7mA and only 6µA in shutdown.Pulse-width modulation (PWM) current-mode control provides precise output regulation and excellent tran-sient responses. Output voltage accuracy is guaran-teed to be ±5% over line, load, and temperature varia-tions. Fixed-frequency switching allows easy filtering of output ripple and noise, as well as the use of small external components. These regulators require only a single inductor value to work in most applications, so no inductor design is necessary.The MAX730A/MAX738A/MAX744A also feature cycle-by-cycle current limiting, overcurrent limiting, undervolt-age lockout, and programmable soft-start protection.___________________________ApplicationsPortable Instruments Cellular Phones and Radios Personal Communicators Distributed Power Systems Computer Peripherals________________________________Featureso 750mA Load Currents (MAX738A/MAX744A)o High-Frequency, Current-Mode PWM o 159kHz to 212.5kHz Guaranteed Oscillator Frequency Limits (MAX744A)o 85% to 96% Efficiencies o 1.7mA Quiescent Current o 6µA Shutdown Supply Current o Single Preselected Inductor Value,No Component Design Required o Overcurrent, Soft-Start, and Undervoltage Lockout Protection o Cycle-by-Cycle Current Limiting o 8-Pin DIP/SO Packages (MAX730A)_________________Ordering InformationOrdering Information continued at end of data sheet.*Contact factory for dice specifications.MAX730A/MAX738A/MAX744A5V , Step-Down,Current-Mode PWM DC-DC Converters________________________________________________________________Maxim Integrated Products 1_________________Pin Configurations__________Typical Operating Circuit19-0165; Rev 2; 1/96For free samples & the latest literature: , or phone 1-800-998-8800M A X 730A /M A X 738A /M A X 744A5V , Step-Down,Current-Mode PWM DC-DC Converters 2_______________________________________________________________________________________ABSOLUTE MAXIMUM RATINGSELECTRICAL CHARACTERISTICS(Circuit of Figure 3, V+ = 9V for the MAX730A, V+ = 12V for the MAX738A/MAX744A, I LOAD = 0mA, T A = T MIN to T MAX , unless otherwise noted.)Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Pin VoltagesV+ (MAX730A)......................................................+12V, -0.3V V+ (MAX738A/MAX744A).....................................+18V, -0.3V LX (MAX730A).................................(V+ - 12V) to (V+ + 0.3V)LX (MAX738A/MAX744A)................(V+ - 21V) to (V+ + 0.3V)OUT.................................................................................±25V SS, CC, SHDN .........................................-0.3V to (V+ + 0.3V)Peak Switch Current (I LX )........................................................2A Reference Current (I REF )...................................................2.5mA Continuous Power Dissipation (T A = +70°C)8-Pin Plastic DIP (derate 9.09mW/°C above +70°C)...727mW 8-Pin SO (derate 5.88mW/°C above +70°C)...............471mW 16-Pin Wide SO (derate 9.52mW/°C above +70°C).....762mW 8-Pin CERDIP (derate 8.00mW/°C above +70°C).......640mWOperating Temperature Ranges:MAX7_ _AC_ _....................................................0°C to +70°C MAX7_ _AE_ _.................................................-40°C to +85°C MAX7_ _AMJA ..............................................-55°C to +125°C Junction Temperatures:MAX7_ _AC_ _/AE_ _...................................................+150°C MAX7_ _AMJA.............................................................+175°C Storage Temperature Range ............................-65°C to +160°C Lead Temperature (soldering, 10sec).............................+300°CMAX730A/MAX738A/MAX744A5V , Step-Down,Current-Mode PWM DC-DC Converters_______________________________________________________________________________________3Note 1:The standby current typically settles to 25µA (over temperature) within 2 seconds; however, to decrease test time, the partis guaranteed at a 100µA maximum value.ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 3, V+ = 9V for the MAX730A, V+ = 12V for the MAX738A/MAX744A, I LOAD = 0mA, T A = T MIN to T MAX , unless otherwise noted.)10090806002006008001000OUTPUT CURRENT (mA)E F F I C I E N C Y (%)MAX730AEFFICIENCY vs. OUTPUT CURRENT704002006008001000OUTPUT CURRENT (mA)E F F I C I E N C Y (%)MAX738AEFFICIENCY vs. OUTPUT CURRENT4002.52.01.50026810Q U I E S C E N T S U P P L Y C U R R E N T (m A )MAX738A/MAX744A QUIESCENT SUPPLY CURRENT vs. SUPPLY VOLTAGE0.541.0121416100080060000100300400500P E A K I N D U C T O R C U R R E N T (m A )MAX738A/MAX744A PEAK INDUCTOR CURRENT vs. OUTPUT CURRENT200200400600700800M A X 730A /M A X 738A /M A X 744A5V , Step-Down,Current-Mode PWM DC-DC Converters 4_________________________________________________________________________________________________________________________________Typical Operating Characteristics(Circuit of Figure 3, T A= +25°C, unless otherwise noted.)1009080602006008001000OUTPUT CURRENT (mA)E F F I C I E N C Y (%)MAX744AEFFICIENCY vs. OUTPUT CURRENT70400-6006080100S T A N D BY S U P P L Y C U R R E N T (µA )STANDBY SUPPLY CURRENTvs. TEMPERATURE161062181412840-40-202040120140160203.02.51.51.00.5-60204080120TEMPERATURE (°C)Q U I E S C E N T S U P P L Y C U R R E N T (m A )QUIESCENT SUPPLY CURRENTvs. TEMPERATURE2.00-40-200601001401601400100048101214SUPPLY VOLTAGE (V)M A X I M U M O U T P U T C U R R E N T (m A )MAXIMUM OUTPUT CURRENT vs.SUPPLY VOLTAGE12008006161400100080048101214SUPPLY VOLTAGE (V)M A X I M U M O U T P U T C U R R E N T (m A )MAXIMUM OUTPUT CURRENT vs.SUPPLY VOLTAGE, NO R11200616600400200MAX730A/MAX738A/MAX744A5V , Step-Down,Current-Mode PWM DC-DC Converters_______________________________________________________________________________________5____________________________Typical Operating Characteristics (continued)(Circuit of Figure 3, T A = +25°C, unless otherwise noted.)4681014SUPPLY VOLTAGE (V)O S C I L L A T O R F R E Q U E N C Y (k H z )OSCILLATOR FREQUENCY vs.SUPPLY VOLTAGE1216220170160150180190200210210190180-60204080120TEMPERATURE (°C)O S C I L L A T O R F R E Q U E N C Y (k H z )MAX744AOSCILLATOR FREQUENCYvs. TEMPERATURE200170-40-20060100140160200180170160-60204080120TEMPERATURE (°C)S U P P L Y C U R R E N T (m A )MAX738AOSCILLATOR FREQUENCY vs. TEMPERATURE190140-40-20060100140160150130120-60204080120TEMPERATURE (°C)O S C I L L A T O R F R E Q U E N C Y (k H z )MAX730AOSCILLATOR FREQUENCY vs. TEMPERATURE-40-200601001401602402001801602200140Note 3:Commercial temperature range external component values in Table 3.Note 4:Wide temperature range external component values in Table 3.Note 5:Standby and shutdown current includes all external component leakage currents. Capacitor leakage currents dominate at T A > +85°C,Sanyo OS-CON capacitors were used.Note 6:Operation beyond the specifications listed in the electrical characteristics may exceed the power dissipation ratings of the device.M A X 730A /M A X 738A /M A X 744A5V , Step-Down,Current-Mode PWM DC-DC Converters 6_______________________________________________________________________________________MAX738A/MAX744A SWITCHING WAVEFORMS,CONTINUOUS CONDITION2µs/divA: SWITCH VOLTAGE (LX PIN), 5V/div, 0V TO +12V B: INDUCTOR CURRENT, 200mA/divC: OUTPUT VOLTAGE RIPPLE, 50mV/div, AC-COUPLED C OUT = 390µF,V+ = 12V, I OUT = 150µA,MAX738A/MAX744A SWITCHING WAVEFORMS,DISCONTINUOUS CONDITION2µs/divA: SWITCH VOLTAGE (LX PIN), 5V/div, 0V TO +12V B: INDUCTOR CURRENT, 200mA/divC: OUTPUT VOLTAGE RIPPLE, 50mV/div, AC-COUPLED C OUT = 390µF,V+ = 12V, I OUT = 150µA12V0V 200mA0mAABC0V 200mA0mAABCMAX730A LINE-TRANSIENT RESPONSE100ms/divA: V OUT , 50mV/div, DC-COUPLED B: V+, 5V/div, 6.0V TO 11.0V I OUT= 300mAMAX738A/MAX744A LINE-TRANSIENT RESPONSE100ms/divA: V OUT , 50mV/div, DC-COUPLED B: V+, 5V/div, 10.2V TO 16.0V I OUT = 750mA11V6V0VAB16V10.2VAB____________________________Typical Operating Characteristics (continued)(Circuit of Figure 3, T A = +25°C, unless otherwise noted.)12V0VMAX730A/MAX738A/MAX744A5V , Step-Down,Current-Mode PWM DC-DC Converters_______________________________________________________________________________________7NAMEFUNCTION1SHDNShutdown—active low. Ground to power-down chip, tie to V+ for normal operation.Output voltage falls to 0V when SHDN is low.2REF3SSSoft-Start. Capacitor between SS and GND provides soft-start and short-circuit protection.510k Ωresistor from SS to SHDN provides current boost.234CC Compensation Capacitor Input externally compensates the outer feedback loop.Connect to OUT with a 330pF capacitor.5OUT Output Voltage Sense Input provides regulation feedback sensing. Connect to +5V output.6GND Ground pins are internally connected. Connect both pins to ground.7LX Drain of internal P-channel power MOSFET.7898V+Supply-Voltage Input. Bypass to GND with 1µF ceramic and large-value electrolytic capaci-tors in parallel. The 1µF capacitor must be as close to V+ and GND pins as possible.N.C.No Connect—no internal connections to these pins.10, 1112, 13, 141, 15, 164, 5, 6______________________________________________________________Pin DescriptionMAX730ALOAD-TRANSIENT RESPONSE50ms/divA: V OUT , 50mV/div, DC-COUPLED B: I OUT , 200mA/div, 20mA TO 300mA V+ = 9VMAX738A/MAX744A LOAD-TRANSIENT RESPONSE50ms/divA: V OUT , 50mV/div, DC-COUPLED B: I OUT , 500mA/div, 50mA TO 750mA V+ = 12V300mA20mAA B____________________________Typical Operating Characteristics (continued)(Circuit of Figure 3, T A = +25°C, unless otherwise noted.)16-PIN WIDE SO8-PIN DIP/SOReference-Voltage Output (+1.23V) supplies up to 100µA for extended loads.Bypass to GND with a capacitor that does not exceed 0.047µF.750mA50mAABPINM A X 730A /M A X 738A /M A X 744A_________________Detailed DescriptionThe MAX730A/MAX738A/MAX744A switch-mode regu-lators use a current-mode pulse-width-modulation (PWM) control system coupled with a simple step-down (buck) regulator topography. They convert an unregu-lated DC voltage from 5.2V to 11V for the MAX730A,and from 6V to 16V for the MAX738A/MAX744A. The current-mode PWM architecture provides cycle-by-cycle current limiting, improved load-transient response characteristics, and simpler outer-loop design.The controller consists of two feedback loops: an inner (current) loop that monitors the switch current via the cur-rent-sense resistor and amplifier, and an outer (voltage)loop that monitors the output voltage through the error amplifier (Figure 1). The inner loop performs cycle-by-cycle current limiting, truncating the power transistor on-time when the switch current reaches a predetermined threshold. This threshold is determined by the outer loop.For example, a sagging output voltage produces an error signal that raises the threshold, allowing the circuit to store and transfer more energy during each cycle.Programmable Soft-StartFigures 1 and 2 show a capacitor and a resistor con-nected to the soft-start (SS) pin to ensure an orderly power-up. Typical values are 0.1µF and 510k Ω. SS con-trols both the SS timing and the maximum output current that can be delivered while maintaining regulation.The charging capacitor slowly raises the clamp on the error-amplifier output voltage, limiting surge currents at power-up by slowly increasing the cycle-by-cycle cur-rent-limit threshold. The 510k Ωresistor sets the SS clamp at a value high enough to maintain regulation,even at currents exceeding 1A. This resistor is not nec-essary for lower-current loads. Refer to the Maximum Output Current vs. Supply Voltage graph in the Typical Operating Characteristics . Table 1 lists timing charac-teristics for selected capacitor values and circuit condi-tions.The overcurrent comparator trips when the load exceeds approximately 1.5A. An SS cycle begins when either an undervoltage or overcurrent fault condition triggers an internal transistor to momentarily discharge the SS capacitor to ground. An SS cycle also begins at power-up and when coming out of shutdown mode.Overcurrent LimitingThe overcurrent comparator triggers when the load cur-rent exceeds approximately 1.5A. On each clock cycle,the output FET turns on and attempts to deliver current until cycle-by-cycle or overcurrent limits are exceeded.Note that the SS capacitor must be greater than 0.01µFfor overcurrent protection to function properly. A typical value is 0.1µF.Undervoltage LockoutThe MAX738A/MAX744A’s undervoltage-lockout fea-ture monitors the supply voltage at V+, and allows operation to start when V+ rises above 5.7V (6V guar-anteed). When V+ falls, operation continues until the supply voltage falls below 5.45V (see the MAX738A/MAX744A Quiescent Supply Current vs.Supply Voltage graph in the Typical Operating Characteristics ). The MAX730A is similar, starting oper-ation at V+ > 4.7V and continuing to operate down to 4.45V. When an undervoltage condition is detected,control logic turns off the output power FET and dis-charges the SS capacitor to ground. This prevents par-tial turn-on of the power MOSFET and avoids excessive power dissipation. The control logic holds the output power FET off until the supply voltage rises above approximately 4.7V (MAX730A) or 5.7V (MAX738A/MAX744A), at which time an SS cycle begins.Shutdown ModeThe MAX730A/MAX738A/MAX744A are shut down by keeping SHDN at ground. In shutdown mode, the output drops to 0V and the output power FET is held in an off state. The internal reference also turns off, which causes the SS capacitor to discharge. Typical standby current in shutdown mode is 6µA. The actual design limit for stand-by current is much less than the 100µA specified in the Electrical Characteristics (see Standby Current vs.Temperature in the Typical Operating Characteristics ).However, testing to tighter limits is prohibitive because the current takes several seconds to settle to a final value.For normal operation, connect SHDN to V+. Note that coming out of shutdown mode initiates an SS cycle.Continuous-/Discontinuous-Conduction ModesThe input voltage, output voltage, load current, and induc-tor value determine whether the IC operates in continuous or discontinuous mode. As the inductor value or load cur-rent decreases, or the input voltage increases, the MAX730A/MAX738A/MAX744A tend to operate in discon-tinuous-conduction mode (DCM). In DCM, the inductor current slope is steep enough so it decays to zero before the end of the transistor off-time. In continuous-conduc-tion mode (CCM), the inductor current never decays to zero, which is typically more efficient than DCM. CCM allows the MAX730A/ MAX738A/MAX744A to deliver maxi-mum load current, and is also slightly less noisy than DCM, because the peak-to-average inductor current ratio is reduced.5V , Step-Down,Current-Mode PWM DC-DC Converters 8_______________________________________________________________________________________Internal ReferenceThe +1.23V bandgap reference supplies up to 100µA at REF. Connect a 0.01µF bypass capacitor from REF to GND.OscillatorThe internal oscillator of the MAX730A typically oper-ates at 170kHz (160kHz for the MAX738A and 185kHz for the MAX744A). The MAX744A is guaranteed to operate at a minimum of 159kHz and a maximum of 212.5kHz over the operating voltage and temperature range, making it ideal for use in portable communica-tions systems. The Typical Operating Characteristics graphs indicate oscillator frequency stability over tem-perature and supply voltage.____________Applications InformationFigure 3 shows the standard 5V step-down application circuits. Table 3 lists the components for the desired operating temperature range. These circuits are useful in systems that require high current at high efficiency and are powered by an unregulated supply, such as a battery or wall-plug AC-DC transformer. These circuits operate over the entire line, load, and temperature ranges using the single set of component values shown in Figure 3 and listed in Table 3.Inductor SelectionThe MAX730A/MAX738A/MAX744A require no inductor design because they are tested in-circuit, and are guaranteed to deliver the power specified in the Electrical Characteristics with high efficiency using aMAX730A/MAX738A/MAX744A5V , Step-Down,Current-Mode PWM DC-DC Converters_______________________________________________________________________________________9Table 1. Typical Soft-Start TimesMAX730A CIRCUIT CONDITIONSSOFT-START TIME (ms) vs. C1 (µF)R1 (k Ω)V+ (V)I OUT (mA)C4 (µF)C1 = 0.01C1 = 0.047C1 = 0.1C1 = 0.4751060100261128510901001461551011010012411510915010014821510930010015927510915039036923510915068046924None 60100163451125None 9010010223482None 1101008182866None 9150100341342701263None 9150390391472801275None9150680401522851280MAX738A/MAX744A CIRCUIT CONDITIONSSOFT-START TIME (ms) vs. C1 (µF)R1 (k Ω)V+ (V)I OUT (mA)C4 (µF)C1 = 0.01C1 = 0.047C1 = 0.1C1 = 0.475107010014618510120100123851016010011265101230010013535101275010015821None 70100122740100None 1201007162554None 1601006132068None12300100271122151114M A X 730A /M A X 738A /M A X 744Asingle 100µH (MAX7__AC) or 33µH (MAX7__AE/AM)inductor. The inductor’s incremental saturation current rating should be greater than 1A, and its DC resistance should be less than 0.8Ω. Table 2 lists inductor types and suppliers for various applications. The surface-mount inductors have nearly equivalent efficiencies to the larger through-hole inductors.Output Filter Capacitor SelectionThe primary criterion for selecting the output filter capacitor is low equivalent series resistance (ESR).The product of the inductor current variation and the output capacitor’s ESR determines the amplitude of the sawtooth ripple seen on the output voltage. Also, mini-mize the output filter capacitor’s ESR to maintain AC stability. The capacitor’s ESR should be less than 0.25Ωto keep the output ripple less than 50mVp-p over the entire current range (using a 100µH inductor).Capacitor ESR rises as the temperature falls, and excessive ESR is the most likely cause of trouble at temperatures below 0°C. Sanyo OS-CON series through-hole and surface-mount tantalum capacitors exhibit low ESR at temperatures below 0°C. Refer to Table 2 for recommended capacitor values and sug-gested capacitor suppliers.Other ComponentsThe catch diode should be a Schottky or high-speed silicon rectifier with a peak current rating of at least 1.5A for full-load (750mA) operation. The 1N5817 is a good choice. The 330pF outer-loop compensation capacitor provides the widest input voltage range and best transient characteristics. For low-current applica-tions, the 510k Ωresistor may be omitted (see the Maximum Output Current vs. Supply Voltage graph (R1removed) in the Typical Operating Characteristics ).5V , Step-Down,Current-Mode PWM DC-DC Converters 10______________________________________________________________________________________Figure 1. Detailed Block Diagram with External ComponentsPrinted Circuit LayoutsA good layout is essential for clean, stable operation.The layouts and component placement diagrams given in Figures 4, 5, 6, and 7 have been successfully tested over a wide range of operating conditions. Note that the 1µF bypass capacitor (C2) must be positioned as close to the V+ and GND pins as possible. Also, place the out-put capacitor as close to the OUT and GND pins as pos-sible. The traces connecting the input and output filter capacitors and the catch diode must be short to mini-mize inductance and capacitance. For this reason, avoid using sockets, and solder the IC directly to the PC board. Use an uninterrupted ground plane if possible.Output-Ripple FilteringA simple lowpass pi-filter (Figure 3) can be added to the output to reduce output ripple to about 5mVp-p.The cutoff frequency shown is 21kHz. Since the filter inductor is in series with the circuit output, its resis-tance should be minimized so the voltage drop across it is not excessive.MAX730A/MAX738A/MAX744ACurrent-Mode PWM DC-DC Converters______________________________________________________________________________________11Table 2. Component Values and SuppliersMAX730AC/MAX738AC/MAX744ACCommercial Temp. Range MAX730AE/M, MAX738AE/M, MAX744AE/MWide Temp. Range Surface MountC3 = 68µF, 16V C4 = 100µF, 6.3V Matsuo (714) 969-2491267 seriesSprague (603) 224-1961595D/293D seriesL1 = 33µHSumida (708) 956-0666CD54-330N (MAX730AC)CD105-330N(MAX738AE/M, MAX744AE/M)Coiltronics (407) 241-7876CTX50 seriesC3 = 68µF, 16V C4 = 100µF, 6.3V Matsuo (714) 969-2491267 seriesSprague (603) 224-1961595D/293D series Miniature Through-HoleL1 = 33µH to 100µHSumida (708) 956-0666RCH654-101K (MAX730A)RCH895-101K(MAX738A/MAX744A)C3 = 150µF, 16V C4 = 150µF, 16V or390µF, 6.3V Nichicon (708) 843-7500PL seriesLow-ESR electrolyticsL1 = 33µHSumida (708) 956-0666RCH654-330M (MAX730A)RCH895-330M(MAX738A/MAX744A)Low-Cost Through-HoleInductorsCapacitors InductorsCapacitorsProduction MethodL1 = 33µH to 100µH Sumida (708) 956-0666CD54-101KC (MAX730AC)CD105-101KC(MAX738AC/MAX744AC)Coiltronics (407) 241-7876CTX100 seriesC3 = 150µF, 16V C4 = 220µF, 10VSanyo (619) 661-6322OS-CON series Low-ESRorganic semiconductor (Rated from -55°C to +105°C)Mallory (317) 273-0090THF seriesC3 = 100µF, 20V C4 = 220µF, 10V(Rated from -55°C to +125°C)L1 = 100µHMaxim MAXL001100µH iron-power toroid Renco (516) 586-5566RL1284-100C3 = 150µF, 16V C4 = 390µF, 6.3V Maxim MAXC001150µF, low-ESR electrolytic United Chemicon (708) 843-7500M A X 730A /M A X 738A /M A X 744ACurrent-Mode PWM DC-DC Converters 12______________________________________________________________________________________Figure 2. Block Diagram of Soft-Start CircuitryFigure 3. Standard +5V Step-Down Application CircuitMAX730A/MAX738A/MAX744ACurrent-Mode PWM DC-DC Converters______________________________________________________________________________________13Figure 4. DIP PC Layout, Through-Hole Component Placement Diagram (1x scale)Figure 6. DIP PC Layout, Solder Side (1x scale)Figure 7. DIP PC Layout, Drill Guide (1x scale)Figure 5. DIP PC Layout, Component Side (1x scale)MAX730 EVALUATION KITM A X 730A /M A X 738A /M A X 744ACurrent-Mode PWM DC-DC Converters 14__________________________________________________________________________________________Pin Configurations (continued)__Ordering Information (continued)PART TEMP. RANGE PIN-PACKAGE MAX738A CPA 0°C to +70°C 8 Plastic DIP MAX738ACWE 0°C to +70°C 16 Wide SO MAX738AC/D 0°C to +70°C Dice*MAX738AEPA -40°C to +85°C 8 Plastic DIP MAX738AEWE -40°C to +85°C 16 Wide SO MAX738AMJA -55°C to +125°C 8 CERDIP MAX744A CPA0°C to +70°C8 Plastic DIP MAX744ACWE 0°C to +70°C 16 Wide SO MAX744AC/D 0°C to +70°C Dice*MAX744AEPA -40°C to +85°C 8 Plastic DIP MAX744AEWE -40°C to +85°C 16 Wide SO MAX744AMJA -55°C to +125°C 8 CERDIP*Contact factory for dice specifications.__________________________________________________________Chip TopographiesLXGNDREFSSSHDNOUTCC0.131" (3.327mm)0.116" (2.946mm)LXGNDSSOUTCC0.116" (2.946mm)0.072" (1.828mm)MAX730AMAX738A/MAX744ATRANSISTOR COUNT: 274 (MAX730A)286 (MAX738A/MAX744A); SUBSTRATE CONNECTED TO V+.MAX730A/MAX738A/MAX744ACurrent-Mode PWM DC-DC Converters______________________________________________________________________________________15________________________________________________________Package InformationMaxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.16__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600©1996 Maxim Integrated ProductsPrinted USAis a registered trademark of Maxim Integrated Products.M A X 730A /M A X 738A /M A X 744ACurrent-Mode PWM DC-DC Converters ___________________________________________Package Information (continued)。

1.3inch LCD HAT 用户手册说明书

产品概述1.3inch LCD HAT 是微雪电子专为树莓派开发的1.3寸LCD显示屏模块，分辨率为240 * 240，LCD带有内部控制器，使用SPI接口通信，与树莓派ZERO大小一致，已封装好基本函数，可以实现图片旋转、画点、线、圆、矩形，显示英文字符，显示BMP图片。

提供树莓派BCM2835库，WiringPi库，以及python例程。

产品参数工作电压： 3.3V通信接口：SPI屏幕类型：TFT控制芯片：ST7789VM分辨率：240(H)RGB x 240(V)显示尺寸：23.4（H）x 23.4（V）mm像素大小：0.0975（H）x 0.0975（V）mm产品尺寸65 x 30.2(mm)1接口说明2硬件说明1.LCD及其控制器本款LCD使用的内置控制器为ST7789VM，是一款240 x RGB x 320像素的LCD控制器,而本LCD本身的像素为240(H)RGB x 240(V),同时由于初始化控制可以初始化为横屏和竖屏两种，因此LCD的内部RAM并未完全使用。

查看数据手册可以得知该控制器支持12位，16位以及18位每像素的输入颜色格式，即RGB444,RGB565,RGB666三种颜色格式，本屏幕使用RGB565格式的颜色格式，这也是常用的RGB格式。

对于大部分的LCD控制器而言，都可以配置控制器的通信方式，通常都有8080并行接口、三线SPI、四线SPI等通信方式。

此LCD使用四线SPI通信接口，这样可以大大的节省GPIO 口，同时通信速度也会比较快。

2.通信协议从上的得知使用的是4线SPI通信，查阅数据手册可以得到如下的通信时序图，以传输RGB556为例：注：与传统的SPI协议不同的地方是：由于是只需要显示，故而将从机发往主机的数据线进行了隐藏，该表格详见Datasheet Page 105。

3RESX为复位，模块上电时拉低，通常情况下置1；CSX为从机片选，仅当CS为低电平时，芯片才会被使能。

mcp73833 73834中文手册

4.20 4.35 4.40 4.50 0.10
0.10
58 47 25
100 1000
3000 300 300
100
3.7 3.6 —
4.232 4.382 4.433 4.533 0.30
0.30
— — —
110 1100
最大输出电流限制
IMAX
—
1200
—
µA 充电中
µA 充电结束
µA 待机（没有接电池或 PROG 悬空）
MCP73833/4
独立线性锂离子 / 锂聚合物电池充电管理控制器
特点
• 完整的线性充电管理控制器 - 内部集成了功率晶体管 - 内部集成了电流检测 - 内部集成了反向阻断保护
• 可进行热调节的恒流 / 恒压控制 • 高精度预置稳压：
- 4.2V， 4.35V， 4.4V 或 4.5V， +0.75% • 可编程充电电流：最大 1A • 对深度放电的电池进行预充
电流 + 限制 -
111 kΩ
+ - 预充
+ - 终止 + - 充电
+ CA 10 kΩ
470.6 kΩ 48 kΩ
+ VA -
充电控制定时器状态逻辑
VBAT
STAT1 STAT2 PG (TE)
DS22005A_CN 第 2 页
2007 Microchip Technology Inc.
MCP73833/4
晶体管导通电阻导通电阻
VPTH / VREG VPHYS
ITERM / IREG
VRTH / VREG RDSON
— 64 69 —
3.75 5.6 7.5 15

IRMCF343中文资料

Data Sheet No. PD60313IRMCF343 Sensorless Motor Control IC for AppliancesFeaturesMCE TM (Motion Control Engine) - Hardware based computation engine for high efficiency sinusoidal sensorless control of permanent magnet AC motor Integrated Power Factor Correction controlSupports both interior and surface permanent magnet motorsBuilt-in hardware peripheral for single shunt current feedback reconstructionNo external current or voltage sensing operational amplifier requiredThree/two-phase Space Vector PWMThree-channel analog output (PWM)Embedded 8-bit high speed microcontroller (8051) for flexible I/O and man-machine controlJTAG programming port for emulation/debugger Serial communication interface (UART)I2C/SPI serial interfaceWatchdog timer with independent analog clockThree general purpose timers/countersTwo special timers: periodic timer, capture timer External EEPROM and internal RAM facilitate debugging and code developmentPin compatible with IRMCK343, OTP-ROM version 1.8V/3.3V CMOS Product SummaryMaximum crystal frequency 60 MHz Maximum internal clock (SYSCLK) frequency 128 MHz Sensorless control computation time 11 μsec typ MCE TM computation data range 16 bit signed Program RAM loaded from external EEPROM 48K bytes Data RAM 8K bytes GateKill latency (digital filtered) 2 μsec PWM carrier frequency counter 16 bits/ SYSCLK A/D input channels 5 A/D converter resolution 12 bits A/D converter conversion speed 2 μsec 8051 instruction execution speed 2 SYSCLK Analog output (PWM) resolution 8 bits UART baud rate (typ) 57.6K bps Number of I/O (max) 23 Package (lead-free) QFP64DescriptionIRMCF343 is a high performance RAM based motion control IC designed primarily for appliance applications. IRMCF343 is designed to achieve low cost and high performance control solutions for advanced inverterized appliance motor control. IRMCF343 contains two computation engines. One is Motion Control Engine (MCE TM) for sensorless control of permanent magnet motors; the other is an 8-bit high-speed microcontroller (8051). Both computation engines are integrated into one monolithic chip. The MCE TM contains a collection of control elements such as Proportional plus Integral, Vector rotator, Angle estimator, Multiply/Divide, Low loss SVPWM, Single Shunt IFB. The user can program a motion control algorithm by connecting these control elements using a graphic compiler. Key components of the sensorless control algorithms, such as the Angle Estimator, are provided as complete pre-defined control blocks implemented in hardware. A unique analog/digital circuit and algorithm to fully support single shunt current reconstruction is also provided. The 8051 microcontroller performs 2-cycle instruction execution (60MIPS at 120MHz). The MCE and 8051 microcontroller are connected via dual port RAM to process signal monitoring and command input. An advanced graphic compiler for the MCE TM is seamlessly integrated into the MATLAB/Simulink environment, while third party JTAG based emulator tools are supported for 8051 developments. IRMCF343 comes with a small QFP64 pin lead-free package.IRMCF343TABLE OF CONTENTS1 Overview (4)2 IRMCF343 Block Diagram and Main Functions (5)3 Pinout (7)4 Input/Output of IRMCF343 (8)4.1 8051 Peripheral Interface Group (8)4.2 Motion Peripheral Interface Group (9)4.3 Analog Interface Group (10)4.4 Power Interface Group (10)4.5 Test Interface Group (11)5 Application Connections (12)6 DC Characteristics (13)6.1 Absolute Maximum Ratings (13)6.2 System Clock Frequency and Power Consumption (13)6.3 Digital I/O DC Characteristics (14)6.4 PLL and Oscillator DC Characteristics (15)6.5 Analog I/O DC Characteristics (15)6.6 Analog I/O DC Characteristics (16)6.7 Under Voltage Lockout DC Characteristics (17)6.8 CMEXT and AREF Characteristics (17)7 AC Characteristics (18)7.1 PLL AC Characteristics (18)7.2 Analog to Digital Converter AC Characteristics (19)7.3 Op Amp AC Characteristics (20)7.4 Op Amp AC Characteristics (20)7.5 SYNC to SVPWM and A/D Conversion AC Timing (21)7.6 GATEKILL to SVPWM AC Timing (22)7.7 Interrupt AC Timing (23)7.8 I2C AC Timing (24)7.9 SPI AC Timing (25)7.9.1 SPI Write AC timing (25)7.9.2 SPI Read AC Timing (26)7.10 UART AC Timing (27)7.11 CAPTURE Input AC Timing (28)7.12 JTAG AC Timing (29)8 Pin List (30)9 Package Dimensions (33)10 Part Marking Information (34)IRMCF343TABLE OF FIGURESFigure 1. Typical Application Block Diagram Using IRMCF343 (4)Figure 2. IRMCF343 Internal Block Diagram (5)Figure 3. IRMCF343 Pin Configuration (7)Figure 4. Input/Output of IRMCF343 (8)Figure 5. Application Connection of IRMCF343 (12)Figure 6. Clock Frequency vs. Power Consumption (13)TABLE OF TABLESTable 1. Absolute Maximum Ratings (13)Table 2. System Clock Frequency (13)Table 3. Digital I/O DC Characteristics (14)Table 4. PLL DC Characteristics (15)Table 5. Analog I/O DC Characteristics (15)Table 6. Analog I/O DC Characteristics (16)Table 7. UVcc DC Characteristics (17)Table 8. CMEXT and AREF DC Characteristics (17)Table 9. PLL AC Characteristics (18)Table 10. A/D Converter AC Characteristics (19)Table 11. Current Sensing OP amp Amp AC Characteristics (20)Table 12. Voltage sensing OP amp Amp AC Characteristics (20)Table 13. SYNC AC Characteristics (21)Table 14. GATEKILL to SVPWM AC Timing (22)Table 15. Interrupt AC Timing (23)Table 16. I2C AC Timing (24)Table 17. SPI Write AC Timing (25)Table 18. SPI Read AC Timing (26)Table 19. UART AC Timing (27)Table 20. CAPTURE AC Timing (28)Table 21. JTAG AC Timing (29)Table 22. Pin List (32)IRMCF343 1 OverviewIRMCF343 is a new International Rectifier integrated circuit device primarily designed as a one-chip solution for complete inverter controlled appliance motor control applications. Unlike a traditional microcontroller or DSP, the IRMCF343 provides a built-in closed loop sensorless control algorithm using the unique Motion Control Engine (MCE TM) for permanent magnet motor. The MCE TM consists of a collection of control elements, motion peripherals, a dedicated motion control sequencer and dual port RAM to map internal signal nodes. IRMCF343 also employs a unique single shunt current reconstruction circuit to eliminate additional analog/digital circuitry and enables a direct shunt resistor interface to the IC. Motion control programming is achieved using a dedicated graphical compiler integrated into the MATLAB/Simulink TM development environment. Sequencing, user interface, host communication, and upper layer control tasks can be implemented in the 8051 high-speed 8-bit microcontroller. The 8051 microcontroller is equipped with a JTAG port to facilitate emulation and debugging tools. Figure 1 shows a typical application schematic using the IRMCF343.IRMCF343 is intended for development purpose and contains 48K bytes of RAM, which can be loaded from external EEPROM for 8051 program execution. For high volume production, IRMCK343 contains OTP ROM in place of program RAM to reduce the cost. Both IRMCF343 and IRMCK343 come in the same 64-pin QFP package with identical pin configuration to facilitate PC board layout and transition to mass productionFigure 1. Typical Application Block Diagram Using IRMCF343IRMCF3432 IRMCF343 Block Diagram and Main FunctionsIRMCF343 block diagram is shown in Figure 2.8b i t u P A d d r e s s /D a t a b u sM o t i o n C o n t r o l B u sFigure 2. IRMCF343 Internal Block DiagramIRMCF343 contains the following functions for sensorless AC motor control applications:• Motion Control Engine (MCE TM )o Proportional plus Integral blocko Low pass filtero Differentiator and lag (high pass filter)o Rampo Limito Angle estimate (sensorless control)o Inverse Clark transformationo Vector rotatoro Bit latchIRMCF343o Peak detecto Transitiono Multiply-divide (signed and unsigned)o Divide (signed and unsigned)o Addero Subtractoro Comparatoro Countero Accumulatoro Switcho Shifto ATAN (arc tangent)o Function block (any curve fitting, nonlinear function)o16-bit wide Logic operations (AND, OR, XOR, NOT, NEGATE)o MCE TM program and data memory (6K byte). Note 1o MCE TM control sequencer•8051 microcontrollero Three 16-bit timer/counterso16-bit periodic timero16-bit analog watchdog timero16-bit capture timero Up to 23 discrete I/Oso Five-channel 12-bit A/DThree buffered channels (0 – 1.2V input)Two unbuffered channels (0 – 1.2V input)o JTAG port (4 pins)o Up to three channels of analog output (8-bit PWM)o UARTo I2C/SPI porto48K byte program RAM loaded from external EEPROMo2K byte data RAM. Note 1Note 1: Total size of RAM is 8K byte including MCE program, MCE data, and8051 data. Different sizes can be allocated depending on applications.IRMCF3433 PinoutV S SV D D 2A V D DA V S SA I N 0A R E FP 2.7/A O P W M 1P 2.6/A O P W MI F B C OI F B C +I F B C -P L L V S SP L L V D DR E S E TT S T M O DT C KP 5.3/T D IP 5.2/T D OP 5.1/T M SS D A /C S 0S C L /S O -S IP 5.0/P F C G K I L L P F C P W MV SSC M E X TA I N 1P 3.2/I N T0P 2.3P 2.4P 2.5P 3.1/A O P W M 2V D D1Figure 3. IRMCF343 Pin ConfigurationIRMCF3434 Input/Output of IRMCF343All I/O signals of IRMCF343 are shown in Figure 4. All I/O pins are 3.3V logic interface except A/D interface pins.Figure 4. Input/Output of IRMCF3434.1 8051 Peripheral Interface GroupUART InterfaceP1.2/TXD Output, Transmit data from IRMCF343P1.1/RXD Input, Receive data to IRMCF343Discrete I/O InterfaceP1.0/T2 Input/output port 1.0, can be configured as Timer/Counter 2 inputP1.3/SYNC/SCK Input/output port 1.3, can be configured as SYNC output or SPI clock,needs to be pulled up to VDD1 in order to boot from I 2C EEPROMP1.4/CAP Input/output port 1.4, can be configured as Capture Timer inputIRMCF343 P1.5 Input/output port 1.5P1.6 Input/output port 1.6P1.7 Input/output port 1.7P2.0/NMI Input/output port 2.0, can be configured as Non-maskable interrupt inputP2.1 Input/output port 2.1P2.2 Input/output port 2.2P2.3 Input/output port 2.3P2.4 Input/output port 2.4P2.5 Input/output port 2.5P3.0/INT2/CS1 Input/output port 3.0, can be configured as INT2 input or SPI chip select1P3.2/INT0 Input/output port 3.2, can be configured as INT0 inputAnalog Output InterfaceP2.6/AOPWM0 Input/output, can be configured as 8-bit PWM output 0 withprogrammable carrier frequencyP2.7/AOPWM1 Input/output, can be configured as 8-bit PWM output 1 withprogrammable carrier frequencyP3.1/AOPWM2 Input/output, can be configured as 8-bit PWM output 2 withprogrammable carrier frequencyCrystal InterfaceXTAL0 Input, connected to crystalXTAL1 Output, connected to crystalReset InterfaceRESET Inout, system reset, needs to be pulled up to VDD1 but doesn’t requireexternal RC time constantI2C/SPI InterfaceI2C clock output or SPI dataSCL/SO-SI Output,I2C data line or SPI chip select 0SDA/CS0 Input/output,P3.0/INT2/CS1 Input/output, INT2 or SPI chip select 1P1.3/SYNC/SCK Input/output, SYNC output or SPI clock, needs to be pulled up to VDD1in order to boot from I2C EEPROM4.2 Motion Peripheral Interface GroupPWMPWMUH Output, PWM phase U high side gate signalPWMUL Output, PWM phase U low side gate signalPWMVH Output, PWM phase V high side gate signalPWMVL Output, PWM phase V low side gate signalPWMWH Output, PWM phase W high side gate signalIRMCF343 PWMWL Output, PWM phase W low side gate signalPFCPWM Output, PFC PWM gate signalFaultGATEKILL Input, upon assertion, this negates all six PWM signals, programmablelogic senseP5.0/PFCGKILL Input, upon assertion, this negates PFCPWM signal, programmable logicsense, can be configured as discrete I/O in which case CGATEKILLnegates PFCPWM4.3 Analog Interface GroupAVDD Analog power (1.8V)AVSS Analog power returnCMEXT Unbuffered 0.6V, input to the AREF buffer, capacitor needs to beconnected.AREF 0.6V buffered outputIFB+ Input, Operational amplifier positive input for shunt resistor currentsensingIFB- Input, Operational amplifier negative input for shunt resistor currentsensingIFBO Output, Operational amplifier output for shunt resistor current sensingIPFC+ Input, Operational amplifier positive input for PFC current sensingIPFC- Input, Operational amplifier negative input for PFC current sensingIPFO Output, Operational amplifier output for PFC current sensingVAC+ Input, Operational amplifier positive input for PFC AC voltage sensingVAC- Input, Operational amplifier negative input for PFC AC voltage sensingVACO Output, Operational amplifier output for PFC AC voltage sensingAIN0 Input, Analog input channel 0 (0 – 1.2V), typically configured for DC busvoltage inputAIN1 Input, analog input channel 1 (0 – 1.2V), needs to be pulled down toAVSS if unused4.4 Power Interface GroupVDD1 Digital power for I/O (3.3V)VDD2 Digital power for core logic (1.8V)VSS DigitalcommonPLLVDD PLL power (1.8V)PLLVSS PLL ground return元器件交易网IRMCF3434.5Test Interface GroupMust be tied to VSS, used only for factory testing. Input, JTAG test data input Input, JTAG test mode select Input, JTAG test clock Output, JTAG test data outputTSTMOD P5.3/TDI P5.1/TMS TCK P5.2/TDOThis document is the property of International Rectifier and may not be copied or distributed without expressed consent.11元器件交易网IRMCF343 5 Application ConnectionsTypical application connection is shown in Figure 5. All components necessary to implement a complete sensorless drive control algorithm are shown connected to IRMCF343.Figure 5.Application Connection of IRMCF343This document is the property of International Rectifier and may not be copied or distributed without expressed consent.12元器件交易网IRMCF343 6 DC Characteristics6.1 Absolute Maximum RatingsParameter Supply Voltage Supply Voltage Analog Input Voltage Digital Input Voltage Ambient Temperature Storage Temperature Table 1. Min Typ Max -0.3 V 3.6 V -0.3 V 1.98 V -0.3 V 1.98 V -0.3 V 3.65 V -40 ˚C 85 ˚C -65 ˚C 150 ˚C Absolute Maximum Ratings Condition Respect to VSS Respect to VSS Respect to AVSS Respect to VSSSymbol VDD1 VDD2 VIA VID TA TSCaution: Stresses beyond those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied.6.2System Clock Frequency and Power ConsumptionParameter System Clock Table 2. Min Typ Max 32 128 System Clock Frequency Unit MHzSymbol SYSCLK240 200 160 Power (mW) 120 80 VDD2 (1.8V) 40 0 0 50 100 Clock Frequency (MHz) 150 VDD1 (3.3V) TotalFigure 6.Clock Frequency vs. Power ConsumptionThis document is the property of International Rectifier and may not be copied or distributed without expressed consent.13元器件交易网IRMCF3436.3VDD1 VDD2 VIL VIH CIN IL IOL1(2) IOH1(2) IOL2(3) IOH2(3)Digital I/O DC CharacteristicsParameter Supply Voltage Supply Voltage Input Low Voltage Input High Voltage Input capacitance Input leakage current Low level output current High level output current Low level output current High level output current Table 3. Min 3.0 V 1.62 V -0.3 V 2.0 V 8.9 mA 12.4 mA 17.9 mA 24.6 mA Typ 3.3 V 1.8 V 3.6 pF ±10 nA 13.2 mA 24.8 mA 26.3 mA 49.5 mA Max 3.6 V 1.98 V 0.8 V 3.6 V ±1 μA 15.2 mA 38 mA 33.4 mA 81 mA Condition Recommended Recommended Recommended Recommended(1)SymbolVO = 3.3 V or 0 V VOL = 0.4 V(1) (1) (1) (1)VOH = 2.4 V VOL = 0.4 V VOH = 2.4 VDigital I/O DC CharacteristicsNote: (1) Data guaranteed by design. (2) Applied to SCL/SO-SI, SDA/CS0 pins. (3) Applied to P1.0/T2, P1.1/RXD, P1.2/TXD, P1.3/SYNC/SCK, P1.4/CAP, P1.5, P1.6, P1.7, P2.0/NMI, P2.1, P2.2, P2.3, P2.4, P2.5, P2.6/AOPWM0, P2.7/AOPWM1, P3.0/INT2/CS1, P3.1/AOPWM2, P3.2/INT0, P5.0/PFCGKILL, P5.1/TMS, P5.2/TDO, P5.3/TDI, GATEKILL, PWMUL, PWMUH, PWMVL, PWMVH, PWMWL, PWMWH, and PFCPWM pins.This document is the property of International Rectifier and may not be copied or distributed without expressed consent.14元器件交易网IRMCF3436.4 PLL and Oscillator DC CharacteristicsParameter Min Typ Max Supply Voltage 1.62 V 1.8 V 1.92 V Oscillator Input Low VPLLVSS 0.2* Voltage VPLLVDD Oscillator Input High 0.8* VPLLVDD Voltage VPLLVDD Table 4. PLL DC Characteristics Condition Recommended VPLLVDD = 1.8 V(1) (1)Symbol VPLLVDD VIL OSC VIH OSCVPLLVDD = 1.8 VNote: (1) Data guaranteed by design.6.5Analog I/O DC Characteristics- OP amps for current sensing (IFB+, IFB-, IFBO, IPFC+, IPFC-, IPFCO) CAREF = 1nF, CMEXT= 100nF. Unless specified, Ta = 25˚C. Symbol Parameter Min Typ VAVDD Supply Voltage 1.71 V 1.8 V VOFFSET Input Offset Voltage VI Input Voltage Range 0V VOUTSW OP amp output 50 mV (1) operating range CIN Input capacitance 3.6 pF RFDBK OP amp feedback 5 kΩ resistor OP GAINCL CMRR ISRC ISNKMax 1.89 V 26 mV 1.2 V 1.2 V 20 kΩCondition Recommended VAVDD = 1.8 V Recommended VAVDD = 1.8 V(1)Operating Close loop 80 db Gain Common Mode 80 db Rejection Ratio Op amp output source 1 mA current Op amp output sink 100 μA current Table 5. Analog I/O DC Characteristics(1) (1)Requested between op amp output and negative inputVOUT = 0.6 V(1) (1)VOUT = 0.6 VNote: (1) Data guaranteed by design.This document is the property of International Rectifier and may not be copied or distributed without expressed consent.15元器件交易网IRMCF3436.6 Analog I/O DC Characteristics- OP amp for voltage sensing (VAC+,VAC-,VACO) CAREF = 1nF, CMEXT= 100nF. Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max VAVDD Supply Voltage 1.71 V 1.8 V 1.89 V VOFFSET Input Offset Voltage 26 mV VI Input Voltage Range 0V 1.2 V 1.2 V VOUTSW OP amp output 50 mV (1) operating range CIN Input capacitance 3.6 pF OP GAINCL Operating Close loop 80 db Gain CMRR Common Mode 80 db Rejection Ratio ISRC Op amp output source 5 mA current ISNK Op amp output sink 500 μA current Table 6. Analog I/O DC Characteristics Note: (1) Data guaranteed by design.Condition VAVDD = 1.8 V VAVDD = 1.8 V(1) (1) (1)VOUT = 0.6 V(1) (1)VOUT = 0.6 VThis document is the property of International Rectifier and may not be copied or distributed without expressed consent.16元器件交易网IRMCF3436.7 Under Voltage Lockout DC Characteristics- Based on AVDD (1.8V) Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max UVCC+ UVcc positive going 1.53 V 1.66 V 1.71 V Threshold UVCCUVcc negative going 1.52 V 1.62 V 1.71 V Threshold UVCCH UVcc Hysteresys 40 mV Table 7. UVcc DC CharacteristicsCondition VDD1 = 3.3 V VDD1 = 3.3 V6.8CMEXT and AREF CharacteristicsCAREF = 1nF, CMEXT= 100nF. Unless specified, Ta = 25˚C. Condition Symbol Parameter Min Typ Max VCM CMEXT voltage 495 mV 600 mV 700 mV VAVDD = 1.8 V VAREF Buffer Output Voltage 495 mV 600 mV 700 mV VAVDD = 1.8 V (1) Load regulation (VDC1 mV ΔVo 0.6) (1) PSRR Power Supply Rejection 75 db Ratio Table 8. CMEXT and AREF DC Characteristics Note: (1) Data guaranteed by design.This document is the property of International Rectifier and may not be copied or distributed without expressed consent.17元器件交易网IRMCF343 7 AC Characteristics7.1FCLKIN FPLL FLWPW JS D TLOCKPLL AC CharacteristicsParameter Min Typ Max Condition (1) Crystal input 3.2 MHz 4 MHz 60 MHz frequency (see figure below) Internal clock 32 MHz 50 MHz 128 MHz (1) frequency (1) Sleep mode output FCLKIN ÷ 256 frequency (1) Short time jitter 200 psec (1) Duty cycle 50 % PLL lock time 500 μsec (1) Table 9. PLL AC CharacteristicsSymbolNote: (1) Data guaranteed by design.R1=1MR2=10XtalC1=30PF C2=30PFThis document is the property of International Rectifier and may not be copied or distributed without expressed consent.18元器件交易网IRMCF3437.2 Analog to Digital Converter AC CharacteristicsMin Typ Max 2.05 μsec 10 μsec Condition(1)Unless specified, Ta = 25˚C. Symbol Parameter TCONV Conversion time THOLD Sample/Hold maximum hold time Table 10. Note: (1) Data guaranteed by design.Voltage droop ≤ 15 LSB (see figure below)A/D Converter AC CharacteristicsInput Voltage Voltage droop S/H VoltagetSAMPLE THOLDThis document is the property of International Rectifier and may not be copied or distributed without expressed consent.19元器件交易网IRMCF3437.3 Op Amp AC Characteristics- OP amps for current sensing (IFB+, IFB-, IFBO, IPFC+, IPFC-, IPFCO) Unless specified, Ta = 25˚C. Symbol Parameter OPSR OP amp slew rate OPIMP TSET OP input impedance Settling time Table 11.Min -Typ 10 V/μsec 108 Ω 400 nsMax -(1)Condition VAVDD = 1.8 V, CL = 33 pF (1)VAVDD = 1.8 V, CL = 33 pF (1) Current Sensing OP amp Amp AC CharacteristicsNote: (1) Data guaranteed by design.7.4Op Amp AC Characteristics- OP amp for voltage sensing (VAC+,VAC-,VACO) Unless specified, Ta = 25˚C. Symbol Parameter OPSR OP amp slew rate OPIMP TSET OP input impedance Settling time Table 12.MinTyp 2.5 V/μsec 108 Ω 650 nsMax --(1)Condition VAVDD = 1.8 V, CL = 33 pF (1)VAVDD = 1.8 V, CL = 33 pF (1) Voltage sensing OP amp Amp AC CharacteristicsNote: (1) Data guaranteed by design.This document is the property of International Rectifier and may not be copied or distributed without expressed consent.20IRMCF343 7.5 SYNC to SVPWM and A/D Conversion AC TimingSYNC IU,IV,IW t wSYNCt dSYNC1AINxt dSYNC2PWMUx,PWMVx,PWMWxt dSYNC3Unless specified, Ta = 25˚C.Symbol Parameter Min Typ Max Unitt wSYNC SYNC pulse width - 32 - SYSCLKt dSYNC1SYNC to currentfeedback conversiontime- - 100 SYSCLKt dSYNC2SYNC to AIN0-6analog inputconversion time - - 200 SYSCLK(1)t dSYNC3SYNC to PWM outputdelay time- - 2 SYSCLKTable 13. SYNC AC CharacteristicsNote:(1) AIN1 through AIN6 channels are converted once every 6 SYNC eventsIRMCF343 7.6 GATEKILL to SVPWM AC TimingUnless specified, Ta = 25˚C.Symbol Parameter Min Typ Max Unitt wGK GATEKILLpulsewidth 32 - - SYSCLKt dGK GATEKILL to PWMoutput delay- - 100 SYSCLK Table 14. GATEKILL to SVPWM AC TimingIRMCF3437.7 Interrupt AC TimingUnless specified, Ta = 25˚C. Symbol Parameter Min Typ Max Unitt wINT INT0, INT1 Interrupt Assertion Time4 - - SYSCLKt dINT INT0, INT1 latency - - 4 SYSCLKTable 15. Interrupt AC TimingIRMCF343 7.8 I2C AC TimingSCLSDA t I2ST1t I2ST2t I2WSETUPT I2CLKt I2WHOLD tI2RSETUPt I2RHOLDT I2CLKt I2EN1t I2EN2Unless specified, Ta = 25˚C.Symbol Parameter Min TypMax Unit T I2CLK I2C clock period 10 - 8192 SYSCLKt I2ST1I2C SDA start time 0.25 - - T I2CLKt I2ST2I2C SCL start time 0.25 - - T I2CLKt I2WSETUP I2C write setup time 0.25 - - T I2CLKt I2WHOLD I2C write hold time 0.25 - - T I2CLKt I2RSETUP I2C read setup time I2C filter time(1) - - SYSCLK t I2RHOLD I2C read hold time 1 - - SYSCLKTable 16. I2C AC TimingNote:(1) I2C read setup time is determined by the programmable filter time applied to I2Ccommunication.IRMCF3437.9 SPI AC Timing7.9.1 SPI Write AC timingUnless specified, Ta = 25˚C.Symbol Parameter Min Typ Max UnitT SPICLK SPI clock period 4 - - SYSCLK tSPICLKHT SPI clock high time - 1/2 - T SPICLKt SPICLKLT SPI clock low time - 1/2 - T SPICLK t CSDELAY CS to data delay time - - 10 nsec t WRDELAY CLK falling edge to datadelay time- - 10 nsect CSHIGH CS high time between two consecutive byte transfer1 - - T SPICLKtCSHOLD CS hold time - 1 - T SPICLKTable 17. SPI Write AC TimingIRMCF3437.9.2 SPI Read AC TimingUnless specified, Ta = 25˚C.Symbol Parameter Min Typ Max UnitTSPICLK SPI clock period 4 - - SYSCLKt SPICLKHT SPI clock high time - 1/2 - T SPICLK t SPICLKLT SPI clock low time - 1/2 - T SPICLKtCSRD CS to data delay time - - 10 nsec t RDSU SPI read data setup time 10 - - nsec t RDHOLD SPI read data hold time 10 - - nsec tCSHIGH CS high time between twoconsecutive byte transfer1 - - T SPICLKt CSHOLD CS hold time - 1 - T SPICLKTable 18. SPI Read AC TimingIRMCF343 7.10 UART AC TimingTXDRXDData and Parity BitStart BitT BAUDStop BitT UARTFILUnless specified, Ta = 25˚C.Symbol Parameter Min Typ Max Unit T BAUD Baud Rate Period - 57600 - bit/secT UARTFIL UART sampling filterperiod (1)- 1/16 - T BAUDTable 19. UART AC TimingNote:(1) Each bit including start and stop bit is sampled three times at center of a bit at an interval of1/16 T BAUD. If three sampled values do not agree, then UART noise error is generated.IRMCF343 7.11 CAPTURE Input AC TimingUnless specified, Ta = 25˚C.Symbol Parameter MinTyp Max UnitT CAPCLK CAPTUREinputperiod8 - - SYSCLKt CAPHIGH CAPTURE input hightime4 - - SYSCLKt CAPLOW CAPTURE input lowtime4 - - SYSCLKt CRDELAY CAPTURE falling edgeto capture register latchtime- - 4 SYSCLKt CLDELAY CAPTURE rising edgeto capture register latchtime- - 4 SYSCLK t INTDELAY CAPTUREinputinterrupt latency time- - 4 SYSCLKTable 20. CAPTURE AC TimingIRMCF343 7.12 JTAG AC TimingTCK TDO t JHIGHT JCLKt COt JLOWt JSETUPt JHOLDTDI/TMSUnless specified, Ta = 25˚C.Symbol Parameter MinTypMaxUnit T JCLK TCKPeriod - - 50 MHzt JHIGH TCK High Period 10 - - nsect JLOW TCK Low Period 10 - - nsect CO TCK to TDO propagationdelay time0 - 5 nsect JSETUP TDI/TMS setup time 4 - - nsect JHOLD TDI/TMS hold time 0 - - nsecTable 21. JTAG AC TimingIRMCF343 8 Pin ListPinNumber Pin Name Internal ICPull-up/Pull-downPinType Description1 XTAL0 I Crystalinput2 XTAL1 O Crystaloutput3 P1.0/T2 I/O Discreteprogrammable I/O or Timer/Counter 2input4 P1.1/RXD I/O Discrete programmable I/O or UART receiveinput5 P1.2/TXD I/O Discrete programmable I/O or UART transmitoutput6 P1.3/SYNC/SCK I/ODiscreteprogrammable I/O or SYNC output orSPI clock, needs to be pulled up to VDD1 inorder to boot from I2C EEPROM7 P1.4/CAP I/O Discreteprogrammable I/O or Capture Timerinput8 P1.5 I/O Discrete programmable I/O9 P1.6 I/O Discrete programmable I/O10 P1.7 I/O Discrete programmable I/O11 VDD2 P 1.8V digital power12 VSS P Digitalcommon13 VDD1 P 3.3V digital power14 P2.0/NMI I/O Discrete programmable I/O or Non-maskableInterrupt input15 P2.1 I/O Discrete programmable I/O16 P2.2 I/O Discrete programmable I/O17 P2.3 I/O Discrete programmable I/O18 P2.4 I/O Discrete programmable I/O19 P2.5 I/O Discrete programmable I/O20 P2.6/AOPWM0I/O Discrete programmable I/O or PWM 0 output21 P2.7/AOPWM1I/O Discrete programmable I/O or PWM 1 output22 VDD2 P 1.8V digital power23 VSS P Digitalcommon24 AIN0 I Analog input channel 0, 0-1.2V range, needs tobe pulled down to AVSS if unused25 AVDD P 1.8V analog power26 AVSS P Analogcommon27 AIN1 I Analog input channel 1, 0-1.2V range, needs tobe pulled down to AVSS if unused。

MCP7383XRD-PPM;中文规格书,Datasheet资料

© 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

FAN73892MX;中文规格书,Datasheet资料

Applications
3-Phase Motor Inverter Driver Air Conditioner, Washing Machine, Refrigerator, Dish Washer Industrial Inverter – Sewing Machine, Power Tool General-Purpose Three-Phase Inverter
28-SOIC
Ordering Information
Part Nuபைடு நூலகம்ber
FAN73892MX(1)
Package
28-SOIC
Operating Temperature
-40 to +125°C
Packing Method
Tape & Reel
Note: 1. These devices passed wave-soldering test by JESD22A-111.
Description
The FAN73892 is a monolithic three-phase half-bridge gate-drive IC designed for high-voltage, high-speed, driving MOSFETs and IGBTs operating up to +600V. Fairchild’s high-voltage process and common-mode noise-canceling technique provide stable operation of high-side drivers under high-dv/dt noise circumstances. An advanced level-shift circuit allows high-side gate driver operation up to VS = -9.8V (typical) for VBS =15V. The protection functions include under-voltage lockout and inverter over-current trip with an automatic faultclear function. Over-current protection that terminates all six outputs can be derived from an external currentsense resistor. An open-drain fault signal is provided to indicate that an over-current or under-voltage shutdown has occurred. The UVLO circuits prevent malfunction when VDD and VBS are lower than the threshold voltage. Output drivers typically source and sink 350mA and 650mA, respectively; which is suitable for three-phase half-bridge applications in motor drive systems.

MCP73831中文

MCP73831
功能原理框图
VDD 6 µA 方向控制 VBAT
6 µA
G=0.001
PROG
0.5 µA + 参考电压发生器（1.22V） VREF 361 kΩ + 89 kΩ 111 kΩ + 终止 + 充电 + VA 15 kΩ STAT 预充 182.3 kΩ 43.6 kΩ 3.9 kΩ CA
温度参数
电气规范：除另有说明外，所有参数适用于 VDD = [VREG （典型值）+ 0.3V] 至 12V。典型值参数条件是在 +25°C， VDD = [VREG （典型值）+ 1.0V] 下。参数温度范围规定温度范围工作温度范围储存温度范围封装热阻 5 引脚， SOT23 8 引脚， 2 mm x 3 mm， DFN θJA θJA — — 230 76 — — °C/W °C/W 4 层 JC51-7 标准 PCB 板，自然对流 4 层 JC51-7 标准 PCB 板，自然对流 TA TJ TA -40 -40 -65 — — — +85 +125 +150 °C °C °C 符号最小值典型值最大值单位条件
7 kΩ
190 kΩ
111 kΩ 0.5 µA VBAT + + 477 kΩ 255 kΩ 100 kΩ + SHDN 方向控制 UVLO
VSS
DS21984A_CN 第 2 页
2006 Microchip Technology Inc.
MCP73831
1.0 电气特性
最大额定值 †
VDDN .................................................................................7.0V 相对于 VSS 的所有输入输出 ...................... -0.3 至 (VDD+0.3)V 最大结温 TJ .............................................................. 内部限制储存温度 ....................................................... -65°C 至 +150°C 所有引脚的 ESD 保护参数：人体模型（1.5 kΩ 与 100pF 串联）..................................≥ 4 kV 机器模型（200pF，无电阻与之串联） ...........................400V † 注：如果器件运行条件超过上述各项绝对最大额定值，即可能对器件造成永久性损坏。上述参数为运行条件的极大值，我们不建议器件在该规定范围外运行。器件长时间工作在绝对最大额定条件下，其稳定性会受到影响。

FAN7388MX;FAN7388M;中文规格书,Datasheet资料

Channels with 270ns Typical Dead Time Built-in Common Mode dv/dt Noise Canceling Circuit Built-in UVLO Functions for All Channels
Applications
3-Phase Motor Inverter Driver
WUWLΒιβλιοθήκη 1 HIN1 2 LIN1 3 HIN2 4 LIN2 5 HIN3 6 LIN3 7 LO3 8 VS3 9 HO3 10 VB3
VB1 20 HO1 19
VS1 18 LO1 17 VB2 16 HO2 15 VS2 14 LO2 13
VDD 12 GND 11
Up to 600V
VS1 Q1
Q3
Q1 Q3 Q5 VS1
Q5 IU
3-Phase Inverter
VS2
VS2
IV
Q4
Q6
Q2
VS3
IW
Q4
Q6
Q2
VS3
U
V W
Figure 1. 3-Phase BLDC Motor Drive Application
Internal Block Diagram
HIN1 HIN2 HIN3 LIN1 LIN2 LIN3
© 2008 Fairchild Semiconductor Corporation
FAN7388 • Rev.1.0.0
3
/

FAN7388 — 3 Half-Bridge Gate-Drive IC
Absolute Maximum Ratings
Tape & Reel

CY37384VP256-100BAXC资料

5V, 3.3V, ISR™ High-Performance CPLDsUltra37000 CPLD FamilyFeatures•In-System Reprogrammable™ (ISR™) CMOS CPLDs —JTAG interface for reconfigurability—Design changes do not cause pinout changes—Design changes do not cause timing changes •High density—32 to 512 macrocells—32 to 264 I/O pins—Five dedicated inputs including four clock pins •Simple timing model—No fanout delays—No expander delays—No dedicated vs. I/O pin delays—No additional delay through PIM—No penalty for using full 16 product terms—No delay for steering or sharing product terms •3.3V and 5V versions•PCI-compatible[1]•Programmable bus-hold capabilities on all I/Os •Intelligent product term allocator provides:—0 to 16 product terms to any macrocell—Product term steering on an individual basis—Product term sharing among local macrocells •Flexible clocking—Four synchronous clocks per device—Product term clocking—Clock polarity control per logic block•Consistent package/pinout offering across all densities —Simplifies design migration—Same pinout for 3.3V and 5.0V devices •Packages—44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP, BGA, and Fine-Pitch BGA packages—Lead(Pb)-free packages available General DescriptionThe Ultra37000™ family of CMOS CPLDs provides a range of high-density programmable logic solutions with unparalleled system performance. The Ultra37000 family is designed to bring the flexibility, ease of use, and performance of the 22V10 to high-density CPLDs. The architecture is based on a number of logic blocks that are connected by a Programmable Inter-connect Matrix (PIM). Each logic block features its own product term array, product term allocator, and 16 macrocells. The PIM distributes signals from the logic block outputs and all input pins to the logic block inputs.All of the Ultra37000 devices are electrically erasable and In-System Reprogrammable (ISR), which simplifies both design and manufacturing flows, thereby reducing costs. The ISR feature provides the ability to reconfigure the devices without having design changes cause pinout or timing changes. The Cypress ISR function is implemented through a JTAG-compliant serial interface. Data is shifted in and out through the TDI and TDO pins, respectively. Because of the superior routability and simple timing model of the Ultra37000 devices, ISR allows users to change existing logic designs while simultaneously fixing pinout assignments and maintaining system performance.The entire family features JTAG for ISR and boundary scan, and is compatible with the PCI Local Bus specification, meeting the electrical and timing requirements. The Ultra37000 family features user programmable bus-hold capabilities on all I/Os.Ultra37000 5.0V DevicesThe Ultra37000 devices operate with a 5V supply and can support 5V or 3.3V I/O levels. V CCO connections provide the capability of interfacing to either a 5V or 3.3V bus. By connecting the V CCO pins to 5V the user insures 5V TTL levels on the outputs. If V CCO is connected to 3.3V the output levels meet 3.3V JEDEC standard CMOS levels and are 5V tolerant. These devices require 5V ISR programming.Ultra37000V 3.3V DevicesDevices operating with a 3.3V supply require 3.3V on all V CCO pins, reducing the device’s power consumption. These devices support 3.3V JEDEC standard CMOS output levels, and are 5V-tolerant. These devices allow 3.3V ISR programming.Note:1.Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to V CC, PCI V IH = 2V.Selection Guide5.0V Selection GuideGeneral InformationDevice Macrocells Dedicated Inputs I/O Pins Speed (t PD)Speed(f MAX) CY37032325326200 CY3706464532/646200 CY37128128564/128 6.5167 CY3719219251207.5154 CY372562565128/160/1927.5154 CY373843845160/19210118 CY375125125160/192/26410118Speed BinsDevice2001671541431251008366 CY37032X X XCY37064X X XCY37128X X XCY37192X X XCY37256 X X XCY37384X XCY37512X X XDevice-Package Offering and I/O CountDevice44-LeadTQFP44-LeadPLCC44-LeadCLCC84-LeadPLCC84-LeadCLCC100-LeadTQFP160-LeadTQFP160-LeadCQFP208-LeadPQFP208-LeadCQFP256-LeadBGA352-LeadBGACY370323737CY370643737376969CY37128696969133CY37192125CY37256133133165197CY37384165197CY37512165165197269 3.3V Selection GuideGeneral InformationDevice Macrocells Dedicated Inputs I/O Pins Speed (t PD)Speed(f MAX) CY37032V325328.5143 CY37064V64532/648.5143 CY37128V128564/80/12810125 CY37192V192512012100 CY37256V2565128/160/19212100 CY37384V3845160/1921583 CY37512V5125160/192/2641583Architecture Overview of Ultra37000 FamilyProgrammable Interconnect MatrixThe PIM consists of a completely global routing matrix for signals from I/O pins and feedbacks from the logic blocks. The PIM provides extremely robust interconnection to avoid fitting and density limitations.The inputs to the PIM consist of all I/O and dedicated input pins and all macrocell feedbacks from within the logic blocks. The number of PIM inputs increases with pin count and the number of logic blocks. The outputs from the PIM are signals routed to the appropriate logic blocks. Each logic block receives 36inputs from the PIM and their complements, allowing for 32-bit operations to be implemented in a single pass through the device. The wide number of inputs to the logic block also improves the routing capacity of the Ultra37000 family.An important feature of the PIM is its simple timing. The propa-gation delay through the PIM is accounted for in the timing specifications for each device. There is no additional delay for traveling through the PIM. In fact, all inputs travel through the PIM. As a result, there are no route-dependent timing param-eters on the Ultra37000 devices. The worst-case PIM delays are incorporated in all appropriate Ultra37000 specifications. Routing signals through the PIM is completely invisible to the user. All routing is accomplished by software—no hand routing is necessary. Warp and third-party development packages automatically route designs for the Ultra37000 family in a matter of minutes. Finally, the rich routing resources of the Ultra37000 family accommodate last minute logic changes while maintaining fixed pin assignments.Logic BlockThe logic block is the basic building block of the Ultra37000architecture. It consists of a product term array, an intelligent product-term allocator, 16 macrocells, and a number of I/O cells. The number of I/O cells varies depending on the device used. Refer to Figure 1 for the block diagram.Product Term ArrayEach logic block features a 72 x 87 programmable product term array. This array accepts 36 inputs from the PIM, which originate from macrocell feedbacks and device pins. Active LOW and active HIGH versions of each of these inputs are generated to create the full 72-input field. The 87 product terms in the array can be created from any of the 72 inputs. Of the 87 product terms, 80 are for general-purpose use for the 16 macrocells in the logic block. Four of the remaining seven product terms in the logic block are output enable (OE)product terms. Each of the OE product terms controls up to eight of the 16 macrocells and is selectable on an individual macrocell basis. In other words, each I/O cell can select between one of two OE product terms to control the output buffer. The first two of these four OE product terms are available to the upper half of the I/O macrocells in a logic block.The other two OE product terms are available to the lower half of the I/O macrocells in a logic block.The next two product terms in each logic block are dedicated asynchronous set and asynchronous reset product terms. The final product term is the product term clock. The set, reset, OE and product term clock have polarity control to realize OR functions in a single pass through the array.Speed BinsDevice 2001671541431251008366CY37032V X X CY37064V XXCY37128V XXCY37192V X X CY37256V XX CY37384V X X CY37512VXXDevice-Package Offering and I/O CountDevice 44-L e a d T Q F P 44-L e a d C L C C 48-L e a d F B G A 84-L e a d C L C C 100-L e a d T Q F P 100-L e a d F B G A 160-L e a d T Q F P 160-L e a d C Q F P 208-L e a d P Q F P 208-L e a d C Q F P 256-L e a d B G A 256-L e a d F B G A 352-L e a d B G A 400-L e a d F B G ACY37032V 3737CY37064V 3737376969CY37128V 696985133CY37192V 125CY37256V 133133165197197CY37384V 165197CY37512V165165197269269Low-Power OptionEach logic block can operate in high-speed mode for critical path performance, or in low-power mode for power conser-vation. The logic block mode is set by the user on a logic block by logic block basis. Product Term AllocatorThrough the product term allocator, software automatically distributes product terms among the 16 macrocells in the logic block as needed. A total of 80 product terms are available from the local product term array. The product term allocator provides two important capabilities without affecting perfor-mance: product term steering and product term sharing. Product Term SteeringProduct term steering is the process of assigning product terms to macrocells as needed. For example, if one macrocell requires ten product terms while another needs just three, the product term allocator will “steer” ten product terms to one macrocell and three to the other. On Ultra37000 devices,product terms are steered on an individual basis. Any number between 0 and 16 product terms can be steered to any macrocell. Note that 0 product terms is useful in cases where a particular macrocell is unused or used as an input register. Product Term SharingProduct term sharing is the process of using the same product term among multiple macrocells. For example, if more than one output has one or more product terms in its equation that are common to other outputs, those product terms are only programmed once. The Ultra37000 product term allocator allows sharing across groups of four output macrocells in avariable fashion. The software automatically takes advantage of this capability—the user does not have to intervene. Note that neither product term sharing nor product term steering have any effect on the speed of the product. All worst-case steering and sharing configurations have been incorporated in the timing specifications for the Ultra37000devices.Ultra37000 MacrocellWithin each logic block there are 16 macrocells. Macrocells can either be I/O Macrocells, which include an I/O Cell which is associated with an I/O pin, or buried Macrocells, which do not connect to an I/O. The combination of I/O Macrocells and buried Macrocells varies from device to device.Buried MacrocellFigure 2 displays the architecture of buried macrocells. The buried macrocell features a register that can be configured as combinatorial, a D flip-flop, a T flip-flop, or a level-triggered latch.The register can be asynchronously set or asynchronously reset at the logic block level with the separate set and reset product terms. Each of these product terms features program-mable polarity. This allows the registers to be set or reset based on an AND expression or an OR expression.Clocking of the register is very flexible. Four global synchronous clocks and a product term clock are available to clock the register. Furthermore, each clock features program-mable polarity so that registers can be triggered on falling as well as rising edges (see the Clocking section). Clock polarity is chosen at the logic block level.Figure 1. Logic Block with 50% Buried MacrocellsI/O CELL 0PRODUCT TERM ALLOCATORI/O CELL 14MACRO-CELL 0MACRO-CELL 1MACRO-CELL 140−16PRODUCT TERMS72x 87PRODUCT TERMARRAY8036816TO PIMFROM PIM732MACRO-CELL 152to cells2, 4, 6 8, 10, 120−16PRODUCT TERMS0−16PRODUCT TERMS0−16PRODUCT TERMSThe buried macrocell also supports input register capability.The buried macrocell can be configured to act as an input register (D-type or latch) whose input comes from the I/O pin associated with the neighboring macrocell. The output of all buried macrocells is sent directly to the PIM regardless of its configuration. I/O MacrocellFigure 2 illustrates the architecture of the I/O macrocell. The I/O macrocell supports the same functions as the buried macrocell with the addition of I/O capability. At the output of the macrocell, a polarity control mux is available to select active LOW or active HIGH signals. This has the added advantage of allowing significant logic reduction to occur in many appli-cations.The Ultra37000 macrocell features a feedback path to the PIM separate from the I/O pin input path. This means that if the macrocell is buried (fed back internally only), the associated I/O pin can still be used as an input.Bus Hold Capabilities on all I/OsBus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latch connected to the pin that does not degrade the device’s performance. As a latch, bus-hold maintains the last state of a pin when the pin is placed in a high-impedance state, thus reducing system noise in bus-interface applications. Bus-hold additionally allows unused device pins to remain unconnected on the board,which is particularly useful during prototyping as designers can route new signals to the device without cutting trace connec-tions to V CC or GND. For more information, see the application note Understanding Bus-Hold—A Feature of Cypress CPLDs .Programmable Slew Rate ControlEach output has a programmable configuration bit, which sets the output slew rate to fast or slow. For designs concerned with meeting FCC emissions standards the slow edge provides for lower system noise. For designs requiring very high perfor-mance the fast edge rate provides maximum system perfor-mance.C2C3DECODE C2C3DECODE 0123OC6C5“0” “1”1OD/T/LQRP 0123OC001OC4FEEDBACK TO PIM FEEDBACK TO PIMBLOCK RESET0−16TERMSI/O MACROCELLI/O CELLFROM PTM1OD/T/LQRP FROM PTM 1OC7FEEDBACK TO PIMBURIED MACROCELLASYNCHRONOUS PRODUCT 0−16TERMSPRODUCT C140123Q4C24C0C1C24C25C254 SYNCHRONOUS CLOCKS (CLK0,CLK1,CLK2,CLK3)1 ASYNCHRONOUS CLOCK(PTCLK)BLOCK PRESETASYNCHRONOUSFASTSLOWC26SLEW011011OE0OE1Figure 2. I/O and Buried MacrocellsClockin gEach I/O and buried macrocell has access to four synchronous clocks (CLK0, CLK1, CLK2 and CLK3) as well as an asynchronous product term clock PTCLK. Each input macrocell has access to all four synchronous clocks.Dedicated Inputs/ClocksFive pins on each member of the Ultra37000 family are desig-nated as input-only. There are two types of dedicated inputs on Ultra37000 devices: input pins and input/clock pins.Figure 3 illustrates the architecture for input pins. Four input options are available for the user: combinatorial, registered,double-registered, or latched. If a registered or latched option is selected, any one of the input clocks can be selected for control.Figure 4 illustrates the architecture for the input/clock pins.Like the input pins, input/clock pins can be combinatorial,registered, double-registered, or latched. In addition, these pins feed the clocking structures throughout the device. The clock path at the input has user-configurable polarity. Product Term ClockingIn addition to the four synchronous clocks, the Ultra37000family also has a product term clock for asynchronous clocking. Each logic block has an independent product term clock which is available to all 16 macrocells. Each product term clock also supports user configurable polarity selection.Timing ModelOne of the most important features of the Ultra37000 family is the simplicity of its timing. All delays are worst case and system performance is unaffected by the features used. Figure 5 illustrates the true timing model for the 167-MHz devices in high speed mode. For combinatorial paths, any input to any output incurs a 6.5-ns worst-case delay regardless of the amount of logic used. For synchronous systems, the input set-up time to the output macrocells for any input is 3.5 ns and the clock to output time is also 4.0 ns. These measurements are for any output and synchronous clock, regardless of the logic used.The Ultra37000 features:•No fanout delays •No expander delays•No dedicated vs. I/O pin delays •No additional delay through PIM •No penalty for using 0–16 product terms •No added delay for steering product terms •No added delay for sharing product terms •No routing delays •No output bypass delaysThe simple timing model of the Ultra37000 family eliminates unexpected performance penalties.Figure 4. Input/Clock MacrocellFigure 3. Input Macrocell0123OC10C11TO PIMDQDQD QLEINPUT/CLOCK PIN012OFROM CLOCK CLOCK PINS01OC12TO CLOCK MUX ONALL INPUT MACROCELLSTO CLOCK MUX IN EACH301CLOCK POLARITY MUX ONE PER LOGIC BLOCK FOR EACH CLOCK INPUTPOLARITY INPUTLOGIC BLOCKC8C9C13,C14,C15OR C16O 0123O C12C13TO PIMDQDQD QLEINPUT PIN012OC10FROM CLOCK POLARITY MUXES3C11JTAG and PCI StandardsPCI Compliance5V operation of the Ultra37000 is fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The 3.3V products meet all PCI requirements except for the output 3.3V clamp, which is in direct conflict with 5V tolerance. The Ultra37000 family’s simple and predictable timing model ensures compliance with the PCI AC specifica-tions independent of the design. IEEE 1149.1-compliant JTAGThe Ultra37000 family has an IEEE 1149.1 JTAG interface for both Boundary Scan and ISR.Boundary ScanThe Ultra37000 family supports Bypass, Sample/Preload,Extest, Idcode, and Usercode boundary scan instructions. The JTAG interface is shown in Figure 6.In-System Reprogramming (ISR)In-System Reprogramming is the combination of the capability to program or reprogram a device on-board, and the ability to support design changes without changing the system timing or device pinout. This combination means design changes during debug or field upgrades do not cause board respins.The Ultra37000 family implements ISR by providing a JTAG compliant interface for on-board programming, robust routingresources for pinout flexibility, and a simple timing model for consistent system performance.Development Software SupportWarpWarp is a state-of-the-art compiler and complete CPLD design tool. For design entry, Warp provides an IEEE-STD-1076/1164VHDL text editor, an IEEE-STD-1364 Verilog text editor, and a graphical finite state machine editor. It provides optimized synthesis and fitting by replacing basic circuits with ones pre-optimized for the target device, by implementing logic in unused memory and by perfect communication between fitting and synthesis. To facilitate design and debugging, Warp provides graphical timing simulation and analysis. Warp Professional ™Warp Professional contains several additional features. It provides an extra method of design entry with its graphical block diagram editor. It allows up to 5 ms timing simulation instead of only 2 ms. It allows comparison of waveforms before and after design changes.Warp Enterprise ™Warp Enterprise provides even more features. It provides unlimited timing simulation and source-level behavioral simulation as well as a debugger. It has the ability to generate graphical HDL blocks from HDL text. It can even generate testbenches.Warp is available for PC and UNIX platforms. Some features are not available in the UNIX version. For further information see the Warp for PC , Warp for UNIX, Warp Professional and Warp Enterprise data sheets on Cypress’s web site ().Third-Party SoftwareAlthough Warp is a complete CPLD development tool on its own, it interfaces with nearly every third party EDA tool. All major third-party software vendors provide support for the Ultra37000 family of devices. Refer to the third-party software data sheet or contact your local sales office for a list of currently supported third-party vendors.ProgrammingThere are four programming options available for Ultra37000devices. The first method is to use a PC with the 37000UltraISR programming cable and software. With this method,the ISR pins of the Ultra37000 devices are routed to a connector at the edge of the printed circuit board. The 37000UltraISR programming cable is then connected between the parallel port of the PC and this connector. A simple configu-ration file instructs the ISR software of the programming operations to be performed on each of the Ultra37000 devices in the system. The ISR software then automatically completes all of the necessary data manipulations required to accomplish the programming, reading, verifying, and other ISR functions.For more information on the Cypress ISR Interface, see the ISR Programming Kit data sheet (CY3700i).The second method for programming Ultra37000 devices is on automatic test equipment (ATE). This is accomplished through a file created by the ISR software. Check the Cypress website for the latest ISR software download information.Figure 5. Timing Model for CY37128Figure 6. JTAG InterfaceCOMBINATORIAL SIGNALREGISTERED SIGNALD,T,LOCLOCKINPUTINPUTOUTPUTOUTPUTt S = 3.5 nst CO = 4.5 nst PD = 6.5 ns Instruction RegisterBoundary Scan idcode Usercode ISR Prog.Bypass Reg.Data RegistersJTAG TAPCONTROLLERTDOTDITMS TCKThe third programming option for Ultra37000 devices is to utilize the embedded controller or processor that already exists in the system. The Ultra37000 ISR software assists in this method by converting the device JEDEC maps into the ISR serial stream that contains the ISR instruction information and the addresses and data of locations to be programmed. The embedded controller then simply directs this ISR stream to the chain of Ultra37000 devices to complete the desired reconfiguring or diagnostic operations. Contact your local sales office for information on availability of this option.The fourth method for programming Ultra37000 devices is to use the same programmer that is currently being used to program F LASH370i devices.For all pinout, electrical, and timing requirements, refer to device data sheets. For ISR cable and software specifications, refer to the UltraISR kit data sheet (CY3700i).Third-Party ProgrammersAs with development software, Cypress support is available on a wide variety of third-party programmers. All major third-party programmers (including BP Micro, Data I/O, and SMS) support the Ultra37000 family.Logic Block DiagramsCY37032/CY37032VLOGIC BLOCK B LOGIC BLOCK A36163616Input Clock/Input 16 I/Os16 I/OsI/O 0−I/O 15I/O 16−I/O 314441616TDI TCK TMSTDOJTAG Tap Controller1PIMJTAG ENLOGIC BLOCK D LOGIC BLOCK CLOGIC BLOCK A LOGIC BLOCK B3616361636163616InputClock/Input16 I/Os16 I/Os16 I/Os16 I/OsI/O 0-I/O 15I/O 16-I/O 31I/O 48-I/O 63I/O 32-I/O 474443232TDI TCK TMSTDOJTAG Tap Controller1PIMCY37064/CY37064V (100-Lead TQFP)Logic Block Diagrams (continued)TDITCK TMSTDOJTAG Tap ControllerCY37128/CY37128V (160-lead TQFP)PIMINPUTMACROCELL CLOCKINPUTS 4436161636LOGIC BLOCK3616163616 I/Os3636361616361616646441INPUT/CLOCK MACROCELLSI/O 0–I/O 15AINPUTS LOGIC BLOCKCLOGIC BLOCKBLOGIC BLOCKDLOGIC BLOCKHLOGIC BLOCKGLOGIC BLOCKFLOGIC BLOCKEI/O 16–I/O 31I/O 32–I/O 47I/O 28–I/O 63I/O 112–I/O 127I/O 96–I/O 111I/O 80–I/O 95I/O 64–I/O 7916 I/Os16 I/Os16 I/Os16 I/Os16 I/Os16 I/Os16 I/OsJTAG ENLOGIC BLOCK H LOGIC BLOCK L LOGIC BLOCKI LOGIC BLOCK J LOGIC BLOCK K LOGIC BLOCK A LOGIC BLOCK B LOGIC BLOCK C LOGIC BLOCK D LOGIC BLOCK E LOGIC BLOCK G LOGIC BLOCK F361636163616361636163616361636163616361636163616PIMInput Clock/Input 10 I/Os10 I/Os10 I/Os10 I/Os10 I/Os10 I/Os10 I/Os10 I/Os10 I/Os10 I/Os10 I/Os10 I/OsI/O 0–I/O 9I/O 10–I/O 19I/O 20–I/O 29I/O 30–I/O 39I/O 40–I/O 49I/O 50–I/O 59I/O 110–I/O 119I/O 100–I/O 109I/O 90–I/O 99I/O 80–I/O 89I/O 70–I/O 79I/O 60–I/O 694446060TDI TCK TMSTDOJTAG Tap Controller1CY37192/CY37192V (160-lead TQFP)Logic Block Diagrams (continued)CY37256/CY37256V (256-lead BGA)LOGIC BLOCK G LOGIC BLOCK HLOGIC BLOCKI LOGIC BLOCK J LOGIC BLOCK L LOGIC BLOCK P LOGIC BLOCK M LOGIC BLOCK N LOGIC BLOCK O LOGIC BLOCK A LOGIC BLOCK B LOGIC BLOCK C LOGIC BLOCK D LOGIC BLOCK E LOGIC BLOCK K LOGIC BLOCK F 3616361636163616361636163616361636163616361636163616361636163616PIMInput Clock/Input 12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os 12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/OsI/O 0−I/O 11I/O 12−I/O 23I/O 24−I/O 35I/O 36−I/O 47I/O 48−I/O 59I/O 60−I/O 71I/O 72−I/O 83I/O 84−I/O 95I/O 180−I/O 191I/O 168−I/O 179I/O 156−I/O 167I/O 144−I/O 155I/O 132−I/O 143I/O 120−I/O 131I/O 108−I/O 119I/O 96−I/O 1074449696TDI TCK TMSTDOJTAG Tap Controller1Logic Block Diagrams (continued)CY37384/CY37384V (256-Lead BGA)LOGIC BLOCK AH LOGIC BLOCK AI LOGIC BLOCK BD LOGIC BLOCK BE LOGIC BLOCK BG LOGIC BLOCK BL LOGIC BLOCK BI LOGIC BLOCK BJ LOGIC BLOCK BK LOGIC BLOCK AA LOGIC BLOCK AB LOGIC BLOCK AC LOGIC BLOCK ADLOGIC BLOCK AFLOGIC BLOCK BF LOGIC BLOCK AG 3616361636163616361636163616361636163616361636163616361636163616PIMInput Clock/Input 12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/OsI/O 0−I/O 11I/O 12−I/O 23I/O 24−I/O 35I/O 48−I/O 59I/O 60−I/O 71I/O 72−I/O 83I/O 168−I/O 191I/O 156−I/O 179I/O 144−I/O 167I/O 120−I/O 143I/O 108−I/O 1314449696TDI TCK TMSTDOJTAG Tap Controller1LOGIC BLOCK AJLOGIC BLOCK BC 161612 I/OsI/O 96−I/O 119LOGIC BLOCK AK LOGIC BLOCK BB 161612 I/OsI/O 84−I/O 95LOGIC BLOCK ALLOGIC BLOCK BA161612 I/OsI/O 96−I/O 107LOGIC BLOCK AE LOGIC BLOCK BH 161612 I/Os12 I/OsI/O 36−I/O 47I/O 132−I/O 1553636363636363636Logic Block Diagrams (continued)CY37512/CY37512V (352-Lead BGA)LOGIC BLOCK AG LOGIC BLOCK AHLOGIC BLOCK BI LOGIC BLOCK BJ LOGIC BLOCK BL LOGIC BLOCK BP LOGIC BLOCK BM LOGIC BLOCK BN LOGIC BLOCK BO LOGIC BLOCK AA LOGIC BLOCK AB LOGIC BLOCK AC LOGIC BLOCK ADLOGIC BLOCK AE LOGIC BLOCK BK LOGIC BLOCK AF361636163616361636163616361636363616361636163616361636163616Input Clock/Input 12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/OsI/O 0−I/O 11I/O 12−I/O 23I/O 24−I/O 35I/O 36−I/O 47I/O 48−I/O 59I/O 60−I/O 71I/O 72−I/O 83I/O 84−I/O 95I/O 252−I/O 263I/O 240−I/O 251I/O 228−I/O 239I/O 216−I/O 227I/O 204−I/O 215444TDI TCK TMSTDOJTAG T ap Controller1PIM16363616LOGIC BLOCK AI LOGIC BLOCK BH 12 I/OsI/O 96−I/O 10716363616LOGIC BLOCK AJLOGIC BLOCK BG 12 I/Os12 I/OsI/O 108−I/O 119I/O 192−I/O 20316363616LOGIC BLOCK AK LOGIC BLOCK BF 12 I/OsI/O 120−I/O 13116363616LOGIC BLOCK AL LOGIC BLOCK BE 12 I/OsI/O 180−I/O 19116363616LOGIC BLOCK AM LOGIC BLOCK BD 12 I/OsI/O 168−I/O 17916363616LOGIC BLOCK AN LOGIC BLOCK BC 12 I/OsI/O 156−I/O 16716363616LOGIC BLOCK AO LOGIC BLOCK BB 12 I/OsI/O 144−I/O 155********LOGIC BLOCK AP LOGIC BLOCK BA 12 I/OsI/O 132−I/O 1431613216。

AN7384N中文资料

4 13
1.8kΩ
5
30µA
元器件交易网
AN7384N
s Pin Descriptions (Cont.)
Pin No.
Pin Name
Description
6
A-ch. Control Voltage Output
Control DC voltage buffer output pin
Tstg
ICs for Audio Common Use
Rating
Unit
±12
V
30
mA
800
mW
–20 ~ + 70
˚C
–55 ~ +150
˚C
s Recommended Operating Range (Ta = 25˚C)
Parameter Operating Supply Voltage Range
10
Volume Mode/Balance Low – independent volume control
Mode Switching
High – coalition volume balance control
mode
10
Vref 2
11
Reference Voltage Output
Reference voltage output pin
Negative Side Circuit Current Attenuation – 1 Attenuation – 2 Channel Balance – 1 Distortion Rate – 1 Distortion Rate – 2 Noise Output Voltage – 1 Noise Output Voltage – 2 Channel Balance – 2 Max. Input Voltage Max. Output Voltage Control Voltage Range

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MCP73837/8AC/USB Dual Input Battery ChargerEvaluation BoardUser’s GuideInformation contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY , PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE . Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnifyand hold harmless Microchip from any and all damages,claims, suits, or expenses resulting from such use. Nolicenses are conveyed, implicitly or otherwise, under anyMicrochip intellectual property rights.TrademarksThe Microchip name and logo, the Microchip logo, Accuron,dsPIC, K EE L OQ , K EE L OQ logo, micro ID , MPLAB, PIC, PICmi-cro, PICSTART, PRO MATE, rfPIC and SmartShunt are regis-tered trademarks of Microchip Technology Incorporated in theU.S.A. and other countries.AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trade-marks of Microchip Technology Incorporated in the U.S.A.Analog-for-the-Digital Age, Application Maestro, CodeGuard,dsPICDEM, , dsPICworks, dsSPEAK, ECAN,ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Cir-cuit Serial Programming, ICSP , ICEPIC, Mindi, MiWi, MPASM,MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM,, PICLAB, PICtail, PowerCal, PowerInfo, Power-Mate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.All other trademarks mentioned herein are property of theirrespective companies.© 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.Note the following details of the code protection feature on Microchip devices:•Microchip products meet the specification contained in their particular Microchip Data Sheet.•Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to ourknowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.•Microchip is willing to work with the customer who is concerned about the integrity of their code.•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.Microchip received ISO/TS-16949:2002 certification for its worldwideheadquarters, design and wafer fabrication facilities in Chandler andTempe, Arizona; Gresham, Oregon and design centers in Californiaand India. The Company’s quality system processes and proceduresare for its PIC ® MCUs and dsPIC ® DSCs, K EE L OQ ® code hoppingdevices, Serial EEPROMs, microperipherals, nonvolatile memory andanalog products. In addition, Microchip’s quality system for the designand manufacture of development systems is ISO 9001:2000 certified.MCP73837/8 AC/USB EVALUATIONBOARD USER’S GUIDETable of ContentsPreface (1)Introduction (1)Document Layout (1)Conventions Used in this Guide (2)Recommended Reading (2)The Microchip Web Site (3)Customer Support (3)Document Revision History (3)Chapter 1. Product Overview1.1 Introduction (5)1.2 What is the MCP73837/8 AC/USB Dual Input Battery Charger EvaluationBoard? (6)1.3 What the MCP73837/8 AC/USB Dual Input Battery Charger Evaluation BoardKit Includes (6)Chapter 2. Installation and Operation2.1 Introduction (7)2.2 Features (7)2.3 Getting Started (8)Appendix A. Schematic and LayoutsA.1 Introduction (11)A.2 Board – Schematic (12)A.3 Board – Top Layer (13)A.4 Board – Top Metal Layer (14)A.5 Board – Bottom Layer (15)Appendix B. Bill Of Materials (BOM)Worldwide Sales and Service (18)MCP73837/8 AC/USB Evaluation Board User’s Guide NOTES:MCP73837/8 AC/USB EVALUATIONBOARD USER’S GUIDEPrefaceAll documentation becomes dated, and this manual is no exception. Microchip tools and documentation are constantly evolving to meet customer needs, so some actual dialogsand/or tool descriptions may differ from those in this document. Please refer to our web site () to obtain the latest documentation available.Documents are identified with a “DS” number. This number is located on the bottom of each page, in front of the page number. The numbering convention for the DS number is“DSXXXXXA”, where “XXXXX” is the document number and “A” is the revision level of the document.For the most up-to-date information on development tools, see the MPLAB® IDE on-line help.Select the Help menu, and then Topics to open a list of available on-line help files.INTRODUCTIONThis chapter contains general information that will be useful to know before using theMCP73837/8 AC/USB Dual Input Battery Charger Evaluation Board. Items discussedin this chapter include:•Document Layout•Conventions Used in this Guide•Recommended Reading•The Microchip Web Site•Customer Support•Document Revision HistoryDOCUMENT LAYOUTThis document describes how to use the MCP73837/8 AC/USB Dual Input BatteryCharger Evaluation Board. The manual layout is as follows:•Chapter 1.“Product Overview” – Important information about the MCP73837/8AC/USB Dual Input Battery Charger Evaluation Board.•Chapter 2.“Installation and Operation” – Includes instructions on how to getstarted with this user’s guide and a description of the user’s guide.•Appendix A.“Schematic and Layouts” – Shows the schematic and layoutdiagrams for the MCP73837/8 AC/USB Dual Input Battery Charger EvaluationBoard.•Appendix B.“Bill Of Materials (BOM)” – Lists the parts used to build theMCP73837/8 AC/USB Dual Input Battery Charger Evaluation Board.MCP73837/8 AC/USB Evaluation Board User’s Guide CONVENTIONS USED IN THIS GUIDEThis manual uses the following documentation conventions:RECOMMENDED READINGThis user's guide describes how to use MCP73837/8 AC/USB Dual Input BatteryCharger Evaluation Board. Other useful documents are listed below. The followingMicrochip documents are available and recommended as supplemental referenceresources.MCP73837/8 Data Sheet, “Advanced Stand-Alone Li-Ion / Li-Polymer BatteryCharge Management Controller with Autonomous AC-Adapter or USB-PortSource Selection”, DS22071This data sheet provides detailed information regarding the MCP73837/8 productfamily.DOCUMENTATION CONVENTIONSDescriptionRepresents Examples Arial font:Italic charactersReferenced books MPLAB ® IDE User’s Guide Emphasized text ...is the only compiler...Initial caps A windowthe Output window A dialogthe Settings dialog A menu selectionselect Enable Programmer Quotes A field name in a window ordialog“Save project before build”Underlined, italic text with right angle bracket A menu pathFile>Save Bold characters A dialog buttonClick OK A tabClick the Power tab N‘Rnnnn A number in verilog format,where N is the total number ofdigits, R is the radix and n is adigit.4‘b0010, 2‘hF1Text in angle brackets < > A key on the keyboardPress <Enter>, <F1>Courier New font:Plain Courier New Sample source code#define START Filenamesautoexec.bat File pathsc:\mcc18\h Keywords_asm, _endasm, static Command-line options-Opa+, -Opa-Bit values0, 1Constants0xFF, ‘A’Italic Courier New A variable argumentfile .o , where file can be any valid filename Square brackets [ ]Optional argumentsmcc18 [options] file [options]Curly brackets and pipe character: { | }Choice of mutually exclusivearguments; an OR selectionerrorlevel {0|1}Ellipses...Replaces repeated text var_name [,var_name...]Represents code supplied by user void main (void){ ...}PrefaceTHE MICROCHIP WEB SITEMicrochip provides online support via our web site at . This website is used as a means to make files and information easily available to customers.Accessible by using your favorite Internet browser, the web site contains the followinginformation:•Product Support – Data sheets and errata, application notes and sampleprograms, design resources, user’s guides and hardware support documents,latest software releases and archived software•General Technical Support – Frequently Asked Questions (FAQs), technicalsupport requests, online discussion groups, Microchip consultant programmember listing•Business of Microchip – Product selector and ordering guides, latest Microchippress releases, listing of seminars and events, listings of Microchip sales offices,distributors and factory representativesCUSTOMER SUPPORTUsers of Microchip products can receive assistance through several channels:•Distributor or Representative•Local Sales Office•Field Application Engineer (FAE)•Technical SupportCustomers should contact their distributor, representative or field application engineerfor support. Local sales offices are also available to help customers. A listing of salesoffices and locations is included in the back of this document.Technical support is available through the web site at: DOCUMENT REVISION HISTORYRevision A (December 2007)•Initial Release of this Document.MCP73837/8 AC/USB Evaluation Board User’s Guide NOTES:MCP73837/8 AC/USB EVALUATION BOARD USER’S GUIDEChapter 1. Product Overview1.1INTRODUCTIONThe MCP73837/8 AC/USB Dual Input Battery Charger Evaluation Board demonstrates the features and abilities of Microchip’s MCP73837 and MCP73838 Single-Chip LinearLi-Ion Battery Charger with Autonomous AC Adapter or USB-Port Power SourceSelection. The MCP73837 and MCP73838 are stand-alone highly integrated linearbattery charger management controllers which employ a constant current / constantvoltage (CCCV) charge algorithm with selectable preconditioning and chargetermination ratio.The MCP73837 and MCP73838 automatically select the AC-Adapter or USB-Port asthe power source for the system. For an AC-Adapter powered system, an externalresistor (R PROG ) sets the magnitude of the charge current up to a maximum of 1000mA. With an USB-port providing power to the system, the MCP73837/8 specificallyadheres to the current limits governed by the USB specification. The host microcontrol-ler can select from two preset charge current rates of typical 90mA (low) or 450mA(High) and will not exceed 100mA (Low) or 500mA (high) maximum charge current.As for USB regulation, a device may draw either low-power at one unit load orhigh-power at 5 unit loads. A unit load is defined to be 100mA. The drawn current per unit load is an absolute maximum value, not an average over time.This chapter covers the following topics:•What is the MCP73837/8 AC/USB Dual Input Battery Charger Evaluation Board?•What the MCP73837/8 AC/USB Dual Input Battery Charger Evaluation Board Kitincludes.FIGURE 1-1:MCP73837 Typical Application.STAT1V AC V SS PG V BAT Single Li-Ion Cell 45312V IN_AC AdapterSTAT2THERM V USB PROG1PROG24.7µF V IN_USB Port67HiLow Thermistor V IN_AC or USB V IN_AC or USB V IN_AC or USB 91084.7µF4.7µFMCP73837/8 AC/USB Evaluation Board User’s Guide 1.2WHAT IS THE MCP73837/8 AC/USB DUAL INPUT BATTERY CHARGEREVALUATION BOARD?The MCP73837/8 AC/USB Dual Input Battery Charger Evaluation Board demonstratesthe use of Single-Chip Linear Li-Ion Battery Charger with Autonomous AC-Adapter orUSB-Port Power Source Selection.The MCP73837/8 AC/USB Dual Input Battery Charger Evaluation Board is set up toevaluate single-cell Li-Ion Battery Charge Management. This board utilizes Microchip'sMCP73837 and MCP73838 (Li-Ion Battery Charge Management Controllers) thateffectively charge Li-Ion batteries with +0.5% high accuracy preset voltage regulation.The MCP73837/8 AC/USB Dual Input Battery Charger Evaluation Board comes withtwo pre-installed circuits: DFN-10 MCP73837 and MSOP-10 MCP73838. Both circuitsare ready to charge Li-Ion battery at a maximum charge current rate up to 1000mAwhen AC Adapter is present and a maximum charge current rate up to 500mA whenUSB-Port is present. A mechanical dip switch is built in to select High (maximum500mA) or Low (maximum 100mA) for the USB-Port powered system.Two built-in LEDs are ready to indicate charge status: STAT1 and STAT2. TheMCP73837 has a Power-Good Monitor that can be observed via the 3rd LED indicatoron the board.Note:Please refer to Table2-1 for MCP73837/8 Charge Status Outputs.The MCP73838 has Timer-Enable to active and disable the internal safety timer forcharge special applications which can be selected from TE test point pin.The MCP73837/8 AC/USB Dual Input Battery Charger Evaluation Board is alsodesigned for easy modifications to support both MCP73837 in 10-pin DFN and MSOPpackages and MCP73838 in 10-pin DFN and MSOP packages. R PROG (R6 and R12)are located in the open area for quick charge current programming.The MCP73837/8 AC/USB Dual Input Battery Charger Evaluation Board is designed toobserve the performance and features on the circuits via multiple test points. Users canalso discover the compact size of the layout in addition to the device itself. The circuitcan also be implemented into suitable applications without additional work.1.3WHAT THE MCP73837/8 AC/USB DUAL INPUT BATTERY CHARGEREVALUATION BOARD KIT INCLUDESThis MCP73837/8 AC/USB Dual Input Battery Charger Evaluation Board kit includes:•MCP73837/8 AC/USB Dual Input Battery Charger Evaluation Board, 102-00120•MCP73837 DFN-10 and MCP73838 MSOP-10 (Pre-Installed)•Analog and Interface Products Demonstration Boards CD-ROM (DS21912)-MCP73837/8 AC/USB Evaluation Board User’s Guide, DS51684分销商库存信息: MICROCHIPMCP7383XEV-DIBC。