DDRSDRAM基础知识
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Column Access Strobe
Time interval between column access command and data return by DRAM device
Row Precharge time
Time interval that it takes for precharge and ready for another row access
Page Close Page Open Bank Interleave Commands Re-Order
DRAMController Basic
DRAMController Function & Architecture Address Mappingin DRAMController
Burst refresh Distributed refresh
Cont’d
DRAM Basic Commands
More about DRAMRefresh
Cont’d
DRAM Basic Commands
More about DRAMRefresh
Cont’d
DRAM Basic Commands
Column ReadCommand
Cont’d
DRAM Basic Commands
Column Write Command
Cont’d
DRAM Basic Commands
Precharge Command
Cont’d
DRAM Basic Commands
Refresh Command
Channel 0
Cont’d
...
0x40
64B cache block 0x00
DIMM 0 Rank 0
DRAM Device Architecture
Example: Transfer a Cache Block
Physical memory space 0xFFFF…F
Chip 0
Chip 1
The value of tRRDand tFAW is Page Size Related
Downside of DRAMRefresh
Power Consume Performance degradation Refresh rate limits DRAMcapacity scaling
DRAM Basic Commands
More about DRAMRefresh
Refresh Method
DRAM Basic Knowledge
DRAMDevice Architecture DRAMAccess Flow DRAMBasic Commands DRAMCommand Schedule
Page Close Page Open Bank Interleave Commands Re-Order
Example: Transfer a Cache Block
Physical memory space 0xFFFF…F
Chip 0
Chip 1
Row 0 Col 1
Cont’d
Rank 0
Chip 7
...
...
<0:7> <8:15> <56:63>
0x40
8B 8B
0x00
64B cache block
PAlf Refresh Only use part of the DRAMto save power
DRAM Basic Commands
AReadCycle
Cont’d
DRAM Basic Commands
Power Consume in DRAMReadCycle
Cont’d
DRAM Basic Knowledge
DRAMDevice Architecture DRAMAccess Flow DRAMBasic Commands & TimingParameters DRAMCommand Schedule
Page Close Page Open Bank Interleave Commands Re-Order
Page Close Page Open Bank Interleave Commands Re-Order
DRAMController Basic
DRAMController Function & Architecture Address Mappingin DRAMController
DRAM Access Flow
DRAMAccess Flow Overview
DRAM Access Flow
Differential Sense Amplifier – Row Buffer
Cont’d
DRAM Access Flow
Circuits of Differential Sense Amplifier
Channel
Cont’d
DRAM Device Architecture
Overview of Bank, Rank, Channel
Cont’d
DRAM Device Architecture
Example: Transfer a Cache Block
Physical memory space 0xFFFF…F
DRAMController Basic
DRAMController Function & Architecture Address Mappingin DRAMController
DRAM Device Architecture
Typical DRAMDevice Architecture
Cont’d
DRAM Basic Commands
Power Related TimingParameters – tRRD
tRRD : Row to Row activationDelay, different bank
Will affect DRAM command scheduling
Cont’d
DRAM Basic Commands
Cont’d
More about DRAMRefresh
The memory controller needs to refresh each row periodically to restore charge
Read and close each row every N ms Typical N = 64 ms
DRAMController Basic
DRAMController Function & Architecture Address Mappingin DRAMController
DRAM Basic Commands
Key TimingParameters
Parameter
Description
Cont’d
DRAM Device Architecture
Bank? Rank? Channel?
Cont’d
DRAM Device Architecture
Bank
Cont’d
DRAM Device Architecture
Rank
Cont’d
DRAM Device Architecture
Simple: 1T-1C Data losses when read or over-time
DRAM Device Architecture
Data Width of DRAMDevice
Also the data width of each bank Each DRAMdevice will have several banks
Physical memory space 0xFFFF…F
Chip 0
Chip 1
Row 0 Col 1
Cont’d
Rank 0
Chip 7
...
...
<0:7> <8:15> <56:63>
0x40
8B 8B
0x00
64B cache block
Data <0:63>
8B
DRAM Device Architecture
Write Recovery time
Minimum time interval between write burst and precharge, restore data to cell
Row Cycle time
Time interval between accesses to different rows in a given bank
tRCD tRAS tCAS tRP tWR tRC tRFC
Row to Column command Delay
Time interval between row access command and data read at sense amplifiers
Row Access Strobe
Time interval between row access command and data restoration in DRAM array
Row 0 Col 0
Cont’d
Rank 0
Chip 7
...
...
<0:7> <8:15> <56:63>
0x40
8B
0x00
64B cache block
Data <0:63>
8B
DRAM Device Architecture
Example: Transfer a Cache Block
Cont’d
DRAM Access Flow
Read Access Step4 – Pre-charge
Cont’d
DRAM Access Flow
Sense Amplifier Voltage Waveform – Read Flow
Cont’d
DRAM Access Flow
Write Access Flow
Data <0:63>
A 64B cache block takes 8 I/O cycles to transfer. During the process, 8 columns are read sequentially.
DRAM Basic Knowledge
DRAMDevice Architecture DRAMAccess Flow DRAMBasic Commands DRAMCommand Schedule
Refresh Cycle time
Time interval between refresh command and activation command
DRAM Basic Commands
Row Access Command– Activation
Cont’d
DRAM Basic Commands
DRAM Basic Knowledge Summary
Hulin Cao – caohulin@
DRAM Basic Knowledge
DRAMDevice Architecture DRAMAccess Flow DRAMBasic Commands DRAMCommand Schedule
Cont’d
DRAMRefresh in LPDDRx
TCSR
Temperature Compensated Self Refresh Embedded temperature sensor, adjust refresh period based on
temperature (Also Adopted in DDR4)
Cont’d
DRAM Basic Commands
Power Related TimingParameters – tFAW
tFAW : Four Bank Activation Window
Will affect DRAM command scheduling
Cont’d
DRAM Basic Commands
Cont’d
DRAM Access Flow
Read Access Step1 – Word Line Select
Cont’d
DRAM Access Flow
Read Access Step2 – Sense Amplifier
Cont’d
DRAM Access Flow
Read Access Step3 – Restore
Time interval between column access command and data return by DRAM device
Row Precharge time
Time interval that it takes for precharge and ready for another row access
Page Close Page Open Bank Interleave Commands Re-Order
DRAMController Basic
DRAMController Function & Architecture Address Mappingin DRAMController
Burst refresh Distributed refresh
Cont’d
DRAM Basic Commands
More about DRAMRefresh
Cont’d
DRAM Basic Commands
More about DRAMRefresh
Cont’d
DRAM Basic Commands
Column ReadCommand
Cont’d
DRAM Basic Commands
Column Write Command
Cont’d
DRAM Basic Commands
Precharge Command
Cont’d
DRAM Basic Commands
Refresh Command
Channel 0
Cont’d
...
0x40
64B cache block 0x00
DIMM 0 Rank 0
DRAM Device Architecture
Example: Transfer a Cache Block
Physical memory space 0xFFFF…F
Chip 0
Chip 1
The value of tRRDand tFAW is Page Size Related
Downside of DRAMRefresh
Power Consume Performance degradation Refresh rate limits DRAMcapacity scaling
DRAM Basic Commands
More about DRAMRefresh
Refresh Method
DRAM Basic Knowledge
DRAMDevice Architecture DRAMAccess Flow DRAMBasic Commands DRAMCommand Schedule
Page Close Page Open Bank Interleave Commands Re-Order
Example: Transfer a Cache Block
Physical memory space 0xFFFF…F
Chip 0
Chip 1
Row 0 Col 1
Cont’d
Rank 0
Chip 7
...
...
<0:7> <8:15> <56:63>
0x40
8B 8B
0x00
64B cache block
PAlf Refresh Only use part of the DRAMto save power
DRAM Basic Commands
AReadCycle
Cont’d
DRAM Basic Commands
Power Consume in DRAMReadCycle
Cont’d
DRAM Basic Knowledge
DRAMDevice Architecture DRAMAccess Flow DRAMBasic Commands & TimingParameters DRAMCommand Schedule
Page Close Page Open Bank Interleave Commands Re-Order
Page Close Page Open Bank Interleave Commands Re-Order
DRAMController Basic
DRAMController Function & Architecture Address Mappingin DRAMController
DRAM Access Flow
DRAMAccess Flow Overview
DRAM Access Flow
Differential Sense Amplifier – Row Buffer
Cont’d
DRAM Access Flow
Circuits of Differential Sense Amplifier
Channel
Cont’d
DRAM Device Architecture
Overview of Bank, Rank, Channel
Cont’d
DRAM Device Architecture
Example: Transfer a Cache Block
Physical memory space 0xFFFF…F
DRAMController Basic
DRAMController Function & Architecture Address Mappingin DRAMController
DRAM Device Architecture
Typical DRAMDevice Architecture
Cont’d
DRAM Basic Commands
Power Related TimingParameters – tRRD
tRRD : Row to Row activationDelay, different bank
Will affect DRAM command scheduling
Cont’d
DRAM Basic Commands
Cont’d
More about DRAMRefresh
The memory controller needs to refresh each row periodically to restore charge
Read and close each row every N ms Typical N = 64 ms
DRAMController Basic
DRAMController Function & Architecture Address Mappingin DRAMController
DRAM Basic Commands
Key TimingParameters
Parameter
Description
Cont’d
DRAM Device Architecture
Bank? Rank? Channel?
Cont’d
DRAM Device Architecture
Bank
Cont’d
DRAM Device Architecture
Rank
Cont’d
DRAM Device Architecture
Simple: 1T-1C Data losses when read or over-time
DRAM Device Architecture
Data Width of DRAMDevice
Also the data width of each bank Each DRAMdevice will have several banks
Physical memory space 0xFFFF…F
Chip 0
Chip 1
Row 0 Col 1
Cont’d
Rank 0
Chip 7
...
...
<0:7> <8:15> <56:63>
0x40
8B 8B
0x00
64B cache block
Data <0:63>
8B
DRAM Device Architecture
Write Recovery time
Minimum time interval between write burst and precharge, restore data to cell
Row Cycle time
Time interval between accesses to different rows in a given bank
tRCD tRAS tCAS tRP tWR tRC tRFC
Row to Column command Delay
Time interval between row access command and data read at sense amplifiers
Row Access Strobe
Time interval between row access command and data restoration in DRAM array
Row 0 Col 0
Cont’d
Rank 0
Chip 7
...
...
<0:7> <8:15> <56:63>
0x40
8B
0x00
64B cache block
Data <0:63>
8B
DRAM Device Architecture
Example: Transfer a Cache Block
Cont’d
DRAM Access Flow
Read Access Step4 – Pre-charge
Cont’d
DRAM Access Flow
Sense Amplifier Voltage Waveform – Read Flow
Cont’d
DRAM Access Flow
Write Access Flow
Data <0:63>
A 64B cache block takes 8 I/O cycles to transfer. During the process, 8 columns are read sequentially.
DRAM Basic Knowledge
DRAMDevice Architecture DRAMAccess Flow DRAMBasic Commands DRAMCommand Schedule
Refresh Cycle time
Time interval between refresh command and activation command
DRAM Basic Commands
Row Access Command– Activation
Cont’d
DRAM Basic Commands
DRAM Basic Knowledge Summary
Hulin Cao – caohulin@
DRAM Basic Knowledge
DRAMDevice Architecture DRAMAccess Flow DRAMBasic Commands DRAMCommand Schedule
Cont’d
DRAMRefresh in LPDDRx
TCSR
Temperature Compensated Self Refresh Embedded temperature sensor, adjust refresh period based on
temperature (Also Adopted in DDR4)
Cont’d
DRAM Basic Commands
Power Related TimingParameters – tFAW
tFAW : Four Bank Activation Window
Will affect DRAM command scheduling
Cont’d
DRAM Basic Commands
Cont’d
DRAM Access Flow
Read Access Step1 – Word Line Select
Cont’d
DRAM Access Flow
Read Access Step2 – Sense Amplifier
Cont’d
DRAM Access Flow
Read Access Step3 – Restore