PAD_A13_STD_V1_24

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micropython hx711方法

micropython hx711⼀、引⾔随着物联⽹技术的快速发展，微控制器在各种应⽤中发挥着越来越重要的作⽤。

其中，micropython作为⼀种轻量级的Python语⾔，在微控制器领域得到了⼴泛的应⽤。

hx711是⼀款⾼精度的24位ADC（模数转换器），⼴泛应⽤于各种传感器数据的采集。

本⽂将介绍如何使⽤micropython控制hx711，并详细介绍其基本⽅法。

⼆、hx711简介hx711是⼀款24位ADC芯⽚，具有⾼精度、低噪声、低功耗等优点。

它采⽤SPI（串⾏外设接⼝）或I2C（双向串⾏总线）通信⽅式，与微控制器连接。

通过读取hx711的寄存器，可以获取传感器的模拟信号值。

三、micropython控制hx711⽅法下⾯介绍如何使⽤micropython控制hx711：步骤⼀：安装micropython库在micropython中，需要安装hx711库才能使⽤hx711模块。

可以使⽤upip 库来安装hx711库。

在micropython的命令⾏界⾯中输⼊以下命令：import upipupip.install('hx711')步骤⼆：导⼊hx711模块在micropython中导⼊hx711模块，可以使⽤以下代码：from machine import I2C,Pinfrom hx711import HX711步骤三：初始化hx711初始化hx711时，需要指定通信⽅式（SPI或I2C）、通信端⼝号以及设备地址等参数。

以下是使⽤I2C通信⽅式初始化的示例代码：i2c=I2C(scl=Pin(22),sda=Pin(21),freq=400000)#初始化I2C通信⽅式，scl和sda分别接在了数字引脚22和21上，频率为400kHzhx711=HX711(i2c)#创建HX711对象，与I2C通信⽅式关联起来步骤四：设置hx711增益值和偏置值在使⽤hx711之前，需要设置增益值和偏置值。

MSI MS-1022 - REV 0B

Cap must close to thermal sensor
THERMDC 31 T_CRIT_CPUT_CRIT_CPUTHERMTRIPRB37 RB35 0_NC 0
CB63 2200PF T_CRIT_A_CPU-
2 3 4
D
LM86_MSOP8 CB66 0.1UF_0402
D
Close to CPU socket
Full ON S1M(Power On Suspend)
A
HIGH HIGH LOW LOW LOW
HIGH HIGH HIGH LOW LOW
HIGH HIGH HIGH HIGH LOW
ON ON ON ON ON
ON ON ON ON ON
ON ON OFF OFF OFF
keep high
U2EB5B #D0 #D1 #D2 #D3 #D4 #D5 #D6 #D7 #D8 #D9 #D10 #D11 #D12 #D13 #D14 #D15 DSTBN0# DSTBP0# DINV0# #D16 #D17 #D18 #D19 #D20 #D21 #D22 #D23 #D24 #D25 #D26 #D27 #D28 #D29 #D30 #D31 DSTBN1# DSTBP1# DINV1# PSI# BSEL0 BSEL1 NC1 NC2 RSVD2 RSVD3 RSVD [GTLREF3] RSVD [GTLREF1] GTLREF0 #D32 #D33 #D34 #D35 #D36 #D37 #D38 #D39 #D40 #D41 #D42 #D43 #D44 #D45 #D46 #D47 DSTBN2# DSTBP2# DINV2# #D48 #D49 #D50 #D51 #D52 #D53 #D54 #D55 #D56 #D57 #D58 #D59 #D60 #D61 #D62 #D63 DSTBN3# DSTBP3# DINV3# COMP0 COMP1 COMP2 COMP3 Y26 AA24 T25 U23 V23 R24 R26 R23 AA23 U26 V24 U25 V26 Y23 AA26 Y25 W25 W24 T24 AB25 AC23 AB24 AC20 AC22 AC25 AD23 AE22 AF23 AD24 AF20 AE21 AD21 AF25 AF22 AF26 AE24 AE25 AD20 P25 P26 AB2 AB1 G1 B7 C19 E4 A6 C5 F23 HD-32 HD-33 HD-34 HD-35 HD-36 HD-37 HD-38 HD-39 HD-40 HD-41 HD-42 HD-43 HD-44 HD-45 HD-46 HD-47 HDSTBN-2 HDSTBP-2 DBI-2 HD-48 HD-49 HD-50 HD-51 HD-52 HD-53 HD-54 HD-55 HD-56 HD-57 HD-58 HD-59 HD-60 HD-61 HD-62 HD-63 HDSTBN-3 HDSTBP-3 DBI-3 HCOMP0 HCOMP1 HCOMP2 HCOMP3 H_DPRSTPH_DPSLPH_DPWRCPU_PWRGD CPUSLPRB31 RB24 1K_NC 1K_NC VTT

全志A13标案原理图

CSI_D3/SDC2_D3 121
CSI_D2/SDC2_D2 120
CSI_D1/SDC2_D1 119
CSI_D0/SDC2_D0 118
CSI_VSYNC/SPI2_MISO 117
LCD-D21 5 LCD-D22 5 LCD-D23 5 LCD-CLK 5 LCD-DE 5 LCD-HSYNC 5 LCD-VSYNC 5 CSI-D7 6 CSI-D6 6 CSI-D5 6 CSI-D4 6 CSI-D3 6 CSI-D2 6 CSI-D1 6 CSI-D0 6 CSI-VSYNC 6 CSI-HSYNC 6 CSI-MCLK 6 CSI-PCLK 6 SD0-D2 4 SD0-D3 4 SD0-CMD 4 SD0-CLK 4 SD0-D0 4 SD0-D1 4 TWI1-SDA 5,6 TWI1-SCK 5,6 PWM0 5 TWI0-SDA 3 TWI0-SCK 3 DP1 6 DM1 6 DP0 6 DM0 6
TPY1 5 TPX1 5
SZQ
17
CSI_HSYNC/SPI2_MOSI 116
SVREF
18
CSI_MCLK/SPI2_CLK/EINT15 115
SDQ1
19
CSI_PCLK/SPI2_CS0/EINT14 114
SDQ3
20
SDC0_D2 113
SDQ7
21
SDC0_D3 112
SDQ5
22
CSI-STY TWI1
TWI2
PG0 PG1
PG2
PG3
B
PG4
PG9
PG10
PG11
PG12
INPUT GPIO-IN GPIO-IN GPIO-OUT GPIO-OUT GPIO-OUT GPIO-OUT EINT GPIO-OUT

PI3EQXDP1201 ActiveEye DisplayPort ReDriver with A

ActiveEye TM DisplayPort1.2 ReDriver TM with AUX ListenerPI3EQXDP1201Features∙VESA DisplayPort 1.1a and 1.2 standard compliant for RBR 1.62Gbps, HBR 2.7Gbps /HBR2 5.4Gbps data rate∙ Full Auto and M anual DP1.2 test mode support for the user friendly system diagnosis∙ FAUX signal pass-through with low signal degrada-tion∙AUX listener supports link training, output level and pre-emphasis configuration during the link initializa-tion with "Sink Request Test Mode"∙ Fixed and Dynamic EQ configuration based on AUX link training requirement∙ Auto equalization based on signal and pre-emphasis level in AUX configuration register∙ Support Hot Plug and Cable Detection function ∙ AUX/DDC combo switch∙Individual lane power down state automatically to enter low power mode when no DP signal is present or no sink device is inserted∙ Support dedicated pins or SM Bus control mode for Equalization (EQ) setting control∙ Internally Biased AC coupled in AUX channel ∙Single 3.3V or Dual 1.5V/3.3V power sources∙ Integrated ESD protection Independent squelch per lane (auto power down) ∙48-contact TQFN, 7mm x 7mmDescriptionPI3EQXDP1201 is the Pericom’s latest DisplayPort1.2 compliant ReDriver (Repeater) to support signal jitter re-duction caused by noisy transmission line effects in the high speed DisplayPort 5.4Gbps data.It has DisplayPort Aux decoder, decipher the link training message and automatically configure the signal outputs with the optimum pre-emphasis and output swing level. In pin control, Auto EQ mode 1/2/3 and 2 bit of pre-emphasis setting provide 12 EQ steps. Programmable SMBus mode provides 16 EQ steps.PI3EQXDP1201 is intended for use in any DP signal com-pliance system including notebook PC and docking sta-tions, graphic cards and other high-speed AC-coupled dig-ital video system.Applications∙ Notebook computers ∙ PC docking station ∙ Dongle, switch boxes ∙Long DisplayPort cablesFig. 1. PI3EQXDP1201 Functional Block DiagramFig. 2. Output Eye Opening at 5.4Gbps, 12-in FR4 input and 36-in Coaxial cable. Auto EQ mode. 1200mV Swing. 0dB Pre-emphasisINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH PERICOM PRODUCT. NO LIN-CENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN PERICOM’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PAR-TICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENR, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.Pericom may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined”. Pericom re-serves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specification. Current characterized errata are available on request.Contact your local Pericom Sales office or your distributor to obtain the latest specifications and before placing your product order.Copyright 2012 Pericom Corporation. All rights reserved. Pericom and the Pericom logo are trademarks of PericomCorporation in the U.S. and other countries.PI3EQXDP1201ActiveEyeTMDisplayPort1.2 ReDriver TM with Aux ListenerOrdering InformationNotes:1. Thermal characteristics can be found on the company web site at /packaging/2. “E” = Pb-free and Green, Adding an “X” suffix = Tape/ReelRelated ProductsPart NumberProduct DescriptionPI3VDP1430 ActiveEye TM Dual Mode DisplayPort to HDMI Level Shifter and Re-driver PI3HD M I412AD ActiveEye TM 1:2 HDMI1.4 compliant Splitter/Re-driverPI3HD M I336 ActiveEye TM 3:1 HDMI1.4 Switch/Re-driver with I2C control and ARC PI3HD M I511 ActiveEye TM HDMI1.4 ReDriver for Source-side application PI3HD M I611 ActiveEye TM HDMI1.4 ReDriver for Sink-side application PI3HDMI521 ActiveEye TM 2:1 HDMI1.4 Switch/Re-driver with ARC and Fast Switching support for Source-sideApplicationPI3HDMI621 ActiveEye TM 2:1 HDMI1.4 Switch/Re-driver with ARC and Fast Switching support for Sink-side ApplicationPI3VDP3212 2-Lane DisplayPort1.2 Compliant Switch PI3VDP124124-Lane DisplayPort1.2 Compliant SwitchOrdering CodePackage Code Package Desc r iptionPI3EQXDP1201ZBE ZBPb-free & Green, 48-pin TQFN。

S32K3X4EVB-Q172 通用汽车应用开发板说明书

Belt-Driven Starter Generator (BSG), Turbo Charger, Fan/Pump ControllerHero SpecsS32K3 FAMILY FEATURESFS26 Safety System Basis Chip[+5 V, +3.3V and +1.5V]MCU Current Monitoring forVDD_HV_A and VDD_HV_B64Mb QSPI Serial NOR FlashMII/RMII Ethernet Interface— SABRE Connector10/100TBase Ethernet— RJ45 ConnectorTJA1043 CAN InterfacesTJA1021 LIN InterfacesMicrocontroller (MCU)32-bit Arm Cortex-M7-based S32K344 (/products/processors-and-microcontrollers/arm-microcontrollers/s32k-automotive-mcus/s32k3-microcoK26 (/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/k-series-cortex-m4/k2x-usb/kinetis-k26-180-mhz-Safety System Basis Chip (SBC)FS26 (/products/power-management/pmics-and-sbcs/safety-sbcs/safety-system-basis-chip-sbc-with-low-power-fit-for-asil-d:FS26): Safety syst Transceivers TJA1021 (/products/interfaces/automotive-lin-solutions/lin-2-1-sae-j2602-transceiver:TJA1021): LIN 2.1/SAE J2602 transceiverTJA1043 (/products/interfaces/can-transceivers/can-with-flexible-data-rate/high-speed-can-transceiver-with-standby-and-sleep-mode:TJA1043Hardware Features 64 Mb QSPI NOR flash100 Mbit Ethernet physical LayerPower supply switchMCU voltage/current measurementUser RGB LED2x user push-buttonsADC rotary potentiometer2x touch pad electrodeSoftware Features Free of charge S32 Design Studio IDE (/design/software/development-software/s32-design-studio-ide:S32-DESIGN-STUDIO-IDE) (Eclipse, GFree of charge (/design/automotive-software-and-tools/real-time-drivers-rtd:AUTOMOTIVE-RTD)Real Time Drivers for AUTOSAR and non-AUConfiguration tools for both AUTOSAR and non-AUTOSAR usersFree of charge security firmware: SHE+ compliant NXP supplied, designed for ISO 21434S32 Safety Software Framework (/design/automotive-software-and-tools/s32-safety-software-framework-saf:SAF) (SAF): Six fault detection anFree of charge Safety Peripheral Drivers (SPD)Structural Core Self Test (/docs/en/product-brief/S32K3xx-SCST-PB.pdf) (SCST)Free of charge inter-platform communication framework (/design/automotive-software-and-tools/inter-platform-communication-framework-ipcf:Free of charge Model-Based Design Toolbox (/design/automotive-software-and-tools/model-based-design-toolbox-mbdt:MBDT) for MATLAB :Programing Debug interfaces On-board S32K3 debug interface20-Pin Cortex debug + ETM connectorCompatibility Arduino UNO pint-out compatible with expansion “shield” supportInterfaces On-board HS-CAN2x on-board LINEthernet 100 Mbit Physical Layer with RJ-45 connector for fast prototypingSWD/JTAG debug interface for S32K3 debugger®®BuyS32K3X4EVB-Q172 (/part/S32K3X4EVB-Q172) S32K3X4EVB-Q172 Evaluation and Development Board for General Purpose(/design/automotive-(/design/software/development-(/design/software/development-Design ResourcesGet Started1. Review this Getting Started guide to get familiar with the hardware specifications.Getting StartedGetting Started with the S32K3X4EVB-Q172 Evaluation Board (/document/guide/getting-started-with-the-s32k3x4evb-q172-evaluation-board:GS-S32K3X4EVB-Q172)HTML Oct 6, 2021 GS-S32K3X4EVB-Q1722. Review this user manual to get familiar with the board.User ManualS32K3X4EVB-Q172 Evaluation Board – HW User Manual (/webapp/Download?colCode=S32K3X4EVB-Q172_HW-UM)PDF Rev A Oct 20, 2021 S32K3X4EVB-Q172_HW-UM EnglishDOCUMENTS ( 8 )DESIGN RESOURCES ( 4 )SOFTWARE ( 7 )Reference Manual ( 1 )User Guide ( 1 )Brochure ( 1 )Errata ( 1 )Product Brief ( 4 )Design Tools & Files ( 4 )Embedded Software ( 3 )Development Software ( 4 )DocumentsReference Manual ( 1 )S32K3X4EVB-Q172 Evaluation Board – HW User Manual (/webapp/Download?colCode=S32K3X4EVB-Q172_HW-UM)Hardware User Manual for the S32K3X4EVB-Q172 Evaluation Board.PDF Rev A Oct 20, 2021 S32K3X4EVB-Q172_HW-UM EnglishUser Guide ( 1 )Getting Started with the S32K3X4EVB-Q172 Evaluation Board (/document/guide/getting-started-with-the-s32k3x4evb-q172-evaluation-board:GS-S32K3X4EVB-Q172)This page will help guide you through the process of learning about your S32K3X4EVB-Q172 evaluation boardHTML Oct 6, 2021 GS-S32K3X4EVB-Q172 EnglishBrochure ( 1 )S32K3 Arm Cortex-M7-based Automotive MCUs – Brochure (/docs/en/brochure/S32KBRA4.pdf)The S32K3 family includes scalable 32-bit Arm Cortex-M7 based MCUs in single, dual and Lockstep core configurations supporting up to ASIL D level safety.Features include a hardware security subsystem with NXP firmware, support for firmware over-the-air (FOTA) updates, and ISO 26262 compliant Real-Time Drivers (RTD) software package for AUTOSARTM and non-AUTOSAR.PDF Rev 0 Oct 19, 2021 S32KBRA4 EnglishErrata ( 1 )Mask Set Errata for Mask 0P55A/1P55A - Errata (/webapp/Download?colCode=S32K3X4-0P55A-1P55A-ERRATA)This report applies to mask 0P55A/1P55A for these products S32K344, S32K324 and S32K314PDF Rev 14 Oct 14, 2021 S32K3X4-0P55A-1P55A-ERRATA EnglishProduct Brief ( 4 )S32 Safety Software Framework (SAF) for S32K3xx Microcontrollers - Product Brief (/docs/en/product-brief/S32K3xx-SAF-PB.pdf)The S32 Safety Software Framework (SAF) is a software product containing software components for establishing the safety foundation for customer’s safety applications compliant with ISO 26262 functional safety.PDF Rev 1 Sep 30, 2021 858.4 KB S32K3xx-SAF-PB EnglishStructural Core Self-Test Library (SCST) for S32K3xx Microcontrollers - Product Brief (/docs/en/product-brief/S32K3xx-SCST-PB.pdf)The SCST (Structural Core Self-Test) Library is the software product used for the runtime detection of permanent HW faults in the MCU core.PDF Rev 1 Oct 14, 2021 S32K3xx-SCST-PB EnglishReal-Time Drivers (RTD) for S32K3xx Microcontrollers – Product Brief (/docs/en/product-brief/RTD-S32K3-PB.pdf)S32-based platform products offer Real-Time Drivers (RTD) software supporting both AUTOSAR and non-AUTOSAR (similar to traditional SDKs) applications.PDF Rev 1.5 Nov 11, 2021 397.5 KB RTD-S32K3-PB EnglishInter-Platform Communication Framework (IPCF) - Product Brief (/docs/en/product-brief/IPCFPB.pdf)Inter-Platform Communication Framework (IPCF) is a subsystem which enables applications, running on multiple homogenous or heterogenous processing cores, located on the same chip or different chips, running on different operating systems (AUTOSAR, FreeRTOS etc.), to communicate over various transport interfaces (Shared Memory, etc.).PDF Rev 1 Oct 13, 2021 441.4 KB IPCFPB EnglishDesign ResourcesDesign Tools & Files ( 4 )Printed Circuit Boards and Schematics ( 3 )S32K3X4EVB-Q172 Evaluation Board – REV A Design Files (/webapp/Download?colCode=S32K3X4EVBQ172_CAD_FILES_REVA)Design Files REV A for the S32K3X4EVB-Q172 Evaluation Board.ZIP Rev A Oct 20, 2021 S32K3X4EVBQ172_CAD_FILES_REVAS32K3X4EVB-Q172 Evaluation Board – REV A Schematics (/webapp/Download?colCode=S32K3X4EVB-Q172_SCH)Schematics REV A for the S32K3X4EVB-Q257 Evaluation Board.PDF Rev A Oct 20, 2021 S32K3X4EVB-Q172_SCHDOWNLOAD (/WEBAPP/DOWNLOAD?COLCODE=S32K3X4EVBQ172_CAD_FILES_REVA)DOWNLOAD (/WEBAPP/DOWNLOAD?COLCODE=S32K3X4EVB-Q172_SCH)S32K3 MCUs for General Purpose – REV A Hardware Design Package (/webapp/Download?colCode=S32K3_HW-DesignPackage)Hardware considerations for the S32K3xx MCUs, covering power considerations, bulk/bypass and decoupling required capacitors, reset, crystal, Ethernet and QSPI configurations, and PCB layout recommendations.ZIP Rev A Sep 29, 2021 8.6 MB S32K3_HW-DesignPackageCalculators ( 1 )S32K Power Estimation Tool (PET) (/design/automotive-software-and-tools/s32k-power-estimation-tool-pet:S32K-PET)S32K PET provides a user interface to generate a power profile for an application use case quickly; it also helps calculate a first estimate of the average power consumption for developing automotive battery-operated applicationsDOWNLOAD OPTIONS (/DESIGN/AUTOMOTIVE-SOFTWARE-AND-TOOLS/S32K-POWER-ESTIMATION-TOOL-PET:S32K-PET?TAB=DESIGN_TOOLS_TAB)SoftwareEmbedded Software ( 3 )Embedded Software ( 3 )S32 Safety Software Framework (SAF) (/design/automotive-software-and-tools/s32-safety-software-framework-saf:SAF)The S32 Safety Software Framework (SAF) is a software product containing software components for establishing the safety foundation for customer’s safety applications compliant with ISO 26262 functional safety.DOWNLOAD OPTIONS (/DESIGN/AUTOMOTIVE-SOFTWARE-AND-TOOLS/S32-SAFETY-SOFTWARE-FRAMEWORK-SAF:SAF?TAB=DESIGN_TOOLS_TAB)Automotive Math and Motor Control Library (AMMCLib) (/design/automotive-software-and-tools/automotive-math-and-motor-control-library-ammclib:AMMCLIB)The Automotive Math and Motor Control Library (AMMCLib) set is a collection of production-ready, easy-to-use, software libraries for rapid development of motor control and other real-time embedded systems.DOWNLOAD OPTIONS (/DESIGN/AUTOMOTIVE-SOFTWARE-AND-TOOLS/AUTOMOTIVE-MATH-AND-MOTOR-CONTROL-LIBRARY-AMMCLIB:AMMCLIB?TAB=DESIGN_TOOLS_TAB)Model-Based Design Toolbox (MBDT) (/design/automotive-software-and-tools/model-based-design-toolbox-mbdt:MBDT)The NXP Model-Based Design Toolbox (MBDT) is a comprehensive collection of tools that plug into the MATLAB and Simulink model-based designenvironment to support fast prototyping, verification, and validationDOWNLOAD OPTIONS (/DESIGN/AUTOMOTIVE-SOFTWARE-AND-TOOLS/MODEL-BASED-DESIGN-TOOLBOX-MBDT:MBDT?TAB=DESIGN_TOOLS_TAB)Development Software ( 4 )IDE and Build Tools ( 2 )S32 Design Studio for S32 Platform (/design/software/development-software/s32-design-studio-ide/s32-design-studio-for-s32-platform:S32DS-S32PLATFORM)The S32 Design Studio is a tool suite for developing your applications for NXP Automotive and Ultra-Reliable MicrocontrollersDOWNLOAD OPTIONS (/DESIGN/SOFTWARE/DEVELOPMENT-SOFTWARE/S32-DESIGN-STUDIO-IDE/S32-DESIGN-STUDIO-FOR-S32-PLATFORM:S32DS-S32PLATFORM?TAB=DESIGN_TOOLS_TAB)S32K3 Standard Software (/webapp/swlicensing/sso/downloadSoftware.sp?catid=SW32K3-STDSW-D)S32K3 Standard Software includes Real Time Drivers for AUTOSAR® and non-AUTOSAR operating systems, Standard HSE Security firmware, SafetyPeripheral Drivers, an Inter-Platform Communication Framework (IPCF) for communications between the Cortex-M7 cores. Additionally user also get access to Real Time Driver of FS26 SBC, S32 Design Studio IDE and EB tresos Studio.EXTERNAL Rev 0 Sep 30, 2021 null KB SW32K3-STDSW-DDOWNLOAD (/WEBAPP/SWLICENSING/SSO/DOWNLOADSOFTWARE.SP?CATID=SW32K3-STDSW-D)Test, Debug and Analyzer Software ( 1 )FreeMASTER Run-Time Debugging Tool (/design/software/development-software/freemaster-run-time-debugging-tool:FREEMASTER)Graphical PC host tool to control and debug embedded applications in run-time.DOWNLOAD OPTIONS (/DESIGN/SOFTWARE/DEVELOPMENT-SOFTWARE/FREEMASTER-RUN-TIME-DEBUGGING-TOOL:FREEMASTER?TAB=DESIGN_TOOLS_TAB)Host Device Drivers ( 1 )Inter-Platform Communication Framework (IPCF) (/design/automotive-software-and-tools/inter-platform-communication-framework-ipcf:IPCF)DOWNLOAD (/WEBAPP/DOWNLOAD?COLCODE=S32K3_HW-DESIGNPACKAGE)Get HelpInter-Platform Communication Framework (IPCF) is a subsystem which enables applications, running on multiple homogenous or heterogenous processing cores, located on the same chip or different chips, running on different operating systems (AUTOSAR, FreeRTOS etc.), to communicate over various transport interfaces (Shared Memory, etc.).DOWNLOAD OPTIONS (/DESIGN/AUTOMOTIVE-SOFTWARE-AND-TOOLS/INTER-PLATFORM-COMMUNICATION-FRAMEWORK-IPCF:IPCF?TAB=DESIGN_TOOLS_TAB)RECOMMENDED COMMUNITIESS32K S32 Design Studio MBDT Community Articles FreeMASTERSUGGESTED LINKSFunctional Safety documents AVAILABLE | Require access to the SafeAssure NDA group(//)ABOUT NXP (///COMPANY/OUR-COMPANY/ABOUT-NXP:ABOUT-NXP)CAREERS (///ABOUT/CAREERS-AT-NXP:CAREERS)INVESTORS (///)MEDIA (//)CONTACT (///COMPANY/ABOUT-NXP/CONTACT-US:CONTACTUS)SUBSCRIBE (///SUBSCRIPTION-CENTER)(///NXP)(///company/nxp-semiconductors)(///NXPsemi)Privacy (///about/privacy:PRIVACYPRACTICES)Terms of Use (///about/terms-of-use:TERMSOFUSE)Terms of Sale (///about/our-standard-terms-and-conditions-of-sale-counter-offer:TERMSCONDITIONSSALE)Slavery and Human Trafficking Statement (///company/about-nxp/sustainability/social-responsibility/labor-and-human-rights:LABOR-AND-HUMAN-RIGHTS)Accessibility (///company/our-company/about-nxp/accessibility:ACCESSIBILITY)©2006-2022 NXP Semiconductors. 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PY32F030系列32位ARM

1.产品特性◼内核—32位ARM®Cortex®-M0+—最高48MHz工作频率◼存储器—最大64Kbytes flash存储器—最大8Kbytes SRAM◼时钟系统—内部4/8/16/22.12/24MHz RC振荡器(HSI)—内部32.768KHz RC振荡器(LSI)—4~32MHz晶体振荡器(HSE)—32.768KHz低速晶体振荡器(LSE)—PLL（支持对HSI或者HSE的2倍频）◼电源管理和复位—工作电压：1.7V~5.5V—低功耗模式:Sleep和Stop—上电/掉电复位(POR/PDR)—掉电检测复位(BOR)—可编程的电压检测(PVD)◼通用输入输出(I/O)—多达30个I/O，均可作为外部中断—驱动电流8mA—4个GPIO支持超强灌电流，可配置为80mA/60mA/40mA/20mA◼3通道DMA控制器◼1x12-bit ADC—支持最多10个外部输入通道PY32F030系列32位ARM®Cortex®-M0+微控制器数据手册—输入电压转换范围:0~VCC◼定时器—1个16bit高级控制定时器（TIM1）—4个通用的16位定时器（TIM3/TIM14/TIM16/TIM17）—1个低功耗定时器(LPTIM)，支持从stop模式唤醒—1个独立看门狗定时器(IWDT)—1个窗口看门狗定时器(WWDT)—1个SysTick timer—1个IRTIM◼RTC◼通讯接口—2个串行外设接口(SPI)—2个通用同步/异步收发器(USART)，支持自动波特率检测—1个I2C接口，支持标准模式(100kHz)、快速模式(400kHz)，支持7位寻址模式◼支持4位7段共阴极LED数码管—可循环扫描1位、2位、3位、4位数字◼硬件CRC-32模块◼2个比较器◼唯一UID◼串行单线调试(SWD)◼工作温度：-40~85℃◼封装LQFP32,QFN32,TSSOP20,QFN20目录1.产品特性 (1)2.简介 (4)3.功能概述 (6)3.1.Arm®Cortex®-M0+内核 (6)3.2.存储器 (6)3.3.Boot模式 (6)3.4.时钟系统 (7)3.5.电源管理 (7)3.5.1.电源框图 (7)3.5.2.电源监控 (8)3.5.3.电压调节器 (9)3.5.4.低功耗模式 (10)3.6.复位 (10)3.6.1.电源复位 (10)3.6.2.系统复位 (10)3.7.通用输入输出GPIO (10)3.8.DMA (10)3.9.中断 (10)3.9.1.中断控制器NVIC (11)3.9.2.扩展中断EXTI (11)3.10.模数转换器ADC (11)3.11.定时器 (12)3.11.1.高级定时器 (12)3.11.2.通用定时器 (12)3.11.3.低功耗定时器 (13)3.11.4.IWDG133.11.5.WWDG (13)3.11.6.SysTick timer (13)3.12.实时时钟RTC (13)3.13.I2C接口 (14)3.14.通用同步异步收发器USART (14)3.15.串行外设接口SPI (16)3.16.SWD (16)4.引脚配置 (17)4.1.端口A复用功能映射 (31)4.2.端口B复用功能映射 (32)4.3.端口F复用功能映射 (33)5.存储器映射 (34)6.电气特性 (38)6.1.测试条件 (38)6.1.1.最小值和最大值 (38)6.1.2.典型值 (38)6.2.绝对最大额定值 (38)6.3.工作条件 (39)6.3.1.通用工作条件 (39)6.3.2.上下电工作条件 (39)6.3.3.内嵌复位和LVD模块特性 (39)6.3.4.工作电流特性 (40)6.3.5.低功耗模式唤醒时间 (41)6.3.6.外部时钟源特性 (42)6.3.7.内部高频时钟源HSI特性 (44)6.3.8.内部低频时钟源LSI特性 (44)6.3.9.锁相环PLL特性 (44)6.3.10.存储器特性 (45)6.3.11.EFT特性 (45)6.3.12.ESD&LU特性 (45)6.3.13.端口特性 (45)6.3.14.NRST引脚特性 (46)6.3.15.ADC特性 (46)6.3.16.比较器特性 (47)6.3.17.温度传感器特性 (48)6.3.18.定时器特性 (48)6.3.19.通讯口特性 (49)7.封装信息 (53)7.1.LQFP32封装尺寸 (53)7.2.QFN32封装尺寸 (54)7.3.QFN20封装尺寸 (55)7.4.TSSOP20封装尺寸 (56)8.订购信息 (57)9.版本历史 (58)2.简介PY32F030系列微控制器采用高性能的32位ARM®Cortex®-M0+内核，宽电压工作范围的MCU。

BF6910(BF6911)ASXX规格书

8.1 上电、掉电复位 ...................................................................................................................................... 20 8.2 FLASH 编程复位 ....................................................................................................................................... 20 8.3 软件复位 .................................................................................................................................................. 21 8.4 看门狗定时器溢出复位 .......................................................................................................................... 21 8.5 PC 指针溢出复位 ..................................................................................................................................... 21
3.1 引脚图 ....................................................................................................................................................... 6 3.2 引脚描述 ................................................................................................................................................... 6

A31原理图

PH9 TMS PH10 TCK PH11 TDO
DEBUG
PL7 STDO PL8 STDI
DEBUG
PM0 BB-WAKE-HOST BB
PA12 LS-INT
PC4 N0CE0
PD12 LCD0-D12
PH12 TDI
PM1
PA13 USB0-DRV
PC5 N0RE
PD13 LCD0-D13
PH13 LCD-PWM
PH18 TWI2-SCK
Sensors PM7 CK32KO
CLOCK
PA19 LCD-SDA PA20 LCD-SCL PA21 FLASH-MODE PA22 FLASH-EN
LCD-eDP PC11 N0DQ3/eMMC-D3 PC12 N0DQ4/eMMC-D4
FLASH LED PC13 N0DQ5/eMMC-D5 PC14 N0DQ6/eMMC-D6
A
A
AllWinner Technology Co.,Ltd
Design Name
PAD_APP4_STD
Size Page Name
Rev
A3 BLOCK
Date:
Friday, March 01, 2013
Sheet
2
of 16
5
4
3
2
1
5
4
3
2
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POWER TREE
3.5V~5V@2A
PS
AXP
CPUS VDD 1.1V for SOC (ON)
3.0V@30mA
VCC-RTC
RTC VCC 3.0V for SOC (ON)
ALDO1
3.3V@300mA

全志A31 平板原理图2014 05 07

A31-BGA609i
VCC-PLL
VCC-PLL VCC-RTC VIO-RTC
RTC/PLL PWR GND-PLL
V19 R21 T19 RTC-VIO C65 4.7uF V18 C0603
VCC-RTC=3.0V VCC-PLL=3.0V
C63 104 C0402 GND UBOOT
MIPI CSI
TP2 TP4 TP5 TP6
STMS STCK STDO STDI
VDD-SYS
SW 3 sw_2p_4x3_h2
CPUS-TDI
1
CPUS Debug
A
Value Can Not be Changed.
1
C77 C78 10uF/25V 1uF C0805 C0402
A31-BGA609i VDD-CPUS U1B
GTXD0 GTXD1 GTXD2 GTXD3 UART1-TX UART1-RX UART1-RTS UART1-CTS SD0-DET GTXEN GTXCLK GRXD0 GRXD1 GRXD2 GRXD3 USB0-IDDET USB0-VBUSDET USB0-DRVVBUS USB-ICTRL GRXDV GRXCLK ETXRR 3G-IO-PW RON TP-INT TP-W AKEUP GCLKIN GMDC GMDIO
5
4
3
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1
VCC-PA
VCC-PA=3.0V
C61 104 C0402 GND
CPU
VCC-HDMI=3.0V
U1A VCC-HDMI U1M
U1E
VCC-USB=3.0V
VCC-USB
GMAC LCD13.3V MISC

嵌入式系统原理与应用实验指导书(合稿+习题)

嵌入式系统原理与应用实验指导书南航金城学院2013.2目录目录 (1)第一部分试验箱硬件结构 (2)第二部分实验 (11)实验一ADS1.2集成开发环境练习 (11)实验二汇编指令实验1 (17)实验三汇编指令实验2 (20)实验四汇编指令实验3 (23)实验五ARM微控制器工作模式实验 (28)实验六 C语言程序实验 (33)实验七 C语言调用汇编程序实验 (36)实验八GPIO输出控制实验 (39)实验九GPIO输入实验 (46)实验十外部中断实验 (50)实验十一UART通讯实验 (56)实验十二I2C接口实验 (64)实验十三定时器实验 (75)实验十四PWM DAC实验 (81)实验十五ADC实验 (87)实验十六RTC实验 (94)实验十七步进电机控制实验 (101)实验十八直流电机控制实验 (105)附录1 DeviceARM2410 专用工程模板 ..................................................... 错误!未定义书签。

第一部分试验箱硬件结构MagicARM2410教学实验开发平台是一款可使用μC/OS-II、Linux和WinCE操作系统、支持QT、MiniGUI图形系统、集众多功能于一身的ARM9教学实验开发平台。

采用Samsung公司的ARM920T内核的S3C2410A微处理器，扩展有充足的存储资源和众多典型的嵌入式系统接口。

MagicARM2410实验箱参考如图1.1所示。

图1.1 MagicARM2410实验箱外观图MagicARM2410实验箱功能框图如图1.2所示。

图1.2 MagicARM2410实验箱功能框图1.1 S3C2410A芯片简介S3C2410A是Samsung公司推出的16/32位RISC处理器（ARM920T内核），适用于手持设备、POS机、数字多媒体播放设备等等，具有低价格、低功耗、高性能等特点。

智能家居毕业设计论文

智能家居毕业设计论文【篇一：智能家居毕业设计】某别墅智能家居系统设计摘要随着计算机网络技术和信息技术的进步，智能家居得到了前所未有的发展，居民对住宅的功能以及质量提出了更多、更高的要求，智能化住宅以其安全舒适、信息通畅、服务完善而深受住户们的喜爱，智能住宅成为现代化住宅的必然发展趋势。

因此研究并开发出适合人们要求的智能化产品具有很重要的意义。

怎样把电气智能化，怎样安排家居格局，我们就涉及到了家居布线系统。

家居布线系统就是把电话、有线电视、电脑网络、影音系统、家庭自动化控制系统的布线统一规划、布局、集中管理，为实现家具智能化提供网路平台。

采用综合布线方式，使得家庭内部布线系统具有良好的扩展性和可升级性，满足不同用户现在和未来的需求。

本论文设计的智能家居布线系统能充分实现以下功能：1.将住宅内的控制系统、安防系统等系统连接起来，并让它们能够正常的工作；2.新型的布线系统让住宅更加的美观；3.让我们的住宅时刻处于一个安全的状态。

智能家居布线系统须遵循 tia/eia 570-a 家居电信布线的国家标准。

布线系统是实现连接功能是由配线箱进行连接，然后再分配到各个功能模块，让功能模块发挥自己的功能。

关键词：智能家居自动化,自动控制 ,信息化和智能化 ,家具综合布线abstractalong with the computer network technology and information technology progress,intelligent household got unprecedented development,residents of residential functionand quality put forward more and higher demand,intelligent residential to its safe andcomfortable,information unobstructed,and perfect serviceand favored by residents of the love,intelligent residentialbecome modern residential trend.so the research and the development of a suitable for people to requirements of the intelligent product has important significance.household telephone wiring system,cable tv,computernetwork,audio-visual systems,the family of the automaticcontrol system of unified planning,layout and wiring forrealizing the centralized management,providing a networkplatform,intelligent ing the comprehensivewiring,internal cabling system has good family theexpansibility and scalability,meet different users of thepresent and future needs.in domestic and abroad existing intelligent home controlsystem are studied andanalyzed,the combination of domestic intelligence changes household to actual requirements standards,puts forward aset of multifunctional smart home wiring system designscheme. this thesis design intelligent household wiring systemcan fully realize the following functions:1.will inside the residence control system,secutity linksup and allow them to normal work;2.type of wiring system to make the house more beautiful;3.make our housing moment in a safe condition.intelligence lives in wiring system must follow tia/eia 570-ahouseholdtelecommunication wiring national standards.wiring systemis to realize the connect function is connected by wiring kit isincluded as standard,then assigned to each functionmodule,make function module play to ones own function.keyword:intelligent household automation;automaticcontrol;information and intelligence;household wiring system.目录第一章、绪论 ....................................................................... １1.1 选题意义、价值和目标 ........................................................ １1.2 课题研究方案 ................................................................ １第二章智能家居的初步介绍 ...........................................................３2.1 智能家居的发展概况 .......................................................... ３2.1.1 国外智能家居的发展概况 ................................................ ３2.1.2 国内智能家居的发展概况 ................................................ ３2.2 智能家居系统的组成 .......................................................... ３2.2.1 弱电子系统 ............................................................ ３2.2.2 综合布线系统 .......................................................... ３2.3 家庭信息接入箱 .............................................................. ３2.3.2 近程访问 /控制 ......................................................... ４2.3.3 中央控制器功能实现 .................................................... ４2.3.4 交换机的工作原理 ...................................................... ４第三章智能家居各模块简单介绍 .......................................................５3.1 娱乐 ........................................................................ ５3.1.1 全宅音响模块 .......................................................... ５3.2 安防 ........................................................................ ５3.2.1 门磁、窗磁防盗报警模块 ................................................ ５3.2.2 感烟探测报警模块 ...................................................... ５3.2.3 煤气泄露报警模块 ...................................................... ６ 3.2.4 报警及联动模块 ........................................................ ７3.2.5 紧急求助模块 .......................................................... ７3.3 便民 ........................................................................ ７3.3.1 智能照明控制模块 ...................................................... ７3.3.2 感应开关模块 .......................................................... ７第四章智能家居布线系统 .............................................................８4.1 智能家居布线系统设计 ........................................................ ８4.1.1 布线标准 .............................................................. ８4.1.2 系统的需求分析 ........................................................ ８4.2 智能家居布线硬件结构设计 .................................................... ８4.2.1 综合布线的基本概念 .................................................... ８4.2.2 系统硬件结构及特点 .................................................... ８4.2.3 配线箱的工作原理 ...................................................... ９4.2.4 具体施工方案 .......................................................... ９4.3 布线系统的管理与维护 ........................................................ ９4.3.1 布线的管理标准与措施 .................................................. ９4.3.2 故障诊断 ............................................................ １０第五章云计算在安防系统中的前景与应用 ............................................. １１5.1 云计算的运用前景..........................................................１１5.2 云计算的应用特性..........................................................１１5.2.1 安全性 .............................................................. １１5.2.2 便携性 .............................................................. １１5.2.3 性能的可用性 ........................................................ １１5.2.4 数据访问 ............................................................ １１致谢 ............................................................................. １３参考文献 ......................................................................... １４附录 1智能家居施工图 ............................................................. １５第一章、绪论1.1 选题意义、价值和目标计算机、自动控制、通信技术以及数字化技术自20 世纪 90 年代后期以来，取得了迅猛的发展并日益渗透到各个领域。

DB_PCap01Ax_0301_电容测试芯片

RMS 噪声和精度 vs. 输出数据频率.......................................................................................................... 2-3
2.2.2
RMS 噪声 vs. 供电电压............................................................................................................................... 2-5
1.2 典型应用
湿度传感器位移传感器压力传感器力学传感器加速度传感器倾角传感器角度传感器无线应用夜位开关传感器麦克风 MEMS 传感器
acam-messelectronic gmbh - Am Hasenbiel 27 - D-76297 Stutensee-Blankenloch - Germany - www.acam.de
3 转换器前端
3.1 CDC 测量原理 3.2 重要 CDC 参数 3.3 CDC 外部电路 3.4 连接电容传感器 3.5 选择放电电阻 3.6 补偿测量
4.1 串行通信
4 接口 (串行通信和 Pulse-Density通信) 4.2 PDM/PWM 和 GPIO
5 读 & 写寄存器 6 DSP, 存储 & 固件
1-1
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1.3 内部结构原理图
图 1-1: 内部结构原理图
PCapØ1Ax-0301
1-2
acam-messelectronic gmbh - Am Hasenbiel 27 - D-76297 Stutensee-Blankenloch - Germany - www.acam.de

TG7100C 开发板用户手册说明书

《xxx芯片数据手册》文档版本发布日期TG7100C开发板用户手册版本：1.0版权@2020Contents1环境配置 (3)2代码编译 (5)3下载运行 (6)3.1芯片选择 (6)3.2配置程序下载方式 (7)3.3配置下载参数 (8)3.4下载程序 (9)1环境配置aos-cube是AliOS Things基于命令行的开发管理工具，主要功能包括：工程配置与编译、Image下载调试、组件生成、组件安装管理、设备管理、代码审查、OTA工具等功能。

它依赖于Python（64bits，2.7.14和3.5已验证）。

Linux 下AliOS-Things开发环境的搭建主要分为两部分：python和pip安装、基于pip安装aos-cube及相关的依赖包。

1.安装python、pip和git：$sudo apt-get install-y python python-pip git#完成python和pip安装后，再安装依赖库和aos-cube，步骤如下：$python-m pip install setuptools wheel aos-cube注解:如果在安装过程中遇到网络问题可以使用国内镜像。

###安装/升级pip$python-m pip install–trusted-host=-i https:///pypi/simple/–upgrade pip###基于pip依次安装第三方包和aos-cube$pip install–trusted-host=-i https:///pypi/simple/setuptools$pip install–trusted-host=-i https:///pypi/simple/wheel$pip install–trusted-host=-i https:///pypi/simple/aos-cube###如需要使用doubanio作备用源$pip install–trusted-host -i /simple/aos-cube###如需指定版本，可改成如aos-cube==0.2.50因涉及多种开发环境和具体版本的依赖，针对开发者的实际情况，还给出一种简单方便且不影响当前系统环境的方法—-基于虚拟环境virtualenv的方法，作为备用。

21.5寸M215HW03 V1

document version 1.1
2
Product Specification
N
Record of Revision
M215HW03 V1
Version and Date 0.1 2010/12/21 0.2 2011/2/10
1.0 2011/3/22
6.4 Timing Characteristics ................................................................................................................... 19
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64位加法器设计解析

六十四位全加器的设计一、实验目的：设计一个64位的全加器实现加法功能。

二、实验要求：用两种方法实现64位全加器。

第一种：用Sedi画出64位全加器电路图，并生成网表，然后进行功能验证，最后将电路图生成版图。

第二种：用VHDL语言写出64位全加器的程序表达式，并进行功能验证，最后将程序语言转换成电路图。

三、实验过程3、1分析一次画出64 位全加很有难度，但考虑到全加器的结构，我们可以用4个16位的全加器组成一个64位的加法器。

同样，一个16位的全加器可以由4个4位全加器组成，一个4位全加器可以由4个一位全加器组成。

一位全加器又可以由三个半加器或两个半加器与一个或门组成。

所以整个设计思路可以简化为：半加器→一位全加器→四位全加器→十六位全加器→六十四位全加器3、2功能设计与验证（画图法）3、2、1半加器设计半加器实现加法，输入A、B，输出C、S（C 为进位，S为本位）；所以得出半加器的电路图为：半加器符号图：SS C CB B A A 半加器（）（）（）与非门或非门非门 3 、2、2一位全加器设计一位全加器可由三个半加器组成电路图如下：A B C iSC 半加器A B CS半加器A B CS半加器A B CS一位全加器的电路图符号如下：SSC iC iCCBBAA全加器3、2、3四位全加器的设计四位全加器可由四个一位全加器组成，四位全加器电路图如下：B 0A 0CS 3S 2S 1S 0C iB 3A 3B 2A 2B 1A 1全加器AB CC i S全加器A B CC i S全加器AB C C iS全加器A B CC i S四位全加器符号图如下：S 3S 3S 2S 2S 1S 1S 0S 0C iC iCC B 3B 3B 2B 2B 1B 1B 0B 0A 3A 3A 2A 2A 1A 1A 0A 0四位全加网表输入如下： 1、添加工作电压； Vvdd vdd GND 52、添加模型文件；.include "D:\iceda\TannerPro9\TSpice7.0\models\ml2_125.md" 3、添加输入信号；VA0 A0 GND PULSE (0 5 0 5n 5n 50n 100n) VA1 A1 GND PULSE (0 5 0 5n 5n 100n 200n) VA2 A2 GND PULSE (0 5 0 5n 5n 150n 300n) VA3 A3 GND PULSE (0 5 0 5n 5n 120n 240n) VB0 B0 GND PULSE (0 5 0 5n 5n 50n 100n) VB1 B1 GND PULSE (0 5 0 5n 5n 100n 200n) VB2 B2 GND PULSE (0 5 0 5n 5n 150n 300n) VB3 B3 GND PULSE (0 5 0 5n 5n 120n 240n) VCi Ci GND PULSE (0 5 0 5n 5n 50n 100n) 4、添加参数设置； .param l=0.5u5、输出设置；.print tran v(A0) v(A1) v(A2) v(A3) v(B0) v(B1) v(B2) v(B3) v(Ci) v(S0) v(S1) v(S2) v(S3) v(C) 6、设置分析；.tran/op 1n 400n method=bdf 总网表如下.include "D:\iceda\TannerPro9\TSpice7.0\models\ml2_125.md" Vvdd vdd GND 5VA0 A0 GND PULSE (0 5 0 5n 5n 50n 100n) VA1 A1 GND PULSE (0 5 0 5n 5n 100n 200n) VA2 A2 GND PULSE (0 5 0 5n 5n 150n 300n) VA3 A3 GND PULSE (0 5 0 5n 5n 120n 240n) VB0 B0 GND PULSE (0 5 0 5n 5n 50n 100n) VB1 B1 GND PULSE (0 5 0 5n 5n 100n 200n) VB2 B2 GND PULSE (0 5 0 5n 5n 150n 300n) VB3 B3 GND PULSE (0 5 0 5n 5n 120n 240n) VCi Ci GND PULSE (0 5 0 5n 5n 50n 100n) .param l=0.5u.tran/op 1n 400n method=bdf.print tran v(A0) v(A1) v(A2) v(A3) v(B0) v(B1) v(B2) v(B3) v(Ci) v(S0) v(S1) v(S2) v(S3) v(C) （由于步骤相同，以此为例，后面网表添加均简写）仿真结果：（四位全加器仿真图）3、2、4十六位全加器的设计十六位全加器可由四个四位全加器组成，十六位全加器电路图如下：A0A 1A 2A3A4A 5A 6A7A 8A 9A 10A11A12A 13A 14A15B0B 1B 2B3B4B 5B 6B7B8B 9B 10B11B12B 13B 14B15Ci S0S 1S 2S3S4S 5S 6S7S8S 9S 10S11S12S 13S 14S15C四位全加A0A1A2A3B0B1B2B3C CiS0S1S2S3四位全加A0A1A2A3B0B1B2B3C CiS0S1S2S3四位全加A0A1A2A3B0B1B2B3C CiS0S1S2S3四位全加A0A1A2A3B0B1B2B3C CiS0S1S2S3十六位全加器符号图如下：S 15S 15S 14S 14S 13S 13S 12S 12S 11S 11S 10S 10S 9S 9S 8S 8S 7S 7S 6S 6S 5S 5S 4S 4S 3S 3S 2S 2S 1S 1S 0S 0C iC iCCB 15B 15B 14B 14B 13B 13B 12B 12B 11B 11B 10B 10B 9B 9B 8B 8B 7B 7B 6B 6B 5B 5B 4B 4B 3B 3B 2B 2B 1B 1B 0B 0A 15A 15A 14A 14A 13A 13A 12A 12A 11A 11A 10A 10A 9A 9A 8A 8A 7A 7A 6A 6A 5A 5A 4A 4A 3A 3A 2A 2A 1A 1A 0A 0十六位全加器网表输入：仿真图如下：3、2、5 六十四位全加器的设计六十四全加器可由四个十六位全加器组成，六十四位全加器电路图如下：CA48A49A 50A51A52A 53A54A 55A56A 57A58A59A60A61A62A63B48B 49B50B 51B52B 53B54B 55B56B57B 58000A32A 33A34A35A 36A37A 38A39A 40A41A 42A43A44A45A46A47B32B33B 34B35B 36B37B 38B39B40B 41B42B43B44B45B46B470A16A17A18A 19A20A 21A22A 23A24A 25A26A27A28A29A30A31B16B 17B18B 19B20B 21B22B23B 24B25B 26B27B28B29B30B3100A0A1A2A3A4A5A6A7A8A9A 10A11A12A13A14A15B0B1B2B3B4B5B6B7B8B9B10B11B12B13B14B1500Ci 十六位全加器A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15B0B1B2B3B4B5B6B7B8B9B10B11B12B13B14B15C CiS0S1S2S3S4S5S6S7S8S9S10S11S12S13S14S15十六位全加器A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15B0B1B2B3B4B5B6B7B8B9B10B11B12B13B14B15CCiS0S1S2S3S4S5S6S7S8S9S10S11S12S13S14S15十六位全加器A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15B0B1B2B3B4B5B6B7B8B9B10B11B12B13B14B15CCiS0S1S2S3S4S5S6S7S8S9S10S11S12S13S14S15十六位全加器A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15B0B1B2B3B4B5B6B7B8B9B10B11B12B13B14B15CCiS0S1S2S3S4S5S6S7S8S9S10S11S12S13S14S15六十四位全加器符号图如下：S63S62S61S60S59S58S57S56S55S54S53S52S51S50S49S48S47S46S45S44S43S42S41S40S39S38S37S36S35S34S33S32S31S30S29S28S27S26S25S24S23S22S21S20S19S18S17S16S15S14S13S12S11S10S9S8S7S6S5S4S3S2S1S0CiC B63B62B61B60B59B58B57B56B55B54B53B52B51B50B49B48B47B46B45B44B43B42B41B39B40B38B37B36B35B34B33B32B31B30B29B28B27B26B25B24B23B22B21B20B19B18B17B16B15B14B13B12B11B10B9B8B7B6B5B4B3B2B1B0A63A62A61A60A59A58A57A56A55A54A53A52A51A50A49A48A47A46A45A44A43A42A41A40A39A38A37A36A35A33A34A32A31A30A29A28A27A26A25A24A23A22A21A20A19A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0Ci 00000000000000C0000000网表添加如：六十四位全加器仿真图：六十四位全加器生成版图： 1、加压焊块将设计好的六十四位全加器的电路图例化进新的module 中，然后引用PAD 模块和端口。

Orient Display AFY1024600A0-7.0INTH-R LCD模块说明书

Specification for LCD ModuleAFY1024600A0-7.0INTH-RRevision DA Orient DisplayFY TFT Type1024600 Resolution 1024 x 600A0 Serial A07.0 7.0”, Module Dimension 164.80 x 99.80 x 6.75 mmI IPS DisplayN Top: -20~+70°C; Tstr: -30~+80°CT TransmissiveH High Brightness, 800 cd/m2R Resistive Touch Panel/ Controller EK79001HN+EK73215BCGA Or Compatible / LVDS InterfaceREVISION RECORDREV NO. REV DATE CONTENTS REMARKS O 2019-11-28 First release PreliminaryA 2020.2.12 CHANGED BACKLIGHT. Detia a pagel of 9.B 2020-03-16 Update EXTERNAL DIMENSIONS Detia apagel of 6C 2020-04-10 Update Module power consumption ANDLED power consumption Detia as pagel of 4D2020-05-04 Update EXTERNAL DIMENSION in page 5CONTENTS1. GENERAL INFORMATION (4)2. ABSOLUTE MAXIMUM RATINGS (4)3. ELECTRICAL CHARACTERISTICS (4)4. BACKLIGHT CHARACTERISTICS (4)5. EXTERNAL DIMENSIONS (5)6. ELECTRO-OPTICAL CHARACTERISTICS (6)7. INTERFACE DESCRIPTION......................................................... (9)8. LVDS CHARACTERISTICS (10)9. POWER SEQUENCE............................................................... .. (15)10. RELIABILITY TEST CONDITIONS (16)11. INSPECTION CRITERION (17)12. HANDLING PRECAUTIONS (17)13. PRECAUTION FOR USE (18)14. PACKING SPECIFICATION (18)No. ItemContentsUnit 1 LCD size 7.0 inch (Diagonal)/ 2 LCD typeIPS/NormallyBlack/TRANSMISSIVE(ANTI-GLARE) / 3 Viewing direction(eye) Free/ 4 Resolution(H*V)1024*600 Pixels / 5 Module size (L*W*H) 164.8*99.8*6.75 mm 6 Active area (L*W) 154.21*85.92 mm 7 Pixel pitch (L*W) 0.1506* 0.1432 mm 8 Interface typeLVDS Interface / 9 Module power consumption 4.905W 10 Back light type White LED/ 11 Driver IC EK79001HN+EK73215BCGA or compatible / 12WeightTBDg 2.ABSOLUTE MAXIMUM RATINGSItemSymbol Min Max Unit Power supply input voltage (LCM) VDD -0.5 5.0 V Backlight current (normal temp.) ILED - 600 mA Operation temperature Top -20 70 °C Storage temperature Tst -30 80°C HumidityRH-90%(Max60°)RH3. ELECTRICAL CHARACTERISTICSDC CHARACTERISTICS （at Ta=25°C ）ItemSymbol Min Typ Max Uni t NotePower supply input voltage (LCM) VDD 2.7 3.3 3.6 V I/O logic voltageVDDIO N/A N/A N/A V =VDD Input voltage 'H' level VIH 0.7VDD - VDD V Input voltage 'L' level VIL 0 - 0.3VDDV Power supply current IVDD - 90 - mA TFT gate on voltage GH N/A N/A N/A V Built in LCMTFT gate off voltageVGL N/A N/A N/A V Analog power supply voltageAVDD N/A N/A N/A V Differential input common mode voltageVcomN/AN/AN/AV4. BACKLIGHT CHARACTERISTICS(at Ta=25°C ,RH=60%)Item Symbol Min. Typ. Max. Unit NoteLED forward voltage VF 8.7 9.6 10.5 V LED forward current IF - 480 - mA LED power consumption PLED - 4.608 - W Note1 Number of LED - 24 PCS Connection mode - 3 in series *8 in parallel / LED life-time - 20000 - - Hrs Note2 Note1.Calculator Value for reference: IF*VF = PLEDNote2.The LED Life-time define as the estimated time to 50% degradation of initial brightness at Ta=25℃ and IF =480mA. The LED lifetime could be decreased if operating IF is larger than 480mA6. ELECTRO-OPTICAL CHARACTERISTICSNote1.Definition of contrast ratioContrast Ratio(CR) is defined mathematically by the following formula. For more information see FIG.2Average Surface Luminance with all white pixels (P1, P2, P3, P4, P5,P6,P7,P8,P9) Average Surface Luminance with all black pixels (P1, P2, P3, P4, P5,P6,P7,P8,P9) Note2.Definition of surface luminanceSurface luminance is the LCD surface from the surface with all pixels displaying white. For more information see FIG.2Lv = Average Surface Luminance with all white pixels(P1, P2, P3, P4, P5,P6,P7,P8,P9) Note3.Definiton of luminance uniformityThe luminance uniformity in surface luminance （δ WHITE ） is determined by measuring luminance at each test position 1 through 9, and then dividing the maximum luminance of 9 points luminance by minimum luminance of 9 points luminance. For more information see FIG.2Minimum Surface Luminance with all white pixels (P1, P2, P3, P4, P5,P6,P7,P8,P9) Maximum Surface Luminance with all white pixels (P1, P2, P3, P4, P5,P6,P7,P8,P9) Note4. Definition of Response timeThe response time is defined as the LCD optical switching time interval between “White” state and“Black”state.Rise time (T ON ) is the time between photo detector output intensity changed from 90% to 10%. And fall time (T OFF ) is the time between photo detector output intensity changed from 10% to 90%.For additional information see FIG1.Note5. Definition of color chromaticity (CIE1931)CIE (x, y) chromaticity ,The x,y value is determined by screen active area center position P5,For more information see FIG.2 Item Symbol ConditionMin Typ Max Unit Remark NoteResponse time Tr+ Tf - - 25 50 ms FIG.1 Note 4 Contrast ratio Cr 400 500 - --- FIG.2 Note 1 Surface Luminance Lv θ=0︒ 650 800 - cd/m2 FIG.2 Note 2 Luminance uniformity - θ=0︒ 75 80 - % FIG.2 Note 3 NTSC -θ=0︒ - 50 - % FIG.2 Note 5 Viewing angle rangeθ∅ = 90︒ 70 80 - deg FIG.3 Note 6∅ = 270︒ 70 80 - deg FIG.3 ∅ = 0︒ 70 80 - deg FIG.3 ∅ = 180︒7080 -deg FIG.3CIE (x, y) chromaticityRed x θ=0︒ ∅=0︒ Ta=25℃Typ -0.04 TBD Typ +0.04-FIG.2 CIE1931Note 5Red y TBD - Green x TBD - Green y TBD - Blue x TBD - Blue y TBD - White x TBD - White yTBD-Contrast Ratio = Yu=Note6. Definition of Viewing angleViewing angle is the angle at which the contrast ratio is greater than 10. angles are determined for thehorizontal or x axis and the vertical or y axis with respect to the z axis which is normal to the LCD surface. For more information see FIG.3For Viewing angle and response time testing, the testing data is base on Autronic-Melchers’s ConoScope or DMS series Instruments or compatible. For contrast ratio, Surface Luminance, Luminance uniformity and CIE,the testing data is base on TOPCON’s BM -5or BM-7 photo detector or compatible.Note: For TFT module, Gray scale reverse occurs in the direction of panel viewing angle.The definition of Response TimeFIG.1. Measuring method for Contrast ratio, surface luminance,Luminance uniformity, CIE (x, y) chromaticitySize:S≤5”(see Figure a) A : 5 mm B : 5 mm H,V : Active AreaLight spot size ∅=5mm(BM-5) or ∅=7.7 (BM-7)50cm distance orcompatible distance from the LCD surface to detector lens. test spot position ：see Figure a.measurement instrument : TOPCON’s luminanc e meter BM-5 orFigure aBM-7 or compatible (see Figure c)AAP1P2P4P3P5HBB VSize:5”＜S≤12.3”(see Figure b) H,V : Active AreaLight spot size ∅=5mm(BM-5) or ∅=7.7mm (BM-7)50cm distance or compatible distance from the LCD surface to detector lens test spot position ：see Figure bmeasurem ent instrument : TOPCON’s luminance meter BM -5 or BM-7 or compatible (see Figure c)Figure bFigure cFIG.2. The definition of viewing angleDown Φ=270(6:00)θ=0UpΦ=90(12:00)Left Φ=180(9:00)θΦRight Φ=0(3:00)x zyBM-5/BM-77. LCM INTERFACE DESCRIPTIONInterface NO. PIN NAME I/O DESCRIPTION1 N/C Float No connection,Please float it2-3 VDD P Power supply for digital4 NC I Dither="L" , to enable internal dithering function; DITHB="H" , to disable internal dithering function;5 REST I Global reset pin. Active Low. Normally pull high.6 STBYB I Display on/off swich,”H” display off7 GND P Ground8 RXIN0- I/O LVDS data lane 0-9 RXIN0+ I/O LVDS data lane 0+10 GND P Ground11 RXIN1- I/O LVDS data lane 1-12 RXIN1+ I/O LVDS data lane 1+13 GND P Ground14 RXIN2- I/O LVDS data lane 2-15 RXIN2+ I/O LVDS data lane 2+16 GND P Ground17 RXCLKIN- I/O LVDS clk lane -18 RXCLKIN+ I/O LVDS clk lane +19 GND P Ground20 RXIN3- I/O LVDS data lane 3-21 RXIN3+ I/O LVDS data lane 3+22 GND P Ground23 NC Float No connection,Please float it24 BIST I SELB="L" for 8-bit LVDS;SELB="H" for 6-bit LVDS;25 INSEL Float SELB="L" for TTL Interface;SELB="H" for LVDS Interface;26 NC Float No connection,Please float it27 GND P Ground28 NC Float No connection,Please float it29 L/R I L/R="L" Scan direction from right to left;L/R="H" Scan direction from left to right;30 U/D I U/D="L" Scan direction from down to up;U/D="H" Scan direction from up to down;31 NC Float No connection,Please float it32-33 LEDK P LED Cathode for BL34 NC Float No connection,Please float it35-36 LEDA P LED ANODE for BL37 XR(NC) I X-Right38 YD(NC) I Y-Up39 XL(NC) I X-Left40 YU(NC) I Y-Bottom8.Lvds CHARACTERISTCiS8.1 Absolute maximum rating（GND=AGND=0V）T able 8.1 Absolute maximum rating8.2 Lvds mode DC electrical characteristicsT able 8.2 Lvds mode DC electrical characteristics 8.3PWM power tableTable 8.3 Power table8.4 Lvds mode AC electrical characteristicsTable 8.4 Lvds mode AC electrical characteristics 8.5Lvds FigureTable 8.5 Lvds Figure8.6Lvds mode data input format8.6.1 6 bit Lvds inputFigure 8.1 6 bit Lvds input 8.6.2 8 bit Lvds inputFigure 8.2 8 bit Lvds data input8.7 SDRRS TIMING DIAGRAMSDRRS(seamless display refresh rate switching)9.POWER SEQUENCE9.1. Power On/Off SequenceIn order to prevent IC from power on reset fail, the rising time (TPOR) of the digital power supply VDD should be maintained within the given spe cifications. Refer to “AC Characteristics” for more detail on timing.9.2. Power-On/Off Timing Sequence10. RELIABILITY TEST CONDITIONSNo. Test ItemTest ConditionInspection after test 1 High Temperature Storage +80C/240 hours Inspection after2~4hours storage at room temperature, the sample shall be free from defects:1.Current changing value before test andafter test is 50% larger ； 2. functiondefect:Non-display ,abn ormal-display,missing lines,Short lines ，ITOcorossion ； 3.visual defect:Air bubble in theLCD,Sealleak,Glass crack 。

播放器全志A31原理图

D
P01: P02: P03: P04: P05: P06: P07: P08: P09: P10: P11: P12: P13:
C
REVISION HISTORY BLOCK POWER TREE GPIO ASSIGNMENT DRAM DRAM CPU PMU NAND CARD-USB-HDMI CAMERA&LCD&SDIO&BASEBAND WIFI&HOST MIC&KEY&IR
SATA_22P
1 2 3 4 5 6 7 8 9 10 11 12
GND1 GPIO0 GPIO3 PIO3 HRST CVDD1 VDD1 GND2 TEST PIO0 PIO1 CVDD2
P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 S7 S6 S5 S4 S3 S2 S1
2
B
ACIN
KEY 1_8V C196 C201 C205 C211 0.01u 0.01u 0.01u 0.01u RXP RXN TXN TXP
GPIO4 PIO1 R114 0R PIO2 PIO4 R110 R113 R111 4.7K
GPIO3 R109 0R USB_DET R107 7.5K ACIN
~
AC Line M GPS MOTO Battery Voltage Supply 3.55V-4.20V
24MHz
32768Hz
G-Sensor Grycroscope Compass Light Sensor
A
A
AllWinner Technology Co.,Ltd
Design Name

A33

PDF created with FinePrint pdfFactory trial version 5544332211DDCCBBAASATA to IDE uBGA 288PCMCIA/ CardReader /1394 LINKIntel Pentium M IC CARD SocketPQFP 808050Q System Block DiagramRTL8100CL/RTL8110SBLnVIDIA 200 Pin DDR2SO-DIMM Socket*2Audio Codec PLCC 32MicrophoneFAN1 For CPUBGA756ClockGeneratorInternal Keyboard ControllerCONTROLLER uFCBGA 1257DMI x2/x4RJ-11(12 pin)SATATPA0212W83L950DSSOP 16Line out /SPDIF Internal Keyboard915GMPower Button PQFP 48512KB Speaker AmplifierLM86IEEE 1394Thermal SenserTFT LCDRJ45JACKMicro-FCPGA 478 pinTPS2220AFlash ROMIntel 82801FBMInternal AlvisoAzaliaPCI BUS 15.4" WSXGAMicrophoneVGA(NA)ICS954226AGMini PCI (wireless)BGA 609External ICH6-MPower Switch S-Video USB X 3NV44M /NV43MLQFP 128PCI7411Secondary EIDE(CDROM/DVD)Touch PADPCI-E x16L P CCPURealtek ALC260MDCLVDSD-SUB 15CRT Dothan 400/533Subwoofer(NA)AmplifierLM4991(NA)RGBFWH Y/CVideo RAM(NA)SATA HDDIDESATA3 in 1 Card Reader slot (NA)Channel BChannel AUSB 2.027Mhz14.318MHz8MHz25MHz24.576MHz32.768KHzPrimary EIDE(HDD)IDE25MHz88SA8040PQFP 64Cover SwitchUSB 2.0CY7C63723(NA)RECEIVER (NA)CIR(NA)R028050QC 235Monday, August 22, 2005316687900001TitleSize Document NumberRev Date:SheetofPDF created with FinePrint pdfFactory trial version PDF created with FinePrint pdfFactory trial version 5544332211D DCCBBAACPU-Dothan (1/2)Close to CPU as possible. < 0.5"HCOMP0 & HCOMP2 should be route with 14 mil widthHCOMP1 & HCOMP3 should be route as Zo=55ohm trace shorter than 0.5"HCOMP0 & HCOMP2 should be route as Zo=27.4ohm trace shorter than 0.5"HCOMP1 & HCOMP3 should be route with 5 mil width Close to CPU as possible.Dothan Ax step is NAPlace close to CPU socket within 2".HCOMP[0..3] should be at least 25mils away from any other toggling signal.Place 1K ± 1% and 2K ± 1%resistive divider less than equal to 0.5" from pin AD26of CPU, using 4mil(55ohm)trace. Space any otherswitching signals away from GTLREF with a minimum separation of 25 mils.FSB533FSB400CPU_BSEL0CPU_BSEL1001R028050QC 435Monday, August 22, 2005316687900001TitleSize Document NumberRev Date:Sheetof-HD30-HD56-HD38-HD62-HDSTBN1-HDSTBP[0..3]-HD14-HD48-HA5-HD31-HD35-HD39HCOMP3-HD51-HA21-HA24-HD0-HREQ3-HSMI -HD10-HA31-HD4-HD44-HDSTBP2-HD59-HRS[0..2]-HDINV[0..3]-HDINV2-HD20-HPSI -HA12-HDSTBP1-HD37-HD13-HD3-HD28-HD61-HD43-HD33-HA18HCOMP0-HA11-HA26-HD50-HD21-HA19-HD7-HD[0..63]-HD63-HA14-HD26CPU_TEST2HCOMP2-HDSTBP3-HD47-HRS1-HDINV1-HA17-HA20M -HD16-HD60-HD19-HA[3..31]-HD27-HA15-HRS0-HD22-HBR0CPU_THERMDC -HD32-HD46-HSLP -HA30-HA13-HDINV3HNMI -HD55-HD5-HREQ1-HA9-HD18-HA20-HD1-HD9-HDPSLP -HREQ[0..4]HCOMP1-HDSTBN[0..3]-HD42-HREQ0-HD52-CLK_ITP_CPU CLK_ITP_CPU -HDSTBN2-HD17-HA10-HSTPCLK -HIGNNE CPU_TEST1HTCLK -HINIT-HD45-HA8-HD36-HTRST -HA27-HD49-HD15-HDSTBN0-HA29-HD53-HA6-HRS2-HD29-HD11-HDINV0-HD41-HREQ4-HA28-HD54-HD40-HA25-HD57-HDSTBP0-HDBR -HD25-HCPURST-HA7-HD34HPWRGD-HDSTBN3-HREQ2-HD23HTDI -HD6-HD12CPU_THERMDA -HA16-HD2-HD24-HD8HINTR -HA4HTMS -HA3-HA22-HD58-HA23HTDO -HPROCHOT-HIERR-HSMI-HSLP-HIERRHPWRGD-HSTPCLK -HPROCHOT HNMI -HDPSLP -HBR0CPU_TEST2HCOMP3CPU_TEST1HCOMP0HCOMP2HCOMP1GTLREFGTLREF HTMS HTDIHTDO HTCLK-HCPURST -HTRST +CPU_CORE+CPU_CORE +VCCP+CPU_COREGNDGND+VCCP GND+VCCPGNDGND +VCCPR767504021%12R700/NA 04025%12R535104025%12C401U/NA 040210V+80-20%12TP351TP291R471K 04021%12R4954.904021%12R5154.904021%12R1155604025%12TP341TP211C39220P/NA 040250V 10%12TP221TP411TP301TP311TP361R462K 04021%12TP321TP451R7315004021%12TP421TP431U504BBANIASBGA479_SKT3D6D8D18D20D22E5E7E9E17E19E21F6F8F18F20F22G5G21H6H22J5J21K22U5V6V22W5W21Y6Y22AA5AA7AA9AA11AA13AA15AA17AA19AA21AB6AB8AB10AB12AB14AB16AB18AB20AB22AC9AC11AC13AC15AC17AC19AD8AD10AD12AD14AD16AD18AE9B15B14AC1A9C9B8C8A13C12A12C11B13B10A10AD26E26G1AF7C14C3C5F23C16P25P26AB2AB1D25J26T24AD20AE11AE13AE15AE17AE19AF8AF10AF12AF14AF16AF18VCC_0VCC_1VCC_2VCC_3VCC_4VCC_5VCC_6VCC_7VCC_8VCC_9VCC_10VCC_11VCC_12VCC_13VCC_14VCC_15VCC_16VCC_17VCC_18VCC_19VCC_20VCC_21VCC_22VCC_23VCC_24VCC_25VCC_26VCC_27VCC_28VCC_29VCC_30VCC_31VCC_32VCC_33VCC_34VCC_35VCC_36VCC_37VCC_38VCC_39VCC_40VCC_41VCC_42VCC_43VCC_44VCC_45VCC_46VCC_47VCC_48VCC_49VCC_50VCC_51VCC_52VCC_53VCC_54VCC_55VCC_56VCC_57VCC_58VCC_59VCC_60BCLK0BCLK1GTLREF3BPM2#BPM3#BPM1#BPM0#TCK TDI TDO TMS TRST#PREQ#PRDY#GTLREF0GTLREF1GTLREF2RSVD_0RSVD_2RSVD_3TEST1TEST2TEST3COMP0COMP1COMP2COMP3DINV0#DINV1#DINV2#DINV3#VCC_61VCC_62VCC_63VCC_64VCC_65VCC_66VCC_67VCC_68VCC_69VCC_70VCC_71TP331R965604025%12TP371TP441R8154.904021%12R9539040212R7468004025%12R8254.904021%12R5227.404021%12U504ABANIASBGA479_SKT3P4U4V3R3V2W1T4W2Y4Y1U1AA3Y3AA2AF4AC4AC7AC3AD3AE4AD2AB4AC6AD5AE2AD6AF3AE1AF1R2P3T2P1T1U3N2AE5A4A19A25A22B21A24B26A21B20C20B24D24E24C26B23E23C25H23G25L23M26H24F25G24J23M23J25L26N24M25H26N25K25Y26AA24T25U23V23R24R26R23AA23U26V24U25V26Y23AA26Y25AB25AC23AB24AC20AC22AC25AD23AE22AF23AD24AF20AE21AD21AF25AF22AF26C23K24W25AE24C22L24W24AE25M2H2B18A18A7B5B11D1D4C6B7C2D3A3B4E4H1K1L2M3K3K4L4N4J3L1J2C19B17E1A6C17A16A15A3#A4#A5#A6#A7#A8#A9#A10#A11#A12#A13#A14#A15#A16#A17#A18#A19#A20#A21#A22#A23#A24#A25#A26#A27#A28#A29#A30#A31#REQ0#REQ1#REQ2#REQ3#REQ4#ADSTB0#ADS#ADSTB1#IERR#D0#D1#D2#D3#D4#D5#D6#D7#D8#D9#D10#D11#D12#D13#D14#D15#D16#D17#D18#D19#D20#D21#D22#D23#D24#D25#D26#D27#D28#D29#D30#D31#D32#D33#D34#D35#D36#D37#D38#D39#D40#D41#D42#D43#D44#D45#D46#D47#D48#D49#D50#D51#D52#D53#D54#D55#D56#D57#D58#D59#D60#D61#D62#D63#DSTBN0#DSTBN1#DSTBN2#DSTBN3#DSTBP0#DSTBP1#DSTBP2#DSTBP3#DBSY#DRDY#THERMDA THERMDC DBR#INIT#RESET#LINT0LINT1STPCLK#DPSLP#A20M#FERR#IGNNE#SMI#PWRGOOD RS0#RS1#RS2#TRDY#HIT#HITM#DEFER#BR0#BPRI#BNR#LOCK#DPWR#PROCHOT#PSI#SLP#THERMTRIP#ITP_CLK0ITP_CLK1R791K/NA 04025%12R5027.404021%12TP471R7520004021%12R661K/NA 04025%12R8327.404021%12-HDPSLP 16-HA20M 16-HSTPCLK 16-HRS[0..2]7-HTRDY7HPWRGD16,27-HBNR 7-HLOCK 7-HIGNNE 16-HBPRI 7-HDEFER 7-HDBSY 7CPU_THERMDC 25HCLK_CPU 6-HHITM 7-HHIT 7CPU_THERMDA 25-HBR07-HDPRSTP16-HDINV[0..3]7-HDSTBN[0..3]7-CPU_THRMTRIP 8,16,25-CLK_ITP_CPU6-HDRDY7CPU_BSEL16,8-HSMI 16CPU_BSEL05,6,8CLK_ITP_CPU 6-HADSTB17-HCLK_CPU6-HCPURST7,27-HSLP 7,16-HINIT16-HADSTB07HNMI 16-HADS 7-HDPWR 7-HREQ[0..4]7-HA[3..31]7HINTR 16-HD[0..63]7-HFERR 16-HDSTBP[0..3]7PDF created with FinePrint pdfFactory trial version 5544332211DDCCBBAA01 1.14811110010.87601111101.5800110100.89201.468111*********.7081.30800100100 1.164001100101 1.1320101100 1.420 1.116010001111000100110001001110 1.052VID0.7640.7161.196100.7801010100100 1.6921111.036010VCC-Core 01100VCC-Core 10000 1.5161 1.676000100200050.92400.86011011111111.564011.3400.8441001111010150001111111 1.2601001.244100101100100100111101100000010111 1.08411001 1.548011.2281 1.1800110010.9080.812011.37200011.532 1.004110.9401.660111110111.388110211011101010011010010011100014011411100100111.4521100.748001.596100110 1.3240110CPU-Dothan (2/2)0000 1.484VID010********.8281010000301110.956101.61210001.404001100.7320101100011000.9721 1.0681000010 1.02010.70001011.3560 1.2761.4361011100 1.292 1.100001000 1.5000101011001.21230.9880100.796100011010(1.05V)1.6441.6281010100001place 9 pcs 10uf to CPU opposite side(Near Vcc_core source)place 9 pcs 10uf to CPU opposite side(far Vcc_core source)place 8 pcs 10uf to CPU opposite side(on Vcc_core source)place 3 pcs 10uf to CPU opposite side(on Vcc_core sourcet-left side)place 3 pcs 10uf to CPU opposite side(on Vcc_core sourcet-right side)place 3 pcs 10uf to CPU side(on Vcc_coresourcet,1-right;2-left)1.05V,2.4A place 10 pcs 0.1uf [X7R] to CPU opposite side(on middle side)VCCP DecouplingCPU Vcore DecouplingVCCA plane>100mile wideX6RX6RX6RX6RX6RX6R1.8V, For Dothan-A use1.5V for Dothan-B/Nwe CPU useFSB 100 -->FS_C High(Vccp)FSB 133 -->FS_C LowCeleron (FSB100)-->VCCA 1.8V Dothan(FSB100)-->VCCA 1.8V Dothan(FSB133)-->VCCA 1.5VPLACE IN CPU SOCKET HOLER0AR0AR0AR0AR0AR0AR028050QC 535Monday, August 22, 2005316687900001TitleSize Document NumberRev Date:SheetofVID1VID4VID3VID5VID3VID1VID[0..5]VID2VID5VID4VID0VID2VID0VCCA1VCCA2VCCA3GND GND +VCCP+5VSGNDGND+VCCQ+CPU_COREGND+VCCA +CPU_COREGND +CPU_CORE+CPU_COREGNDGND+CPU_COREGND+CPU_COREGND +VCCP GNDGNDGNDGND+VCCA+3VS+3VS GNDGND+VCCQ +VCCP+CPU_COREGND +CPU_COREGNDC750.01U 040250V 10%12C800.01U 040250V 10%12U9GS1116Y SOT89N132ADJ/GNDVOUTVINU504D BANIASBGA479_SKT3AD1AC8AC10AC12AC14AC16AC18AC21AC24E2F2F3G3G4H4D10D12D14D16E11E13E15F10F12F14F16K6L5L21M6M22N5N21P6P22R5R21T6T22P23W4AE7F26B1N1AC5AC2AB26AB23AB21AB19AD4AD7AD9AD11AD13U21AE8AE6AE3AD25AD22AD19AD17AD15AE10AE12AE14AE16AE18AE20AE23AE26AF2AF5AF9AF11AF13AF15AF17AF19AF21AF6AF24AC26VSS_160VSS_152VSS_153VSS_154VSS_155VSS_156VSS_157VSS_158VSS_159VID0VID1VID2VID3VID4VID5VCCP_0VCCP_1VCCP_2VCCP_3VCCP_4VCCP_5VCCP_6VCCP_7VCCP_8VCCP_9VCCP_10VCCP_11VCCP_12VCCP_13VCCP_14VCCP_15VCCP_16VCCP_17VCCP_18VCCP_19VCCP_20VCCP_21VCCP_22VCCP_23VCCQ0VCCQ1VCCSENSE VCCA0VCCA1VCCA2VSS_151VSS_150VSS_149VSS_148VSS_147VSS_146VSS_161VSS_162VSS_163VSS_164VSS_165VCCP_24VSS_173VSS_172VSS_171VSS_170VSS_169VSS_168VSS_167VSS_166VSS_174VSS_175VSS_176VSS_177VSS_178VSS_179VSS_180VSS_181VSS_182VSS_183VSS_184VSS_185VSS_186VSS_187VSS_188VSS_189VSS_190VSSENSE VSS_191VCCA3C3510U 6.3V080512C6410U 6.3V 080512C2810U 6.3V080512C850.1U 040210V10%12R8044.206031%12C4610U 6.3V080512C2910U 6.3V080512C570.1U 040210V 10%12C730.1U 040210V 10%12R6910004021%12C6710U 080512C540.1U 040210V10%12C2310U/NA 6.3V 080512+PC56470U 2.5V734312R65 4.7K/NA 04025%12C830.1U 040210V 10%12R72 4.7K/NA 04025%12R1Q12DTC114TKA 213C81910U 6.3V080512C4710U 6.3V 080512TP261C560.1U 040210V 10%12TP231C8110U 6.3V 080512C3710U 6.3V080512C82510U 6.3V 080512C4410U 6.3V080512R1160040212C82010U 6.3V080512C7610U 6.3V 080512L15120Z/100M 160812C5010U 6.3V080512C4810U 6.3V 080512C2710U/NA 6.3V080512R68 4.7K/NA 04025%12C710.1U 040210V 10%12C82710U 6.3V 080512C6510U 6.3V 080512R4454.9/NA 04021%12C81610U 6.3V 080512C3010U 6.3V080512C2610U/NA 6.3V080512C6210U 6.3V 080512R4554.9/NA 04021%12C580.1U 040210V 10%12R9737.406031%12C5110U 6.3V080512R59 4.7K/NA 04025%12D S Q132N7002LT1GD SC3310U 6.3V080512C3610U 6.3V080512C740.1U 040210V 10%12C2410U/NA 6.3V080512C3410U 6.3V080512C864.7U 6.3V 060312C610.1U 040210V10%12C700.1U 040210V 10%12U504CBANIASBGA479_SKT3A2A5A8A11A14A17A20A23A26B3B6B9B12B16B19B22B25C1C4C7C10C13C15C18C21C24D2D5D7D9D11D13D15D17D19D21D23D26E3E6E8E10E12E14E16E18E20E22E25F1F4F5F7F9F11F13F15F17F19F21F24G2G6G22G23G26H3H5H21H25J1J4J6J22J24K2K5K21K23K26L3L6L22L25M1M4M5M21M24N3N6N22N23N26P2P5P21P24R1R4R6R22R25T3T5T21T23T26U2U6U22U24V1V4V5V21V25W3W6W22W23W26Y2Y5Y21Y24AA1AA4AA6AA8AA10AA12AA14AA16AA18AA20AA22AA25AB3AB5AB7AB9AB11AB13AB15AB17VSS_0VSS_1VSS_2VSS_3VSS_4VSS_5VSS_6VSS_7VSS_8VSS_9VSS_10VSS_11VSS_12VSS_13VSS_14VSS_15VSS_16VSS_17VSS_18VSS_19VSS_20VSS_21VSS_22VSS_23VSS_24VSS_25VSS_26VSS_27VSS_28VSS_29VSS_30VSS_31VSS_32VSS_33VSS_34VSS_35VSS_36VSS_37VSS_38VSS_39VSS_40VSS_41VSS_42VSS_43VSS_44VSS_45VSS_46VSS_47VSS_48VSS_49VSS_50VSS_51VSS_52VSS_53VSS_54VSS_55VSS_56VSS_57VSS_58VSS_59VSS_60VSS_61VSS_62VSS_63VSS_64VSS_65VSS_66VSS_67VSS_68VSS_69VSS_70VSS_71VSS_72VSS_73VSS_74VSS_75VSS_76VSS_77VSS_78VSS_79VSS_80VSS_81VSS_82VSS_83VSS_84VSS_85VSS_86VSS_87VSS_88VSS_89VSS_90VSS_91VSS_92VSS_93VSS_94VSS_95VSS_96VSS_97VSS_98VSS_99VSS_100VSS_101VSS_102VSS_103VSS_104VSS_105VSS_106VSS_107VSS_108VSS_109VSS_110VSS_111VSS_112VSS_113VSS_114VSS_115VSS_116VSS_117VSS_118VSS_119VSS_120VSS_121VSS_122VSS_123VSS_124VSS_125VSS_126VSS_127VSS_128VSS_129VSS_130VSS_131VSS_132VSS_133VSS_134VSS_135VSS_136VSS_137VSS_138VSS_139VSS_140VSS_141VSS_142VSS_143VSS_144VSS_145R61 4.7K/NA 04025%12C550.1U 040210V 10%12C81710U 6.3V 080512C6610U 6.3V 080512C5210U 6.3V080512C6310U 6.3V 080512C4510U 6.3V080512C7710U 6.3V 080512C4210U 6.3V080512C4310U 6.3V080512TP381R117100K 04025%12C8210U 6.3V080512C5310U 6.3V080512C870.1U 040210V10%12C82610U 6.3V 080512C2510U/NA 6.3V080512C590.1U 040210V10%12C720.1U 040210V 10%12R57 4.7K/NA 04025%12C81810U 6.3V 080512VID[0..5]32CPU_BSEL04,6,8PDF created with FinePrint pdfFactory trial version A AB BC CD DEE44332211FSB 1CPU 33.3396.000100.0048.00CLOCK SYNTHERIZERLayout note: Place crystal within 500 mils of CLK Gen.100.001shortUNIT: MHzDOT SRC 100.00USB Place termination close to source ICFSA FSC PCI*048.00133.0096.0033.331For ICS 954226A use to sel Pin 32/33 ,H--> PEREQ L-->PCI-ECLKPull-low 96HZ Pull-High 100HZNB LVDSCPUCLK2 Enable H--> ENABLE L--> Disablefrom 0 othm to 10K in R0C R0A : DEL R327 FOR 48M CLKR0A : DEL C382, C383, C689FOR 48M CLKR01R01CPU_BSEL100FSB533CPU_BSEL00FSB4001R028050QC 635Monday, August 22, 2005316687900001TitleSize Document NumberRev Date:Sheetof-CLK_PCIE_PEG -DREFSSCLK-HCLK_CPUCLK_MCH_3GPLL DREFCLK +3.3VCLKSRCVDD CLK_PCIE_ICH -CLK_PCIE_ICH-CLK_MCH_BCLK DREFSSCLK CLK_PCIE_PEG -CLK_PCIE_ICH -CLK_MCH_BCLK -HCLK_CPU-CLK_PCIE_PEGHCLK_CPU -CLK_ITP_CPU -DREFCLK CLK_MCH_BCLK -CLK_ITP_CPU -CLK_MCH_3GPLL -DREFCLK CLK_ITP_CPU CLK_USB48CLK_ICHPCI PCI_KBC_CLK PCI_MINI_CLK PCI_1394_CLK PCICLK_FWH-DREFSSCLKPCIF0REQ_SEL X1+3.3VCLKSRCVDDPCIF0FS_B X2-VTT_PWRGD -CLK_PCI_STOP-CLK_CPU_STOP -CLK_MCH_3GPLL SEL100/96CPU_BSEL1CPU_BSEL0CPU_BSEL1PCI_KBC_CLK -SATA_CLKSATA_CLK -SATA_CLK REQ_SELFS_C CPU_BSEL0FS_APCI_LAN_CLKSEL100/96PCI_LAN_CLK CLK48M_CARD FS_ACLK48M_CARD SIO_48MSIO_48M-CLK_PCI_STOP -CLK_CPU_STOPCLK_ICH14-CORE_CLKEN -VTT_PWRGDX1X2GND+3VCLKPCIGND+3VCLKPCI+3VS+3VSGNDGND GND +3VS+3VS+3VCLKANAGNDGNDGNDGNDGND+3VCLKANA+3.3VCLKSRCVDDGND GND+3VS GND+VCCPGND+3VSGND+3VS GND+3VSD SPQ5172N7002LT1GDSC68110P 040250V 5%12R71349.904021%12C6900.1U 040216V10%12C66310P 040250V 5%12C68027P 040250V 5%12R75049.904021%12R71649.904021%12C6930.1U 040216V 10%12R6933304025%12R8971M/NA 04021%12R74749.9/NA 04021%12R7023304025%12R7103304025%12R73533/NA 040212C6790.1U 040216V10%12R32510K/NA 04025%12R70510K/NA 04025%12R71933040212C66410P 040250V 5%12R72549.904021%12R69910K 04025%12C7050.1U 040216V10%12C38210P/NA040250V 5%12R7113304025%12R6770_DFS 04025%12R72049.904021%12R6913304025%12R7493304025%12R6908.2K/NA 04025%12R73449.904021%12R7553304025%12C7132.2U 0603+/-10%12R3430/NA 04025%12R340004025%12R72249.904021%12R6768.2K/NA 04025%12R7060_DFS 04025%12R68810K 04025%12C67710P 040250V 5%12R6973304025%12R7233304025%12L523120Z/100M160812R70110K/NA 04025%12U510ICS954226TSSOP565049555452474612371074811392128126132945513895634518202317192281624252627533031323334353640414243441415X1X2PCI/SRC_STOP#CPU_STOP#*REF0SDATA SCLKFS_A/USB_48MHZVDDA VTT_PWRGD#/PDVDDPCI1VDDREF VDD48IREFVDDPCIEX0VDDPCIEX1VDDPCI0GND0GND1GND2GND3GND4GND5GNDA**SELPCIEX_LCDCLK/PCICLK_F1PCICLK2/REQ_SEL**PCICLK3PCICLK4PCICLK5LCDCLK_SS/PCIEX0CPCIEXC1PCIEXC2LCDCLK_SS/PCIEX0TPCIEXT1PCIEXT2ITP_EN/PCICLK_F0FS_B/TEST_MODE PCIEXT3PCIEXC3SATACLKT SATACLKC REF1/FS_C/TEST_SEL PCIEXC4PCIEXT4PEREQ2#*/PCIEXC5PEREQ1#*/PCIEXT5VDDPCIEX2CPUCLKC2_ITP/PCIEXC6CPUCLKT2_ITP/PCIEXT6CPUCLKC1CPUCLKT1VDDCPU CPUCLKC0CPUCLKT0DOTT_96MHZ DOTC_96MHZR7393304025%12C67510P040250V5%12R74249.904021%12C6742.2U 0603+/-10%12C68327P 040250V 5%12R7613304025%12C7070.1U 040216V10%12L526120Z/100M160812R76249.904021%12R6963304025%12R7583304025%12R70410K 04025%12R73149.904021%12R71710K 04025%12L524120Z/100M160812C7010.1U 040216V10%12R32733040212R74049.904021%12C6760.1U 040216V10%12R7210/NA 04025%12R6700/NA 04025%12R74333/NA 040212C6610.1U 040216V10%12R70949.904021%12R6953304025%12R75333/NA 04025%12R75949.904021%12R71433040212R69210K/NA 04025%12PR55710K 04025%12C6880.1U 040216V10%12R75249.9/NA 04021%12R3411K 04025%12R7303304025%12C38310P/NA040250V 5%12R6943304025%12R74833/NA 04025%12R72749.904021%12C67810P 040250V 5%12R7243304025%12R75649.904021%12R32833040212R72947504021%12R7153304025%12R6731K 04025%12C6912.2U 0603+/-10%12C6850.1U 040216V10%12R74549.904021%12R6890_DFS04025%12C66210P 040250V 5%12X50414.31818MHZ12R7443304025%12C68910P/NA040250V 5%12C7120.1U 040216V10%12R72833040212DREFCLK 8PCICLK_FWH 27CLK_USB4816-CLK_PCIE_ICH 16SMBDATA 14,16HCLK_CPU 4-CLK_ITP_CPU 4PCI_MINI_CLK 26CLK_ICHPCI 16-DREFCLK 8CLK_MCH_BCLK 7CLK_ITP_CPU 4SMBCLK14,16PCI_1394_CLK 21CLK_PCIE_ICH 16-CLK_MCH_BCLK 7-HCLK_CPU 4-DREFSSCLK 8DREFSSCLK 8-STOP_CPU 16,32-STOP_PCI16CLK_ICH1416CPU_BSEL14,8CPU_BSEL04,5,8CLK_MCH_3GPLL 7-CLK_MCH_3GPLL 7-CLK_PCIE_PEG 10CLK_PCIE_PEG 10PCI_KBC_CLK25SATA_CLK 16-SATA_CLK 16PCI_LAN_CLK 18VCCP_GD30CLK48M_CARD 21SIO_48M26-VTT_PWRGD 32PDF created with FinePrint pdfFactory trial version 1122334455667788AABBCCDDNB-ALVISO(1/3)Dothan Ax step is NA Close to J20 of NB0=No sdvo Device present (Default)1=SDVO sevicepresent(SDVOCTRL_DATA)15milsUse 10 mil wide trace and 20 mils space to other signals.Close to J11 of NBClose to D1 of NBClose to P1 of NBClose to J18 of NB Close to D34,D36 of NB;Trace width 10 milFor INTEL IGPR028050QC 735Monday, August 22, 2005316687900001TitleSize Document NumberRev Date:Sheetof-HD20-HDINV1-HA12-HA3-HA20-HD58-HD52HYRCOMP -HD53-HD36-HA24-HA18-HA5-HD39-HD25-HDINV3-HD18-HA27-HDSTBP1-HD5-HD62-HD8-HD22-HD57-HD6-HD12-HA13-HD13-HD29-HD21-HD17-HD24-HA6-HRS[0..2]-HDSTBP[0..3]-HD63-HREQ0-HREQ1-HD7-HD27-HA4-HA17-HREQ2-HA[3..31]HXRCOMP -HD49-HA11-HA30-HD31-HD4-HD16-HDSTBP2HYSWINGHYSCOMP -HPCREQ -HA16-HD41-HD1HXSCOMP HEDRDY -HA9-HD32-HD9-HD56-HA28-HD34-HREQ4-HD[0..63]-HD44-HD33-HA8-HD48-HDINV2-HRS1-HA19-HREQ3-HD61-HD3-HA10-HA26-HA22-HD50-HA23-HD28-HD11-HD40-HD59-HRS2-HD60-HD35-HRS0-HA14-HD45-HD2-HD51-HA31-HD10-HDSTBP0-HD54-HD55-HD14-HD30-HD47-HDINV0-HA15-HD37-HD38-HD15-HD43-HD42-HD19-HA25-HDSTBP3-HA21HXSWING -HD46-HD0-HD23-HA29-HD26-HA7-HREQ[0..4]-HDSTBN[0..3]-HDSTBN3-HDSTBN2-HDSTBN0-HDSTBN1HVREFPEG_TXP1NB_TXOUTCLK1+PEG_TXP2PEG_TXP10PEG_TXP9PEG_TXN1PEG_TXN3NB_TXOUTCLK1-PEG_TXN0PEG_RXP8PEG_TXN12PEG_RXN4NB_TXOUT10-PEG_RXN12PEG_TXP13PEG_RXP14PEG_RXN14PEG_TXP14TV_REFSETPEG_TXP6NB_CRT_BLUE PEG_RXN5PEG_TXP15PEG_TXN14PEG_RXN0PEG_TXN8PEG_TXP0PEG_RXN7PEG_RXP12NB_CRT_DDDA NB_TXOUT11-PEG_RXN13NB_TXOUT11+PEG_TXN13PEG_RXP2PEG_RXP5NB_TXOUT12+NB_CRT_GREEN PEG_TXP8PEG_TXP3PEG_RXN9PEG_RXP7PEG_RXN3PEG_TXP4PEG_TXN2PEG_RXP3NB_CRT_REDPEG_TXN15NB_TXOUT12-PEG_RXN15PEG_RXN10PEG_RXN1PEG_TXN4PEG_RXN8PEG_TXP7PEG_TXN10PEG_TXN9PEG_RXP10PEG_RXN2PEG_TXP11PEG_RXP15PEG_RXP4PEG_RXP0PEG_RXP6PEG_TXN6PEG_RXP1PEG_RXP11PEG_TXN7PEG_TXP12PEG_RXP13NB_CRT_DDCK PEG_TXN11PEG_RXN11PEG_TXP5NB_TXOUT10+PEG_TXN5PEG_RXP9PEG_RXN6HVREFHXSWINGHYSWINGHXRCOMP HXSCOMP HYRCOMPHYSCOMP NB_TV_COMP NB_TV_LUMA NB_TV_CRMA NB_CRT_BLUE NB_CRT_REDNB_CRT_GREEN GND+2.5VSGND+2.5VSGND GNDGND+1.5VS+VCCPGNDGND +VCCPGND+VCCP+VCCP GNDGNDGNDTP771R1690/NA 04025%12C5410.1U/NA 040210%12C5430.1U/NA 040210%12R59239040212R1382.2K/NA 04025%12R1343.48K/NA 060312TP751C5380.1U/NA 040210%12R6020040212C5810.1U/NA 040210%12R18925504021%12C5900.1U/NA 040210%12C5790.1U/NA 040210%12C5480.1U/NA 040210%12R21624.904021%12R60424.904021%12C6040.1U/NA 040210%12TP5081R143 2.2K/NA 04025%12R60610004021%12R1413.48K/NA 060312C5490.1U/NA 040210%12C5460.1U/NA 040210%12C5360.1U/NA 040210%12R6000040212C5850.1U/NA 040210%12C5450.1U/NA 040210%12R21022106031%12R59815004021%12R60354.904021%12C6060.1U/NA 040210%12R20254.904021%12C5960.1U/NA 040210%12C5800.1U/NA 040210%12R59615004021%12R59515004021%12TP781C5630.1U/NA 040210%12C5560.1U/NA 040210%12R1640040212R1650040212C5700.1U/NA 040210%12R19310004021%12R59315004021%12C5940.1U/NA 040210%12R59139040212R17924.904021%12R19220004021%12U507A ALVISO-915PMBGA1257_10668MME4E1F4H7E2F1E3D3K7F2J7J8H6F3K8H5H1H2K5K6J4G3H3J1L5K4J5P7L7J3P5L3U7V6R6R5P3T8R7R8U8R4T4T5R1T3V8U6W6U3V5W8W7U2U1Y5Y2V4Y7W1W3Y3Y6W2C1C2D1T1L1P1G9C9E9B7A10F9D8B10E10G10D9E11F10G11G13C10C11D11C12B13A12F12G12E12C13B11D13A13F13F8B9E13J11A5D5E7H10AB1AB2C6E6H8K3T7U5G6F7G4K1R3V3G5K2R2W4F6D4D6B3A11A7D7B8C7A8A4C5B4G8B5HD0#HD1#HD2#HD3#HD4#HD5#HD6#HD7#HD8#HD9#HD10#HD11#HD12#HD13#HD14#HD15#HD16#HD17#HD18#HD19#HD20#HD21#HD22#HD23#HD24#HD25#HD26#HD27#HD28#HD29#HD30#HD31#HD32#HD33#HD34#HD35#HD36#HD37#HD38#HD39#HD40#HD41#HD42#HD43#HD44#HD45#HD46#HD47#HD48#HD49#HD50#HD51#HD52#HD53#HD54#HD55#HD56#HD57#HD58#HD59#HD60#HD61#HD62#HD63#HXRCOMP HXSCOMP HXSWING HYRCOMP HYSCOMP HYSWINGHA3#HA4#HA5#HA6#HA7#HA8#HA9#HA10#HA11#HA12#HA13#HA14#HA15#HA16#HA17#HA18#HA19#HA20#HA21#HA22#HA23#HA24#HA25#HA26#HA27#HA28#HA29#HA30#HA31#HADS#HADSTB0#HADSTB1#HVREF HBNR#HBPRI#HBREQ0#HCPURST#HCLKN HCLKP HDBSY#HDEFER#HDINV0#HDINV1#HDINV2#HDINV3#HDPWR#HDRDY#HDSTBN0#HDSTBN1#HDSTBN2#HDSTBN3#HDSTBP0#HDSTBP1#HDSTBP2#HDSTBP3#HEDRDY#HHIT#HHITM#HLOCK#HPCREQ#HREQ0#HREQ1#HREQ2#HREQ3#HREQ4#HRS0#HRS1#HRS2#HCPUSLP#HTRDY#C5540.1U/NA 040210%12R60522106031%12C6090.1U/NA040210%12C5440.1U 040250V +80-20%12C5950.1U/NA 040210%12R190 4.99K 04021%12R1630040212C5650.1U/NA 040210%12U507CALVISO-915PMBGA1257_10668MMH24H25AB29AC29A15C16A17J18B15B16B17E24E23E21D21C20B20A19B19H21G21J20E25F25C23C22F23F22F26C33C31F28F27B30B29C25C24B34B33B32A34A33B31C29D28C27C28D27C26D36D34E30F34G30H34J30K34L30M34N30P34R30T34U30V34W30Y34D30E34F30G34H30J34K30L34M30N34P30R34T30U34V30W34E32F36G32H36J32K36L32M36N32P36R32T36U32V36W32Y36D32E36F32G36H32J36K32L36M32N36P32R36T32U36V32W36SDVOCTRL_DATASDVOCTRL_CLKGCLKNGCLKP TVDAC_A TVDAC_B TVDAC_C TV_REFSET TV_IRTNA TV_IRTNB TV_IRTNCDDCCLK DDCDATA BLUE BLUE#GREEN GREEN#RED RED#VSYNC HSYNC REFSETLBKLT_CRTL LBKLT_EN LCTLA_CLK LCTLB_DATA LDDC_CLK LDDC_DATA LVDD_EN LIBG LVBG LVREFH LVREFL LACLKN LACLKP LBCLKN LBCLKP LADATAN0LADATAN1LADATAN2LADATAP0LADATAP1LADATAP2LBDATAN0LBDATAN1LBDATAN2LBDATAP0LBDATAP1LBDATAP2EXP_COMPI EXP_ICOMPO EXP_RXN0EXP_RXN1EXP_RXN2EXP_RXN3EXP_RXN4EXP_RXN5EXP_RXN6EXP_RXN7EXP_RXN8EXP_RXN9EXP_RXN10EXP_RXN11EXP_RXN12EXP_RXN13EXP_RXN14EXP_RXN15EXP_RXP0EXP_RXP1EXP_RXP2EXP_RXP3EXP_RXP4EXP_RXP5EXP_RXP6EXP_RXP7EXP_RXP8EXP_RXP9EXP_RXP10EXP_RXP11EXP_RXP12EXP_RXP13EXP_RXP14EXP_RXP15EXP_TXN0EXP_TXN1EXP_TXN2EXP_TXN3EXP_TXN4EXP_TXN5EXP_TXN6EXP_TXN7EXP_TXN8EXP_TXN9EXP_TXN10EXP_TXN11EXP_TXN12EXP_TXN13EXP_TXN14EXP_TXN15EXP_TXP0EXP_TXP1EXP_TXP2EXP_TXP3EXP_TXP4EXP_TXP5EXP_TXP6EXP_TXP7EXP_TXP8EXP_TXP9EXP_TXP10EXP_TXP11EXP_TXP12EXP_TXP13EXP_TXP14EXP_TXP15C5660.1U/NA 040210%12R6010040212R1490/NA04025%12R59415004021%12C5860.1U/NA 040210%12C5300.1U/NA 040210%12R5990040212C5760.1U/NA 040210%12C5320.1U/NA 040210%12R153 2.2K/NA 04025%12C6120.1U/NA 040210%12C2020.1U 040250V+80-20%12R151 2.2K/NA 04025%12C5730.1U/NA 040210%12C5620.1U/NA 040210%12TP711R162 1.5K 040212R59715004021%12R1660040212R20910004021%12C2540.1U 040250V+80-20%12-HSLP 4,16-HRS[0..2]4-HD[0..63]4-HDINV[0..3]4-HHITM 4-HDSTBP[0..3]4-CLK_MCH_BCLK 6-HBNR 4CLK_MCH_BCLK 6-HDBSY 4-HDRDY 4-HREQ[0..4]4-HCPURST 4,27-HA[3..31]4-HLOCK 4-HBR04-HBPRI 4-HHIT 4-HDPWR 4-HADSTB14-HADS 4-HTRDY 4-HADSTB04-HDEFER 4-HDSTBN[0..3]4NB_CRT_RED15-CLK_MCH_3GPLL 6-FPVDDEN 15NB_CRT_DDCK 15NB_CRT_BLUE 15CLK_MCH_3GPLL6BLADJ 10,15,25TXOUTCLK1+10,15PEG_TXN[0..15]10NB_CRT_GREEN15NB_CRT_HSYNC15TXOUTCLK1-10,15PEG_RXP[0..15]10TXOUT12-10,15PEG_TXP[0..15]10TXOUT12+10,15TXOUT10+10,15TXOUT11+10,15TXOUT10-10,15TXOUT11-10,15NB_CRT_DDDA 15PEG_RXN[0..15]10ENABKL_NB15NB_CRT_VSYNC 15NB_TV_COMP 20NB_TV_LUMA 20NB_TV_CRMA20PDF created with FinePrint pdfFactory trial version 1122334455667788AABBCCDDAlviso Strapping ConfigurationCFG[17:3] have internal pull-up101=FSB4000=mobile Prescott CF7 CPU Strap1=Dothan(Default)CFG[13:12] XOR/ALL Z test straps 01=XOR Mode Enabled 10=All Z Mode Enabled 11=Normal Operation (default)CFG[19] CPU VTT select internal pull-down 0=1.05 V (default) 1=1.2 V0=Reserve Lanes(15->0,14->1 etc)1=Normal Operation(Default)CFG5 DMI X2 Select1=DMI X 4(Default)CFG[2:0] 001=FSB533CFG[18] CPU Core VCC select internal pull-down 0=1.05 V (default) 1=1.5 VCF9 PCI ExpressGraphics Lane Reversal0=DMI X 2NB-ALVISO(2/3)CFG[16] FBS Dynamic ODT have internal pull-up 0=Dynamic ODT Disabled1=Dynamic ODT Enabled(default)CFG6 DDR VS DDR21=DDR(Default)0=DDR2Route as short as possibleLayout note:DMI For EMI UseClose to AD1 of NBClose to AF37 of NBClose to AK10 of NB Close to AK11 of NBTrace Width 10 mil15 mil15 mil R01R028050QC 835Monday, August 22, 2005316687900001TitleSize Document NumberRev Date:SheetofCFG9M_RCOMPPDMI_TXP2DMI_TXN2-PM_EXTTS1-TP_SMCK5M_RCOMPN DMI_RXN3DMI_TXP3DMI_TXN1M_0CDCOMP0DMI_RXP2DMI_RXN2CFG19CFG5CFG16CFG7DMI_RXP0DMI_RXN1DMI_RXN0DMI_TXP1DMI_RXP3DMI_TXN3DMI_RXP1SMYSLEW -DREFCLK SMXSLEW -PM_EXTTS0DMI_TXP0DMI_TXN0-DREFSSCLK DREFCLK M_0CDCOMP1TP_SMCK5-TP_SMCK2DREFSSCLKCFG18CFG2CFG1CFG0SMVREFCFG16-PM_EXTTS0CFG7M_RCOMPN CFG19CFG1CFG18-PM_EXTTS1M_RCOMPP CFG9SMVREF TP_SMCK2CFG6DDRB_MA9-DDRB_BS0-DDRB_WEDDRB_MA1-DDRB_RASDDRB_DQS1-DDRB_DQS7DDRB_MA8DDRB_DQS7DDRB_MA10DDRB_DQS0DDRB_MD0-DDRB_DQS2DDRB_DQS5DDRB_DQS6-DDRB_DQS3-DDRB_DQS5DDRB_MA5DDRB_DQS3-DDRB_DQS1-TP_MB_RCVENIN DDRB_DQS2DDRB_MD4DDRB_MA7-DDRB_BS1-TP_MB_RCVENOUT -DDRB_CAS -DDRB_DQS0DDRB_MD2DDRB_DQS4DDRB_MA0DDRB_MA2DDRB_MA12DDRB_MA11DDRB_MD1DDRB_MD5DDRB_MA4-DDRB_DQS6DDRB_MD3DDRB_MD7DDRB_MA13DDRB_MA3DDRB_MA6-DDRB_BS2DDRB_MD6-DDRB_DQS4DDR_B_DQ58DDR_B_DQ19DDR_B_DQ27DDR_B_DQ54DDR_B_DQ38DDR_B_DQ37DDR_B_DQ61DDR_B_DQ44DDR_B_DQ32DDR_B_DQ47DDR_B_DQ36DDR_B_DQ7DDR_B_DQ55DDR_B_DQ21DDR_B_DQ35DDR_B_DQ16DDR_B_DQ48DDR_B_DQ1DDR_B_DQ13DDR_B_DQ50DDR_B_DQ11DDR_B_DQ51DDR_B_DQ18DDR_B_DQ31DDR_B_DQ3DDR_B_DQ4DDR_B_DQ15DDR_B_DQ56DDR_B_DQ24DDR_B_DQ[0..63]DDR_B_DQ30DDR_B_DQ23DDR_B_DQ22DDR_B_DQ6DDR_B_DQ26DDR_B_DQ33DDR_B_DQ57DDR_B_DQ46DDR_B_DQ59DDR_B_DQ34DDR_B_DQ8DDR_B_DQ39DDR_B_DQ17DDR_B_DQ42DDR_B_DQ49DDR_B_DQ60DDR_B_DQ53DDR_B_DQ62DDR_B_DQ9DDR_B_DQ28DDR_B_DQ52DDR_B_DQ43DDR_B_DQ29DDR_B_DQ12DDR_B_DQ2DDR_B_DQ5DDR_B_DQ63DDR_B_DQ10DDR_B_DQ45DDR_B_DQ25DDR_B_DQ41DDR_B_DQ14DDR_B_DQ20DDR_B_DQ0DDR_B_DQ40DDRA_MA0DDRA_MA4DDRA_MA2DDRA_MA3-DDRA_DQS3-DDRA_DQS6DDRA_MA10DDRA_MA9DDRA_MA1DDRA_MA8-DDRA_DQS1-TP_MA_RCVENIN -DDRA_DQS4-DDRA_DQS7-TP_MA_RCVENOUT DDRA_MA5DDRA_MA11-DDRA_DQS5-DDRA_BS0DDRA_MA7DDRA_MA6-DDRA_DQS2-DDRA_BS1DDRA_MA13-DDRA_DQS0-DDRA_BS2DDRA_MA12DDR_A_DQ62DDR_A_DQ24DDR_A_DQ14DDR_A_DQ45DDR_A_DQ36DDR_A_DQ54DDR_A_DQ28DDR_A_DQ1DDR_A_DQ33DDR_A_DQ46DDR_A_DQ41DDR_A_DQ[0..63]DDR_A_DQ25DDR_A_DQ38DDR_A_DQ44DDR_A_DQ32DDR_A_DQ63DDR_A_DQ61DDR_A_DQ5DDR_A_DQ17DDR_A_DQ42DDR_A_DQ57DDR_A_DQ7DDR_A_DQ52DDR_A_DQ48DDR_A_DQ59DDR_A_DQ21DDR_A_DQ3DDR_A_DQ50DDR_A_DQ16DDR_A_DQ55DDR_A_DQ43DDR_A_DQ40DDR_A_DQ49DDR_A_DQ8DDR_A_DQ20DDR_A_DQ27DDR_A_DQ56DDR_A_DQ6DDR_A_DQ23DDR_A_DQ19DDR_A_DQ10DDR_A_DQ13DDR_A_DQ0DDR_A_DQ37DDR_A_DQ18DDR_A_DQ39DDR_A_DQ12DDR_A_DQ15DDR_A_DQ53DDR_A_DQ60DDR_A_DQ9DDR_A_DQ11DDR_A_DQ31DDR_A_DQ30DDR_A_DQ26DDR_A_DQ35DDR_A_DQ51DDR_A_DQ4DDR_A_DQ22DDR_A_DQ29DDR_A_DQ34DDR_A_DQ2DDR_A_DQ58DDR_A_DQ47DDRA_DQS3DDRA_MD7DDRA_MD4DDRA_MD6DDRA_DQS6DDRA_MD2DDRA_DQS7DDRA_DQS4DDRA_DQS2DDRA_MD0DDRA_DQS1DDRA_DQS5DDRA_DQS0DDRA_MD1DDRA_MD3DDRA_MD5-DDR_CS1-DDR_CKE3-DDR_CS2-DDR_CS3-DDR_CKE2-DDR_CKE1-DDR_CKE0-DDR_CS0DDR_ODT3DDR_ODT0DDR_ODT2DDR_ODT1CFG6CFG2CFG5SMVREF GND+2.5VSGND+1.8VGND+1.8V GND+VCCP+3VS GND+3VS+1.5VS+1.8VGNDGNDTP671TP641R1721K 04025%12U507B ALVISO-915PMBGA1257_10668MMAA31AB35AC31AD35Y31AA35AB31AC35AA33AB37AC33AD37Y33AA37AB33AC37AM33AL1AJ34AF6AN33AK1AJ33AF5AP21AM21AH21AK21AN16AM14AH15AG16AF22AF16AP14AL15AM11AN10AK10AK11AF37AD1AE27AE28AF9AF10G16H13G14F16F15G15E16D17J16D15E15D14E14H12C14H15J15H14G22G23D23G25G24J17A31A30D26D25AE11AE10AC10AD10J23J21H22F5AD30AE29A24A23C37D37AP37AN37AP36AP2AP1AN1B1A2B37A36A37DMI_RXN0DMI_RXN1DMI_RXN2DMI_RXN3DMI_RXP0DMI_RXP1DMI_RXP2DMI_RXP3DMI_TXN0DMI_TXN1DMI_TXN2DMI_TXN3DMI_TXP0DMI_TXP1DMI_TXP2DMI_TXP3SM_CK0SM_CK1SM_CK3SM_CK4SM_CK0#SM_CK1#SM_CK3#SM_CK4#SM_CKE0SM_CKE1SM_CKE2SM_CKE3SM_CS0#SM_CS1#SM_CS2#SM_CS3#SMOCDCOMP0SMOCDCOMP1SM_ODT0SM_ODT1SM_ODT2SM_ODT3SMRCOMPN SMRCOMPP SMVREF0SMVREF1SMXSLEWIN SMXSLEWOUT SMYSLEWIN SMYSLEWOUT CFG0CFG1CFG2CFG3CFG4CFG5CFG6CFG7CFG8CFG9CFG10CFG11CFG12CFG13CFG14CFG15CFG16CFG17CFG18CFG19CFG20RSVD21RSVD22RSVD23RSVD24RSVD25RSVD26RSVD27SM_CK2SM_CK2#SM_CK5SM_CK5#BM_BUSY#EXT_TS0#EXT_TS1#THRMTRIP#PWROK RSTIN#DREF_CLKNDREF_CLKP DREF_SSCLKNDREF_SSCLKPNC1NC2NC3NC4NC5NC6NC7NC8NC9NC10NC11C930.1U040250V +80-20%12R175 2.2K/NA 04025%12TP721TP631R6467504021%12R15510K 04025%12R14610K 04025%12R1731K 04025%12R14710K 04025%12R201 2.2K04025%12TP681R24440.2/NA04021%12R24310012R2567504021%12R167 2.2K/NA 04025%12C3010.1U040250V +80-20%12TP991R27780.606031%12R6447504021%12R1451K/NA 04025%12TP661U507E ALVISO-915PMBGA1257_10668MMAE31AE32AG32AG36AE34AE33AF31AF30AH33AH32AK31AG30AG34AG33AH31AJ31AK30AJ30AH29AH28AK29AH30AH27AG28AF24AG23AJ22AK22AH24AH23AG22AJ21AG10AG9AG8AH8AH11AH10AJ9AK9AJ7AK6AJ4AH5AK8AJ8AJ5AK4AG5AG4AD8AD9AH4AG6AE8AD7AC5AB8AB6AA8AC8AC7AA4AA5AJ15AG17AG21AF32AK34AK27AK24AJ10AK5AE7AB7AF34AK32AJ28AK23AM10AH6AF8AB4AF35AK33AK28AJ23AL10AH7AF7AB5AH17AK17AH18AJ18AK18AJ19AK19AH19AJ20AH20AJ16AG18AG20AG15AH14AK14AF15AF14AH16SB_DQ0SB_DQ1SB_DQ2SB_DQ3SB_DQ4SB_DQ5SB_DQ6SB_DQ7SB_DQ8SB_DQ9SB_DQ10SB_DQ11SB_DQ12SB_DQ13SB_DQ14SB_DQ15SB_DQ16SB_DQ17SB_DQ18SB_DQ19SB_DQ20SB_DQ21SB_DQ22SB_DQ23SB_DQ24SB_DQ25SB_DQ26SB_DQ27SB_DQ28SB_DQ29SB_DQ30SB_DQ31SB_DQ32SB_DQ33SB_DQ34SB_DQ35SB_DQ36SB_DQ37SB_DQ38SB_DQ39SB_DQ40SB_DQ41SB_DQ42SB_DQ43SB_DQ44SB_DQ45SB_DQ46SB_DQ47SB_DQ48SB_DQ49SB_DQ50SB_DQ51SB_DQ52SB_DQ53SB_DQ54SB_DQ55SB_DQ56SB_DQ57SB_DQ58SB_DQ59SB_DQ60SB_DQ61SB_DQ62SB_DQ63SB_BS0SB_BS1SB_BS2SB_DM0SB_DM1SB_DM2SB_DM3SB_DM4SB_DM5SB_DM6SB_DM7SB_DQS0SB_DQS1SB_DQS2SB_DQS3SB_DQS4SB_DQS5SB_DQS6SB_DQS7SB_DQS0#SB_DQS1#SB_DQS2#SB_DQS3#SB_DQS4#SB_DQS5#SB_DQS6#SB_DQS7#SB_MA0SB_MA1SB_MA2SB_MA3SB_MA4SB_MA5SB_MA6SB_MA7SB_MA8SB_MA9SB_MA10SB_MA11SB_MA12SB_MA13SB_CAS#SB_RAS#SB_RCVENIN#SB_RCVENOUT#SB_WE#R25040.2/NA 04021%12TP931TP971R2607504021%12TP651R178004025%12C44510P/NA040250V12TP1011R171 2.2K/NA 04025%12U507D ALVISO-915PMBGA1257_10668MMAG35AH35AL35AL37AH36AJ35AK37AL34AM36AN35AP32AM31AM34AM35AL32AM32AN31AP31AN28AP28AL30AM30AM28AL28AP27AM27AM23AM22AL23AM24AN22AP22AM9AL9AL6AP7AP11AP10AL7AM7AN5AN6AN3AP3AP6AM6AL4AM3AK2AK3AG2AG1AL3AM2AH3AG3AF3AE3AD6AC4AF2AF1AD4AD5AK15AK16AL21AJ37AP35AL29AP24AP9AP4AJ2AD3AK36AP33AN29AP23AM8AM4AJ1AE5AK35AP34AN30AN23AN8AM5AH1AE4AL17AP17AP18AM17AN18AM18AL19AP20AM19AL20AM16AN20AM20AM15AN15AP16AF29AF28AP15SA_DQ0SA_DQ1SA_DQ2SA_DQ3SA_DQ4SA_DQ5SA_DQ6SA_DQ7SA_DQ8SA_DQ9SA_DQ10SA_DQ11SA_DQ12SA_DQ13SA_DQ14SA_DQ15SA_DQ16SA_DQ17SA_DQ18SA_DQ19SA_DQ20SA_DQ21SA_DQ22SA_DQ23SA_DQ24SA_DQ25SA_DQ26SA_DQ27SA_DQ28SA_DQ29SA_DQ30SA_DQ31SA_DQ32SA_DQ33SA_DQ34SA_DQ35SA_DQ36SA_DQ37SA_DQ38SA_DQ39SA_DQ40SA_DQ41SA_DQ42SA_DQ43SA_DQ44SA_DQ45SA_DQ46SA_DQ47SA_DQ48SA_DQ49SA_DQ50SA_DQ51SA_DQ52SA_DQ53SA_DQ54SA_DQ55SA_DQ56SA_DQ57SA_DQ58SA_DQ59SA_DQ60SA_DQ61SA_DQ62SA_DQ63SA_BS0SA_BS1SA_BS2SA_DM0SA_DM1SA_DM2SA_DM3SA_DM4SA_DM5SA_DM6SA_DM7SA_DQS0SA_DQS1SA_DQS2SA_DQS3SA_DQS4SA_DQS5SA_DQS6SA_DQS7SA_DQS0#SA_DQS1#SA_DQS2#SA_DQS3#SA_DQS4#SA_DQS5#SA_DQS6#SA_DQS7#SA_MA0SA_MA1SA_MA2SA_MA3SA_MA4SA_MA5SA_MA6SA_MA7SA_MA8SA_MA9SA_MA10SA_MA11SA_MA12SA_MA13SA_CAS#SA_RAS#SA_RCVENIN#SA_RCVENOUT#SA_WE#TP571TP911C3020.1U040250V +80-20%12TP741R200 2.2K/NA 04025%12R27680.606031%12R15410K/NA 04025%12R174 2.2K/NA 04025%12TP621TP941TP951TP701R1481K/NA 04025%12C940.1U040250V +80-20%12R168 2.2K/NA 04025%12TP961DREFCLK 6M_CLK_DDR114DMI_RXP[3..0]16DMI_TXP[3..0]16-M_CLK_DDR114M_CLK_DDR314DMI_RXN[3..0]16-CPU_THRMTRIP 4,16,25-PLT_RST 10,16,19,27-DREFCLK 6SB_PWRGD 16,25,27M_CLK_DDR014-M_CLK_DDR314DMI_TXN[3..0]16-PM_BMBUSY 16-M_CLK_DDR014M_CLK_DDR414-M_CLK_DDR414CPU_BSEL14,6CPU_BSEL04,5,6-DDRB_WE 14DDRB_MA[0..13]14-DDRB_RAS 14DDRB_DQS[0..7]14-DDRB_CAS 14-DDRB_DQS[0..7]14-DDRB_BS014-DDRB_BS214DDRB_MD[0..7]14-DDRB_BS114DDR_B_DQ[0..63]14-DDRA_BS214-DDRA_BS014-DDRA_BS114DDRA_MA[0..13]14-DDRA_CAS 14-DDRA_WE 14-DDRA_DQS[0..7]14-DDRA_RAS 14DDR_A_DQ[0..63]14DDRA_MD[0..7]14DDRA_DQS[0..7]14-DDR_CS314-DDR_CS214-DDR_CS114-DDR_CKE114-DDR_CS014-DDR_CKE014-DDR_CKE314-DDR_CKE214DDR_ODT014DDR_ODT314DDR_ODT214DDR_ODT114-DREFSSCLK 6DREFSSCLK 6PDF created with FinePrint pdfFactory trial version 。

树莓派OLED模块的使用教程大量例程详解

树莓派OLED模块的使⽤教程⼤量例程详解简介Python有两个可以⽤的OLED库[Adafruit_Python_SSD1306库]—>只⽀持SSD1306[Luma.oled库]—>⽀持SSD1306 / SSD1309 / SSD1322 / SSD1325 / SSD1327 / SSD1331 / SSD1351 / SSD1362 / SH1106 / WS0010驱动芯⽚通过本篇教程，你可以学习树莓派环境下I2C接⼝OLED基础功能的使⽤，以及获取到复杂功能的Demo例程。

故事背景时常有看到⽹络上有⼀些OLED做的智能⼩时钟，⾮常漂亮，OLED作为⼀款⾃发光、低功耗、低成本的屏幕，⾮常受⼤家的喜爱，因此我也⽐较好奇，研究了⼀下OLED的使⽤，说⼲就⼲，那我们就开始吧！硬件准备HDMI显⽰屏（推荐直接使⽤VNC或SSH⼯具远程登录，则可以少准备⼀个显⽰屏）（有线也可以，远程访问则可以不⽤）路由器Windows主机给今天的主⾓OLED亮个像吧：软件准备1. 启动树莓派I2C功能2. OLED的驱动库的选择Python有两个可以⽤的OLED库[Adafruit_Python_SSD1306库]—>只⽀持SSD1306[Luma.oled库]—>⽀持SSD1306 / SSD1309 / SSD1322 / SSD1325 / SSD1327 / SSD1331 / SSD1351 / SSD1362 / SH1106 / WS0010驱动芯⽚在这⾥我们应该怎么选择呢？先说结论：我⽐较推荐Luma.oled这个库。

下⾯分析对⽐⼀下两个库的优缺点：库优点缺点Adafruit上⼿简单例程少，功能弱，只⽀持⼀种芯⽚Luma.oled例程丰富，功能强⼤，⽀持芯⽚丰富上⼿难度稍⼤这⾥顺便贴出Luma和Adafruit库的链接：Luma官⽅⽰例代码截图⽰例代码⽬录如下从⽰例代码截图也可以看到Adafruit的例程确实很少3. Luma.oled驱动库的安装Luma.oled是基于 Python 的OLED 库，所以要⽤pip来安装，现在⽐较流⾏python3，所以推荐⽤pip3，输⼊指令sudo pip3 install luma.oledpython2 安装只需要将pip3换成pip即可Adafruit的安装指令为：sudo pip3 install Adafruit-SSD1306[外链图⽚转存失败,源站可能有防盗链机制,建议将图⽚保存下来直接上传(img-7p3KdxSL-1631859093083)(index_files/04ecc9f6-9e43-4abc-a966-78822de0a1e4.png)]如果安装失败，注意检查pip⼯具是否需要更新，注意检查⽹络是否通畅硬件连接1. 参考树莓派引脚图这个图⽐较详细，也⽐较复杂了，我们暂时只需要关注表格中间功能名，物理引脚，功能名这三列，找到1--3.3v，3--SDA.1，5--SCL.1，6--GND这四个引脚2. 参考OLED模块的引脚图引脚编号功能功能说明1GND电源地线，电源负极2VCC电源正极，⼤部分OLED模块3.3v即可驱动3SCL I2C时钟线4SDA I2C数据线3. 使⽤双母头杜邦线按照上述引脚图Pin-to-Pin连接即可，连接好后树莓派的引脚分布为L形状，接线⽰意图如下千万注意电源正负极别接反了，容易烧板⼦知识储备以下知识不在本教程详细讨论范围，但还是列举出来，有兴趣的可以⽹上找找资料深⼊学习1. OLED显⽰原理，驱动原理（嵌⼊式内容），推荐这篇博客进⾏了解2. I2C通信原理，I2C总线特点例程⼀：使⽤OLED显⽰“Hello，World”编代码先从Hello，World开始，有了⼀，就有了⽆限可能，步骤如下：1. 根据前⽂的步骤连接好OLED模块，查找oled的I2C地址，每个OLED模块的I2C地址不⼀定都相同，需要先查找获取地址，同时也检查⼀下OLED模块是否连接正常。

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C33 1uF C0402
C34 1uF C0402
C35 C36 104 104 C0402 C0402 X24MO GND
1 2
XIN GND GND XOUT
4 3
24M-20pF-10PPM
C312 18pF-1% C0402
D
HPVCC AVCC UVCC DRAM-VCC DRAM-VCC CPUVDD CPU-VDD COREVDD CORE-VDD VCC-3V3 VCC GND GND 5 5 5 5 5 5 5 5 5 LCD-D20 LCD-D19 LCD-D18 LCD-D15 LCD-D14 LCD-D13 LCD-D12 LCD-D11 LCD-D10 LCD-D7 LCD-D6 LCD-D5 LCD-D4 LCD-D3 LCD-D2 U1
LCD_D20 LCD_D19 LCD_D18 LCD_D15 LCD_D14 LCD_D13 LCD_D12 LCD_D11 LCD_D10 VCC3 LCD_D7 LCD_D6 LCD_D5 LCD_D4 LCD_D3 LCD_D2 VDD5_INT PB3/EINT17 PG4/UART1_RX/EINT4 PG3/UART1_TX/EINT3 PG2/EINT2 PG1/EINT1 PG0/EINT0 VDD5_CPU UBOOT NMI_N RESET_N PB18 PB17 NDQS VCC4 VDD6_CPU NDQ7/SDC2_D7 NDQ6/SDC2_D6 NDQ5/SDC2_D5 NDQ4/SDC2_D4 VDD7_CPU NDQ3/SDC2_D3 NDQ2/SDC2_D2 NDQ1/SDC2_D1 VDD8_CPU NDQ0/SDC2_D0 NRB1/SDC2_CLK NRB0/SDC2_CMD
B
NRE NCE0 NCE1/SPI0_CS0 VDD1_CPU VCC1 NCLE/SPI0_CLK NALE/SPI0_MISO NWE/SPI0_MOSI VDD2_CPU PB10/EINT24 VDD3_CPU PG9/SPI1_CS0/UART3_TX/EINT9 PG10/SPI1_CLK/UART3_RX/EINT10 PG11/SPI1_MOSI/UART3_CTS/EINT11 PG12/SPI1_MISO/UART3_RTS/EINT12 VDD4_CPU DZQ SVREF DDR3_D4 DDR3_D6 DDR3_D2 DDR3_D0 VCC1_DRAM DDR3_D11 DDR3_D9 DDR3_D13 DDR3_D15 DDR3_DM1 DDR3_DM0 VCC2_DRAM DDR3_DQS0 DDR3_DQS0_N DDR3_DQS1 DDR3_DQS1_N VDD1_INT DDR3_D12 DDR3_D8 DDR3_D14 DDR3_D10 DDR3_D1 DDR3_D3 DDR3_D7 VCC3_DRAM DDR3_D5
OPTION
PG4 PG9 PG10 PG11 PG12
PMU
AP1231B18ZRM LP3992-18B5F
OPTION
CARD NAND G-SENSOR TP MOTOR SY7208
LCD BL
B
OPTION
AP1231B28ZRM LP3992-28B5F
1V8@1A 2V8@1A 5V@1A
Function
DRAM
特别提醒： 1：PG0 / PG1 / PG2这三个PIN脚只具有INPUT/中断/专有功能。 2：PMU的GPIO0/1/2/3这四个PIN脚只做GPIO-OUTPUT功能。 3：PG10 /PG11 /PG12这三个PIN脚的功能不可改变。 4：CSI-PCLK 、 CSI-MCLK这两个PIN脚只具有INPUT/中断/专有功能。 5：CSI-HSYNC只具有INPUT/专有功能，不作其他用途。
4 NRB1-N 4 NRB0-N
133 134 135 136 137 138 139 140 141 142 VCC 143 144 145 146 147 148 CORE-VDD 149 150 151 152 153 154 155 CPU-VDD 156 157 158 159 160 161 162 163 VCC CPU-VDD 164 165 ND7 166 ND6 167 ND5 168 ND4 CPU-VDD 169 170 ND3 171 ND2 172 ND1 CPU-VDD 173 174 ND0 175 176
LP3220 SY8008B
OPTION
TWI2
AP3031KTR SY7201
9V9@1A
PG0 PG1 PG2 PG3
B
INPUT GPIO-IN GPIO-IN GPIO-OUT GPIO-OUT GPIO-OUT GPIO-OUT EINT GPIO-OUT
Define
SD0-DET-N USB0-VBUSDET USB0-IDDET CSI-STY-1 CSI-RST-1 MT-EN PA-SHDN TP-INT USB0-DRV
ACIN(5V)2A
Interconnect Network,and Power Driven
USBVBUS （5V-900mA） BAT(4.2V)
Battery charger /detect
DCDC3 LDO1 LDO2
01 02 03 04 05 06 07
COVER CPU POWER MEMORY DISPLAY MISC WIFI
Revision
A
Description
version 1.22 version 1.23 version 1.24
Date
2012.08.14
Drawn
YT YT YT
Checked
Approved
A
APP3_PAD_DDR3_V1_22 APP3_PAD_DDR3_V1_23 PAD_A13_STD_V1_24
5
4
3
2
1
COVER
BLOCK POWER TREE LAYOUT：ACIN、BAT、IPSOUT输入或输出线，从PMU管脚处就要保证尽量粗。 Schematics Index
D
MPU TQFP177
PMU AXP209
LCD G-Sensor USB0 OTG USB1 WIFI
TP
DCDC2 1V2@1.6A 1V2@1.2A 3V3@30mA 3V@200mA 3V3@400mA CPU VDD CORE VDD RTC AVCC WIFI
Title PAD_A13_STD Size A3 Date:
5 4 3 2
Document Name COVER Sheet
1
Rev 1 of 7
5
4
3
2
1
CPU
4 SDQ[15:0] 4 SA[14:0] 4 SBA[2:0] 4
D
DRAM
SDQ[15:0] SVREF SD0-D0 4 SD0-D1 4 TWI1-SDA 5,6 TWI1-SCK 5,6 3 3 SA[14:0] SBA[2:0] ND[7:0] LCD-D21 5 LCD-D22 5 LCD-D23 5 LCD-CLK 5 LCD-DE 5 LCD-HSYNC 5 LCD-VSYNC 5 CSI-D7 6 CSI-D6 6 CSI-D5 6 CSI-D4 6 CSI-D3 6 CSI-D2 6 CSI-D1 6 CSI-D0 6 CSI-VSYNC 6 CSI-HSYNC 6 CSI-MCLK 6 CSI-PCLK 6 SD0-D2 4 SD0-D3 4 SD0-CMD 4 SD0-CLK 4 C148 104 C0402 C142 4.7uF C0402 DRAM-VCC
LP3301 AP3019KTR
10V4@1A
GPIO0 GPIO1 GPIO2 GPIO3

GPIO-OUT GPIO-OUT GPIO-OUT GPIO-OUT
LCD-PWR LCD-BL-EN CSI-PWR-EN CSI-RST
CSI-CORE
CSI-CORE
USB OTG
LCD AVDD
REVISION HISTORY
方框内的元件标号请不要修改layout时请直接COPY原厂提供的DRAM参考PCB。 X24MI
CRYSTAL
X4
C313 18pF-1% C0402
PWM0 5 TWI0-SDA TWI0-SCK
DP1 6 DM1 6 DP0 6 DM0 6
TPY1 5 TPX1 5
ND[7:0] HPVCC
LCD_D21 LCD_D22 LCD_D23 LCD_CLK LCD_DE LCD_HSYNC LCD_VSYNC CSI_D7/URAT1_RX CSI_D6/UART1_TX CSI_D5/SDC2_CLK CSI_D4/SDC2_CMD CSI_D3/SDC2_D3 CSI_D2/SDC2_D2 CSI_D1/SDC2_D1 CSI_D0/SDC2_D0 CSI_VSYNC/SPI2_MISO CSI_HSYNC/SPI2_MOSI CSI_MCLK/SPI2_CLK/EINT15 CSI_PCLK/SPI2_CS0/EINT14 SDC0_D2 SDC0_D3 SDC0_CMD SDC0_CLK VDD4_INT SDC0_D0 SDC0_D1 PB16 PB15 PB4/EINT18 PB2/EINT16 TWI0-SDA TWI0-SCK VCC2 NC VDD3_INT V33_USB UDP1 UDM1 UDP0 UDM0 X24MIN X24MOUT TPY1 TPX1
TWI0_SCK TWI0_SDA PWM0 GPIO-OUT NC GPIO-OUT TWI1_SCK TWI1_SDA TWI2_SCK TWI2_SDA