MEMORY
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专利名称：MEMORY 发明人：ITO KIYOO 申请号：J P 14 300186 申请日：19860620 公开号：J wenku.baidu.com S63894 A 公开日：19880105
摘要：PURPOSE:To enable a data line to be operated with a low voltage, and to make a device into high speed, high integration, and low power consumption, by impressing a pulse on the storage node of a dynamic RAM cell having an ampli fying function through a capacitor, and controlling a node voltage. CONSTITUTION:When a word line W0 and a capacitor driving line WC0 of 5V are selected after pre-charging each data line at 0.75V, 1V is impressed on the word line W0, and the bit of storage information of an accumulation MOSFETQs is read out. Afterwards, a pair of data lines are set at 0V, and 1.5V, and the voltage of a word line W is set at 2V or more, and the driving line WC0 is lowered to 0V, and the voltage of a storage node NS is fixed at the voltage of the data line. Next, by setting the word line at 1V, and the driving line WC0 at 5V, the potential of the node NS goes to 3.5V, when a bit of information it '1', and it goes to 0V and is held when the bit of informa tion is '0', because the FETQs is turned on. Therefore, it is possible to set an accumulation voltage higher than the voltage of the data line, and to prevent malfunction even when the voltage of the data line is low, and to realize the low power consumption and the high integration.
申请人：HITACHI LTD
更多信息请下载全文后查看
专利名称：MEMORY 发明人：ITO KIYOO 申请号：J P 14 300186 申请日：19860620 公开号：J wenku.baidu.com S63894 A 公开日：19880105
摘要：PURPOSE:To enable a data line to be operated with a low voltage, and to make a device into high speed, high integration, and low power consumption, by impressing a pulse on the storage node of a dynamic RAM cell having an ampli fying function through a capacitor, and controlling a node voltage. CONSTITUTION:When a word line W0 and a capacitor driving line WC0 of 5V are selected after pre-charging each data line at 0.75V, 1V is impressed on the word line W0, and the bit of storage information of an accumulation MOSFETQs is read out. Afterwards, a pair of data lines are set at 0V, and 1.5V, and the voltage of a word line W is set at 2V or more, and the driving line WC0 is lowered to 0V, and the voltage of a storage node NS is fixed at the voltage of the data line. Next, by setting the word line at 1V, and the driving line WC0 at 5V, the potential of the node NS goes to 3.5V, when a bit of information it '1', and it goes to 0V and is held when the bit of informa tion is '0', because the FETQs is turned on. Therefore, it is possible to set an accumulation voltage higher than the voltage of the data line, and to prevent malfunction even when the voltage of the data line is low, and to realize the low power consumption and the high integration.
申请人：HITACHI LTD
更多信息请下载全文后查看