NEW-第06章(完整)
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a.列出扩展后的真值表;
b.将扩展后的真值表与单个芯片的真值表进行对 照，找出多的变量 ，拆分真值表;
c.充分利用使能端解决问题。
23
6-5-6 Expansion （难点：扩展）
A 4-bit decoder（4线-16线） by using 74LS138
24
6-5-6 Expansion （难点：扩展）
详见康华光教材P145 功能表
17
6-5-5 Implement Combinational Logic by Decoders (重点：用译码器实现逻辑函数）
A common decoder can accomplish any combinational logic because its outputs include all the possible combinations for the input variables, and any logic can be converted to the standard SOP form (minterms).
19
6-5-5 Implement Combinational Logic by Using Decoders Ex1：Implement Y=AB+BC by using 74138
Y=AB（C+C）+BC（A+A） =ABC+ABC+ABC =m7+m6+m3 1 பைடு நூலகம்A SB =Y Y Y 7 6 3 SC
Demultiplexers
2
6-1 Basic Adders
1. The Half-Adder (半加器）
The half-adder can fulfill the function of binary addition. The 1-bit half-adder (1位半加器） accepts two 1-bit binary digits on its inputs and produces two binary digits on its outputs a sum bit （和） and a carry bit （进位）.
(只考虑两个加数本身，而不考虑相邻低位进位的加法运算）
思考：如何设计一个半加器？
3
6-1 Basic Adders
1-bit half-adder truth table
Cout AB,
A B
• Logic Symbol
half-adder
思考：半加器的局限性？
4
6-1 Basic Adders
31
1
6-5-7 The BCD-to-7-Segment Decoder (74LS47芯片)
Zero Suppression （灭零信号） Used for multidigit displays to blank out unnecessar y zeros. Leading zero suppression (灭整数前的零） T railingzero suppression (灭小数后的零）
27
6-5-7 The BCD-to-7-Segment Decoder -- LED (Light Emitter Diode 发光二极管）
f g a b
a f g b
+ +
a b c d
+ + •
e f g
+
LED Commoncathode 共阴极
e
d c
•
•
+
e d c •
a b c
d
e f g
The input carry
Block diagram (方框图）
9
6-2 Parallel Binary Adders
Logic symbol
10
6-2 Parallel Binary Adders
ICs: integrated circuits (集成电路）
MSI Adders (Medium-scale integrated)(中规模 加法器） 74LS283 is one device of 4-bit parallel adders.
• Logic Symbol
A BC in AB C in A B C in ABC in
(A B ) C in
6
6-1 Basic Adders
Arrangement of two half-adders to form a full-adder.
7
6-1 Basic Adders
18
6-5-5 Implement Combinational Logic by Decoders Procedures
Step 1: Convert the logic expression to its standard SOP form. Step 2: Determine the corresponding relationship between the expression inputs and the decoder’s inputs.
设计：用3个半加器同时实现下列函数？
F1 A B C F2 ABC A BC F3 AB C AC BC F4 ABC
8
6-2 Parallel Binary Adders (多位全加器） ——自学
1. Four-bit Parallel Adders (4位全加器）
试用四片74HC138和一片74HC139构成5线-32线译码器。
25
6-5-6 Expansion （难点：扩展）
6-5-7 The BCD-to-7-Segment Decoder （7段显示译码器）
The BCD-to-7-segment decoder accepts the BCD code on its inputs and provides outputs to drive 7-segment display devices to produce a decimal readout.
Step 3: If the decoder’s output is LOW-active, convert the expression to NAND form.
Step 4: Draw the circuit with OR gates if the output is active-HIGH, or NAND gates if it is active-LOW.
21
6-5-5 Implement Combinational Logic Using Decoders
(2) Conversion
(3) Logic Circuit
总结：利用译码器和与非门实现
22
6-5-6 Expansion（难点：扩展）
方法归纳： 1.确定扩展所需的芯片数量
2.明确所有芯片的工作方式（同时，分时）
13
6-5-3 Decoders-- a 2-line-to-4-line decoder (2线-4线译码器）
The truth table
康华光教材P144
4.4.5
Y
0
E A1 A0
The output expressions
Y1 E A1A0 Y 2 E A1 A0 Y 3 E A1A0
管脚图 Logic symbo l
11
6-5-1 Decoders (译码器）--定义
The basic function of a decoder is to detect the presence of a specified combination of bits (code) on its inputs and to indicate the presence of that code by a specified output level.
Commonanode 共阳极
28
6-5-7 The BCD-to-7-Segment Decoder –Truth Table
f g a b
a f g b
e
d c
•
e d c •
29
6-5-7 The BCD-to-7-Segment Decoder (74LS47芯片)
Pin diagram and logic symbol for the 74LS47 BCD-to-7-segment decoder/driver
总结：表达式规律
Y i mi(当E 0时）
14
（提问：画出逻辑图？）
6-5-3 Decoders-- a 2-line-to-4-line decoder (2线-4线译码器）
Logic symbol (74X139) 康华光教材P145 图4.4.8
注意：说明符号。
15
6-5-4 Decoders--An MSI 1-of-8 Decoder
The Full-Adder (全加器） The 1-bit full-adder accepts two input bits and an input carry (低位的进位） and generates a sum output and an output carry. The difference between a full-adder and a halfadder is that the full-adder accepts an input carry.
Y3
Y6 Y7
&
A2 A1 A0 A B C
20
74LS138
Y
6-5-5 Implement Combinational Logic Using Decoders
Ex2: Use 74138 to implement a multi-output logic expressions.
(1) Convert to the SOP forms
(不仅要考虑两个加数，还要考虑来自相邻低位的进位）
思考：如何设计一个全加器？
5
6-1 Basic Adders
1-bit full-adder truth table
C out ABC in A BC in AB C in ABC in
AB (A B ) C in
BI / RBO(Blanking Input/ Ripple Blanking Output) (灭灯输入端/灭零输出端） When used as a BI, all segment outputs are HIGH(nonactive) when BI is LOW, which overrides all other inputs.
30
6-5-7 The BCD-to-7-Segment Decoder (74LS47芯片)
Lamp test (灯测试信号） ： When LT 0 and BI/ RBO 1, all of the7 segmentsin thedisplay are turnedon. It is used to verify th at no segments are burned out. 0
6 Functions of Combinational Logic
1
Contents
Basic Adders Parallel Binary Adders
Comparators
Decoders Encoders Code Converters Multiplexers (Data Selectors)
(将具有特定含义的二进制码转换成对应的输出信号）
12
6-5-2 Decoders --二进制译码器结构图
In its general form, a decoder has n input lines to handle n bits and from one to 2n output lines. （康华光教材P144 图4.4.6） Notice：There is an enable function(EN使能端) provided on this device.
66encodersapriorityencoder42线优先编码器设计1列出功能表输入输入输出输出2写出逻辑表达式输入编码信号高电平有效输出为二进制代码输入编码信号优先级从高到低为i3?i0输入为编码信号i3?i0输出为y1y0i0i1i2i3y1y0100000100011010111高低3画出逻辑电路略3321iiiy33210iiiiy存在的问题
(74LS138)
74LS138 is a very common 1-of-8 decoder.
W h e n S 1 1 , S 2 S 3 0 , the o utp ut is a c tive
16
6-5-4 Decoders--An MSI 1-of-8 Decoder
(74LS138)
b.将扩展后的真值表与单个芯片的真值表进行对 照，找出多的变量 ，拆分真值表;
c.充分利用使能端解决问题。
23
6-5-6 Expansion （难点：扩展）
A 4-bit decoder（4线-16线） by using 74LS138
24
6-5-6 Expansion （难点：扩展）
详见康华光教材P145 功能表
17
6-5-5 Implement Combinational Logic by Decoders (重点：用译码器实现逻辑函数）
A common decoder can accomplish any combinational logic because its outputs include all the possible combinations for the input variables, and any logic can be converted to the standard SOP form (minterms).
19
6-5-5 Implement Combinational Logic by Using Decoders Ex1：Implement Y=AB+BC by using 74138
Y=AB（C+C）+BC（A+A） =ABC+ABC+ABC =m7+m6+m3 1 பைடு நூலகம்A SB =Y Y Y 7 6 3 SC
Demultiplexers
2
6-1 Basic Adders
1. The Half-Adder (半加器）
The half-adder can fulfill the function of binary addition. The 1-bit half-adder (1位半加器） accepts two 1-bit binary digits on its inputs and produces two binary digits on its outputs a sum bit （和） and a carry bit （进位）.
(只考虑两个加数本身，而不考虑相邻低位进位的加法运算）
思考：如何设计一个半加器？
3
6-1 Basic Adders
1-bit half-adder truth table
Cout AB,
A B
• Logic Symbol
half-adder
思考：半加器的局限性？
4
6-1 Basic Adders
31
1
6-5-7 The BCD-to-7-Segment Decoder (74LS47芯片)
Zero Suppression （灭零信号） Used for multidigit displays to blank out unnecessar y zeros. Leading zero suppression (灭整数前的零） T railingzero suppression (灭小数后的零）
27
6-5-7 The BCD-to-7-Segment Decoder -- LED (Light Emitter Diode 发光二极管）
f g a b
a f g b
+ +
a b c d
+ + •
e f g
+
LED Commoncathode 共阴极
e
d c
•
•
+
e d c •
a b c
d
e f g
The input carry
Block diagram (方框图）
9
6-2 Parallel Binary Adders
Logic symbol
10
6-2 Parallel Binary Adders
ICs: integrated circuits (集成电路）
MSI Adders (Medium-scale integrated)(中规模 加法器） 74LS283 is one device of 4-bit parallel adders.
• Logic Symbol
A BC in AB C in A B C in ABC in
(A B ) C in
6
6-1 Basic Adders
Arrangement of two half-adders to form a full-adder.
7
6-1 Basic Adders
18
6-5-5 Implement Combinational Logic by Decoders Procedures
Step 1: Convert the logic expression to its standard SOP form. Step 2: Determine the corresponding relationship between the expression inputs and the decoder’s inputs.
设计：用3个半加器同时实现下列函数？
F1 A B C F2 ABC A BC F3 AB C AC BC F4 ABC
8
6-2 Parallel Binary Adders (多位全加器） ——自学
1. Four-bit Parallel Adders (4位全加器）
试用四片74HC138和一片74HC139构成5线-32线译码器。
25
6-5-6 Expansion （难点：扩展）
6-5-7 The BCD-to-7-Segment Decoder （7段显示译码器）
The BCD-to-7-segment decoder accepts the BCD code on its inputs and provides outputs to drive 7-segment display devices to produce a decimal readout.
Step 3: If the decoder’s output is LOW-active, convert the expression to NAND form.
Step 4: Draw the circuit with OR gates if the output is active-HIGH, or NAND gates if it is active-LOW.
21
6-5-5 Implement Combinational Logic Using Decoders
(2) Conversion
(3) Logic Circuit
总结：利用译码器和与非门实现
22
6-5-6 Expansion（难点：扩展）
方法归纳： 1.确定扩展所需的芯片数量
2.明确所有芯片的工作方式（同时，分时）
13
6-5-3 Decoders-- a 2-line-to-4-line decoder (2线-4线译码器）
The truth table
康华光教材P144
4.4.5
Y
0
E A1 A0
The output expressions
Y1 E A1A0 Y 2 E A1 A0 Y 3 E A1A0
管脚图 Logic symbo l
11
6-5-1 Decoders (译码器）--定义
The basic function of a decoder is to detect the presence of a specified combination of bits (code) on its inputs and to indicate the presence of that code by a specified output level.
Commonanode 共阳极
28
6-5-7 The BCD-to-7-Segment Decoder –Truth Table
f g a b
a f g b
e
d c
•
e d c •
29
6-5-7 The BCD-to-7-Segment Decoder (74LS47芯片)
Pin diagram and logic symbol for the 74LS47 BCD-to-7-segment decoder/driver
总结：表达式规律
Y i mi(当E 0时）
14
（提问：画出逻辑图？）
6-5-3 Decoders-- a 2-line-to-4-line decoder (2线-4线译码器）
Logic symbol (74X139) 康华光教材P145 图4.4.8
注意：说明符号。
15
6-5-4 Decoders--An MSI 1-of-8 Decoder
The Full-Adder (全加器） The 1-bit full-adder accepts two input bits and an input carry (低位的进位） and generates a sum output and an output carry. The difference between a full-adder and a halfadder is that the full-adder accepts an input carry.
Y3
Y6 Y7
&
A2 A1 A0 A B C
20
74LS138
Y
6-5-5 Implement Combinational Logic Using Decoders
Ex2: Use 74138 to implement a multi-output logic expressions.
(1) Convert to the SOP forms
(不仅要考虑两个加数，还要考虑来自相邻低位的进位）
思考：如何设计一个全加器？
5
6-1 Basic Adders
1-bit full-adder truth table
C out ABC in A BC in AB C in ABC in
AB (A B ) C in
BI / RBO(Blanking Input/ Ripple Blanking Output) (灭灯输入端/灭零输出端） When used as a BI, all segment outputs are HIGH(nonactive) when BI is LOW, which overrides all other inputs.
30
6-5-7 The BCD-to-7-Segment Decoder (74LS47芯片)
Lamp test (灯测试信号） ： When LT 0 and BI/ RBO 1, all of the7 segmentsin thedisplay are turnedon. It is used to verify th at no segments are burned out. 0
6 Functions of Combinational Logic
1
Contents
Basic Adders Parallel Binary Adders
Comparators
Decoders Encoders Code Converters Multiplexers (Data Selectors)
(将具有特定含义的二进制码转换成对应的输出信号）
12
6-5-2 Decoders --二进制译码器结构图
In its general form, a decoder has n input lines to handle n bits and from one to 2n output lines. （康华光教材P144 图4.4.6） Notice：There is an enable function(EN使能端) provided on this device.
66encodersapriorityencoder42线优先编码器设计1列出功能表输入输入输出输出2写出逻辑表达式输入编码信号高电平有效输出为二进制代码输入编码信号优先级从高到低为i3?i0输入为编码信号i3?i0输出为y1y0i0i1i2i3y1y0100000100011010111高低3画出逻辑电路略3321iiiy33210iiiiy存在的问题
(74LS138)
74LS138 is a very common 1-of-8 decoder.
W h e n S 1 1 , S 2 S 3 0 , the o utp ut is a c tive
16
6-5-4 Decoders--An MSI 1-of-8 Decoder
(74LS138)