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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS,VOL.62,NO.5,MAY20152859 A Modular Multilevel Converter Pulse Generation
and Capacitor Voltage Balance Method
Optimized for FPGA Implementation
Wei Li,Member,IEEE,Luc-AndréGrégoire,Student Member,IEEE,and Jean Bélanger,Member,IEEE
Abstract—To generate numerous gating signals at a fast rate,industry controllers of modular multilevel converter (MMC)usually implement the pulse generation function in field-programmable gate array(FPGA)boards.Many meth-ods of submodule(SM)capacitor voltage balance control (VBC)require knowing the gating signals and are therefore also implemented in the same FPGA.As the number of SMs in an MMC increases,both the latency and required resources for the implementation could become too large to meet the control requirements orfit into the FPGA. Conventional methods impose a limitation on the design of large MMC.This paper presents a pulse generation and VBC method that is optimized for FPGA implementation. With least comparison operation,this method produces the same valve voltage as other modulation methods,and it removes the need for a sorting operation in VBC,which is the main difficulty in FPGA implementation.The proposed method is implemented in the FPGA-based RT-LAB real-time simulator and tested in a hardware-in-the-loop setup. The performance of this method is validated in various tests.
Index Terms—Field-programmable gate array(FPGA), modular multilevel converter(MMC),power system simu-lation,real-time systems.
I.I NTRODUCTION
M ODULAR multilever converters(MMCs)are gaining popularity in high-voltage direct current(HVDC)appli-cations.Currently,two multiterminal MMC HVDC projects are being built in Nan’ao and Zhoushan,China.As MMC has many advantages,including low ac harmonic contents,low switching loss,fast fault recovery,and high reliability,it also presents many challenges[1]–[6].One of them is the implementation of the pulse generation and capacitor voltage balance control (VBC)due to the enormous number of submodules(SMs)in one MMC.
Different gating signal generation techniques are proposed in the literature for MMC control.Space vector modulation schemes are used in[7]–[9]for MMC with a low number of voltage levels.Multicarrier pulsewidth modulation(PWM)
Manuscript received February13,2014;revised May22,2014, July22,2014,and September8,2014;accepted September17, 2014.Date of publication October14,2014;date of current version April8,2015.
The authors are with Opal-RT Technologies,Montréal,QC H3K1G6, Canada(e-mail:wei.li@;luc-andre.gregoire@; jean.belanger@).
Color versions of one or more of thefigures in this paper are available online at .
Digital Object Identifier10.1109/TIE.2014.2362879schemes become more applicable as the MMC voltage level in-creases and,thus,are more commonly proposed in the literature [10]–[22].Particularly,the phase-shifted multicarrier PWM is used in[11]–[17],and the level-shifted multicarrier PWM is used in[19]–[23].A comparison and evaluation of the two categories of PWM is given in[24]and[25].A PWM scheme using the moving-average concept is introduced and used in [26]–[29].
Mainly two capacitor VBC approaches,namely,the individ-ual control loop approach and the pulse reassignment approach, are proposed in the literature.In thefirst approach,capacitor voltage control loops are added for each SM,and therefore,all references for pulse generation are different,[10]–[14],[30], [31].By using two loops,capacitor voltage balancing among valves and inside each valve can be achieved.Since the ref-erence combines the components from different control loops, tuning the control parameters,which is system dependent, becomes important but difficult[11].A large weight of the VBC signal in the reference could affect other control loops,whereas a small weight could lead to a slow response.
For the second approach,there is no capacitor voltage control loop.The voltage reference is the same for all SMs in one valve.The generated pulses are reassigned to SMs according to the sorting results of the capacitor voltage and valve cur-rent direction[8],[15]–[22],[25]–[28],[32].This approach, which is effective for balancing inside each valve,is decoupled from other control loops and does not require tuning control parameters.It usually has faster response compared with the individual control loop approach.As this approach is applied after pulse generation,both the pulse generation and VBC are usually implemented in thefield-programmable gate array (FPGA)[7],[21],[22],[27],[28].The difficulty is in the FPGA implementation since the conventional methods need to sort the capacitor voltages in ascending or descending order and reassign the pulses according to the sorting result.
This paper discusses the practical difficulties in implement-ing the pulse generation and VBC,particularly for MMC with a large number of SMs.A method optimized for FPGA imple-mentation is then presented.
II.P ULSE G ENERATION
The MMC topology with a half-bridge SM is given in Fig.1. When the capacitor voltages are well controlled to the nominal value,i.e.,V cap·nom,the valve output voltage,i.e.,V MMC,is expressed as
V MMC=Σ(N i∗V cap·i)=V cap·nomΣN i(1)
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Fig.1.
Schematic of MMC and
SM.
Fig. 2.Multiple carriers and reference for the phase-shifted PWM method.
where N i is the gating pulse,V cap ·i is the capacitor voltage,and subscript i denotes that the value is for the i th SM.The MMC performance,including its harmonic contents,is only determined by the pulse summation or the number of ON -state SM.The selection of the ON -state SM will not affect the results.
The principle of the proposed pulse generation method is to generate the exact same number of ON -state SMs as other modulation methods but with minimal operation.Thus,it is op-timized for FPGA implementation without any negative impact on the MMC performance or harmonic contents.The selection of the ON -state SM is made at a later VBC stage.
A typical multicarrier phase-shifted PWM is illustrated in Fig.2.The number of triangle carriers is the same as the SM number in one MMC valve,which is denoted as M .The carriers are evenly interleaved,i.e.,a 2π/M phase shift between every two consecutive carriers.The magnitude of all carriers and the reference are multiplied by M times for easier demonstration.For each SM,the pulse is determined by comparison between the reference and the carrier.The summation,i.e.,N Σ,is given as
N Σ=ΣN i =ΣU (S ref ,S car ·i )
(2)
where S ref is the reference,S car ·i is the carrier,and U (x,y )is
the comparison operator,which gives one if the first parameter x is greater than the second parameter y ,or 0otherwise.
The carriers take the range of [0M ]on the y -axis,which can be evenly divided into M number of contiguous bands.The i th band is between (i −1)and i on the y -axis,where i is 1,2,...,M .The carriers cross each other simultaneously (2∗M )times per carrier period.The crossing points are all at the band boundaries.At any time,each band contains only one carrier.
Since all SMs are not differentiated at this stage,the carriers can be reindexed without affecting the value of N Σ.At any time,the carrier currently in the i th band is dynamically
indexed
Fig.3.Reindexed carriers and reference for the phase-shifted PWM
method.
Fig.4.Schematic diagram to achieve the pulse summation N Σ
.
Fig. 5.N Σis the sum of (a)the reference integer part,and (b)comparison result between the reference factional part (red)and a reindexed carrier (black).
as the new i th carrier,which is marked as S
car ·i (see Fig.3).S
car ·i takes a value in the range [i −1,i ].Thus,(2)becomes
N Σ=
M i =1U (S ref ,S
car ·i )=
SN i =1
U (S ref ,S car ·i )
+U
S ref ,S
car ·(SN +1)
+
M
i =SN +2U (S ref ,S
car ·i )
=SN +U
S ref −
SN,S
car ·(SN +1)
−SN
(3)
where SN is the integer part of S ref .
The term (S ref −SN )represents the fractional parts of S ref ,
which is identified as SR .The waveform of (S
car ·(SN +1)−
SN ),which is identified as S
car ,is either the same as or the
reverse of S
car1,depending on if SN is even or odd.Therefore,the pulse summation,rewritten as
N Σ=SN +U (SR,S
car
)(4)
can be achieved by adding the integer part of the reference with
the comparison result of the fractional part of the reference with a new carrier,which has a frequency M times of the original multicarriers.The carrier flips when the integer part of the ref-erence is an even number.Fig.4gives the schematic diagram,and Fig.5gives the new reference and carrier waveforms for the same case in Fig.2.
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Fig.6.Carriers of level-shifted PWM for(a)the phase disposition method,(b)the phase-opposition disposition method,and(c)the alternative-phase-opposition disposition method.
This method can be easily adapted to other modulation meth-ods.Three typical multicarrier level-shifted PWM methods are illustrated in ing the same principle,the pulse summation can also be achieved by(4),where S car has the same frequency as the original level-shifted multicarrier.The S car waveforms for the phase-shifted and the three level-shifted PWM methods are slightly different,but can be generated by the same code in the FPGA.
When the number of SMs in a valve increases to a large number,e.g.,200,the harmonic becomes less of a concern. Some industry controllers use nearest level control(NLC) modulation to reduce the switching loss.This method can also be adapted to the NLC modulation.By setting S car in(4)to the constant of1,or0.5,0,the resulting NΣgives thefloor integer, rounded integer,or ceiling integer of the reference,respectively. Therefore,the proposed method can produce the same valve voltage as other modulation methods,e.g.,phase-shifted PWM, level-shifted PWM,or NLC,without recompilation of the FPGA program.The user can check the impact of different methods and carrier frequencies on the system harmonics on-the-fly.
More important,this method requires the comparison op-eration only once,regardless of the SM pared with the conventional multicarrier PWM methods,which need M carriers for M times the comparison operation,it takes minimumfixed FPGA resources regardless of the MMC size.
III.C APACITOR V OLTAGE B ALANCE
A.Difficulties of Implementing Sorting Algorithm in FPGA To balance the capacitor voltage,the conventional pulse reassignment approaches need to sort the capacitor voltage. In practice,the bubble sort algorithm is often used due to its simplicity to program in FPGA.For real-time applications, the algorithm performance in the worst case is considered. To sort M SMs,the bubble sort needs(M−1)number of passes.In the n th pass,(M−n)number of steps consecutively compare,and swap if necessary,a pair of adjacent voltages. This algorithm requires a total of0.5M(M−1)steps and has complexity of O(M2),where the big O notation describes limiting behaviors of a function,and in this case,the complexity is asymptotically equivalent to M2when M tends toward infinite.
The bubble sort implementation in FPGA can be in series, e.g.,with one function of the compare-and-swap step being called for0.5M(M−1)times,or in partial parallel,e.g., with multiple functions being called for fewer times.Each call of the function will take one FPGA clock.Hence,the series implementation will take at least0.5M(M−1)FPGA clocks. In a partial-parallel implementation of(M−1)functions,each function works for one pass,and the function for thefirst pass is called for the most times,i.e.,(M−1)times.Thus,it takes minimum(M−1)FPGA pared with the series implementation,the partial-parallel implementation is faster. However,for a large M,it is still too slow as required by control and takes too much FPGA resources for the large number of functions.
Moreover,once the capacitor voltages are sorted,the pulses have to be reassigned according to the sorting results.This has to be done individually,which could also take considerable FPGA resources.
Improvements on the bubble sort algorithm are proposed for MMC applications,but the complexity order remains similar. There exist other sorting algorithms with better worst-case complexity of O(M log M).
Due to its nature,the FGPA resources and latency of sorting algorithm dramatically increase as M increases.The VBC could become too slow to meet the upper level control require-ments,or the implementation is too large to be accommodated in the FPGA.The design of the SM number in an MMC is limited by the VBC using the sorting method.
B.Flowchart of Proposed Max/Min Method
Without sorting operation,the proposed VBC method only needs tofind the SM of the maximum or minimum capacitor voltage.The actual number of ON-state SMs,i.e.,NΣact,is calculated and compared with its reference,i.e.,NΣref,in each FPGA cycle,the simulation time step in the FPGA.Depending on the result and the current direction(the charging direction is defined as positive),this method changes,if necessary,only one SM’s state according to the following rules.
•If NΣact<NΣref and positive current,turn on the OFF-state SM of the minimum capacitor voltage.
•If NΣact<NΣref and nonpositive current,turn on the OFF-state SM of the maximum capacitor voltage.
•If NΣact>NΣref and positive current,turn off the ON-state SM of the maximum capacitor voltage.
•If NΣact>NΣref and nonpositive current,turn off the ON-state SM of the minimum capacitor voltage.
•If NΣact=NΣref,no switching.
Theflowchart for the proposed method is given in Fig.7. There are seven steps in each FPGA cycle.Step1reads the pulse summation generated in Fig.4as the reference number of ON-state SM.Step2initializes the SM states if it is the first cycle since the MMC pulse is enabled.As all capaci-tors are charged to a similar voltage in the diode mode,the first NΣref number of SMs are set to ON-state and others to OFF-state.In Step3,the actual number of ON-state SMs is calculated and compared with the reference value.Steps4–7 take action according to the rules explained above.
In Step5,Cmax and zero are the maximum and minimum possible capacitor voltages.Since this method searches only the maximum or minimum capacitor voltage of SM with a specific state,this step is to exclude the SM of the opposite state from
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Fig.7.Flowchart of proposed capacitor voltage balance method. being selected.For example,to select a previous OFF-state SM of the minimum voltage,the voltages of all previous ON-state SMs are set to the value of Cmax.Note in Steps5and6that the logic in different paths is similar and can be implemented using the same function to save FPGA resources.
plexity and Latency of Proposed Method
Tofind the maximum or minimum among M values,(M−1)number of comparison operations are required,which has complexity of O(M),which is a lower order than the complex-ity of sorting operations.
The implementation in FPGA can be in series,parallel, or partial parallel.The series implementation has only one function being called for(M−1)time.The parallel implemen-tation requires floor(M/2)number of functions and maximum ceiling(log2(M))number of call for one function,where floor(x)and ceiling(x)give thefloor and ceiling integers of x.In the partial-parallel implementation,the M voltages are divided into K groups.Each group is treated in series,and the Kfinalists of each group are treated in parallel.It requires (M/K−1+ceiling(log2(K)))number of FPGA clocks and (K+floor(K/2))number of functions.
The series implementation takes longer time,and the paral-lel implementation takes more FPGA resources.The partial-parallel implementation provides a good combination of speed and resources,which can be adjusted by changing the value K. For example,when a valve has1024SMs,the required FPGA resources and latency for the implementation of the bubble sorting and the proposed method are summarized in Table I. Even taking enormous FPGA resources(1023functions),the bubble sorting in partial-parallel implementation takes more than10μs(for a10-ns FPGA clock),which might not meet the controller’s requirements.The proposed method(with K=32)
TABLE I
FPGA R ESOURCES AND L ATENCY FOR D IFFERENT M
ETHODS approximately takes21times less resource and is28times
faster(in less than halfμs).
D.Features of Proposed Method
When a big disturbance occurs to the system,the valve volt-age has to rapidly change according to its reference in order to recover the system fast.That means the derivative of the valve voltage has to be large.This method can change the number of ON-state SMs by one at each FPGA cycle as in Fig.7,which is smaller than the switch signal sampling time.For example,
if the sampling time is10μs and the FPGA cycle is500ns,a maximum20(=10μs/500ns)SMs of the specific state with thefirst20maximum or minimum capacitor voltages could change their states at each10μs sampling period.Therefore, this method can achieve a very high valve voltage derivative. The per-unitized maximum absolute value is given as
d
dt
V MMCpu
max
=
|ΔNΣ|max/M
Δt
=
1/M
T FPGAcycle
(5)
which is1000pu/s for an MMC with2000SMs per valve,and the FPGA cycle,i.e.,T FPGAcycle,being500ns.For a typical application with less SM number and equal or smaller FPGA cycle,the maximum derivative is even larger than1000pu/s, much higher than a control design may require.Therefore,by changing only one SM’s state at each FPGA cycle,this method will not decrease the system performance or slow down the system recovery at big disturbances.
In a phase-shift modulation method with M SMs and carrier frequency of f car,each SM has a switching frequency of f car and switches twice(one for switching-on and another for switching-off)in each carrier signal period.The total switching number is2M in one valve.As in Fig.3,the proposed method only reindexes the carriers without modifying their pattern,the total switching number in a valve is not changed,2M in each period in this case.Although in one period,each individual SM might switch more or less times,the average switching number and,thus,the average switching frequency,is the same as in the original modulation method.For the level-shifted or NLC modulation method,the adapted method has the same average switching frequency as the original method.
For multicarrier modulation methods,a reference may cross an interaction point of two carriers,which means one SM switches to ON-state and the other switches to OFF-state at the same instant.For those rare occasions,the total number of ON-state SMs does not change,and thus,the proposed method has less total switching number than the original methods.An
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Fig.8.Front and back views of the RT -LAB simulator-based HIL test
bench.
Fig.9.Schematic of the MMC ac–dc–ad system.
optional watchdog can be added as in Step 4in Fig.7,to force one switching if a no-switching period lasts too long,which only occurs in abnormal conditions such as a constant voltage reference.
The gating signals are sent from the controller to MMC devices through fiber optic or copper wires.Note that the sampling time in the I/O may not be same as the FPGA cycle.The I/O sampling time is in a few μs to tens of μs in industrial controllers.Having a much smaller FPGA cycle,e.g.,500ns,the same implementation of this method can be used for different I/O sampling times with minimum aliasing effect of two sampling time systems.Inside the FPGA,the synchronization requirement between the pulse generation part and the I/O driver becomes trivial.
IV .T EST B ENCH S ETUP AND S TUDY S YSTEM
A hardware-in-the-loop (HIL)test bench,based on the RT-LA
B real-time simulation platform,is set up to validate the proposed method (see Fig.8).The test system is a two-terminal MM
C HVDC system (see Fig.9).One MMC terminal is controlled by an external controller,whereas the other has an internal controller simulated in the same simulator.The system parameters of the external controller side are given in Table II.The SM capacitance is selected to store typically 1.5cycle of the energy for HVDC applications.
The external controller is simulated in a second independent real-time simulator.The MMC valve control,using the pro-posed pulse generation and VBC method,is implemented in a Virtex-7FPGA board with a cycle of 500ns.The MMC pole control,explained in [33],is implemented in the CPU with a sampling rate of 25μs.
TABLE II
S YSTEM P ARAMETER ON THE E XTERNAL C ONTROLLER S
IDE
The system measurements,including the ac-side voltages and currents,dc-link voltages,and valve currents,are sent from the plant to the controller through copper wires (the white cables in the back view).They have to be calibrated to minimize the error and noise introduced in the analog and digital conversion and in the cables.
The MMC measurements and commands are transferred through optical fibers.Each pair of fibers is used for one valve,and thus,six fibers are used for one station (the orange cables in the front view).For the controller,an outgoing message includes one valve current and 250capacitor voltages,and an incoming message includes 250MMC commands.No calibra-tion is required since all signals are transferred in digital format.The update rates of the outgoing and incoming messages can be individually adjusted during real-time simulation to study their impacts on the system performance.
V .C ASE S TUDY AND R ESULTS
A.Performances at System T ransient
Fig.10provides the MMC waveforms at the system transient when the reactive power references changes from 0.5to −0.5pu and the active power reference keeps 0.The control has a rate limiter;hence,the reference ramps to its final value in five cy-cles for a smooth transient.The frequency carrier is at 300Hz,i.e.,six times the system frequency.The MMC measurements and commands are updated every 20and 2μs,respectively.Note that the MMC terminal voltage,terminal current,and valve currents are highly sinusoidal and well controlled.Fig.10(e)gives the individual capacitor voltages of the first three SMs and the upper and lower boundaries of all capacitor voltages in one valve.All capacitor voltages are controlled in a very narrow band within the boundaries and,therefore,are well balanced.
In the plant simulator,the power grid is simulated in CPU with a time step of 25μs,and the MMC is simulated in the FPGA with at a time step of 500ns.Therefore,those system measurements in Fig.10(a)–(d)have a resolution of 25μs.Every 25μs,a group of 32capacitor voltages is sent from the FPGA to the CPU for data logging purposes only.Therefore,the voltages in Fig.10(e)have a resolution of 1.5ms and might not be simultaneously sampled.The upper and lower boundaries are calculated by the logged data and,thus,have a small error due to the consecutive logging manner.The actual difference between the boundaries should be smaller than the calculated value.
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Fig.10.Waveforms at a system transient.(a)MMC ac voltages,(b)ac currents,(c)ac-side active and reactive power,(d)valve currents,and (e)capacitor voltages of three SMs and the upper and lower boundaries of one valve.
B.Impact of Carrier Frequency and Signal Rate
The carrier frequency has a significant impact on the VBC performance.Fig.11gives the capacitor voltages and their boundaries when the carrier frequency is50Hz,the active and reactive power references are0and−0.5pu,respectively. The other parameters are the same as the previous test.The voltages vary in a larger band between the upper and lower boundaries compared with that in Fig.10.For the two carrier frequencies,the bandwidth,i.e.,the upper boundary minus the lower boundary,is given in Fig.12.The time-averaged values at different carrier frequencies are given in Table III.Note that increasing the carrier frequency will have a better balance on the capacitor voltage because each SM switches more
often.Fig.11.System waveforms as the carrier frequency is50Hz.(a)MMC valve currents.(b)Capacitor voltages of three SMs and the upper and lower boundaries of one
valve.
Fig.12.Width of capacitor voltage band when the carrier frequency is 50Hz(red)and300Hz(blue).
TABLE III
W IDTH OF V OLTAGE B AND AT D IFFERENT C ARRIER F
REQUENCIES
TABLE IV
A VERAGE W IDTH OF V OLTAGE
B AND AT D IFFERENT
S IGNAL C OMMUNICATION R
ATES
At a certain carrier frequency,e.g.,200Hz,it achieved a
good performance.Further increasing the carrier frequency will
improve the performance but slowly.
The effect of the MMC measurements and commands update
rates on the VBC performance is studied and summarized in
Table IV.The results are achieved when the carrier frequency
is200Hz,the active and reactive power references are0and −0.5pu,respectively.It is observed that the signal update rating between the MMC and its controller has little effect on the
performance.
C.Performances at Single SM Short-Circuit Fault Normally,the short circuit of a capacitor could cause per-manent damage of the device,and the faulty SM has to be by-passed.In this paper,the hypothetical temporary short circuit,
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Fig.13.Waveforms at single fault on SM 1.(a)MMC ac voltages,(b)ac currents,(c)valve currents,and (d)capacitor voltage of SM1,SM2,SM3,and voltage boundaries of one
valve.
Fig.14.Capacitor voltage of the fault SM at different power conditions.
where the device recovers after the fault is cleared,is used to examine the effectiveness of the proposed VBC method in an extreme condition where the capacitor voltage of some SM deviates far away from others.
The capacitor voltage in the fault SM is completely dis-charged to 0before the fault is cleared in 25μs.In all the following fault tests,the carrier frequency is 200Hz;the update rates of the MMC measurements and commands are 100and 20μs,respectively.Since this study is focused on voltage balancing within each valve,same faults are applied to all six valves to eliminate the effects from other control loops.
Fig.13shows the system response to a temporary fault at SM 1when the active and reactive power is 0.5pu and 0,re-spectively.The complete discharge of one SM has a negligible impact on the ac voltages,ac currents,and valve currents.The SM 1capacitor voltage,coincident with the lower boundary as
TABLE V
S INGLE F AULT R ECOVERY T IMES AT D IFFERENT P OWER C
ONDITIONS
Fig.15.Waveforms at simultaneous fault on SM1,SM2,and SM3.(a)MMC ac voltages,(b)ac currents,(c)valve currents,and (d)capacitor voltage of SM1,SM2,SM3,and the voltage boundaries of one valve.
in Fig.13(d),recovers fast after the fault.The recovery time,i.e.,the interval between the fault clearance and the instant that the width of the voltage band reduces to less than 5%,is 49.8ms,less than three cycles.
In each cycle,the valve current changes its direction twice.At recovery,the fault SM is switched on at the beginning of the charging half cycle to increase its capacitor voltage and is switched off at the beginning of the discharge half cycle to maintain it voltage.Depending on the fault point on the valve current waveform,the recovery time may vary for a half cycle,i.e.,10ms.
The capacitor voltage charging rate is determined by the valve current magnitude,which is proportional to the appar-ent power in the steady state.The capacitor voltages of the fault SM at different power conditions are given in Fig.14,and the recovery times are given in Table V.Generally speaking,the larger the apparent power is,the faster the fault SM recovers.
D.Performances at Multiply SM Short-Circuit Fault Multifault scenarios are studied where simultaneous short-circuit faults are applied to multiple SMs and cleared after 25μs.Fig.15shows the system response when the SM 1,2,。