大学计算机组织与结构习题

前二章作业1.计算机的四个基本功能（Functions）是什么？2.在计算机的top-level structure view中，四个structural components 是什么？3.谁提出了store-program concept ?你能用汉语简单地描述这个存储程序的概念吗？4.CPU的英文全称是什么？汉语意义是什么？5.ALU的英文全称是什么？汉语意义是什么？6.V on Neumann 的IAS机的五大部件都是什么？7.在第一章中我们认识到的四个结构性部件（第2题）与V on Neumann的IAS机（第6题）中部件有本质差别吗？8.Fundamental Computer Elements 有哪几个？它们与计算机的四个基本功能的关系是什么？9.Moore’s Law在中文翻译为什么？它描述了什么事物的一般规律？10.本书的次标题和第二章第二节标题均为“Designing forPerformance”,Performance 主要指什么？Performance Balance的（balance）平衡要平衡什么？11.本书作者将他要研究的范围局限在“desktop, workstation , server“中，它们的中文名称是什么？各自的工作范围是什么？Chapter 3Homework1.PC means _________.A. personal computerB. programming controllerC. program counterD. portable computer2. PC holds _______________ .A. address of next instructionB. next instructionC. address of operandD. operand3. At the end of fetch cycle, MAR holds _____.A. address of instructionB. instructionC. address of operandD. operand4. Interrupt process steps are __________.A. suspending , resuming , branching & processingB. branching , suspending , processing & resumingC. suspending , branching , processing & resumingD. processing , branching , resuming & suspending5. A unsigned binary number is n bits, so it is can represent a value in the range between _________ .A. 0 to n-1B. 1 to nC. 0 to 2n-1D. 1 to 2n6.The length of the address code is 32 bits, so addressing range (or the range of address) is ________________.A. 4GB.from –2G to 2GC.4G-1D. from 1 to 4G7.There are three kinds of BUSes. Which is not belong to them?A. address busB. system busC. data busD. control busQuestions1.Translate the following terms (Note: function)PC, MAR, MBR, IR, AC, bus, system bus, data bus , address bus , control bus , handler*, opcode, Bus arbitrate* , multiplexed bus* , interrupt, ISR, Instruction cycle , fetch cycle , execute cycle(带“*”为选做题)2.Page90 problems3.1What general categories of functions are specified by computer instruction?3. Describe simply the operations of PC and IR in an instruction cycle.4.Suppose the length of word is n-bit, describe simply operand(操作数) format and instruction format.5. Describe simply the procedure of the interruption6. Describe simply the types and functions of the BUS.一：选择题1.The computer memory system refers to _________A.RAMB.ROMC.Main memoryD.Register , main memory, cache, external memory2.If the word of memory is 16 bits, which the following answer is right ?A.The address width is 16 bitsB.The address width is related with 16 bitsC.The address width is not related with 16 bitsD.The address width is not less than 16 bits3.The characteristics of internal memory compared to external memoryA.Big capacity, high speed, low costB.Big capacity, low speed, high costC.small capacity, high speed, high costD.small capacity, high speed, low cost4．On address mapping of cache, any block of main memory can be mapped toany line of cache, it is ___________ .A) Associative Mapping B) Direct MappingC) Set Associative Mapping D) Random Mapping5. Cache’s write-through polity means write operation to main memory _______.A)as well as to cacheB)only when the cache is replacedC)when the difference between cache and main memory is foundD)only when direct mapping is used6.Cache’s write-back polity means write operation to main memory ______________.a)as well as to cacheb)only when the relative cache is replacedc)when the difference between cache and main memory is foundd)only when using direct mapping7. On address mapping of cache, the data in any block of main memory can be mapped to fixed line of cache, it is _________________.associative mapping B) direct mappingC)set associative mapping D) random mapping8.On address mapping of cache, the data in any block of main memory can be mapped to fixed set any line(way) of cache, it is _________________.associative mapping B) direct mappingD)set associative mapping D) random mapping二：计算题(from page 126)Problem 4.1 , Problem 4.3 , Problem 4.4 , Problem 4.5 , , Problem 4.7, Problem 4.10第五章作业1.which type of memory is volatile?A.ROMB. E2PROMC. RAMD. flash memory2.which type of memory has 6-transistor structure?A. DRAMB. SRAMC. ROMD. EPROMing hamming code, its purpose is of one-bit error.A. detecting and correctingB. detectingC. correctingD. none of all4.Flash memory is .A. read-only memoryB. read-mostly memoryC. read-write memoryD. volatile5.Which answer about internal memory is not true?A. RAM can be accessed at any time, but data would be lost when power down..B. When accessing RAM, access time is non-relation with storage location.C. In internal memory, data can’t be modified.D. Each addressable location has a unique address.Page161 Problems: 5.4 5.5 5.6 5.7 5.8第六章作业一、选择题1. RAID levels_________make use of an independent access technique.A. 2B. 3C. 4D. all2. In RAID 4, to calculate the new parity, involves _________reads.A. oneB. twoC. threeD.four3. During a read/write operation, the head is ___________A. movingB. stationaryC. rotatingD. above all4. On a movable head system, the time it takes to position the head at the track is know as______.A. seek timeB. rotational delayC. access timeD. transfer time5. RAID makes use of stored______information that enable the recovery of data lost due to a disk failure.A. parityB. user dataC. OSD. anyone6. Recording and retrieval via _________called a headA. conductive coilB. aluminiumC. glassD. Magnetic field7.In Winchester disk track format, _________is a unique identifier or address used to locate a particular sector.A. SYNCHB. GapC. ID fieldD. Data field8. Data are transferred to and from the disk in ________.A. trackB. sectorC. gapD. cylinder9. In _________, each logical strip is mapped to two separate physical disk.A. RAID 1B. RAID 2C. RAID 3D. RAID 410. With _________, the bits of an error correcting code are stored in the corresponding bit position on multiple parity disk.A. RAID 1B. RAID 2C. RAID 3D. RAID 411. The write-once read-many CD, known as ________.A. CD-ROMB. CD-RC. CD-R/WD. DVD二、How are data written onto a magnetic disk?三、In the context of RAID, what is the distinction between parallel access and independent access?Homework in Chapter 71.“When the CPU issues a command to the I/O module, it must wait until the I/Ooperation is complete”. It is programmed I/O , the word “wait”means ___________________.a. the CPU stops and does nothingb. the CPU does something elsec. the CPU periodically reads & checks the status of I/O moduled. the CPU wait the Interrupt Request Signal2.See Figure 7.7. To save (PSW & PC) and remainder onto stack, why theoperations of restore them is reversed? Because the operations of stack are ________________.a. first in first outb. randomc. last in first outd. sequenceding stack to save PC and remainder, the reason is ____________________ .a.some information needed for resuming the current program at the point ofinterruptb.when interrupt occurs, the instruction is not executed over, so the instructionat the point of interrupt must be executed once againc.the stack must get some information for LIFOd.the start address of ISR must transfer by stack4.The signals of interrupt request and acknowledgement exchange between CPUand requesting I/O module. The reason of CPU’s acknowledgement is ________________a.to let the I/O module remove request signalb. to let CPU get the vectorfrom data busc.both a & bd. other aims5.In DMA , the DMA module takes over the operations of data transferring fromCPU, it means _________________________a.the DMA module can fetch and execute instructions like CPU doesb.the DMA module can control the bus to transfer data to or from memoryusing stealing cycle techniquec.the DMA module and CPU work together(co-operate) to transfer data into orfrom memoryd.when DMA module get ready, it issues interrupt request signal to CPU forgetting interrupt service6.Transfer data with I/O modules, 3 types of techniques can be used. Which one isnot belong them?a. Interrupt-driven I/Ob. programmed I/Oc. direct I/O accessd. DMA7.Think 2 types of different data transferring, to input a word from keyboard and tooutput a data block of some sectors to harddisk. The best choice is to use ___________.a. interrupt-driven I/O and DMAb. DMA and programmed I/O C. both interrupt-driven I/Os d. both DMAsparing with interrupt-driven I/O, DMA further raises the usage rate of CPUoperations, because __________a. it isn’t necessary for CPU to save & restore sceneb. it isn’t necessary for CPU to intervene the dada transferc. it isn’t necessary for CPU to read & check status repeatedlyd. both a and b9.Simply script the all actions when using Interrupt-driven I/O technique totransferring data with I/O module.(please insert the “vector “at step3 & step5)10.See Figure 7.7 & 7.8. Redraw figure 7.8, and mark the sequence numberaccording to Figure 7.7, to indicate the sequence of the information flowing.11. According to DMA technique, write all information of CPU sending to DMA module, and write at which time the DMA module issues interrupt request signal to CPU and why the INTR is issued ?.Chapter9 homework1.Suppose bit long of two’s complement is 5 bits, which arithmetic operation brings OVERFLOW?A. 5+8B. (-8)+(-8)C. 4-(-12)D.15-72.Overflow occurs sometime in ______arithmetic operation.A. addB. subtractC. add and subtractD. multiply3. In twos complement, two positive integers are added, when does overflow occurs?A. There is a carryB. Sign bit is 1C. There is a carry, and sign bit is 0D. Can’t determine4. An 8-bit twos complement 1001 0011 is changed to a 16-bit that equal to____.A.1000 0000 1001 0011B. 0000 0000 1001 0011C.1111 1111 1001 0011D.1111 1111 0110 1101 115. An 8-bit twos complement 0001 0011 is changed to a 16-bit that equal to____.A. 1000 0000 1001 0011B. 0000 0000 0001 0011C. 1111 1111 0001 0011D. 1111 1111 1110 11016.Booth’s algorithm is used for Twos complement ______.A. additionB. subtractionC. multiplicationD. division7. In floating-point arithmetic, addition can divide to 4 steps: ______.A. load first operand, add second operand, check overflow and store resultB. compare exponent, shift significand, add significands and normalizeC. fetch instruction, indirectly address operand, execute instruction and interruptD. process scheduling states: create, get ready, is running and is blocked8. In floating-point arithmetic, multiplication can divide to 4 steps: ______.A. load first operand, add second operand, check overflow and store resultB. fetch instruction, indirectly address operand, execute instruction and interruptC. process scheduling states: create, get ready, is running and is blockedD. check for zero, add exponents, multiply significands, normalize, and round.9.The main functions of ALU are?A. LogicB. ArithmeticC. Logic and arithmeticD. Only addition10. Which is true?A. Subtraction can not be finished by adder and complement circuits in ALUB. Carry and overflow are not sameC.In twos complement, the negation of an integer can be formed with thefollowing rules: bitwise not (excluding the sign bit), and add 1.D. In twos complement, addition is normal binary addition, but monitor sign bit foroverflowPage326：9.4, 9.5 and 9.7(其中9.4选作)To prove: in twos complement, sign-extension rule (converting between different bit length) and negation rule ( (-X)补= X补+ 1).Chapter 10 and Chapter 111: In instruction, the number of addresses is 0, the operand(s)’address is implied, which is(are) in_______.A. accumulatorB. program counterC. top of stackD. any register2: Which the following addressing mode can achieve the target of branch in program?A.Direct addressing modeB.Register addressing modeC.Base-register addressing modeD.Relative addressing mode （有问题）3: In index-register addressing mode , the address of operand is equal toA.The content of base-register plus displacementB.The content of index-register plus displacementC.The content of program counter plus displacementD.The content of AC plus displacement4: The address of operand is in the instruction, it is_________ ?A.Direct addressing modeB.Register indirect addressing modeC.Stack addressing modeD.Displacement addressing mode5: Which the following is not the area that the source and result operands can be stored in ?A.Main or virtual memoryB.CPU registerC.I/O deviceD.Instruction6: Compared with indirect addressing mode , the advantage of register indirect addressing mode isrge address spaceB.Multiple memory referenceC.Limit address spaceD.Less memory access7:With base-register ADDRESSING , the ______________ register can be used.A. BASEB. INDEXC. PCD. ANY8:The disadvantage of INDIRECT ADDRESSING is ____________.A. large addressing rangeB. no memory accessC. more memory accessD. large value range9:Which is not an advantage with REGISTER INDIRECT?A. just one times of operand’s accessB. large memory spaceC. large value rangeD. no memory reference10:The REGISTER ADDRESSING is very fast, but it has _________________.A. very less value rangeB. very less address spaceC. more memory accessD. very complex address’ calculating11:The disadvantage of IMMEDIATE ADDRESSING is ___________.A. limited address rangeB. more memory accessC. limit value rangeD. less memory access12:In instruction, the number of addresses is 2, one address does double duty both _______________.A. a result and the address of next instructionB.an operand and a resultC.an operand and the address of next instructionD.two closed operands13.In instruction, the number of addresses is 3, which are _______________.A. two operands and one resultB. two operands and an address of next instructionC. one operand, one result and an address of next instructionD. two operands and an address of next instruction14.The address is known as a type of data, because it is represented by __________.A. a number of floating pointB. a signed integerC. an unsigned integerD. a number of hexadecimal15.Which is not a feature of Pentium .A. complex and flex addressingB. abundant instruction setC. simple format and fixed instruction lengthD. strong support to high language16. Which is not a feature of Power PC .A. less and simple addressing modeB. basic and simple instruction setC. variable instruction length and complex formatD. strong support to high languageChapter 12 and Chapter 181. After the information flow of fetch subcycle, the content of MBR is_____________.A.oprandB.address of instructionC. instructionD. address of operand2. After the information flow of instruction subcycle, the content of MBR is_____________.A.oprandB.address of instructionC. instructionD. address of operand3. The worse factor that limits the performance of instruction pipeline is _________________.A.conditional branch delaying the operation of target addressB. the stage number of pipeline c an’t exceed 6C. two’s complement arithmetic too complexD. general purpose registers too few4.The most factor to affect instruction pipeline effectiveness is __________.A. The number of stagesB. the number of instructionC. the conditional branch instructionD. the number of pipelines5. RISC rejects ______.A. few, simple addressing modesB. a limited and simple instruction setC. few, simple instruction formatsD. a few number of general purpose registers6. RISC rejects ______.A.a large number of general-purpose registersB. indirect addressingC. a single instruction sizeD. a small number of addressing mode7. Which is NOT a characteristic of RISC processor.A. a highly optimized pipeline.B. Register to registeroperationsC. a large number of general-purpose registersD. a complexed instructionformat8.Control unit use some input signals to produce control signals that open the gatesof information paths and let the micro-operations implement. Which is NOT the input signals of control unit/A.clock and flagsB.instruction registerC.interrupt request signalD.memory read or write9.Control unit use some output signals to cause some operations. Which is notincluded in the output signals?A.signals that cause data movementB.signals that a ctivate specific functions(e.g. add/sub/…)C.flagsD.read or write or acknowledgement10. Symmetric Multi-Processor (SMP) system is tightly coupled by _______.A. high-speed data-link and distributed memoryB. shared RAIDs and high-speed data-linkC. distributed caches and shared memoryD. interconnect network and distributed memory11. The SMP means __________.A.Sharing Memory ProcessesB.Split Memory to PartsD.Stack and Memory Pointer D.Symmetric Multi-Processo r12.The “MESI” means states of ____________ .A.Modified, Exclusive, Stored and InclusiveB.Modified, Expected, Shared and InterruptedC.Modified, Exclusive, Shared and InvalidD.Moved, Exchanged, Shared and Invalid13.The protocol “MESI” is also called __________.A. write back policyB. write-update protocolC. write-invalidate protocolD. write through policyChapter 121.Which register is user –visible but is not directly operated in 8086 ?A. DSB. SPC. IPD. BP2.The indirect sub-cycle is occurred _____________ ?A. before fetch sub-cycleB. after execute sub-cycleC. after interrupt sub-cycleD. after fetch sub-cycle and before execute sub-cycle3.Within indirect sub-cycle , the thing the CPU must do is ______________?A. fetch operand or store resultB. fetch operand’s address from memoryC. fetch next instruction from memoryD. nothing4.In general, which register is used for relative addressing ---- the content inthis register plus the A supplied by instruction to make a target address in branch or loop instructions.A. SPB. IRC. BRD. PC5.The Memory Address Register connects to ____________ BUS .A. systemB. addressC. dataD. control6.The Memory Buffer Register links to ________ BUS.A. systemB. addressC. dataD. control7.After Indirect cycle , there is a ______________ cycle .A. FetchB. IndirectC. ExecuteD. Interrupt8.The Interrupt cycle is __________ ______ Execute cycle .A. always afterB. never afterC. sometime afterD. maybe before9.The correct cycle sequence is _________________ .A. Fetch , Indirect , Execute and InterruptB. Fetch , Execute , Indirect and InterruptC. Fetch , Indirect , Interrupt and ExecuteD. Indirect , Fetch , Execute and Interrup10.The aim of the indirect cycle is to get __________________.A. an operandB. an instructionC. an address of an instructionD. an address of an operand11.Which is not in the ALU ?A. shifterB. adderC. complementerD. accumulator12.The registers in the CPU is divided _____registers and ________registers .A. general purpose , user-visibleB. user-visible , control and statusC. data , addressD. general purpose , control and status13.The Base register is a(n) __________ register in 8086.A. general purposeB. dataC. addressD. control14.The Instruction Pointer is a(n) __________ register in 8086.A. general purposeB. dataC. addressD. control15.The Index register is a(n) __________ register in 8086.A. general purposeB. dataC. addressD. control16.The Stack Pointer is a(n) __________ register in 8086.A. general purposeB. dataC. addressD. control17.The Accumulator is a(n) __________ register in 8086.A. general purposeB. dataC. addressD. control18.The Programming Status W ord is a(n) __________ register .A. general purposeB. dataC. addressD. controlShow all the micro-operations and control signals for the following instruction:1. ADD AX, X; —The contents of AC adds the contents of location X, result is stored to AC.2. MOV AX, [X];—Operand pointed by the content of location X is moved to AX, that means ((X))->AX—[ ] means indirect addressing.3. ADD AX, [BX];—Operand pointed by the content of Register BX is added to AX, that means (AX)+((BX))->AX—[ ] means register indirect addressing.4. JZ NEXT1; —If (ZF)=0,then jump to (PC)+ NEXT1.5. CALL X; —Call x function, save return address on the top of stack.6. RETURN; —From top of stack return to PC.。