外文翻译HDB3码

电子信息与电气工程学院学院
2014 届毕业设计外文阅读与翻译
毕业设计题目
基于FPGA的HDB3码编译码研究
外文翻译题目The introduction of VHDL
原文出处Song Pan , Guodong Wang . VHDL Application Course
专业电子信息与电气工程班级10信二
姓名马震学号10020217
指导教师肖闽进职称副教授
The introduction of VHDL
Field Programmable Gate Arrays (FPGA) are ASIC that can be configured by the user to perform specific functions. They combine the logic integration benefits of custom VLSI with the design, production, and time-to-market advantages of standard logic IC‟s. Unlike gate arrays, standard cells, and custom IC‟s, programmable logic devices do not require non-recurring costs or custom factory fabrication. This permits the designers to define the logic functions of the circuit and revise these functions as necessary at a low cost.
The latest wave of FPGA combines capabilities that until now were unique to gate arrays, and design benefits will now be found only in the programmable-array logic. These devices split broadly into two groups with different levels of granularity-that is, the size of their basic electronic structures varies. Some chips have large logic structures; the Logic Cell Array from Xilinx Inc., consists of 1/0blocks surrounding configurable logic blocks that include Flip-flops as well as combinational logic. Other chips resemble conventional gate arrays in their granularity; the Act 1 and Act 2 FPGA from Actel Corp., comprises a matrix of logic modules, with the rows separated by wiring channels. The Actel architecture is based on an anti-fuse technology where logic gates and their interconnections are programmed by shorting wire segments in prescribed locations. So, they are used repeatedly.
The most common FPGA architecture consists of an array of configurable logic blocks (CLB), I/O pads, and routing channels. Generally, all the routing channels have the same width (number of wires). Multiple I/O pads may fit into the height of one row or the width of one column in the array. An application circuit must be mapped into an FPGA with adequate resources. While the number of CLB and I/Os required is easily determined from the design, the number of routing tracks needed may vary considerably even among designs with the same amount of logic. (For example, a crossbar switch requires much more routing than a systolic array with the same gate count.) Since unused routing tracks increase the cost (and decrease the performance) of the part without providing any benefit, FPGA manufacturers try to provide just enough tracks so that most designs that will fit in terms of LUT and I/Os can be routed. This is determined by estimates such as those derived from Rent's rule or by experiments with existing designs.
Applications of FPGA include digital signal processing, software-defined radio, aerospace and defense systems, ASIC prototyping, medical imaging, computer vision, speech recognition, cryptography, bioinformatics, computer hardware emulation, radio astronomy and a growing range of other areas.
The use of Hardware Description Languages (HDL) has been steadily increasing as
digital designs become larger and more complex. Previously used methods such as schematic capture have not been as well suited to design re-use and rapid prototyping of large chip designs. Although not new, HDL has recently become popular with the widespread use of two similar but distinct languages. The older of these languages, VHDL (VHSIC Hardware Description language), is heavily used by U.S. defense agencies and large corporations, as well as a majority of European companies. The other major HDL currently in use is Verilog, which is more common among smaller companies and corporations with fewer ties to the military. While both languages are very powerful and can be used to obtain the same results, the VHDL syntax is more complex than Verilog.
VHDL is a description language for delineating digital electronic systems. It arose out of the United States government's Very High Speed Integrated Circuits (VHSIC) program. During this program, the need for a standard language for describing the structure and function of integrated circuits became clear. Hence, the VHSIC Hardware Description Language (VHDL) was developed.
VHDL subsequently was developed further under the auspices of the IEEE. It was adopted in the form of the IEEE Standard 1076 Standard VHDL Language Reference Manual in 1987. Like all IEEE standards, the VHDL standard is subject to review every five years. Comments and suggestions from users of the 1987 standard were analyzed by the IEEE working group responsible for VHDL. In 1992, a revised version of the standard was proposed. This was eventually adopted in 1993. The standard is due to be reviewed again this year. VHDL is now used worldwide as a tool for designing digital systems in many application areas.
VHDL is designed to fill a number of needs in the design flow. First, it allows a description of the system's structure. It describes how the system is decomposed into subsystems and how those subsystems are interconnected. Second, it allows the specification of the function of a system using familiar programming language forms. Third, as a result, it allows the design of a system to be simulated before being manufactured. Thus, designers can quickly compare alternatives and test for correctness without the delay and expense of hardware prototyping. Fourth, it allows the detailed structure of a design to be synthesized from a more abstract specification. This allows designers to concentrate more on strategic design decisions and reduces time to market.
A digital system consists of a number of modules wired together. Each module performs some function and communicates information with other modules via the interconnecting signals. An important concept for managing the complexity of a design is abstraction. Rather than trying to track all the inner details of each module, we focus just on
those aspects relevant to its use in the design. We call those aspects the interface of the module.
The structure of an entity defines how it is composed of instances of other entities. We can describe the structure in VHDL by writing an architecture body that contains entity instances instead of processes. The entities are placed in a working library (called work) along with behavioral architectures named basic. We can use them anytime.
As integrated circuit technology advances, the number of components we can put on a chip is steadily increasing. This allows us to design systems to perform increasingly complex functions. The main challenge confronting engineers today is managing the complexity in large designs. The key strategy is a defined, managed development process, often called design flow in the hardware design community.
A good design flow relies on modeling, simulation and synthesis to minimize risk and reduce development time. We first collect and analyze requirements to determine what the system should do. Next, we develop a system-level design of architecture to implement the required functions. The architecture consists of a small number of interacting blocks, each implementing part of the functionality. We use a hardware description language, such as VHDL, to model the system and simulate its operation to detect design defects.
We refine the system-level design to a detailed RTL design by developing implementations for each of the blocks. We do further simulation testing, including regression testing, to verify operation of the refined design. Next, we synthesize the final implementation from the RTL description. We do a final round of simulation to verify that the synthesized implementation is correct and meets performance goals. We may need to revise the RTL description and re-synthesize if goals are not met.
A design flow such as this reduces risk by catching design defects as early as possible. Correcting defects in the early stages is faster and significantly less costly. Risk is also reduced by allowing alternative designs to be compared early in the design flow. The alternative that best meets requirements with the lowest cost is then further developed. This design flow reduces time and cost compared to a flow using hardware prototyping and testing. Ultimately, this leads to cheaper, more reliable products.
Transmission of serial data over any distance, be it a twisted pair, fiber optic link, coaxial cable, etc., requires maintenance of the data as it is transmitted through repeaters, echo chancellors and other electronically equipment. The data integrity must be maintained through data reconstruction, with proper timing, and retransmitted. Line codes were created to facilitate this maintenance.
In selecting a particular line-coding scheme some considerations must be made, as not
all line codes adequately provide the all-important synchronization between transmitter and receiver. Other considerations for line code selection are noise interference levels, error detection and error checking, implementation requirements, and the available bandwidth.
The HDB3（High Density Bipolar of order 3 code）code is a bipolar signaling technique (i.e. relies on the transmission of both positive and negative pulses). It is based on Alternate Mark Inversion (AMI), but extends this by inserting violation codes whenever there is a run of 4 or more 0's. This and similar (more complex) codes have replaced AMI in modern distribution networks.
The encoding rules follow those for AMI, except that a sequence of four consecutive “0” are encoding using a special "violation" bit. This bit has the same polarity as the last 1-bit which was sent using the AMI encoding rule. The purpose of this is to prevent long runs of 0's in the data stream which may otherwise prevent a DPLL from tracking the centre of each bit. Such a code is sometimes called a "run length limited" code, since it limits the runs of 0's which would otherwise be produced by AMI.
By introducing violations, extra "edges" are introduced, enabling a DPLL to provide reliable reconstruction of the clock signal at the receiver. This encoding rule is said to make HDB3 transparent to the sequence of bits being transmitted (i.e. whatever data is sent, the DPLL will be able to reconstruct the data and extract the bits at the receiver).
One refinement is necessary, to prevent a dc voltage being introduced by excessive runs of zeros. This refinement is to encode any pattern of more than four bits as B00V, where B is a balancing pulse. The value of B is assigned as + or - , so as to make alternate "V"s of opposite polarity.
The receiver removes all Violation pulses, but in addition a violation preceded by two zeros and a pulse is treated as the "BOOV" pattern and both the viloation and balancing pulse are removed from the receieved bit stream. This restores the original bit stream.
硬件描述语言的介绍
现场可编程门阵列（FPGA）是用户可自行配置的实现某种特定功能的专用集成电路（ASIC）。

它们将定制超大规模集成电路（VLSI）的逻辑集成的好处与标准逻辑集成电路（IC）的设计、生产和上市时间的优势结合起来。

与门阵列、标准单元和定制集成电路不同，可编程逻辑器件不需要非经常性费用，也不需要向工厂定制制造。

这就允许设计师们以低廉的成本定义电路的逻辑功能和在必要时修改这些功能。

最新的FPGA结合了目前独特的门阵列和只在可编程逻辑阵列中才有的设计优势的能力。

这些器件按照粒度，即它们基本电子结构大小的不同程度大致分成两组。

一些芯片有很大的逻辑结构，比如来自Xilinx公司的逻辑单元阵列，就是由围绕着配置逻辑模块的1/0模块组成，其中包括触发器和组合逻辑。

其它在粒度上类似于常规门阵列的芯片，比如Actel公司的Act1和Act2 可编程门阵列，就是由一个逻辑单元矩阵和因布线渠道而分开的行组成的。

Actel公司产品的结构是基于反熔丝技术的，它的逻辑门和相互连接都可以通过缩短指定位置的线段进行编程。

因此，可以反复使用。

最常用的FPGA结构是由一系列的可配置逻辑块（CLB）、I/O端口和寻址线路组成。

一般所有的寻址线路具有相同的宽度。

多个I/O端口适用于一行高一列宽的阵列中。

一个专用电路必须与FPGA充足的资源相对应，虽然所要求的CLB和I/0的数量在设计时很容易决定，但是寻址线路的数量即便是在相同逻辑的设计中也会出现很大的变化。

（比如，一个交叉开关比起有相同门数的脉冲阵列就需要更多的寻址线路。

）由于未被使用的寻址线路会增加成本（和降低性能）而没有任何好处，所以FPGA制造商试图只提供刚够的线路以致于达到大多数符合LUT和I/Os的设计。

这是由比如Rent公司规则的评估或者现有设计的实践所决定的。

FPGA的运用包括数字信号处理、软件定义无线电、航空航天、防御系统、ASIC 建模、医疗成像、电脑视屏、语音识别、加密技术、生物信息学、计算机硬件仿真、无线电天文学和越来越多的其它领域。

作为越来越大、越来越复杂的数字设计，硬件描述语言（HDL）的使用正在稳步地增加。

以前的设计方法，比如示意图截取，已经不适合于设计的再利用和大型芯片设计的快速建模。

随着两种既相似又有区别的语言的广泛使用，HDL虽然不是什么新技术，目前还是非常流行。

这些语言中较早的一种，VHDL得到了美国国防部和一些大公司以及很多欧洲公司的大量使用。

目前使用的其它主要的HDL是Verilog，它在一些与军事机构有较少联系的小公司中更加普遍。

虽然这两种语言功能非常强大，也能得到同样的结果，但VHDL的语法比Verilog更加复杂。

VHDL是一种描述数字电子系统的描述性语言。

它产生于美国政府的甚高速集成电路（VHSIC）工程。

在这个工程中，对用一个标准语言来描述集成电路的结构和功能的需要变得越来越明显，因此，VHSIC硬件描述语言（VHDL）发展了起来。

随后，VHDL在IEEE的支持下有了很大的发展。

在1987年出版的1076标准VHDL语言参
考手册上，IEEE标准就采用了它的形式。

像所有的IEEE标准一样，VHDL标准每五年就审查一次。

负责VHDL的IEEE工作小组就分析了来自用户对1987版VHDL标准的评论和建议。

并在1992年，提出了一个修订后的VHDL标准版本，最终在1993年被采用。

预计这个标准又会在今年收到审查。

VHDL作为一种很多应用领域内的设计工具，现在已经得到了全球范围的使用。

VHDL填补了在设计流程中的很多需要。

首先它允许对系统的结构进行描述。

它描述了系统是如何分解成多个子系统的，也描述了这些子系统式如何连接的；第二，允许一个系统的专用功能使用熟悉的编程语言形式；第三，在投入生产之前，它可以对一个系统的设计进行模拟仿真，这样，在没有任何硬件原型的延时和花费之下，，设计者就可以很快的相互比较和测试其正确性；第四，它允许了一个设计的详细结构得到了一个更加抽象规范的合成，这样就允许了设计者们更加专注于策略性的设计决策，也减少了产品上市的时间。

一个数字系统是由很多用线连在一起的模块组成。

每一个模块实现一些功能，并通过内部联系信号与其它模块交流信息。

对一个设计的管理是一个重要的抽象概念。

我们关注的仅仅是在设计中与它相关的那些方面，而不是试图去掌握每一个模块的内部细节。

我们称那些方面为那些模块的接口。

一个实体的构造定义了它是如何由其它实体案例组成的，我们可以通过用VHDL 编写一个构造体来描述实体的构造，这个构造体包含了实体案例而不是进程。

这些实体与被称为基本构造体的行为构造体被存放在工作库里。

我们可以随时调用它们。

随着集成电路的发展，我们能够在芯片上使用的部件数量也在不断地增加，这样，我们就可以设计系统来实现越来越复杂的功能。

现在工程师面临的主要挑战是管理大型设计的复杂性。

这个关键的策略是定义的，管理的开发进程，在硬件设计领域通常被称为设计流程。

一个好的设计流程是基于建模、仿真和综合来使风险降到最小化，也减少了开发时间。

首先，我们搜集和分析需要来决定应该做什么样的系统。

然后，我们开发一个系统水平的构造体设计来执行所需要的功能。

这个构造体是由少量的相互作用的模块—-每一个功能的执行部分。

我们使用硬件描述语言，比如VHDL，来仿真系统和模拟操作以检测设计的缺陷。

我们通过开发每一个模块的功能来完善系统级的设计到详细的RTL设计。

我们做进一步的仿真测试，包括衰退检测来修正完善后的设计。

下一步，我们从RTL中合成最终的执行模块。

我们做了最后一轮仿真，以验证这个合成执行部分是正确的，符合实现目标的。

如果不能达到目标，我们也许还需要对RTL描述进行修订和重新合成。

像这种设计流程应尽早地通过捕获设计缺陷来降低风险，在设计的早期阶段纠正缺陷是比较快的，也能大大减少成本。

也可以通过在设计流程中对可选择的设计进行比较来降低风险。

用最低成本最好达到要求的设计然后进行更进一步的开发。

相对于硬
件建模和测试的设计流程，这种设计流程减少了时间和成本。

归根结底，这就产生了更便宜，更可靠的产品。

无论传输距离的长短，无论是用双绞线、光纤、同轴电缆对串行数据进行传输，因为数据是通过中继器、回波校验和其它电子设备传输，所要它都要求数据的连续性。

数据的完整性必须通过数据重建、合适的时钟提取来保持和转交。

线路码就是为了完成这个功能的。

在选择某一种特定线路码方案上，必须做一些考虑，因为不是所有的线路码都能在发射器和接收器之间完全提供所有重要的同步时钟。

选择线路码的其它考虑是噪音干扰水平、错误检测、执行要求和可用的带宽等等。

HDB3码(三阶高密度双极性码)是一种双极性信号技术，即依靠正负脉冲的传输。

它是基于极性反转码（AMI）的，但它也有改进，当有4个或4个以上的连“0”码时便插入一个破坏码。

在现代分区网络中，这种和其它相似（更复杂）的码型已经取代了AMI码。

HDB3码的编码规则采取了AMI码的编码规则，只是当出现四个连“0”码时，HDB3码编码时要使用一个特殊的破坏位。

这位与上一位用AMI编码规则编码的1码同极性。

这样的目的是为了抑制数据流中过长的连“0”串，否则过长的连“0”串会阻止数字锁相环（DPLL）去提取每一位脉冲。

这种码有时称为“连…0‟长度限制”码，因为它限制了在AMI码中产生的连“0”码长度。

通过引入破坏码，会产生一个额外的边沿信号，这样就使得数字锁相环在接收时提供一个可靠的时钟信号的恢复。

这种编码规则使HDB3码在传输一串数据位时的作用更加明显，即无论传送什么类型的数据，数字锁相环都能够在接收时恢复数据和提取数据位。

一种抑制因过长的连“0”串引起的直流信号的改进是非常必要的。

这种改进是为了对任何多余四位连“0”码的码型都编成B00V，这个B是一个平衡脉冲，B的值被指定为+和-，从而使相邻的V码之间保持相反的极性。

接收器撤消所有的破坏脉冲，但是除了撤消B00V模式中两个“0”码之后的破坏脉冲，也要从接收比特流中将平衡脉冲B撤消掉。

这样就还原了原始数据串。