example

您好！请您告知您所使用的参考源频率，如果以61.44MHz作为参考源的话，下面是与LO相关的设置，供您参考
//************************************************************
// Setup RF PLL non-frequency-dependent registers
//************************************************************
SPIWrite 261,00 // Set Rx LO Power mode
SPIWrite 2A1,00 // Set Tx LO Power mode
SPIWrite 248,0B // Enable Rx VCO LDO
SPIWrite 288,0B // Enable Tx VCO LDO
SPIWrite 246,02 // Set VCO Power down TCF bits
SPIWrite 286,02 // Set VCO Power down TCF bits
SPIWrite 249,8E // Set VCO cal length
SPIWrite 289,8E // Set VCO cal length
SPIWrite 23B,80 // Enable Rx VCO cal
SPIWrite 27B,80 // Enable Tx VCO cal
SPIWrite 243,0D // Set Rx prescaler bias
SPIWrite 283,0D // Set Tx prescaler bias
SPIWrite 23D,00 // Clear Half VCO cal clock setting
SPIWrite 27D,00 // Clear Half VCO cal clock setting
SPIWrite 015,0C // Set Dual Synth mode bit
SPIWrite 014,15 // Set Force ALERT State bit
SPIWrite 013,01 // Set ENSM FDD mode
WAIT 1 // waits 1 ms
SPIWrite 23D,04 // Start RX CP cal
WAIT_CALDONE RXCP,100 // Wait for CP cal to complete, Max RXCP Cal time: 2400.000 (us)(Done when 0x244[7]==1)
SPIWrite 27D,04 // Start TX CP cal
WAIT_CALDONE TXCP,100 // Wait for CP cal to complete, Max TXCP Cal time: 2400.000 (us)(Done when 0x284[7]==1)
SPIWrite 23D,00 // Disable RX CP Calibration since the CP Cal start bit is not self-clearing.? Only important if the script is run again without restting the DUT SPIWrite 27D,00 // Disable TX CP Calibration since the CP Cal start bit is not self-clearing.? Only important if the script is run again without restting the DUT //************************************************************
// FDD RX,TX Synth Frequency: 902.200000,902.200000 MHz
//************************************************************
//************************************************************
// Setup Rx Frequency-Dependent Syntheisizer Registers
//************************************************************
SPIWrite 23A,4A // Set VCO Output level[3:0]
SPIWrite 239,C1 // Set Init ALC Value[3:0] and VCO Varactor[3:0]
SPIWrite 242,17 // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
SPIWrite 238,78 // Set VCO Cal Offset[3:0]
SPIWrite 245,00 // Set VCO Cal Ref Tcf[2:0]
SPIWrite 251,0C // Set VCO Varactor Reference[3:0]
SPIWrite 250,70 // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0] SPIWrite 23B,94 // Set Synth Loop Filter charge pump current (Icp)
SPIWrite 23E,C3 // Set Synth Loop Filter C2 and C1
SPIWrite 23F,EF // Set Synth Loop Filter? R1 and C3
SPIWrite 240,0B // Set Synth Loop Filter R3
//************************************************************
// Setup Tx Frequency-Dependent Syntheisizer Registers
//************************************************************
SPIWrite 27A,4A // Set VCO Output level[3:0]
SPIWrite 279,C1 // Set Init ALC Value[3:0] and VCO Varactor[3:0]
SPIWrite 282,17 // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
SPIWrite 278,78 // Set VCO Cal Offset[3:0]
SPIWrite 285,00 // Set VCO Cal Ref Tcf[2:0]
SPIWrite 291,0C // Set VCO Varactor Reference[3:0]
SPIWrite 290,70 // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0] SPIWrite 27B,94 // Set Synth Loop Filter charge pump current (Icp)
SPIWrite 27E,C3 // Set Synth Loop Filter C2 and C1
SPIWrite 27F,EF // Set Synth Loop Filter? R1 and C3
SPIWrite 280,0B // Set Synth Loop Filter R3
//************************************************************
// Write Rx and Tx Frequency Words
//************************************************************
SPIWrite 233,9D // Write Rx Synth Fractional Freq Word[7:0]
SPIWrite 234,AA // Write Rx Synth Fractional Freq Word[15:8]
SPIWrite 235,72 // Write Rx Synth Fractional Freq Word[22:16]
SPIWrite 232,01 // Write Rx Synth Integer Freq Word[10:8]
SPIWrite 231,D5 // Write Rx Synth Integer Freq Word[7:0]
SPIWrite 005,22 // Set LO divider setting
SPIWrite 273,9D // Write Tx Synth Fractional Freq Word[7:0]
SPIWrite 274,AA // Write Tx Synth Fractional Freq Word[15:8]
SPIWrite 275,72 // Write Tx Synth Fractional Freq Word[22:16]
SPIWrite 272,01 // Write Tx Synth Integer Freq Word[10:8]
SPIWrite 271,D5 // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal) SPIWrite 005,22 // Set LO divider setting
SPIRead 247 // Check RX RF PLL lock status (0x247[1]==1 is locked)
SPIRead 287 // Check TX RF PLL lock status (0x287[1]==1 is locked)。