Quartus II基本设计流程

© 2008 Altera Corporation—Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 9
使用Quartus® II软件: 简介
© 2008 Altera Corporation—Confidential
目的
建立新的Quartus® II工程 通过不同的设计输入方法来建立设计文件 将设计编译至FPGA 找到得出的编译信息 建立设置和分配 管理I/O约束 配置（编程）FPGA
Quartus II开发系统
提供MegaWizard® Plug-In Manager & SOPC Builder设计 工具
TimeQuest时序分析工具 增量编译特性 PowerPlay功耗分析工具 支持32 & 64-bit Windows & Linux 支持Multi-processor处理
欢迎界面
Get
Turn on or off in Tools Options
© 2008 Altera Corporation—Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 10
使用Quartus® II软件
Altera及Altera产品介绍
© 2008 Altera Corporation—Confidential
PLD完整方案提供商
CPLDs
Low-cost FPGAs
High-density,
Low-cost Transceiver FPGAs
high-performance FPGAs
Quartus II软件 – 两个版本
Subscription Edition
Web Edition
Devices Supported Features
Distribution Price
All 100% Internet & DVD Paid
Selected Devices 95%
Internet & DVD Free (no license required)
© 2008 Altera Corporation—Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 2
可分离窗口
从Quartus II GUI框架中分离子窗口(Window menu Detach/Attach Window)
再次单击来 合并窗口
Click to detach window
© 2008 Altera Corporation—Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 13
新工程向导
File按钮
任务
工程名推荐用顶层文件名
顶层实体命名不需要和顶层 文件名相同
选择工作路径
基于一个存在的工程和设 置重新建立一个新工程
Tcl: project_new <project_name>
© 2008 Altera Corporation—Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 19
使用Quartus II软件
Quartus II开发系统特性概述
© 2008 Altera Corporation—Confidential
Quartus II开发系统
全集成设计工具
多种设计输入方法 逻辑综合 布局布线 仿真 时序和功耗分析 器件编程
© 2008 Altera Corporation—Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 8
ASICs
Embedded soft processors
Intellectual Property (IP)
Design software
Development kits
© 2008 Altera Corporation—Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 5
Quartus II工作环境
工程向导
工具窗口
状态窗口
消息窗口
© 2008 Altera Corporation—Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 11
name are not the same • Absolute & relative paths are supported
增加用户库路径
• User libraries (any directory containing files)
• MegaCore®/AMPPSM libraries • Pre-compiled VHDL packages
Tcl: set_global_assignment –name VHDL_FILE* <filename.vhd> Tcl: set_global_assignment –name USER_LIBRARIES <library_path_name> * Replace with VERILOG_FILE, EDIF_FILE, AHDL_FILE or BDF_FILE
主工具条
文件控制按钮
动态菜单 引脚规划器
芯片规划器
执行控制
编译报告
TimeQuest时序分 析工具
复位视图: 1. Tools Customize Toolbars Reset All 2. 重新启动Quartus II
© 2008 Altera Corporation—Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 12
© 2008 Altera Corporation—Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 20
课程议程
Altera器件介绍 Quartus II软件特征概
要
设计方法 工程
设计输入
编译 设置和分配 I/O管理 编程/配置
© 2008 Altera Corporation—Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 3
使用Quartus II软件
Quartus II工程
© 2008 Altera Corporation—Confidential
Quartus II工程
说明
收集相关的设计文件和库 必须有指定的顶层实体 针对单个器件 在Quartus II设置文件(.QSF)中存储设置 编译的网表信息会存储在db文件夹
© 2008 Altera Corporation—Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 16
- 验证逻辑模型和数据流程 (没有时序延迟)
综合 (映射)
- 将设计转换为器件特定基元 - 进行优化，满足面积和性能和功耗约束要求 - Quartus II Synthesis, Precision Synthesis, Synplify/Synplify Pro,
Design Compiler FPGA
典型的PLD设计流程
tclk
时序分析(TimeQuest Timing Analyzer)
- 验证是否达到性能规范
- 静态时序分析
门级仿真
- 时序仿真 - 验证设计能否在目标器件中工作
PCB板仿真和测试
- 仿真电路板设计 - 板上器件编程和测试 - 使用SignalTap II 或者其他片内工具
来进行调试
利用新工程向导建立新工程
也可以由Tcl脚本建立
© 2008 Altera Corporation—Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 18
布局布线 (适配)
- 参考面积和性能约束，将基元映射至目标器件的 特定位置。
- 指定要使用的布局资源
© 2008 Altera Corporation—Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 15
Feature Comparison available on Altera web site
© 2008 Altera Corporation—Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 6
增加文件
增加设计文件
• Graphic (.BDF) • VHDL • Verilog • EDIF • VQM
Notes: • Files in project directory do not need to
be added • Add top-level file if filename & entity
选择器件
选择器件家族和 用筛选选项快速
定位器件 新器件的预先支持
选择特定的型号
Tcl: set_global_assignment –name FAMILY “device family name” Tcl: set_global_assignment –name DEVICE <part_number>
使用Quartus II软件
设计方法
© 2008 Altera Corporation—Confidential
典型的PLD设计流程
设计规范
设计输入/RTL 编码
- 设计行为或者结构化描述
LE M512
M4K
I/O
RTL 仿真
- 功能仿真 (ModelSim® or Quartus II simulators)