Power optimization issues in dual voltage design

td = K CV VddV )2 (2) ( dd ? T where C is the loading capacitance, VT the threshold voltage, and K a constant. If Vdd is much greater than VT , then the delay is almost inversely proportional to supply voltage. For supply voltage near the threshold voltage, however, the VT term causes the delay to increase rapidly. In order to reduce the voltage and, hence, power dissipation without performance degradation, some timing slacks are required in the circuit so that the increased gate delays do not diminish the desired throughput. The slack time of gate v is
2 Pavg = 0:5Vdd f C (v )E (v ) (1) where f is the clock frequency, Vdd the supply voltage, C(v) the loading capacitance of gate v, and E(v) is the switching activity at the output of gate v. Since the dynamic power consumption is quadratically related to supply voltage, reducing supply voltage (or voltage-scaling) promises to be most e ective for power saving. The basic problem with such an approach is the increased circuit delay, since the relation between delay (td) and supply voltage (Vdd ) is given by 1]
1. INTRODUCTION
de ned to be s(v)=r(v) - a(v) 13], where r(v) and a(v) are the required time and arrival time of gate v, respectively. Most of prior work on voltage scaling have focused on behavioral and/or logic levels 5, 6, 7, 8, 9]. Due to the very limited accuracy with power and delay modeling at these levels, it is di cult, if not impossible, to predict exactly whether the power reduction in these levels does result in the nal power saving. For instance, important parameters (such as wiring capacitance) in power calculation cannot be taken into account at logic level. Thus, some kind of feedback between logic and physical levels is required in order to know its exact e ect on physical level. While voltagescaling approach has been shown to be e ective at these higher levels, little work was done to physically place the gates with di erent supply voltages so that power dissipation can be minimized. In 10], Yeh proposed some new layout structures where voltage-scaling at logic level put additional constraints on the subsequent layout stage, and the nal placement had to conform to some speci ed ordering of high voltage and low voltage cells. In this paper, we will address power optimization issues with dual supply voltages. In the logic level, we use the framework of SIS 12] to implement dual voltage design 9], which gives an estimate of gate power reduction associated with dual voltage technique. In the physical level, we use simulated annealing with additional constraints for placement followed by some post processing with an ultimate goal of reducing power. This paper is organized as follows. In Section 2, we review existing techniques with voltage-scaling for low power and describe our design ow. Section 3 describes the MWIS algorithm for maximizing power reduction at the logic level. Section 4 discusses algorithmic aspects of logic and physical level design with dual supply voltages, with emphasis on how to optimize power dissipation during the placement stage. We report experimental results in Section 5, and conclude the paper in Section 6. Many researchers have addressed power reduction techniques using variable voltage or multiple supply voltages 4, 5, 6, 7]. In 6], for example, an optimal scheduling algorithm is proposed to reduce the system's power while meeting the timing constraints, while 7] uses a dynamic programming technique to minimize the average energy consumption. In these works, the authors basically focused on the scheduling techniques for low power at the behavioral level. In particular, the dual voltage approach tries to apply a higher voltage (Vhigh ) on critical paths of the circuit, while
POWER OPTIMIZATION ISSUES IN DUAL VOLTAGE DESIGN
Anshuman Nayak Prithviraj Banerjee Chunhong Chen fnayak,banerjee,chen,majidg@ Department of Electrical and Computer Engineering Northwestern University, Evanston, IL 60208 Majid Sarrafzadeh
ABSTRACT In this paper, we look at power optimization issues under dual supply voltage environment, with the goal of optimizing power consumption due to interconnection and gate capacitances. Logic level synthesis is used as a good starting point for power reduction, while subsequent placement stage modi es or veri es logic level design by providing more accurate estimate of power dissipation. We try to reduce power dissipation due to gate capacitance at logic level using two supply voltages. This however imposes a constraint on the placement stage as the nal placement has to conform to the speci c layout structure. We discuss how both levels interact with one another, and propose an e ective algorithm to nd the tradeo between power reduction and placement legality. Experimental results show that, on an average, a nal power reduction of nearly 16% is obtained by our approach. Advances in semiconductor technologies have led to chips with million transistors. Power dissipation becomes a critical parameter in portable computing and communication systems as well as desktop computers. A lot of research has been done for power reduction at various design levels of abstraction (such as system, architectural, logic and layout levels) 2]. The average dynamic power consumed by a CMOS circuit is given by 1]