74VCX16373MTD中文资料
sn74lvth16373—锁存器
FEATURESSN54LVTH16373...WD PACKAGESN74LVTH16373... DGG OR DL PACKAGE(TOP VIEW)CCCC DESCRIPTION/ORDERING INFORMATIONSN54LVTH16373,SN74LVTH163733.3-V ABT16-BIT TRANSPARENT D-TYPE LATCHESWITH3-STATE OUTPUTSSCBS144P–MAY1992–REVISED NOVEMBER2006•Members of the Texas Instruments Widebus™Family•State-of-the-Art Advanced BiCMOSTechnology(ABT)Design for3.3-V Operationand Low Static-Power Dissipation•Support Mixed-Mode Signal Operation(5-VInput and Output Voltages With3.3-V V CC)•Support Unregulated Battery Operation Downto2.7V•Typical V OLP(Output Ground Bounce)<0.8Vat V CC=3.3V,T A=25°C•I off and Power-Up3-State Support HotInsertion•Bus Hold on Data Inputs Eliminates the Needfor External Pullup/Pulldown Resistors•Distributed V CC and GND Pins MinimizeHigh-Speed Switching Noise•Flow-Through Architecture Optimizes PCBLayout•Latch-Up Performance Exceeds500mA PerJESD17•ESD Protection Exceeds JESD22–2000-V Human-Body Model(A114-A)–200-V Machine Model(A115-A)The'LVTH16373devices are16-bit transparent D-type latches with3-state outputs designed for low-voltage (3.3-V)V CC operation,but with the capability to provide a TTL interface to a5-V system environment.These devices are particularly suitable for implementing buffer registers,I/O ports,bidirectional bus drivers,and working registers.ORDERING INFORMATIONT A PACKAGE(1)ORDERABLE PART NUMBER TOP-SIDE MARKINGFBGA–GRD SN74LVTH16373GRDRReel of1000LL373FBGA–ZRD(Pb-free)SN74LVTH16373ZRDRTube of25SN74LVTH16373DLSN74LVTH16373DLG4SSOP–DL LVTH16373–40°C to85°C Reel of1000SN74LVTH16373DLRSN74LVTH16373DLRG4TSSOP–DGG Reel of2000SN74LVTH16373DGGR LVTH16373VFBGA–GQL SN74LVTH16373GQLRReel of1000LL373VFBGA–ZQL(Pb-free)SN74LVTH16373ZQLR(1)Package drawings,standard packing quantities,thermal data,symbolization,and PCB design guidelines are available at/sc/package.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Widebus is a trademark of Texas Instruments.PRODUCTION DATA information is current as of publication date.Copyright©1992–2006,Texas Instruments Incorporated Products conform to specifications per the terms of the Texas On products compliant to MIL-PRF-38535,all parameters are Instruments standard warranty.Production processing does not tested unless otherwise noted.On all other products,production necessarily include testing of all parameters.processing does not necessarily include testing of all parameters.DESCRIPTION/ORDERING INFORMATION (CONTINUED)GQL OR ZQL PACKAGE(TOP VIEW)J H G F E D C B A 213465KSN54LVTH16373,SN74LVTH163733.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTSSCBS144P–MAY 1992–REVISED NOVEMBER 2006ORDERING INFORMATION (continued)T APACKAGE (1)ORDERABLE PART NUMBER TOP-SIDE MARKING TubeSNJ54LVTH16373WD –55°C to 125°CCFP –WDSNJ54LVTH16373WD5962-9681001QXAThese devices can be used as two 8-bit latches or one 16-bit latch.When the latch-enable (LE)input is high,the Q outputs follow the data (D)inputs.When LE is taken low,the Q outputs are latched at the levels set up at the D inputs.A buffered output-enable (OE)input can be used to place the eight outputs in either a normal logic state (high or low logic levels)or a high-impedance state.In the high-impedance state,the outputs neither load nor drive the bus lines significantly.The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.OE does not affect internal operations of the latch.Old data can be retained or new data can be entered while the outputs are in the high-impedance state.Active bus-hold circuitry holds unused or undriven inputs at a valid logic e of pullup or pulldown resistors with the bus-hold circuitry is not recommended.When V CC is between 0and 1.5V,the devices are in the high-impedance state during power up or power down.However,to ensure the high-impedance state above 1.5V,OE should be tied to V CC through a pullup resistor;the minimum value of the resistor is determined by the current-sinking capability of the driver.These devices are fully specified for hot-insertion applications using I off and power-up 3-state.The I off circuitry disables the outputs,preventing damaging current backflow through the devices when they are powered down.The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,which prevents driver conflict.TERMINAL ASSIGNMENTS (1)(56-Ball GQL/ZQL Package)123456A 1OE NC NC NC NC 1CLK B 1Q21Q1GND GND 1D11D2C 1Q41Q3V CC V CC 1D31D4D 1Q61Q5GNDGND1D51D6E 1Q81Q71D71D8F 2Q12Q22D22D1G 2Q32Q4GND GND 2D42D3H 2Q52Q6V CC V CC 2D62D5J 2Q72Q8GND GND 2D82D7K 2OENCNCNCNC2CLK(1)NC –No internal connection2Submit Documentation FeedbackGRD OR ZRD PACKAGE(TOP VIEW)JH G F E D C B A 2134651OE 1LE1D1To Seven Other Channels1Q12OE 2LE2D12Q1To Seven Other ChannelsPin numbers shown are for the DGG, DL, and WD packages.SN54LVTH16373,SN74LVTH163733.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSSCBS144P–MAY 1992–REVISED NOVEMBER 2006TERMINAL ASSIGNMENTS (1)(54-Ball GRD/ZRD Package)123456A 1Q1NC 1OE 1LE NC 1D1B 1Q31Q2NC NC 1D21D3C 1Q51Q4V CC V CC 1D41D5D 1Q71Q6GND GND 1D61D7E 2Q11Q8GND GND 1D82D1F 2Q32Q2GND GND 2D22D3G 2Q52Q4V CC V CC 2D42D5H 2Q72Q6NC NC 2D62D7J2Q8NC2OE2LENC2D8(1)NC –No internal connectionFUNCTION TABLE (8-BIT SECTION)INPUTSOUTPUTQOE CLK D L H H H L H L L L L X Q 0HXXZLOGIC DIAGRAM (POSITIVE LOGIC)3Submit Documentation FeedbackAbsolute Maximum Ratings (1)Recommended Operating Conditions (1)SN54LVTH16373,SN74LVTH163733.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTSSCBS144P–MAY 1992–REVISED NOVEMBER 2006over operating free-air temperature range (unless otherwise noted)MINMAX UNIT V CC Supply voltage range –0.5 4.6V V I Input voltage range (2)–0.57V V O Voltage range applied to any output in the high-impedance or power-off state (2)–0.57V V O Voltage range applied to any output in the high state (2)–0.5V CC +0.5V SN54LVTH1637396I O Current into any output in the low state mA SN74LVTH16373128SN54LVTH1637348I O Current into any output in the high state (3)mA SN74LVTH1637364I IK Input clamp current V I <0–50mA I OKOutput clamp currentV O <0–50mADGG package70DL package 63θJAPackage thermal impedance (4)°C GQL/ZQL package 42GRD/ZRD package36T stg Storage temperature range–65150°C (1)Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.(3)This current flows only when the output is in the high state and V O >V CC .(4)The package thermal impedance is calculated in accordance with JESD 51-7.SN54LVTH16373SN74LVTH16373UNIT MINMAX MIN MAX V CC Supply voltage 2.7 3.62.73.6V V IH High-level input voltage 22V V IL Low-level input voltage 0.80.8V V I Input voltage5.5 5.5V I OH High-level output current –24–32mA I OL Low-level output current 4864mA ∆t/∆v Input transition rise or fall rate Outpts enabled1010ns/V ∆t/∆V CC Power-up ramp rate200200µs/V T A Operating free-air temperature–55125–4085°C(1)All unused control inputs of the device must be held at V CC or GND to ensure proper device operation.Refer to the TI application report,Implications of Slow or Floating CMOS Inputs ,literature number SCBA004.4Submit Documentation FeedbackElectrical CharacteristicsSN54LVTH16373,SN74LVTH16373 3.3-V ABT16-BIT TRANSPARENT D-TYPE LATCHESWITH3-STATE OUTPUTSSCBS144P–MAY1992–REVISED NOVEMBER2006over recommended operating free-air temperature range(unless otherwise noted)SN54LVTH16373SN74LVTH16373 PARAMETER TEST CONDITIONS UNITMIN TYP(1)MAX MIN TYP(1)MAXV IK V CC=2.7V,I I=–18mA–1.2–1.2V V CC=2.7V to3.6V,I OH=–100µA V CC–0.2V CC–0.2V CC=2.7V,I OH=–8mA 2.4 2.4V OH VI OH=–24mA2V CC=3VI OH=–32mA2I OL=100µA0.20.2V CC=2.7VI OL=24mA0.50.5I OL=16mA0.40.4V OL VI OL=32mA0.50.5V CC=3VI OL=48mA0.55I OL=64mA0.55V CC=0or3.6V,V I=5.5V1010ControlV CC=3.6V,V I=V CC or GND±1±1 inputsI IµAV I=V CC11 DataV CC=3.6Vinputs VI=0–5–5I off V CC=0,V I or V O=0to4.5V±100µAV I=0.8V7575V CC=3VDataI I(hold)V I=2V–75–75µAinputsV CC=3.6V,(2)V I=0to3.6V±500I OZH V CC=3.6V,V O=3V55µAI OZL V CC=3.6V,V O=0.5V–5–5µAV CC=0to1.5V,V O=0.5V to3V,I OZPU±100(3)±100µAOE=don't careV CC=1.5V to0,V O=0.5V to3V,I OZPD±100(3)±100µAOE=don't careOutputs high0.190.19 V CC=3.6V,I CC I O=0,Outputs low55mAV I=V CC or GND Outputs disabled0.190.19V CC=3V to3.6V,One input at V CC–0.6V,∆I CC(4)0.20.2mA Other inputs at V CC or GNDC i V I=3V or033pFC o V O=3V or099pF(1)All typical values are at V CC=3.3V,T A=25°C.(2)This is the bus-hold maximum dynamic current.It is the minimum overdrive current required to switch the input from one state toanother.(3)On products compliant to MIL-PRF-38535,this parameter is not production tested.(4)This is the increase in supply current for each input that is at the specified TTL voltage level,rather than V CC or GND.5Submit Documentation FeedbackTiming RequirementsSwitching CharacteristicsSN54LVTH16373,SN74LVTH163733.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTSSCBS144P–MAY 1992–REVISED NOVEMBER 2006over recommended operating free-air temperature range (unless otherwise noted)(see Figure 1SN54LVTH16373SN74LVTH16373V CC =3.3V V CC =3.3V V CC =2.7V V CC =2.7V UNIT±0.3V ±0.3V MIN MAXMIN MAXMIN MAXMIN MAXt w Pulse duration,LE high 3333ns t su Setup time,data before LE ↓2210.6ns t hHold time,data after LE ↓33.311.1ns over recommended operating free-air temperature range,C L =50pF (unless otherwise noted)(see Figure 1)SN54LVTH16373SN74LVTH16373FROM TO V CC =3.3V V CC =3.3V PARAMETERV CC =2.7V V CC =2.7V UNIT(INPUT)(OUTPUT)±0.3V ±0.3V MIN MAXMINMAX MIN TYP (1)MAX MINMAX t PLH 1.4 4.5 5.2 1.5 2.7 3.8 4.2D Q ns t PHL 1.4 4.4 4.8 1.5 2.5 3.64t PLH 1.8 5.5 5.8 2.13 4.3 4.8LE Q ns t PHL 1.8 5.2 5.6 2.1 2.944t PZH 1.4 5.7 6.7 1.5 2.8 4.3 5.1OE Q ns t PZL 1.4 5.56 1.5 2.8 4.3 4.7t PHZ 26 6.2 2.4 3.55 5.4OEQns t PLZ 1.45.25.623.24.7 4.8t sk(LH)0.5ns t sk(HL)0.5(1)All typical values are at V CC =3.3V,T A =25°C.6Submit Documentation FeedbackPARAMETER MEASUREMENT INFORMATIONFrom Output Under TestC LLOAD CIRCUITOpen Data Input Timing Input2.7 V0 V2.7 V0 V2.7 V0 VInputVOLTAGE WAVEFORMS SETUP AND HOLD TIMESVOLTAGE WAVEFORMS PROPAGATION DELAY TIMESINVERTING AND NONINVERTING OUTPUTSVOLTAGE WAVEFORMSPULSE DURATIONV OHV OHV OLV OL2.7 V0 V InputOutput Control Output Waveform 1S1 at 6 V (see Note B)Output Waveform 2S1 at GND (see Note B)V OLV OH 3 V0 V≈0 V2.7 VVOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLINGOutputOutputt PLH /t PHL t PLZ /t PZL t PHZ /t PZHOpen 6 V GNDTEST S1NOTES: A.C L includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 Ω, t r ≤ 2.5 ns, t f ≤ 2.5 ns.D.The outputs are measured one at a time, with one transition per measurement.SN54LVTH16373,SN74LVTH163733.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSSCBS144P–MAY 1992–REVISED NOVEMBER 2006Figure 1.Load Circuit and Voltage Waveforms7Submit Documentation FeedbackPACKAGING INFORMATIONOrderable Device Status (1)Package Type PackageDrawing Pins Package Qty Eco Plan (2)Lead/Ball FinishMSL Peak Temp (3)Samples(Requires Login)5962-9681001QXA ACTIVE CFP WD481TBD Call TI Call TI74LVTH16373DGGRG4ACTIVE TSSOP DGG482000Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIM74LVTH16373DLRG4ACTIVE SSOP DL481000Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LVTH16373DGGR ACTIVE TSSOP DGG482000Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LVTH16373DL ACTIVE SSOP DL4825Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LVTH16373DLG4ACTIVE SSOP DL4825Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LVTH16373DLR ACTIVE SSOP DL481000Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LVTH16373GQLR NRND BGAMICROSTARJUNIORGQL561000TBD SNPB Level-1-240C-UNLIMSN74LVTH16373GRDR ACTIVE BGAMICROSTARJUNIORGRD541000TBD SNPB Level-1-240C-UNLIMSN74LVTH16373ZQLR ACTIVE BGAMICROSTARJUNIOR ZQL561000Green (RoHS& no Sb/Br)SNAGCU Level-1-260C-UNLIMSN74LVTH16373ZRDR ACTIVE BGAMICROSTARJUNIOR ZRD541000Green (RoHS& no Sb/Br)SNAGCU Level-1-260C-UNLIMSNJ54LVTH16373WD ACTIVE CFP WD481TBD A42N / A for Pkg Type(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.Addendum-Page 1(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check /productcontent for the latest availability information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.OTHER QUALIFIED VERSIONS OF SN54LVTH16373, SN74LVTH16373 :•Catalog: SN74LVTH16373•Enhanced Product: SN74LVTH16373-EP, SN74LVTH16373-EP•Military: SN54LVTH16373NOTE: Qualified Version Definitions:•Catalog - TI's standard catalog product•Enhanced Product - Supports Defense, Aerospace and Medical Applications•Military - QML certified for Military and Defense ApplicationsAddendum-Page 2TAPE AND REELINFORMATION*All dimensionsare nominalDevicePackage Type Package Drawing Pins SPQReel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant SN74LVTH16373DGGR TSSOP DGG 482000330.024.48.615.8 1.812.024.0Q1SN74LVTH16373DLR SSOP DL 481000330.032.411.3516.2 3.116.032.0Q1SN74LVTH16373GQLRBGA MI CROSTA R JUNI OR GQL561000330.016.44.87.31.458.016.0Q1SN74LVTH16373GRDR BGA MI CROSTA R JUNI OR GRD 541000330.016.4 5.88.3 1.558.016.0Q1SN74LVTH16373ZQLR BGA MI CROSTA R JUNI OR ZQL 561000330.016.4 4.87.3 1.458.016.0Q1SN74LVTH16373ZRDR BGA MI CROSTA R JUNI ORZRD 541000330.016.4 5.88.3 1.558.016.0Q1PACKAGE MATERIALS INFORMATION23-Jul-2011Pack Materials-Page 1*Alldimensions are nominal DevicePackage Type Package Drawing Pins SPQ Length (mm)Width (mm)Height (mm)SN74LVTH16373DGGRTSSOP DGG 482000346.0346.041.0SN74LVTH16373DLRSSOP DL 481000346.0346.049.0SN74LVTH16373GQLRBGA MICROSTAR JUNIOR GQL 561000333.2345.928.6SN74LVTH16373GRDRBGA MICROSTAR JUNIOR GRD 541000333.2345.928.6SN74LVTH16373ZQLRBGA MICROSTAR JUNIOR ZQL 561000333.2345.928.6SN74LVTH16373ZRDR BGA MICROSTARJUNIOR ZRD 541000333.2345.928.6PACKAGE MATERIALS INFORMATION 23-Jul-2011Pack Materials-Page 2IMPORTANT NOTICETexas Instruments Incorporated and its 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74LVT16373MTD资料
© 2005 Fairchild Semiconductor Corporation DS012021January 1999Revised June 200574LVT16373 • 74LVTH16373 Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs74LVT16373 • 74LVTH16373Low Voltage 16-Bit Transparent Latch with 3-STATE OutputsGeneral DescriptionThe LVT16373 and LVTH16373 contain sixteen non-invert-ing latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state.The LVTH16373 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.These latches are designed for low-voltage (3.3V) V CC applications, but with the capability to provide a TTL inter-face to a 5V environment. The LVT16373 and LVTH16373are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation.Featuress Input and output interface capability to systems at 5V V CC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH16373),also available without bushold feature (74LVT16373)s Live insertion/extraction permitteds Power Up/Power Down high impedance provides glitch-free bus loading s Outputs source/sink 32 mA/ 64 mAs Functionally compatible with the 74 series 16373s Latch-up performance exceeds 500 mA s ESD performance:Human-body model ! 2000V Machine model ! 200V Charged-device model ! 1000Vs Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary)Ordering Code:Note 1: BGA package available in Tape and Reel only.Note 2: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.Logic SymbolOrder Number Package Number Package Description74LVT16373GX (Note 1)BGA54A (Preliminary)54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL]74LVT16373MEA (Note 2)MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVT16373MTD (Note 2)MTD4848-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 74LVTH16373GX (Note 1)BGA54A (Preliminary)54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL]74LVTH16373MEA (Note 2)MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVTH16373MTD (Note 2)MTD4848-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 274L V T 16373 • 74L V T H 16373Connection DiagramsPin Assignment for SSOP and TSSOPPin Assignment for FBGA(Top Thru View)Pin DescriptionsFBGA Pin Assignments Truth TablesH HIGH Voltage LevelL LOW Voltage Level X ImmaterialZ HIGH ImpedanceO o Previous output prior to HIGH-to-LOW transition of LEPin Names DescriptionOE nOutput Enable Input (Active LOW)LE nLatch Enable Input I 0–I 15 Inputs O 0–O 15 3-STATE Outputs NC No Connect123456A O 0NC OE 1LE 1NC I 0BO 2O 1NCNC I 1I 2C O 4O 3V CC V CC I 3I 4D O 6O 5GND GND I 5I 6E O 8O 7GND GND I 7I 8F O 10O 9GND GND I 9I 10G O 12O 11V CC V CC I 11I 12H O 14O 13NC NC I 13I 14JO 15NCOE 2LE 2NCI 15InputsOutputs LE 1OE 1 I 0–I 7 O 0–O 7X H X ZH LL L H L H H LL XO o InputsOutputs LE 2OE 2 I 8–I 15 O 8–O 15X H XZ H L L L HL H H LLXO o74LVT16373 • 74LVTH16373Functional DescriptionThe LVT16373 and LVTH16373 contain sixteen D-typelatches with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but inde-pendent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LE n ) input is HIGH, data on the D n enters the latches. In this condition the latches are transparent, i.e, a latch output will change states each time its D input changes. When LE n is LOW,the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE n . The 3-STATE standard outputs are controlled by the Output Enable (OE n ) input. When OE n is LOW, the standard outputs are in the 2-state mode. When OE n is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.Logic DiagramsPlease note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. 474L V T 16373 • 74L V T H 16373Absolute Maximum Ratings (Note 3)Recommended Operating ConditionsNote 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.Note 4: I O Absolute Maximum Rating must be observed.DC Electrical CharacteristicsSymbol ParameterValueConditionsUnits V CC Supply Voltage 0.5 to 4.6V V I DC Input Voltage 0.5 to 7.0VV O DC Output Voltage 0.5 to 7.0Output in 3-STATEV 0.5 to 7.0Output in HIGH or LOW State (Note 4)I IK DC Input Diode Current 50V I GND mA I OK DC Output Diode Current 50V O GND mA I O DC Output Current64V O ! V CC Output at HIGH State mA 128V O ! V CCOutput at LOW StateI CC DC Supply Current per Supply Pin r 64mA I GND DC Ground Current per Ground Pin r 128mAT STGStorage Temperature65 to 150q CSymbol ParameterMin Max Units V CC Supply Voltage 2.7 3.6V V I Input Voltage5.5V I OH HIGH Level Output Current 32mA I OL LOW Level Output Current 64mAT AFree-Air Operating Temperature4085q C 't/'VInput Edge Rate, V IN 0.8V –2.0V, V CC 3.0V10ns/VSymbol ParameterV CC T A 40q C to 85q C Units Conditions(V)MinMax V IK Input Clamp Diode Voltage 2.7 1.2V I I 18 mA V IH Input HIGH Voltage 2.7–3.6 2.0V V O d 0.1V or V IL Input LOW Voltage 2.7–3.60.8VV O t V CC 0.1V V OHOutput HIGH Voltage2.7–3.6V CC 0.2VI OH 100 P A 2.7 2.4I OH 8 mA 3.02.0I OH 32 mA V OLOutput LOW Voltage2.70.2V I OL 100 P A 2.70.5I OL 24 mA3.00.4I OL 16 mA 3.00.5I OL 32 mA 3.00.55I OL 64 mA I I(HOLD)Bushold Input Minimum Drive3.075P A V I 0.8V (Note 5) 75V I 2.0V I I(OD)Bushold Input Over-Drive 3.0500P A (Note 6)(Note 5)Current to Change State 500(Note 7)I IInput Current3.610P AV I 5.5V Control Pins 3.6r 1V I 0V or V CC Data Pins3.6 5V I 0V 1V I V CCI OFF Power Off Leakage Current 0r 100P A 0V d V I or V O d 5.5V I PU/PD Power Up/Down 3-STATE 0–1.5V r 100P A V O 0.5V to 3.0V Output CurrentV I GND or V CC I OZL 3-STATE Output Leakage Current 3.6 5P A V O 0.5V I OZH 3-STATE Output Leakage Current 3.65P A V O 3.0V I OZH3-STATE Output Leakage Current 3.610P A V CC V O d 5.5V74LVT16373 • 74LVTH16373DC Electrical Characteristics (Continued)Note 5: Applies to bushold versions only (74LVTH16373).Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than V CC or GND.Dynamic Switching Characteristics (Note 9)Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested.Note 10: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. Output under test held LOW.AC Electrical CharacteristicsNote 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t OSHL ) or LOW-to-HIGH (t OSLH ).Capacitance (Note 12)Note 12: Capacitance is measured at frequency f 1 MHz, per MIL-STD-883, Method 3012.Symbol ParameterV CC T A 40q C to 85q C Units Conditions(V)MinMax I CCH Power Supply Current 3.60.19mA Outputs HIGH I CCL Power Supply Current 3.65mA Outputs LOW I CCZ Power Supply Current 3.60.19mA Outputs Disabled I CCZ Power Supply Current3.60.19mA V CC d V O d 5.5V,Outputs Disabled 'I CCIncrease in Power Supply Current 3.60.2mAOne Input at V CC 0.6V (Note 8)Other Inputs at V CC or GNDSymbol ParameterV CC T A 25q C Units Conditions (V)MinTyp MaxC L 50 pF, R L 500:V OLP Quiet Output Maximum Dynamic V OL 3.30.8V (Note 10)V OLVQuiet Output Minimum Dynamic V OL3.30.8V(Note 10)Symbol ParameterT A 40q C to 85q C, C L 50pF, R L 500:UnitsV CC 3.3V r 0.3V V CC 2.7VMin Max Min Max t PHL Propagation Delay 1.5 3.9 1.5 4.3ns t PLH D n to O n1.5 3.8 1.5 4.2t PHL Propagation Delay 1.9 4.2 1.9 4.4ns t PLH LE to O n1.6 4.3 1.6 4.8t PZL Output Enable Time1.3 4.3 1.3 4.9ns t PZH 1.0 4.3 1.0 5.1t PLZ Output Disable Time1.5 4.7 1.5 4.8ns t PHZ2.0 5.02.0 5.4t S Setup Time, D n to LE 1.00.8ns t H Hold Time, D n to LE 1.0 1.1ns t W LE Pulse Width3.03.0ns t OSHL Output to Output Skew (Note 11) 1.0 1.0ns t OSLH1.0 1.0Symbol ParameterConditionsTypical Units C IN Input Capacitance V CC Open, V I 0V or V CC 4pF C OUTOutput CapacitanceV CC 3.0V, V O 0V or V CC8pF 674L V T 16373 • 74L V T H 16373Physical Dimensionsinches (millimeters) unless otherwise noted54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm WidePackage Number BGA54APreliminary74LVT16373 • 74LVTH16373Physical Dimensionsinches (millimeters) unless otherwise noted (Continued)48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" WidePackage Number MS48A874L V T 16373 • 74L V T H 16373 L o w V o l t a g e 16-B i t T r a n s p a r e n t L a t c h w i t h 3-S T A T E O u t p u t sPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm WidePackage Number MTD48Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。
74HCT377中文资料
Fig.4 Functional diagram.
December 1990
Fig.5 Logic diagram. 4
元器件交易网
Philips Semiconductors
Octal D-type flip-flop with data enable; positive-edge trigger
NAME AND FUNCTION data enable input (active LOW) flip-flop outputs data inputs ground (0 V) clock input (LOW-to-HIGH, edge-triggered) positive supply voltage
Product specification
74HC/HCT377
FUNCTION TABLE
OPERATING MODES
load “1” load “0” hold (do nothing)
INPUTS
CP E Dn
↑
l
h
↑
l
l
↑hX XHX
OUTPUTS
Qn H L no change no change
90
15
18
13
15
ns 2.0 Fig.7 4.5 6.0
3 −8
3
3
3 −3
3
3
3 −2
3
3
4 −3
4
4
4 −1
4
4
4 −14ຫໍສະໝຸດ 46 235
4
30 70
24
20
35 83
28
24
ns 2.0 Fig.7 4.5 6.0
(完整word版)74HC573功能说明(原创编辑)0001
74CH573锁存器的功能74HC573和74LS373原理一样，8数据锁存器。
主要用于数码管、按键等等的控制 74HC573有20个脚，数据的进和出没有逻辑关系，这个芯片主要是看高电压激活还是低 电压激活：1是低电压激活芯片2~9脚是数据的输入脚从 DO 到D710脚是接地11脚是高电压激活芯片12~19脚是数据的输出脚20是电源SNS4HCS7 3A . . FK PACKAGE(TOP VIEW)1•真值表3 2 1 20 19 厂ZUIH E苛［ 171stOE1D益3D 4D5Dec0D GKD]^ec ]1Q]%]4a ]5Q ]7Q 1 5Q ■ ■ILEOurPLFT ENABLE乂＞EXPAMJtD I 1MAC ；K\M3C4D 5 口 6D7D/ t_n_IT _re_r~ir~LT~u~~m2Q 3Q4Q50fid亡I □ Ld □口 B N —l 在 g功能範高阻抗74HC573真值表，意思如下：第一行/第二行：当0E = 0、LE = 1时，输出端数据等于输入端数据；第三行：当0E = 0、LE = 0时，输出端保持不变；第四行：当0E = 1是无论Dn、LE为何，输出端为高阻态；2. 高阻态就是输出既不是高电平，也不是低电平，而是高阻抗的状态；在这种状态下，可以多个芯片并联输出；但是，这些芯片中只能有一个处于非高阻态状态，否则会将芯片烧毁。
高阻态的概念在RS232和RS422通讯中还可以用到。
3. 数据锁存当输入的数据消失时，在芯片的输出端，数据仍然保持；这个概念在并行数据扩展中经常使用到。
4. 数据缓冲加强驱动能力：74LS244/74LS245/74LS373/74LS573 都具备数据缓冲的能力。
0E : output_enable，输出使能；LE : latch_enable，数据锁存使能，atch是锁存的意思；Dn ：第n路输入数据；On ：第n路输出数据；74HC573波形图，在实际应用的时候是这样做的:OE = 0;先将数据从单片机的口线上输出到 出的数据了；实际上，单片机现在在忙着干别的事情，串行通信、扫描键盘 片机的资源有限啊。
74LVC16373ADGG,118,74LVC16373ADGG,518,74LVC16373ADGG,118,74LVC16373ADGG,118,规格书,Datasheet 资料
74LVC16373A; 74LVCH16373A
DESCRIPTION data input data input latch enable input (active HIGH)
4, 10, 15, 21, 28, ground (0 V) 34, 39, 45 5 6 7, 18, 31, 42 8 9 11 12 13 14 16 17 19 20 22 23 24 25 26 27 29 30 32 33 35 36 37 38 40 41 43 44 data output data output supply voltage data output data output data output data output data output data output data output data output data output data output data output data output output enable input (active LOW) latch enable input (active HIGH) data input data input data input data input data input data input data input data input data input data input data input data input data input data input Fig.1 Pin configuration SSOP48 and TSSOP48.
2003 Dec 08
2
芯天下--/
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
74LCX16373A中文资料
74LCX16373A LOW VOLTAGE16-BIT D-TYPE LATCH3-STATEWITH5V TOLERANT INPUTS AND OUTPUTPRELIMINARY DATANovember1997ORDER CODES: 74LCX16373Ts5V TOLERANT INPUTS AND OUTPUTSs HIGH SPEED:t PD=5.4ns(MAX.)at V CC=3V s POWER-DOWN PROTECTION ON INPUTS AND OUTPUTSs SYMMETRICAL OUTPUT IMPEDANCE: |I OH|=I OL=24mA(MIN)s PCI BUS LEVELS GUARANTEED AT24mAs BALANCED PROPAGATION DELAYS: t PLH≅t PHLs OPERATING VOLTAGE RANGE:V CC(OPR)=2.0V to3.6V(1.5V Data Retention)s PIN AND FUNCTION COMPATIBLE WITH 74SERIES16373s LATCH-UP PERFORMANCE EXCEEDS500mA s ESD PERFORMANCE:HBM>2000V;MM>200VDESCRIPTIONThe LCX16373is a low level CMOS16-BIT D-TYPE LATCH with3STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.It is ideal for low power and high speed3.3V applications;it can be interfaced to 5V signal enviroment for both inputs and outputs. These16bit D-Type latchs are byte controlled by two latch enable inputs(nLE)and two output enable inputs(nOE).While the nLE input is held at a high level,the nQ outputs will follow the data input precisely.When the nLE is taken low,the nQ outputs will be latched precisely at the logic level of D input data. While the(nOE)input is low,the nQ outputs will be in a normal logic state(high or low logic level) and while high level the outputs will be in a high impedance state.It has better speed performance at3.3V than5V LSTTL family combined with the true CMOS low power consumption.All inputs and outputs are equipped with protection circuits against static discharge,giving them2KV ESD immunity and transient excess voltage.T(TSSOP48Package)PIN CONNECTION1/974LCX16373AINPUT AND OUTPUT EQUIVALENT CIRCUITPIN DESCRIPTIONIEC LOGIC SYMBOLS PIN No SYMBOL NAME AND FUNCTION11OE3State Output EnableInput(Active LOW)2,3,5,6,1Q0to1Q7Data Inputs8,9,11,122Q0to2Q7Data Inputs13,14,16,17,19,20,22,23242OE3State Output EnableInput(Active LOW)252LE Latch Enable Input2D0to2D73State Outputs36,35,33,32,30,29,27,261D0to1D73State Outputs47,46,44,43,41,40,38,37481LE Latch Enable InputGND Ground(0V)4,10,15,21,28,34,39,457,18,31,42V CC Positive Supply VoltageTRUTH TABLEINPUTS OUTPUTSOE LE D QH X X ZL L X NO CHANGE*L H L LL H H HX:Don’t careZ:High imp edance*Q output are latched at the timewhen the LE inputs taken low logic2/974LCX16373A LOGIC DIAGRAMABSOLUTE MAXIMUM RATINGSSymbol Parameter Value Unit V CC Supply Voltage-0.5to+7.0V V I DC Input Voltage-0.5to+7.0V V O DC Output Voltage(OFF state)-0.5to+7.0V V O DC Output Voltage(High or Low State)(note1)-0.5to V CC+0.5VI IK DC Input Diode Current-50mAI OK DC Output Diode Current(note2)±50mAI O DC Output Source/Sink Current±50mAI CC or I GND DC V CC or Ground Current Per Supply Pin±100mAT stg Storage Temperature-65to+150o C T L Lead Temperature(10sec)300o C Absolute Maximum Ratings are those values beyond which damage to the device may occur.Functional operation under these condition is not implied.1)I O absolute maximum rating must be observed2)V O<GND,V O>V CCRECOMMENDED OPERATING CONDITIONSSymbol Parameter Value Unit V CC Supply Voltage(note1) 2.0to3.6V V I Input Voltage0to5.5V V O Output Voltage(OFF state)0to5.5V V O Output Voltage(High or Low State)0to V CC VI OH,I OL High or Low Level Output Current(V CC= 3.0to3.6V)±24mAI OH,I OL High or Low Level Output Current(V CC= 2.7to3.0V)±12mAT op Operating Temperature:-40to+85o C dt/dv Input Transition Rise or Fall Rate(V CC=3.0V)(note2)0to10ns/V1)Truth Table guaranteed:1.5V to3.6V2)V IN from0.8V to2.0V3/9DC SPECIFICATIONSSymbol Parameter Test Conditions Value UnitV CC (V)-40to85o C Min.Max.V IH High Level Input Voltage2.7to3.62.0VV IL Low Level Input Voltage0.8VV OH High Level Output Voltage 2.7to3.6V I=V IHor V IL I O=-100µA V CC-0.2V2.7I O=-12mA 2.23.0I O=-18mA 2.4 I O=-24mA 2.2V OL Low Level Output Voltage 2.7to3.6V I=V IHor V IL I O=100µA0.2V2.7I O=12mA0.43.0I O=16mA0.43.0I O=24mA0.55I I Input Leakage Current 2.7to3.6V I=0to5.5V±5µAI OZ3State Output Leakage Current 2.7to3.6V I=V IH or V ILV O=0to5.5V±5µAI off Power Off Leakage Current0V I or V O=5.5V(per pin)10µAI CC Quiescent Supply Current 2.7to3.6V I=V CC or GND20µAV I or V O=3.6to5.5V±20∆I CC ICC incr.per input 2.7to3.6V IH=V CC-0.6V500µA DYNAMIC SWITCHING CHARACTERISTICSSymbol Parameter Test Conditions Value UnitV CC (V)T A=25o C Min.Typ.Max.V OLP Dynamic Low Voltage Quiet Output (note1)3.3C L=50pFV IL=0VV IH=3.3V0.8VV OLV-0.81)Number of outputs defined as”n”.Me asured with”n-1”outputs switching from HIGH to LOW or LOW to HIGH.The remaining output is measured in the LOW state.74LCX16373A4/9CAPACITIVE CHARACTERISTICSSymbolParameterTest ConditionsValue UnitV CC (V)T A =25oCMin.Typ.Max.C IN Input Capacitance 3.3V IN =0to V CC 7pF C OU T Output Capacitance3.3V IN =0to V CC 8pF C PDPower Dissipation Capacitance (note 1)3.3f IN =10MHz V IN =0or V CC20pF1)C PD isdefined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.Average operting current can be obtained by the following equation.I CC (opr)=C PD •V CC •f IN +I CC /n (per circuit)AC ELECTRICAL CHARACTERISTICS (C L =50pF,R L =500Ω,Input t r =t f =2.5ns)SymbolParameterTest ConditionValue UnitV CC (V)Waveform-40to 85oC Min.Max.t PLH t PHL Propagation Delay Time Dn to Qn 2.71 1.58.0ns 3.0to 3.6 1.57.0t PLH t PHL Propagation Delay Time LE to Qn 2.71 1.58.0ns 3.0to 3.6 1.57.0t PZL t PZH Output Enable Time to HIGH and LOW level2.72 1.58.2ns3.0to 3.6 1.57.2t PLZ t PHZ Output Disable Time from HIGh and LOW level2.72 1.58.2ns3.0to 3.6 1.57.2t s Setup Time,HIGh or LOW level Dn to LE2.71 2.5ns3.0to 3.6 2.5t h Hold Time,HIGh or LOW level Dn to LE 2.71 1.5ns 3.0to 3.6 1.5t w LE Pulse Width,HIGH or LOW2.734.0ns 3.0to 3.6 3.0t OSLZ t OS HLOutput to Output Skew Time (note 1,2)3.0to 3.61.0ns1)Skew is defined as the absolute value of the difference between the ac tual propagation delay for any two outputs of the same device switching in the same direction,either HIGH or LOW (t OSLH =|t PLHm -t PLHn |,t OSHL =|t PHL m -t pHLn |)2)Parameter guaranteed by design74LCX16373A5/974LCX16373ATEST CIRCUITTEST SWITCH t PLH,t PHL Open t PZL,t PLZ6Vt PZH,t PHZ GND C L=50pF or equivalent(includes jig and probe capacitance)R L=R1=500Ωor equiva lentR T=Z OUT of pulse generator(typically50Ω)WAVEFORM1:LE TO Qn PROPAGATION DELAYS,LE MINIMUM PULSE WIDTH,Dn TO LE SETUP AND HOLD TIMES(f=1MHz;50%duty cycle)6/974LCX16373A WAVEFORM2:OUTPUT ENABLE AND DISABLE TIMES(f=1MHz;50%duty cycle)WAVEFORM3:PROPAGATION DELAY TIME(f=1MHz;50%duty cycle)7/9DIM.mminch MIN.TYP.MAX.MIN.TYP.MAX.A 1.10.433A10.050.100.150.0020.0040.006A20.850.90.950.3350.3540.374b 0.170.270.00670.011c 0.090.200.00350.0079D 12.412.512.60.4080.4920.496E 7.958.18.250.3130.3190.325E1 6.06.1 6.20.2360.2400.244e 0.5BSC 0.0197BSCK 0o 4o 8o 0o 4o 8o L0.500.600.700.0200.0240.028cEbA2AE1D1PIN 1IDENTIFICATIONA1LK eTSSOP48MECHANICAL DATA74LCX16373A8/974LCX16373A Information furnished is believed to be accurate and reliable.However,SGS-THOMSON Microelectronics assumes no responsabilit y for the consequences of use of such information nor for any infringemen t of patents or other rights of third parties which may results from its use.No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectr onics.Specifications mention ed in this publication are subject to change without notice.This publication supersede s and replaces all information previously supplied.SGS-THOMSON Microelectr onics products are not auth orized for use as critical compon ents in life support devices or systems without expre ss written approval of SGS-THOMSON Microelectonics.©1997SGS-THOMSON Microelectronics-Printed in Italy-All Rights Reserve dSGS-THOMSON Microelectronics GROUP OF COMPANIESAustralia-Brazil-Canada-China-France-Germany-Italy-Japan-Korea-Malaysia-Malta-Morocco-The Netherlands-Singapore-Spain-Sweden-Switzerland-Taiwan-Thailand-United Kingdom-U.S.A...9/9。
0_74系列芯片功能略表
74系列芯片功能略表技术2008-12-17 10:47:39 阅读422 评论0 字号：大中小引自廖世迁的blog电子元件知识-74系列芯片功能略表74HC01 2输入四与非门(oc)74HC02 2输入四或非门74HC03 2输入四与非门(oc)74HC04 六倒相器74HC05 六倒相器(oc)74HC06 六高压输出反相缓冲器/驱动器(oc,30v)74HC07 六高压输出缓冲器/驱动器(oc,30v)74HC08 2输入四与门74HC09 2输入四与门(oc)74HC10 3输入三与非门74HC11 3输入三与门74HC12 3输入三与非门(oc)74HC13 4输入双与非门(斯密特触发)74HC14 六倒相器(斯密特触发)74HC15 3输入三与门(oc)74HC16 六高压输出反相缓冲器/驱动器(oc,15v)74HC17 六高压输出缓冲器/驱动器(oc,15v)74HC18 4输入双与非门(斯密特触发)74HC19 六倒相器(斯密特触发)74HC20 4输入双与非门74HC21 4输入双与门74HC22 4输入双与非门(oc)74HC23 双可扩展的输入或非门74HC24 2输入四与非门(斯密特触发)74HC25 4输入双或非门(有选通)74HC26 2输入四高电平接口与非缓冲器(oc,15v)74HC27 3输入三或非门74HC28 2输入四或非缓冲器74HC30 8输入与非门74HC31 延迟电路74HC32 2输入四或门74HC33 2输入四或非缓冲器(集电极开路输出)74HC34 六缓冲器74HC35 六缓冲器(oc)74HC36 2输入四或非门(有选通)74HC37 2输入四与非缓冲器74HC38 2输入四或非缓冲器(集电极开路输出)74HC39 2输入四或非缓冲器(集电极开路输出)74HC40 4输入双与非缓冲器74HC41 bcd-十进制计数器74HC42 4线-10线译码器(bcd输入)74HC43 4线-10线译码器(余3码输入)74HC44 4线-10线译码器(余3葛莱码输入)74HC45 bcd-十进制译码器/驱动器74HC46 bcd-七段译码器/驱动器74HC47 bcd-七段译码器/驱动器74HC48 bcd-七段译码器/驱动器74HC49 bcd-七段译码器/驱动器(oc)74HC50 双二路2-2输入与或非门(一门可扩展)74HC51 双二路2-2输入与或非门74HC51 二路3-3输入,二路2-2输入与或非门74HC52 四路2-3-2-2输入与或门(可扩展)74HC53 四路2-2-2-2输入与或非门(可扩展)74HC53 四路2-2-3-2输入与或非门(可扩展)74HC54 四路2-2-2-2输入与或非门74HC54 四路2-3-3-2输入与或非门74HC54 四路2-2-3-2输入与或非门74HC55 二路4-4输入与或非门(可扩展)74HC60 双四输入与扩展74HC61 三3输入与扩展74HC62 四路2-3-3-2输入与或扩展器74HC63 六电流读出接口门74HC64 四路4-2-3-2输入与或非门74HC65 四路4-2-3-2输入与或非门(oc)74HC70 与门输入上升沿jk触发器74HC71 与输入r-s主从触发器74HC72 与门输入主从jk触发器74HC73 双j-k触发器(带清除端)74HC74 正沿触发双d型触发器(带预置端和清除端)74HC75 4位双稳锁存器74HC76 双j-k触发器(带预置端和清除端)74HC77 4位双稳态锁存器74HC78 双j-k触发器(带预置端,公共清除端和公共时钟端) 74HC80 门控全加器74HC81 16位随机存取存储器74HC82 2位二进制全加器(快速进位)74HC83 4位二进制全加器(快速进位)74HC84 16位随机存取存储器74HC85 4位数字比较器74HC86 2输入四异或门74HC87 四位二进制原码/反码/oi单元74HC89 64位读/写存储器74HC90 十进制计数器74HC91 八位移位寄存器74HC92 12分频计数器(2分频和6分频)74HC93 4位二进制计数器74HC94 4位移位寄存器(异步)74HC95 4位移位寄存器(并行io)74HC96 5位移位寄存器74HC97 六位同步二进制比率乘法器74HC100 八位双稳锁存器74HC103 负沿触发双j-k主从触发器(带清除端)74HC106 负沿触发双j-k主从触发器(带预置,清除,时钟) 74HC107 双j-k主从触发器(带清除端)74HC108 双j-k主从触发器(带预置,清除,时钟)74HC109 双j-k触发器(带置位,清除,正触发)74HC110 与门输入j-k主从触发器(带锁定)74HC111 双j-k主从触发器(带数据锁定)74HC112 负沿触发双j-k触发器(带预置端和清除端)74HC113 负沿触发双j-k触发器(带预置端)74HC114 双j-k触发器(带预置端,共清除端和时钟端) 74HC116 双四位锁存器74HC120 双脉冲同步器/驱动器74HC121 单稳态触发器(施密特触发)74HC122 可再触发单稳态多谐振荡器(带清除端)74HC123 可再触发双单稳多谐振荡器74HC125 四总线缓冲门(三态输出)74HC126 四总线缓冲门(三态输出)74HC128 2输入四或非线驱动器74HC131 3-8译码器74HC132 2输入四与非门(斯密特触发)74HC133 13输入端与非门74HC134 12输入端与门(三态输出)74HC135 四异或/异或非门74HC136 2输入四异或门(oc)74HC137 八选1锁存译码器/多路转换器74HC138 3-8线译码器/多路转换器74HC139 双2-4线译码器/多路转换器74HC140 双4输入与非线驱动器74HC141 bcd-十进制译码器/驱动器74HC142 计数器/锁存器/译码器/驱动器74HC145 4-10译码器/驱动器74HC147 10线-4线优先编码器74HC148 8线-3线八进制优先编码器74HC150 16选1数据选择器(反补输出)74HC151 8选1数据选择器(互补输出)74HC152 8选1数据选择器多路开关74HC153 双4选1数据选择器/多路选择器74HC154 4线-16线译码器74HC155 双2-4译码器/分配器(图腾柱输出)74HC156 双2-4译码器/分配器(集电极开路输出)74HC157 四2选1数据选择器/多路选择器74HC158 四2选1数据选择器(反相输出)74HC160 可预置bcd计数器(异步清除)74HC161 可预置四位二进制计数器(并清除异步)74HC162 可预置bcd计数器(异步清除)74HC163 可预置四位二进制计数器(并清除异步)74HC164 8位并行输出串行移位寄存器74HC165 并行输入8位移位寄存器(补码输出)74HC166 8位移位寄存器74HC167 同步十进制比率乘法器74HC168 4位加/减同步计数器(十进制)74HC169 同步二进制可逆计数器74HC170 4*4寄存器堆74HC171 四d触发器(带清除端)74HC172 16位寄存器堆74HC173 4位d型寄存器(带清除端)74HC174 六d触发器74HC175 四d触发器74HC176 十进制可预置计数器74HC177 2-8-16进制可预置计数器74HC178 四位通用移位寄存器74HC179 四位通用移位寄存器74HC180 九位奇偶产生/校验器74HC181 算术逻辑单元/功能发生器74HC182 先行进位发生器74HC183 双保留进位全加器74HC184 bcd-二进制转换器74HC185 二进制-bcd转换器74HC190 同步可逆计数器(bcd,二进制)74HC191 同步可逆计数器(bcd,二进制)74HC192 同步可逆计数器(bcd,二进制)74HC193 同步可逆计数器(bcd,二进制)74HC199 八位移位寄存器74HC210 2-5-10进制计数器74HC213 2-n-10可变进制计数器74HC221 双单稳触发器74HC230 八3态总线驱动器74HC231 八3态总线反向驱动器74HC240 八缓冲器/线驱动器/线接收器(反码三态输出) 74HC241 八缓冲器/线驱动器/线接收器(原码三态输出) 74HC242 八缓冲器/线驱动器/线接收器74HC243 4同相三态总线收发器74HC244 八缓冲器/线驱动器/线接收器74HC245 八双向总线收发器74HC246 4线-七段译码/驱动器(30v)74HC247 4线-七段译码/驱动器(15v)74HC248 4线-七段译码/驱动器74HC249 4线-七段译码/驱动器74HC251 8选1数据选择器(三态输出)74HC253 双四选1数据选择器(三态输出)74HC256 双四位可寻址锁存器74HC257 四2选1数据选择器(三态输出)74HC258 四2选1数据选择器(反码三态输出)74HC259 8为可寻址锁存器74HC260 双5输入或非门74HC261 4*2并行二进制乘法器74HC265 四互补输出元件74HC266 2输入四异或非门(oc)74HC270 2048位rom (512位四字节,oc)74HC271 2048位rom (256位八字节,oc)74HC273 八d触发器74HC274 4*4并行二进制乘法器74HC275 七位片式华莱士树乘法器74HC276 四jk触发器74HC278 四位可级联优先寄存器74HC279 四s-r锁存器74HC280 9位奇数/偶数奇偶发生器/较验器74HC28174HC283 4位二进制全加器74HC290 十进制计数器74HC291 32位可编程模74HC293 4位二进制计数器74HC294 16位可编程模74HC295 四位双向通用移位寄存器74HC298 四-2输入多路转换器(带选通)74HC299 八位通用移位寄存器(三态输出)74HC348 8-3线优先编码器(三态输出)74HC352 双四选1数据选择器/多路转换器74HC353 双4-1线数据选择器(三态输出)74HC354 8输入端多路转换器/数据选择器/寄存器,三态补码输出74HC355 8输入端多路转换器/数据选择器/寄存器,三态补码输出74HC356 8输入端多路转换器/数据选择器/寄存器,三态补码输出74HC357 8输入端多路转换器/数据选择器/寄存器,三态补码输出74HC365 6总线驱动器74HC366 六反向三态缓冲器/线驱动器74HC367 六同向三态缓冲器/线驱动器74HC368 六反向三态缓冲器/线驱动器74HC373 八d锁存器74HC374 八d触发器(三态同相)74HC375 4位双稳态锁存器74HC377 带使能的八d触发器74HC378 六d触发器74HC379 四d触发器74HC381 算术逻辑单元/函数发生器74HC382 算术逻辑单元/函数发生器74HC384 8位*1位补码乘法器74HC385 四串行加法器/乘法器74HC386 2输入四异或门74HC390 双十进制计数器74HC391 双四位二进制计数器74HC395 4位通用移位寄存器74HC396 八位存储寄存器74HC398 四2输入端多路开关(双路输出)74HC399 四-2输入多路转换器(带选通)74HC422 单稳态触发器74HC423 双单稳态触发器74HC440 四3方向总线收发器,集电极开路74HC441 四3方向总线收发器,集电极开路74HC442 四3方向总线收发器,三态输出74HC443 四3方向总线收发器,三态输出74HC444 四3方向总线收发器,三态输出74HC445 bcd-十进制译码器/驱动器,三态输出74HC446 有方向控制的双总线收发器74HC448 四3方向总线收发器,三态输出74HC449 有方向控制的双总线收发器74HC465 八三态线缓冲器74HC466 八三态线反向缓冲器74HC467 八三态线缓冲器74HC468 八三态线反向缓冲器74HC490 双十进制计数器74HC540 八位三态总线缓冲器(反向)74HC541 八位三态总线缓冲器74HC589 有输入锁存的并入串出移位寄存器74HC590 带输出寄存器的8位二进制计数器74HC591 带输出寄存器的8位二进制计数器74HC592 带输出寄存器的8位二进制计数器74HC593 带输出寄存器的8位二进制计数器74HC594 带输出锁存的8位串入并出移位寄存器74HC595 8位输出锁存移位寄存器74HC596 带输出锁存的8位串入并出移位寄存器74HC597 8位输出锁存移位寄存器74HC598 带输入锁存的并入串出移位寄存器74HC599 带输出锁存的8位串入并出移位寄存器74HC604 双8位锁存器74HC605 双8位锁存器74HC606 双8位锁存器74HC607 双8位锁存器74HC620 8位三态总线发送接收器(反相)74HC621 8位总线收发器74HC622 8位总线收发器74HC623 8位总线收发器74HC640 反相总线收发器(三态输出)74HC641 同相8总线收发器,集电极开路74HC642 同相8总线收发器,集电极开路74HC643 8位三态总线发送接收器74HC644 真值反相8总线收发器,集电极开路74HC645 三态同相8总线收发器74HC646 八位总线收发器,寄存器74HC647 八位总线收发器,寄存器74HC648 八位总线收发器,寄存器74HC649 八位总线收发器,寄存器74HC651 三态反相8总线收发器74HC652 三态反相8总线收发器74HC653 反相8总线收发器,集电极开路74HC654 同相8总线收发器,集电极开路74HC668 4位同步加/减十进制计数器74HC669 带先行进位的4位同步二进制可逆计数器74HC670 4*4寄存器堆(三态)74HC671 带输出寄存的四位并入并出移位寄存器74HC672 带输出寄存的四位并入并出移位寄存器74HC673 16位并行输出存储器,16位串入串出移位寄存器74HC674 16位并行输入串行输出移位寄存器74HC681 4位并行二进制累加器74HC682 8位数值比较器(图腾柱输出)74HC683 8位数值比较器(集电极开路)74HC684 8位数值比较器(图腾柱输出)74HC685 8位数值比较器(集电极开路)74HC686 8位数值比较器(图腾柱输出)74HC687 8位数值比较器(集电极开路)74HC688 8位数字比较器(oc输出)74HC689 8位数字比较器74HC690 同步十进制计数器/寄存器(带数选,三态输出,直接清除)。
CD74ACT373中文资料
Data sheet acquired from Harris SemiconductorSCHS289This data sheet is applicable to the CD54/74AC373, CD54/74ACT373, and CD54ACT533. The CD74AC533 and CD74ACT533 were notacquired from Harris Semiconductor.IMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK.In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.Copyright © 1999, Texas Instruments Incorporated。
MC74LCX16373中文资料
nLE
Inputs LE1 X H H L OE1 H L L L D0:7 X L H X
Outputs O0:7 Z L H O0 LE2 X H H L
Inputs OE2 H L L L D8:15 X L H X
Outputs O8:15 Z L H O0
H = High Voltage Level; L = Low Voltage Level; Z = High Impedance State; X = High or Low Voltage Level and Transitions Are Acceptable, for ICC reasons, DO NOT FLOAT Inputsபைடு நூலகம்
MOTOROLA
2
LCX DATA BR1339 — REV 3
元器件交易网
MC74LCX16373
ABSOLUTE MAXIMUM RATINGS*
Symbol VCC VI VO Parameter DC Supply Voltage DC Input Voltage DC Output Voltage Value –0.5 to +7.0 –0.5 ≤ VI ≤ +7.0 –0.5 ≤ VO ≤ +7.0 –0.5 ≤ VO ≤ VCC + 0.5 IIK IOK DC Input Diode Current DC Output Diode Current –50 –50 +50 IO ICC IGND TSTG DC Output Source/Sink Current DC Supply Current Per Supply Pin DC Ground Current Per Ground Pin Storage Temperature Range ±50 ±100 ±100 –65 to +150 Output in 3–State Note 1. VI < GND VO < GND VO > VCC Condition Unit V V V V mA mA mA mA mA mA °C
74hc573完整中文资料
74hc573中文资料参数-74hc573引脚图-功能原理-74hC573的作用-应用电路-74hC563-54hC57高性能硅门CMOS器件SL74HC573跟LS/AL573的管脚一样。
器件的输入是和标准CMOS输出兼容的；加上拉电阻，他们能和LS/ALSTTL输出兼容。
当锁存使能端为高时，这些器件的锁存对于数据是透明的（也就是说输出同步）。
当锁存使能变低时，符合建立时间和保持时间的数据会被锁存。
×输出能直接接到CMOS，NMOS和TTL接口上×操作电压范围：2.0V~6.0V×低输入电流：1.0uA×CMOS器件的高噪声抵抗特性·三态总线驱动输出·置数全并行存取·缓冲控制输入·使能输入有改善抗扰度的滞后作用原理说明：M54HC563/74HC563/M54HC573/74HC573的八个锁存器都是透明的D 型锁存器，当使能（G）为高时，Q 输出将随数据（D）输入而变。
当使能为低时，输出将锁存在已建立的数据电平上。
输出控制不影响锁存器的内部工作，即老数据可以保持，甚至当输出被关闭时，新的数据也可以置入。
这种电路可以驱动大电容或低阻抗负载，可以直接与系统总线接口并驱动总线，而不需要外接口。
特别适用于缓冲寄存器，I/O 通道，双向总线驱动器和工作寄存器。
HC563引脚功能表：HC573引脚功能表：图1 HC573引脚图图2 HC573 国际电工委员会逻辑符号图3 HC563引脚图图4 HC563 国际电工委员会逻辑符号图5 HC563 逻辑图图6 HC573 逻辑图图7 输入输出等效电路真值表：ABSOLUTE MAXIMUM RATINGS绝对最大额定值：Top Operating Temperature: M54HC Series M74HC Series 操作温度：M54HC系列M74HC系列-55 to +125 -40 to +85℃tr,tf Input Rise and Fall Time输入上升和下降时间VCC =2V0 to 1000ns VCC=4.5V0 to 500VCC =6V0 to 400VOHHigh Level Output Voltage输出高电平电压2.0 VI = VIH or VILIO=-20 μA1.92.0-1.9 -1.9 -V4.54.44.54.44.4---6.05.96.05.95.9-4.5IO=-6.0mA4.184.314.134.10-6.0IO=-7.8 mA5.685.85.635.60-VOLLow Level Output Voltage输出低电平电压2.0 VI = VIH or VILIO=20μA-0.0 0.1 -0.1-0.1V4.5-0.00.1 0.10.16.0-0.00.10.10.14.5IO=6.0mA-0.170.260.330.406.0IO=7.8mA-0.180.260.330.40IIInput Leakage Current输入漏电流6.0VI =VCC or GND--±0.1-±1±1μA IOZState Output Off State Current关断状态3态输出电流6.0VI =VIH or VIL VO =VCC or GND--±0.5-±5.0-±10μAICCQuiescent Supply Current静态电源电流6.0VI =VCC or GND--4-40-80μA应用电路图：点击图片查看大图图8。
SN74LVC3G07中文资料
_ _ _CV_
NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free)
SN74LVC3G07YZPR
SSOP – DCT
Reel of 3000 SN74LVC3G07DCTR
C07_ _ _
VSSOP – DCU
Reel of 3000 Reel of 250
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The output of the SN74LVC3G07 is open drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 32 mA.
NanoFree™ – WCSP (DSBGA) 0.17-mm Small Bump – YZA (Pb-free)
NanoStar™ – WCSP (DSBGA) 0.23-mm Large Bump – YEP
Reel of 3000
SN74LVC3G07YZAR SN74LVC3G07YEPR
TA –40°C to 85°C
ORDERING INFORMATION
PACKAGE (1)
ORDERABLE PART NUMBER TOP-SIDE MARKING(2)
NanoStar™ – WCSP (DSBGA) 0.17-mm Small Bump – YEA
SN74LVC3G07YEAR
LT1637 1637FD 微型电源操场类型电阻电压输出电流输入电阻说明书
100µs/DIV1637 TA01b1231637fdInput Offset Voltage Drift (Note 9)N8, S8 Packages, –40°C ≤ T A ≤ 85°C ●13µV/°C MS8 Package, –40°C ≤ T A ≤ 85°C ●26µV/°C DDPackage, –40°C ≤ T A ≤ 85°C ●26µV/°C I OSInput Offset Current●0.4 6.0nA V CM = 44V (Note 5)● 2.5µA I BInput Bias Current●2050nA V CM = 44V (Note 5)●2360µA V S = 0V0.1nA Input Noise Voltage0.1Hz to 10Hz 0.6µV P-P e n Input Noise Voltage Density f = 1kHz 27nV/√Hz i n Input Noise Current Density f = 1kHz0.08pA/√Hz R IN Input Resistance Differential1 2.6M ΩCommon Mode, V CM = 0V to 44V0.7 1.4M ΩC IN Input Capacitance 4pF Input Voltage Range●044V CMRR Common Mode Rejection Ratio V CM = 0V to (V CC – 1V)●88110dB (Note 5)V CM = 0V to 44V (Note 8)●8098dB A VOLLarge-Signal Voltage GainV S = 3V, V O = 500mV to 2.5V, R L = 10k 150400V/mV V S = 3V, 0°C ≤ T A ≤ 70°C ●100V/mV V S = 3V, –40°C ≤ T A ≤ 85°C●75V/mV V S = 5V, V O = 500mV to 4.5V, R L = 10k 300800V/mV V S = 5V, 0°C ≤ T A ≤ 70°C ●200V/mV V S = 5V, –40°C ≤ T A ≤ 85°C●150V/mVV OLOutput Voltage Swing LOWNo Load ●38mV I SINK = 5mA●325700mV V S = 5V, I SINK = 10mA ●5801300mV V OHOutput Voltage Swing HIGHV S = 3V, No Load● 2.94 2.975V V S = 3V, I SOURCE = 5mA ● 2.25 2.67V V S = 5V, No Load● 4.94 4.975V V S = 5V, I SOURCE = 10mA●3.804.45V I SCShort-Circuit Current (Note 2)V S = 3V, Short Output to Ground 1014mA V S = 3V, Short Output to V CC 1545mA V S = 5V, Short Output to Ground 1522mA V S = 5V, Short Output to V CC1560mA PSRRPower Supply Rejection Ratio V S = 3V to 12.5V, V CM = V O = 1V●9098dBMinimum Supply Voltage ● 2.7V Reverse Supply VoltageI S = –100µA●2540V I SSupply Current 190250µA (Note 6)●295µA Supply Current, SHDNV PIN5 = 2V, No Load (Note 6)●312µA I SHDNShutdown Pin CurrentV PIN5 = 0.3V, No Load (Note 6)●0.215nA V PIN5 = 2V, No Load (Note 5)● 1.05µA V PIN5 = 3.3V 2.5µA V PIN5 = 5V4.3µA Output Leakage Current, SHDN V PIN5 = 2V, No Load (Note 6)●0.021µALT1637C/LT1637I SYMBOLPARAMETERCONDITIONSMIN TYP MAXUNITS The ● denotes the specifications which apply over the full operating temperature range of –40°C ≤ T A ≤ 85°C, otherwisespecifications are at T A = 25°C. V S = 3V, 0V; V S = 5V, 0V; V SHDN = V –,V CM = V OUT = half supply unless otherwise specified. (Note 4)3V 5V A D ELECTRICAL CHARACTERISTICS41637fdLT1637C/LT1637I SYMBOL PARAMETER CONDITIONS MIN TYP MAXUNITS V OSInput Offset VoltageN8, S8 Packages 100450µV 0°C ≤ T A ≤ 70°C ●650µV –40°C ≤ T A ≤ 85°C ●800µV MS8 Package 100450µV 0°C ≤ T A ≤ 70°C ●800µV –40°C ≤ T A ≤ 85°C ●1150µV DD Package 125650µV 0°C ≤ T A ≤ 70°C ●1000µV –40°C ≤ T A ≤ 85°C●1150µV Input Offset Voltage Drift (Note 9)N8, S8 Packages, –40°C ≤ T A ≤ 85°C ●13µV/°C MS8 Package, –40°C ≤ T A ≤ 85°C ●26µV/°C DD Package, –40°C ≤ T A ≤ 85°C●26µV/°C I OS Input Offset Current ●16nA I B Input Bias Current ●1750nA Input Noise Voltage 0.1Hz to 10Hz 0.6µV P-P e n Input Noise Voltage Density f = 1kHz 27nV/√Hz i n Input Noise Current Density f = 1kHz0.08pA/√Hz R IN Input Resistance Differential13M ΩCommon Mode, V CM = –15V to 14V2200M ΩC IN Input Capacitance 4pFInput Voltage Range●–1529V CMRR Common Mode Rejection Ratio V CM = –15V to 29V ●80110dB A VOLLarge-Signal Voltage GainV O = ±14V, R L = 10k 100400V/mV 0°C ≤ T A ≤ 70°C ●75V/mV –40°C ≤ T A ≤ 85°C ●50V/mVV OLOutput Voltage Swing LOWNo Load ●–14.997–14.95V I SINK = 5mA ●–14.680–14.25V I SINK = 10mA ●–14.420–13.65VThe ● denotes the specifications which apply over the full operating temperature range of –40°C ≤ T A ≤85°C, otherwise specifications are at T A = 25°C. V S = ±15V, V CM = 0V, V OUT = 0V, V SHDN = V – unless otherwise specified. (Note 4)±15V ELECTRICAL CHARACTERISTICSThe ● denotes the specifications which apply over the full operating temperature range of –40°C ≤ T A ≤85°C, otherwisespecifications are at T A = 25°C. V S = 3V, 0V; V S = 5V, 0V; V SHDN = V –, V CM = V OUT = half supply unless otherwise specified. (Note 4)3V 5V A D ELECTRICAL CHARACTERISTICSLT1637C/LT1637I SYMBOL PARAMETERCONDITIONSMIN TYP MAXUNITS Maximum Shutdown Pin Current V PIN5 = 32V, No Load (Note 5)●20150µA t ON Turn-On Time V PIN5 = 5V to 0V, R L = 10k 45µs t OFF Turn-Off Time V PIN5 = 0V to 5V, R L = 10k 3µs t SETTLING Settling Time0.1% A V = 1, ∆V O = 2V 9µs GBWGain-Bandwidth Product f = 10kHz6501000kHz (Note 5)0°C ≤ T A ≤ 70°C ●550kHz –40°C ≤ T A ≤ 85°C ●500kHz SR Slew Rate A V = –1, R L = ∞0.2100.35V/µs (Note 7)0°C ≤ T A ≤ 70°C ●0.185V/µs –40°C ≤ T A ≤ 85°C●0.170V/µs51637fdV OHOutput Voltage Swing HIGHNo Load●14.914.967V I SOURCE = 5mA ●14.214.667V I SOURCE = 10mA ●13.714.440V I SCShort-Circuit Current (Note 2)Short Output to GND ±25±31.7mA 0°C ≤ T A ≤ 70°C ●±20mA –40°C ≤ T A ≤ 85°C ●±15mA PSRR Power Supply Rejection Ratio V S = ±1.5V to ±22V●90115dBMinimum Supply Voltage ●±1.35V I SSupply Current230300µA ●370µA Positive Supply Current, SHDNV PIN5 = –20V, V S = ±22V, No Load ●640µA I SHDNShutdown Pin Current V PIN5 = –21.7V, V S = ±22V, No Load ●0.315nA V PIN5 = –20V, V S = ±22V, No Load ●0.98µA Maximum Shutdown Pin Current V PIN5 = 32V, V S = ±22V●20150µA Output Leakage Current, SHDNV PIN5 = –20V, V S = ±22V, No Load ●0.022µA V L Shutdown Pin Input Low Voltage V S = ±22V ●–21.7–21.6V V H Shutdown Pin Input High Voltage V S = ±22V●–20.8–20.0V t ON Turn-On Time V PIN5 = –10V to –15V, R L = 10k 35µs t OFF Turn-Off Time V PIN5 = –15V to –10V, R L = 10k 3µs GBWGain-Bandwidth Productf = 10kHz7501100kHz 0°C ≤ T A ≤ 70°C ●650kHz –40°C ≤ T A ≤ 85°C●600kHz SR Slew Rate A V = –1, R L = ∞, V O = ±10V, Measure at V O = ±5V 0.2250.4V/µs 0°C ≤ T A ≤ 70°C ●0.200V/µs –40°C ≤ T A ≤ 85°C●0.180V/µsThe ● denotes the specifications which apply over the full operating temperature range of –40°C ≤ T A ≤85°C, otherwise specifications are at T A = 25°C. V S = ±15V, V CM = 0V, V OUT = 0V, V SHDN = V – unless otherwise specified. (Note 4)LT1637C/LT1637I SYMBOL PARAMETERCONDITIONS MIN TYP MAX UNITS±15V ELECTRICAL CHARACTERISTICS61637fdLT1637H/LT1637MP SYMBOL PARAMETER CONDITIONSMIN TYP MAXUNITS V OSInput Offset Voltage100450µV●3mV Input Offset Voltage Drift (Note 9)●310µV/°C I OS Input Offset Current●15nA V CM = 44V (Note 5)●10µA I BInput Bias Current●150nA V CM = 44V (Note 5)●100µA Input Voltage Range●0.344V CMRR Common Mode Rejection Ratio V CM = 0.3V to (V CC – 1V)●72dB (Note 5)V CM = 0.3V to 44V●74dBA VOLLarge-Signal Voltage GainV S = 3V, V O = 500mV to 2.5V, R L = 10k150400V/mV ●20V/mV V S = 5V, V O = 500mV to 4.5V, R L = 10k300800V/mV ●35V/mVV OLOutput Voltage Swing LOWNo Load ●15mV I SINK = 5mA●900mV V S = 5V, I SINK = 10mA ●1500mV V OHOutput Voltage Swing HIGHV S = 3V, No Load● 2.90V V S = 3V, I SOURCE = 5mA ● 2.05V V S = 5V, No Load● 4.90V V S = 5V, I SOURCE = 10mA● 3.50V PSRR Power Supply Rejection Ratio V S = 3V to 12.5V, V CM = V O = 1V ●80dB Minimum Supply Voltage ●2.7V Reverse Supply VoltageI S = –100µA ●23VI SSupply Current (Note 6)190250µA ●400µA Supply Current, SHDNV PIN5 = 2V, No Load (Note 6)●15µA I SHDNShutdown Pin Current V PIN5 = 0.3V, No Load (Note 6)●200nA V PIN5 = 2V, No Load (Note 5)●7µA Output Leakage Current, SHDN V PIN5 = 2V, No Load (Note 6)●5µA Maximum Shutdown Pin CurrentV PIN5 = 32V, No Load (Note 5)●200µA GBW Gain-Bandwidth Product f = 10kHz (Note 5)6501000kHz ●350kHz SRSlew RateA V = –1, R L = ∞ (Note 7)0.2100.35V/µs ●0.1V/µsThe ● denotes the specifications which apply over the full operating temperature range of –40°C ≤ T A ≤125°C for LT1637H and –55°C ≤ T A ≤ 125°C for LT1637MP. V S = 3V, 0V; V S = 5V, 0V; V CM = V OUT = half supply unless otherwise specified. (Note 4)3V 5V A UD ELECTRICAL CHARACTERISTICSThe ● denotes the specifications which apply over the full operating temperature range of –40°C ≤ T A≤125°C for LT1637H and–55°C ≤ T A≤ 125°C for LT1637MP. V S = ±15V, V CM = 0V, V OUT = 0V, V SHDN = V–, unless otherwise specified. (Note 4)±15V ELECTRICAL CHARACTERISTICSLT1637H/LT1637MPSYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OS Input Offset Voltage100550µV● 3.4mVInput Offset Voltage Drift (Note 9)●311µV/°C I OS Input Offset Current●25nA I B Input Bias Current●250nA CMRR Common Mode Rejection Ratio V CM = –14.7V to 29V●72dBA VOL Large-Signal Voltage Gain V O = ±14V, R L = 10k100400V/mV●4V/mV V O Output Voltage Swing No Load●±14.8VI OUT = ±5mA●±14.0VI OUT= ±10mA●±13.4V PSRR Power Supply Rejection Ratio V S = ±1.5V to 22V●84dB Minimum Supply Voltage●±1.35VI S Supply Current230300µA●500µAPositive Supply Current, SHDN V PIN5 = –20V, V S = ±22V, No Load●60µA I SHDN Shutdown Pin Current V PIN5 = –21.7V, V S = ±22V, No Load●200nAV PIN5 = –20V, V S = ±22V, No Load●10µA Maximum Shutdown Pin Current V PIN5 = 32V, V S = ±22V●200µA Output Leakage Current, SHDN V PIN5 = –20V, V S = ±22V, No Load●100µA V L Shutdown Pin Input Low Voltage V S = ±22V●–21.7V V H Shutdown Pin Input High Voltage V S = ±22V●–20V GBW Gain-Bandwidth Product f = 10kHz7501100kHz●400kHz SR Slew Rate A V = –1, R L = ∞, V O = ±10V,0.2250.4V/µsMeasure at V O = ±5V●0.1V/µsNote 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: A heat sink may be required to keep the junction temperature below absolute maximum. The θJA specified for the DD package is with minimal PCB heat spreading metal. Using expanded metal area on all layers of a board reduces this value.Note 3: The LT1637C and LT1637I are guaranteed functional over the operating temperature range of –40°C to 85°C. The LT1637H is guaranteed functional over the operating temperature range of –40°C to 125°C. The LT1637MP is guaranteed functional over the operating temperature range –55°C to 125°C.Note 4: The LT1637C is guaranteed to meet specified performance from 0°C to 70°C. The LT1637C is designed, characterized and expected to meet specified performance from –40°C to 85°C but is not tested or QA sampled at these temperatures. The LT1637I is guaranteed to meet specified performance from –40°C to 85°C. The LT1637H is guaranteed to meet specified performance from –40°C to 125°C and the LT1637MP is guaranteed to meet specified performance from –55°C to 125°C.Note 5: V S = 5V limits are guaranteed by correlation to V S = 3V andV S = ±15V or V S = ±22V tests.Note 6: V S = 3V limits are guaranteed by correlation to V S = 5V andV S = ±15V or V S = ±22V tests.Note 7: Guaranteed by correlation to slew rate at V S = ±15V and GBW at V S = 3V and V S = ±15V tests.Note 8: This specification implies a typical input offset voltage of 650µV at V CM = 44V and a maximum input offset voltage of 5.4mV at V CM = 44V. Note 9: This parameter is not 100% tested.71637fd8TIME (s)081637 G0724619357109100V 10V OUTPUT VOLTAGE (5V/DIV)C1637 G241637 G25A: R L = 2k B: R L = 10k C: R L = 50k1637 G26AB–10V V S = ±15VV S = ±15V A V = –1V S = ±15V A V = 1A B C111637fdSupply VoltageThe positive supply pin of the LT1637 should be bypassed with a small capacitor (about 0.01µF) within an inch of the pin. When driving heavy loads an additional 4.7µF electro-lytic capacitor should be used. When using split supplies,the same is true for the negative supply pin.The LT1637 is protected against reverse battery voltages up to 25V. In the event a reverse battery condition occurs,the supply current is typically less than 1nA.When operating the LT1637 on total supplies of 30V or more, the supply must not be brought up faster than 1µs.This is especially true if low ESR bypass capacitors are used. A series RLC circuit is formed from the supply lead inductance and the bypass capacitor. 5Ω of resistance in the supply or the bypass capacitor will dampen the tuned circuit enough to limit the rise time.InputsThe LT1637 has two input stages, NPN and PNP (see the Simplified Schematic), resulting in three distinct operat-ing regions as shown in the Input Bias Current vs Common Mode typical performance curve.For input voltages about 0.9V or more below V +, the PNP input stage is active and the input bias current is typically –20nA. When the input voltage is about 0.5V or less from V +, the NPN input stage is operating and the input bias current is typically 80nA. Increases in temperature will cause the voltage at which operation switches from the PNP stage to the NPN stage to move towards V +. The input offset voltage of the NPN stage is untrimmed and is typically 600µV.A Schottky diode in the collector of each NPN transistor of the NPN input stage allows the LT1637 to operate with either or both of its inputs above V +. At about 0.3V above V + the NPN input transistor is fully saturated and the input bias current is typically 23µA at room temperature. The input offset voltage is typically 600µV when operating above V +. The LT1637 will operate with its input 44V above V – regardless of V +.APPLICATIO S I FOR ATIOW UUU The inputs are protected against excursions as much as 22V below V – by an internal 1.3k resistor in series with each input and a diode from the input to the negative supply. There is no output phase reversal for inputs up to 5V below V –. There are no clamping diodes between the inputs and the maximum differential input voltage is 44V.OutputThe output voltage swing of the LT1637 is affected by input overdrive as shown in the typical performance curves. When monitoring input voltages within 100mV of V +, gain should be taken to keep the output from clipping.The output of the LT1637 can be pulled up to 25V beyond V + with less than 1nA of leakage current, provided that V +is less than 0.5V.The normally reverse biased substrate diode from the output to V – will cause unlimited currents to flow when the output is forced below V –. If the current is transient and limited to 100mA, no damage will occur.The LT1637 is internally compensated to drive at least 200pF of capacitance under any output loading condi-tions. A 0.22µF capacitor in series with a 150Ω resistor between the output and ground will compensate these amplifiers for larger capacitive loads, up to 4700pF, at all output currents.DistortionThere are two main contributors of distortion in op amps:output crossover distortion as the output transitions from sourcing to sinking current and distortion caused by nonlinear common mode rejection. Of course, if the op amp is operating inverting there is no common mode induced distortion. When the LT1637 switches between input stages there is significant nonlinearity in the CMRR.Lower load resistance increases the output crossover distortion, but has no effect on the input stage transition distortion. For lowest distortion the LT1637 should be operated single supply, with the output always sourcing current and with the input voltage swing between ground and (V + – 0.9V). See the Typical Performance Character-istics curves.121314Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.1516Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 ● FAX: (408) 434-0507 ● © LINEAR TECHNOLOGY CORPORA TION 2007LT 0107 REV D • PRINTED IN USA。
74LCX16373G中文资料
© 2005 Fairchild Semiconductor Corporation DS012002February 1994Revised May 200574LCX16373 Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and Outputs74LCX16373Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and OutputsGeneral DescriptionThe LCX16373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applica-tions. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state.The LCX16373 is designed for low voltage (2.5V or 3.3V)V CC applications with capability of interfacing to a 5V signal environment.The LCX16373 is fabricated with an advanced CMOS tech-nology to achieve high speed operation while maintaining CMOS low power dissipation.Featuress 5V tolerant inputs and outputs s 2.3V–3.6V V CC specifications provided s 5.4 ns t PD max (V CC 3.3V), 20 P A I CC max s Power down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1)s r 24 mA output drive (V CC 3.0V)s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance:Human body model ! 2000V Machine model ! 200Vs Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA)Note 1: To ensure the high-impedance state during power up or down, OE should be tied to V CC through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver.Ordering Code:Note 2: Ordering code “G ” indicates Trays.Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X ” to the ordering code.Logic SymbolOrder Number Package NumberPackage Description74LCX16373G (Note 2)(Note 3)BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 74LCX16373MEA (Note 3)MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LCX16373MTD (Note 3)MTD4848-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 274L C X 16373Connection DiagramsPin Assignment for SSOP and TSSOPPin Assignment for FBGA(Top Thru View)Pin DescriptionsFBGA Pin AssignmentsTruth TablesH HIGH Voltage Level L LOW Voltage Level X ImmaterialZ High ImpedanceO 0 Previous O 0 before HIGH-to-LOW transition of Latch EnablePin Names DescriptionOE n Output Enable Input (Active LOW)LE n Latch Enable Input I 0–I 15Inputs O 0–O 15Outputs NCNo Connect123456A O 0NC OE 1LE 1NC I 0B O 2O 1NC NC I 1I 2C O 4O 3V CC V CC I 3I 4D O 6O 5GND GND I 5I 6E O 8O 7GND GND I 7I 8F O 10O 9GND GND I 9I 10G O 12O 11V CC V CC I 11I 12H O 14O 13NC NC I 13I 14JO 15NCOE 2LE 2NCI 15InputsOutputs LE 1OE 1I 0–I 7O 0–O 7XH X Z H L L L H L H H LL XO 0InputsOutputs LE 2OE 2I 8–I 15O 8–O 15X H X Z H L L L H L H H LLX O 074LCX16373Functional DescriptionThe LCX16373 contains sixteen D-type latches with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LE n ) input is HIGH, data on the I n enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each timeits I input changes. When LE n is LOW, the latches store information that was present on the I inputs a setup time preceding the HIGH-to-LOW transition of LE n . The 3-STATE standard outputs are controlled by the Output Enable (OE n ) input. When OE n is LOW, the standard out-puts are in the 2-state mode. When OE n is HIGH, the stan-dard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.Logic DiagramsPlease note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 474L C X 16373Absolute Maximum Ratings (Note 4)Recommended Operating Conditions (Note 6)Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-mended Operating Conditions ” table will define the conditions for actual device operation.Note 5: I O Absolute Maximum Rating must be observed.Note 6: Unused inputs must be held HIGH or LOW. They may not float.DC Electrical CharacteristicsSymbol ParameterValueConditionsUnits V CC Supply Voltage 0.5 to 7.0V V I DC Input Voltage 0.5 to 7.0VV O DC Output Voltage 0.5 to 7.0Output in 3-STATEV 0.5 to V CC 0.5Output in HIGH or LOW State (Note 5)I IK DC Input Diode Current 50V I GND mA I OK DC Output Diode Current 50V O GND mA 50V O ! V CCI O DC Output Source/Sink Current r 50mA I CC DC Supply Current per Supply Pin r 100mA I GND DC Ground Current per Ground Pin r 100mAT STGStorage Temperature65 to 150q CSymbol ParameterMin Max Units V CC Supply Voltage Operating 2.0 3.6V Data Retention1.5 3.6V I Input Voltage 0 5.5V V O Output Voltage HIGH or LOW State0V CC V3-STATE5.5I OH /I OLOutput CurrentV CC 3.0V 3.6V r 24mAV CC 2.7V 3.0V r 12V CC 2.3V 2.7Vr 8T AFree-Air Operating Temperature4085q C 't/'VInput Edge Rate, V IN 0.8V –2.0V, V CC 3.0V10ns/VSymbol ParameterConditionsV CC T A 40q C to 85q C Units (V)Min MaxV IH HIGH Level Input Voltage 2.3 2.7 1.7V 2.7 3.6 2.0V IL LOW Level Input Voltage 2.3 2.70.7V2.73.60.8V OHHIGH Level Output VoltageI OH 100 P A 2.3 3.6V CC 0.2VI OH 8 mA 2.3 1.8I OH 12 mA 2.7 2.2I OH 18 mA 3.0 2.4I OH 24 mA3.0 2.2V OLLOW Level Output VoltageI OL 100 P A 2.3 3.60.2V I OL 8 mA 2.30.6I OL 12 mA 2.70.4I OL 16 mA 3.00.4I OL 24 mA3.00.55I I Input Leakage Current 0 d V I d 5.5V 2.3 3.6r 5.0P A I OZ 3-STATE Output Leakage 0 d V O d 5.5V 2.3 3.6r 5.0P A V I V IH or V IL I OFFPower-Off Leakage CurrentV I or V O 5.5V10P A74LCX16373DC Electrical Characteristics (Continued)Note 7: Outputs disabled or 3-STATE only.AC Electrical CharacteristicsNote 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t OSHL ) or LOW-to-HIGH (t OSLH ). Parameter guaranteed by design.Dynamic Switching CharacteristicsCapacitanceSymbol ParameterConditionsV CC T A 40q C to 85q C Units (V)MinMax I CC Quiescent Supply Current V I V CC or GND2.33.620P A 3.6V d V I , V O d 5.5V (Note 7) 2.3 3.6r 20'I CCIncrease in I CC per InputV IH V CC 0.6V2.33.6500P ASymbolParameterT A 40q C to 85q C, R L 500:UnitsV CC 3.3V r 0.3VV CC 2.7V V CC 2.5V r 0.2VC L 50 pF C L 50 pF C L 30 pF MinMax Min Max Min Max t PHL Propagation Delay 1.5 5.4 1.5 5.9 1.5 6.5ns t PLH I n to O n1.5 5.4 1.5 5.9 1.5 6.5t PHL Propagation Delay 1.5 5.5 1.5 6.4 1.5 6.6ns t PLH LE to O n1.5 5.5 1.5 6.4 1.5 6.6t PZL Output Enable Time1.5 6.1 1.5 6.5 1.57.9ns t PZH 1.5 6.1 1.5 6.5 1.57.9t PLZ Output Disable Time 1.5 6.0 1.5 6.3 1.57.2ns t PHZ 1.5 6.01.5 6.31.57.2t S Setup Time, I n to LE 2.5 2.5 3.0ns t H Hold Time, I n to LE 1.5 1.5 2.0ns t W LE Pulse Width3.03.03.5ns t OSHL Output to Output Skew (Note 8) 1.0ns t OSLH1.0Symbol ParameterConditionsV CC T A 25q C Units (V)Typical V OLP Quiet Output Dynamic Peak V OL C L 50 pF, V IH 3.3V, V IL 0V 3.30.8V C L 30 pF, V IH 2.5V, V IL 0V 2.50.6V OLVQuiet Output Dynamic Valley V OLC L 50 pF, V IH 3.3V, V IL 0V 3.3 0.8VC L 30 pF, V IH 2.5V, V IL 0V2.50.6Symbol ParameterConditionsTypical Units C IN Input Capacitance V CC Open, V I 0V or V CC 7pF C OUT Output CapacitanceV CC 3.3V, V I 0V or V CC8pF C PDPower Dissipation CapacitanceV CC 3.3V, V I 0V or V CC , f 10 MHz20pF 674L C X 16373AC LOADING and WAVEFORMS Generic for LCX FamilyFIGURE 1. AC Test Circuit (C L includes probe and jig capacitance)Waveform for Inverting and Non-Inverting FunctionsPropagation Delay. Pulse Width and t rec Waveforms3-STATE Output Low Enable andDisable Times for Logic3-STATE Output High Enable andDisable Times for LogicSetup Time, Hold Time and Recovery Time for Logict rise and t fallFIGURE 2. Waveforms(Input Characteristics; f =1MHz, t r = t f = 3ns)Test Switch t PLH , t PHL Opent PZL , t PLZ 6V at V CC 3.3 r 0.3V, and 2.7V V CC x 2 at V CC 2.5 r 0.2Vt PZH , t PHZGNDSymbol V CC3.3V r 0.3V2.7V 2.5V r 0.2V V mi 1.5V 1.5V V CC /2V mo 1.5V 1.5V V CC /2V x V OL 0.3V V OL 0.3V V OL 0.15V V yV OH 0.3VV OH 0.3VV OH 0.15V74LCX16373 Schematic DiagramGeneric for LCX Family 874L C X 16373Physical Dimensionsinches (millimeters) unless otherwise noted54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm WidePackage Number BGA54A74LCX16373 Physical Dimensions inches (millimeters) unless otherwise noted (Continued)48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" WidePackage Number MS48A1074L C X 16373 L o w V o l t a g e 16-B i t T r a n s p a r e n t L a t c h w i t h 5V T o l e r a n t I n p u t s a n d O u t p u t sPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm WidePackage Number MTD48Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。
VCH16373ADGG资料
元器件交易网SSOP48:plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1TSSOP48:plastic thin shrink small outline package; 48 leads; body width 6.1mm SOT362-1Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.LIFE SUPPORT APPLICATIONSPhilips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.This data sheet contains preliminary data, and supplementary data will be published at a later date. PhilipsSemiconductors reserves the right to make changes at any time without notice in order to improve designand supply the best possible product.Philips Semiconductors811 East Arques AvenueP.O. Box 3409Sunnyvale, California 94088–3409Telephone 800-234-7381DEFINITIONSData Sheet Identification Product Status DefinitionObjective SpecificationPreliminary SpecificationProduct SpecificationFormative or in DesignPreproduction ProductFull ProductionThis data sheet contains the design target or goal specifications for product development. Specificationsmay change in any manner without notice.This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changesat any time without notice, in order to improve design and supply the best possible product.© Copyright Philips Electronics North America Corporation 1998All rights reserved. Printed in U.S.A.print code Date of release: 05-96。
HD74LVC16373A中文资料
HD74LVC16373A16-bit D-type Transparent Latches with 3-state OutputsADE-205-121B(Z)3rd EditionDecember 1996 DescriptionThe HD74LVC16373A has sixteen D type latches with three state outputs in a 48 pin package. When the latch enable input is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input (1G, 2G), all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Low voltage and high speed operation is suitable at the battery drive product (note type personal computer) and low power consumption extends the life of a battery for long time operation.Features• V CC = 2.0 V to 5.5 V• All inputs V IH (Max.) = 5.5 V (@V CC = 0 V to 5.5 V)• All outputs V OUT (Max.) = 5.5 V (@V CC = 0 V or output off state)• Typical V OL ground bounce < 0.8 V (@V CC = 3.3 V, Ta = 25°C)• Typical V OH undershoot > 2.0 V (@V CC = 3.3 V, Ta = 25°C)• High output current ±24 mA (@V CC = 3.0 V to 5.5 V)Function TableInputsG LE D Output QH X X ZL H L LL H H HL L X QlevelH: HighL:Low levelX:ImmaterialZ:High impedanceQ:Level of Q before the indicated steady input conditions were established.HD74LVC16373A Pin Arrangement2HD74LVC16373A3Absolute Maximum RatingsItemSymbol Ratings Unit ConditionsSupply voltage V CC –0.5 to 6.0V Input diode current I IK –50mA V I = –0.5 V Input voltage V I –0.5 to 6.0V Output diode current I OK –50mA V O = –0.5 V 50mA V O = V CC +0.5 V Output voltage V O –0.5 to V CC +0.5V Output "H" or "L"–0.5 to 6.0V Output "Z" or V CC :OFF Output current I O±50mA V CC , GND current / pin I CC or I GND 100mA Storage temperatureTstg–65 to +150°CNote:The absolute maximum ratings are values which must not individually be exceeded, and furthermore,no two of which may be realized at the same time.Recommended Operating ConditonsItemSymbol Ratings Unit Conditions Supply voltage V CC 1.5 to 5.5V Data hold 2.0 to 5.5V At operation Input / output voltageV I 0 to 5.5V G , LE, D V O0 to V CC V Output "H" or "L"0 to 5.5V Output "Z" or V CC :OFFOperating temperature Ta –40 to 85°C Output currentI OH –12mA V CC = 2.7 V –24*2mA V CC = 3.0 V to 5.5 V I OL12mA V CC = 2.7 V 24*2mA V CC = 3.0 V to 5.5 V Input rise / fall time *1t r , t f10ns/VNotes: 1.This item guarantees maximum limit when one input switches.Waveform : Refer to test circuit of switching characteristics.2.duty cycle ≤ 50%HD74LVC16373A4Electrical CharacteristicsTa = –40 to 85°CItem Symbol V CC (V)Min Max Unit Test Conditions Input voltageV IH 2.7 to 3.6 2.0—V 4.5 to 5.5V CC ×0.7—V V IL2.7 to3.6—0.8V4.5 to5.5—V CC ×0.3V Output voltageV OH2.7 to 5.5V CC –0.2—V I OH = –100 µA 2.7 2.2—V I OH = –12 mA3.0 2.4—V 3.0 2.2—V I OH = –24 mA4.53.8—V V OL2.7 to 5.5—0.2V I OL = 100 µA 2.7—0.4V I OL = 12 mA3.0—0.55V I OL = 24 mA4.5—0.55V Input currentI IN 0 to 5.5—±5.0µA V IN = 5.5 V or GND Off state output current I OZ 2.7 to 5.5—±5.0µA V IN = V CC , GNDV OUT = 5.5 V or GND Output leak currentI OFF0—20µA V IN / V OUT = 5.5 V Quiescent supply current I CC2.7 to3.6—±20µA V IN / V OUT = 3.6 to 5.5 V 2.7 to 5.5—20µA V IN = V CC or GND∆I CC3.0 to 3.6—500µAV IN = one input at(V CC –0.6)V,other inputs at V CC or GNDHD74LVC16373A5Switching CharacteristicsTa = –40 to 85°CItemSymbol V CC (V)Min Typ Max Unit From (Input)To (Output)Propagation delay timet PLH 2.7——7.7ns DQt PHL 3.3±0.3 1.5—7.0ns 5.0±0.5—— 5.5ns t PLH 2.7——8.0ns LEQt PHL3.3±0.3 2.0—7.0ns 5.0±0.5—— 5.5ns Output enable timet ZH 2.7——8.0ns GQt ZL3.3±0.3 1.5—7.0ns 5.0±0.5—— 6.0ns Output disable timet HZ 2.7——8.0ns GQt LZ3.3±0.3 1.5—7.0ns 5.0±0.5—— 6.0ns Setup timet su2.7 2.0——ns3.3±0.3 2.0——ns 5.0±0.52.0——ns Hold timet h2.7 1.5——ns3.3±0.3 1.5——ns 5.0±0.51.5——ns Pulse widtht w2.73.0——ns 3.3±0.3 3.0——ns 5.0±0.53.0——ns Between output pins skew *1t OSLH 2.7———ns t OSHL3.3±0.3—— 1.0ns 5.0±0.5—— 1.0ns Input capacitance C IN 2.7— 3.0—pF Output capacitance C O2.7—15.0—pFNote:1.This parameter is characterized but not tested.tos LH = | t PLHm – t PLHn |, tos HL = | t PHLm – t PHLn |HD74LVC16373A Test CircuitWaveforms – 16HD74LVC16373A Waveforms – 2Waveforms – 37HD74LVC16373A Waveforms – 48Hitachi CodeJEDECEIAJWeight (reference value)TTP-48DB——0.20 gUnit: mm*Dimension including the plating thickness Base material dimensionCautions1.Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,copyright, trademark, or other intellectual property rights for information contained in this document.Hitachi bears no responsibility for problems that may arise with third party’s rights, includingintellectual property rights, in connection with use of the information contained in this document.2.Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.3.Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,traffic, safety equipment or medical equipment for life support.4.Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installationconditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.5.This product is not designed to be radiation resistant.6.No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi.7.Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.Hitachi, Ltd.Semiconductor & Integrated Circuits.Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.Hitachi Asia Pte. Ltd.16 Collyer Quay #20-00Hitachi TowerSingapore 049318Tel: 535-2100Fax: 535-1533URLNorthAmerica : http:/Europe : /hel/ecg Asia (Singapore): .sg/grp3/sicd/index.htm Asia (Taiwan): /E/Product/SICD_Frame.htm Asia (HongKong): /eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htmHitachi Asia Ltd.Taipei Branch Office3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105)Tel: <886> (2) 2718-3666Fax: <886> (2) 2718-8180Hitachi Asia (Hong Kong) Ltd.Group III (Electronic Components)7/F., North Tower, World Finance Centre,Harbour City, Canton Road, Tsim Sha Tsui,Kowloon, Hong Kong Tel: <852> (2) 735 9218Fax: <852> (2) 730 0281 Telex: 40815 HITEC HXHitachi Europe Ltd.Electronic Components Group.Whitebrook ParkLower Cookham Road MaidenheadBerkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000Fax: <44> (1628) 778322Hitachi Europe GmbHElectronic components Group Dornacher Stra§e 3D-85622 Feldkirchen, Munich GermanyTel: <49> (89) 9 9180-0Fax: <49> (89) 9 29 30 00Hitachi Semiconductor (America) Inc.179 East Tasman Drive,San Jose,CA 95134 Tel: <1> (408) 433-1990Fax: <1>(408) 433-0223For further information write to:。
74VCX162827MTDX技术手册
© 2004 Fairchild Semiconductor Corporation DS500138March 1998Revised October 200474VCX162827 Low Voltage 20-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs and 26Ω Series Resistors in the Outputs74VCX162827Low Voltage 20-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs and 26Ω Series Resistors in the OutputsGeneral DescriptionThe VCX162827 contains twenty non-inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is byte controlled. Each byte has NOR output enables for maximum control flexibility.The 74VCX162827 is designed for low voltage (1.4V to 3.6V) V CC applications with I/O capability up to 3.6V. The VCX162827 is also designed with 26Ω resistors in the out-puts.The 74VCX162827 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain-ing low CMOS power dissipation.Featuress 1.4V–3.6V V CC supply operation s 3.6V tolerant inputs and outputs s 26Ω series resistors in outputs s t PD3.4 ns max for 3.0V to 3.6V V CCs Power-off high impedance inputs and outputs s Supports live insertion and withdrawal (Note 1)s Static Drive (I OH /I OL )±12 mA @ 3.0V V CCs Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 300 mA s ESD performance:Human body model > 2000V Machine model > 200VNote 1: To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.Ordering Code:Devices also available in T ape and Reel. Specify by appending the suffix “X ” to the ordering code.Logic Symbol Pin DescriptionsOrder Number Package NumberPackage Description74VCX162827MTDMTD5656-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm WidePin NamesDescriptionOE n Output Enable Input (Active LOW)I 0–I 19Inputs O 0–O 19Outputs 274V C X 162827Connection Diagram Truth TablesH = HIGH Voltage Level L = LOW Voltage LevelX = Immaterial (HIGH or LOW, inputs may not float)Z = High ImpedanceFunctional DescriptionThe 74VCX162827 contains twenty non-inverting buffers with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of each other. The control pins may be shorted together to obtain full 20-bit operation. The 3-STATE outputs are controlled by Output Enable (OE n ) inputs. When OE 1, and OE 2 are LOW, O 0–O 10 are in the 2-state mode. When either OE 1 or OE 2 are HIGH, the standard outputs are in the high imped-ance mode but this does not interfere with entering new data into the inputs. The same applies for byte two with OE 3 and OE 4.Logic DiagramsInputsOutputs OE 1OE 2I 0–I 9O 0–O 9L L L L L L H H H X X Z XH XZ InputsOutputs OE 3OE 4I 0–I 9O 10–O 19L L L L L L H H H X X Z XHX Z74VCX162827Absolute Maximum Ratings (Note 2)Recommended Operating Conditions (Note 4)Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Rat-ings. The “Recommended Operating Conditions ” table will define the condi-tions for actual device operation.Note 3: I O Absolute Maximum Rating must be observed.Note 4: Floating or unused inputs must be held HIGH or LOW.DC Electrical CharacteristicsSupply Voltage (V CC )−0.5V to +4.6V DC Input Voltage (V I )−0.5V to +4.6V Output Voltage (V O )Outputs 3-STATE −0.5V to +4.6V Outputs Active (Note 3)−0.5V to V CC + 0.5VDC Input Diode Current (I IK ) V I < 0V −50 mA DC Output Diode Current (I OK )V O < 0V −50 mA V O > V CC+50 mA DC Output Source/Sink Current (I OH /I OL )±50 mA DC V CC or GND Current per Supply Pin (I CC or GND)±100 mAStorage Temperature Range (T STG )−65°C to +150°CPower Supply Operating 1.4V to 3.6VInput Voltage −0.3V to +3.6VOutput Voltage (V O )Output in Active States 0V to V CC Output in 3-STATE 0.0V to 3.6VOutput Current in I OH /I OL V CC = 3.0V to 3.6V ±12 mA V CC = 2.3V to 2.7V ±8 mA V CC = 1.65V to 2.3V ±3 mA V CC = 1.4V to 1.6V±1 mAFree Air Operating Temperature (T A )−40°C to +85°CMinimum Input Edge Rate (∆t/∆V)V IN = 0.8V to 2.0V, V CC = 3.0V10 ns/VSymbol ParameterConditionsV CC Min MaxUnits(V)V IHHIGH Level Input Voltage2.7 -3.6 2.0V2.3 - 2.7 1.61.65 - 2.30.65 x V CC 1.4 - 1.60.65 x V CCV ILLOW Level Input Voltage2.7 -3.60.8V 2.3 - 2.70.71.65 - 2.30.35 x V CC 1.4 - 1.60.35 x V CCV OHHIGH Level Output VoltageI OH = −100 µA 2.7 - 3.6V CC - 0.2VI OH = −6 mA 2.7 2.2I OH = −8 mA 3.0 2.4I OH = −12 mA 3.0 2.2I OH = −100 µA 2.3 - 2.7V CC - 0.2I OH = −4 mA 2.3 2.0I OH = −6 mA 2.3 1.8I OH = −8 mA 2.3 1.7I OH = −100 µA 1.65 - 2.3V CC - 0.2I OH = −3 mA 1.65 1.25I OH = −100 µA 1.4 - 1.6V CC - 0.2I OH = −1 mA1.41.05 474V C X 162827DC Electrical Characteristics (Continued)Note 5: Outputs disabled or 3-STATE only.AC Electrical Characteristics (Note 6)Note 6: For C L = 50 P F, add approximately 300 ps to the AC maximum specification.Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t OSHL ) or LOW-to-HIGH (t OSLH ).Symbol ParameterConditionsV CC Min Max Units(V)V OLLOW Level Output VoltageI OL = 100 µA 2.7 - 3.60.2VI OL = 6 mA 2.70.4I OL = 8 mA 3.00.55I OL = 12 mA 3.00.8I OL = 100 µA 2.3 - 2.70.2I OL = 6 mA 2.30.4I OL = 8 mA 2.30.6I OL = 100 µA 1.65 - 2.30.2I OL = 3 mA 1.650.3I OL = 100 µA 1.4 - 1.60.2I OL = 1 mA1.40.35I I Input Leakage Current 0 ≤ V I ≤ 3.6V 1.4 - 3.6±5.0µA I OZ 3-STATE Output Leakage 0 ≤ V O ≤ 3.6V 1.4 - 3.6±10.0µA V I = V IH or V IL I OFF Power-OFF Leakage Current 0 ≤ (V I , V O ) ≤ 3.6V 010.0µA I CC Quiescent Supply Current V I = V CC or GND1.4 - 3.620.0µA V CC ≤ (V I , V O ) ≤ 3.6V (Note 5) 1.4 - 3.6±20.0∆I CCIncrease in I CC per InputV IH = V CC −0.6V2.7 -3.6750µASymbol ParameterConditionsV CC T A = −40°C to +85°C UnitsFigure (V)Min Max Number t PHL Propagation DelayC L = 30 pF, R L = 500Ω3.3 ± 0.30.8 3.4nsFigures 1, 2t PLH2.5 ± 0.2 1.0 4.11.8 ± 0.15 1.58.2C L = 15 pF, R L = 2k Ω1.5 ± 0.1 1.016.4Figures 5, 6t PZL Output Enable TimeC L = 30 pF, R L = 500Ω3.3 ± 0.30.84.3nsFigures 1, 3, 4t PZH2.5 ± 0.2 1.0 5.91.8 ± 0.15 1.59.8C L = 15 pF, R L = 2k Ω1.5 ± 0.1 1.019.6Figures 5, 7, 8t PLZ Output Disable TimeC L = 30 pF, R L = 500Ω3.3 ± 0.30.84.3nsFigures 1, 3, 4t PHZ2.5 ± 0.2 1.0 4.91.8 ± 0.15 1.58.8C L = 15 pF, R L = 2k Ω1.5 ± 0.1 1.017.6Figures 5, 7, 8t OSHL Output to Output Skew C L = 30 pF, R L = 500Ω3.3 ± 0.30.5nst OSLH(Note 7)2.5 ± 0.20.51.8 ± 0.150.75C L = 15 pF, R L = 2k Ω1.5 ± 0.11.574VCX162827Dynamic Switching CharacteristicsCapacitanceSymbol ParameterConditionsV CC T A = +25°C Units(V)Typical V OLPQuiet Output Dynamic Peak V OLC L = 30 pF, V IH = V CC , V IL = 0V1.80.152.50.25V3.30.35V OLVQuiet Output Dynamic Valley V OLC L = 30 pF, V IH = V CC , V IL = 0V1.8−0.152.5−0.25V3.3−0.35V OHVQuiet Output Dynamic Valley V OHC L = 30 pF, V IH = V CC , V IL = 0V1.8 1.552.5 2.05V3.32.65Symbol ParameterConditionsT A = +25°C Units Typical C IN Input Capacitance V CC = 1.8, 2.5V or 3.3V, V I = 0V or V CC 6.0pF C OUT Output CapacitanceV I = 0V or V CC , V CC = 1.8V, 2.5V or 3.3V7.0pF C PDPower Dissipation CapacitanceV I = 0V or V CC , f = 10 MHz, V CC = 1.8V, 2.5V or 3.3V20.0pF 674V C X 162827AC Loading and Waveforms (V CC3.3V ± 0.3V to 1.8V ± 0.15V)FIGURE 1. AC Test CircuitFIGURE 2. Waveform for Inverting and Non-Inverting FunctionsFIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage LogicFIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage LogicTEST SWITCH t PLH , t PHL Opent PZL , t PLZ 6V at V CC = 3.3 ± 0.3V;V CC x 2 at V CC = 2.5 ± 0.2V; 1.8V ± 0.15Vt PZH , t PHZGNDSymbol V CC3.3V ± 0.3V2.5V ± 0.2V 1.8V ± 0.15VV mi 1.5V V CC /2V CC /2V mo 1.5V V CC /2V CC /2V X V OL + 0.3V V OL + 0.15V V OL + 0.15V V YV OH − 0.3VV OH − 0.15VV OH − 0.15V74VCX162827AC Loading and Waveforms (VCC 1.5V ± 0.1V)FIGURE 5. AC Test CircuitFIGURE 6. Waveform for Inverting and Non-Inverting FunctionsFIGURE 7. 3-STATE Output High Enable and Disable Times for Low Voltage LogicFIGURE 8. 3-STATE Output Low Enable and Disable Times for Low Voltage LogicTEST SWITCH t PLH , t PHL Opent PZL , t PLZ V CC x 2 at V CC = 1.5 ± 0.1Vt PZH , t PHZGNDSymbol V CC 1.5V ± 0.1V V mi V CC /2V mo V CC /2V X V OL + 0.1V V YV OH − 0.1V874V C X 162827 L o w V o l t a g e 20-B i t B u f f e r /L i n e D r i v e r w i t h 3.6V T o l e r a n t I n p u t s a n d O u t p u t s a n d 26Ω S e r i e s R e s i s t o r s i n t h e O u t p u t sPhysical Dimensions inches (millimeters) unless otherwise noted56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm WidePackage Number MTD56Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。
TM1637四段数码管模块驱动
TM1637四段数码管模块驱动：轻松上手，点亮你的数字生活一、模块简介1. 支持共阴极或共阳极数码管；2. 内置键扫描电路，可驱动8个按键；3. 通过两个IO口与单片机通信，节省IO资源；4. 可调节显示亮度，满足不同环境需求。
二、模块接口及引脚功能TM1637四段数码管模块共有6个引脚，分别为VCC、GND、DIO、CLK、KEY1和KEY2。
各引脚功能如下：1. VCC：电源正极，接3.3V或5V电源；2. GND：电源负极，接GND；3. DIO：数据输入/输出引脚，与单片机IO口相连；4. CLK：时钟引脚，与单片机IO口相连；5. KEY1、KEY2：按键引脚，可接至单片机IO口，实现按键功能。
三、驱动原理TM1637四段数码管模块的驱动原理如下：1. 初始化：上电后，对TM1637进行初始化，设置显示亮度、扫描频率等参数；2. 数据写入：通过DIO和CLK引脚，将显示数据写入TM1637内部寄存器；3. 显示更新：TM1637内部自动扫描数码管，根据寄存器中的数据更新显示内容；4. 按键扫描：TM1637内置键扫描电路，可实时检测按键状态，并将结果输出至单片机。
四、编程控制1. 引入TM1637库文件；2. 初始化TM1637对象，并设置CLK和DIO引脚；3. 编写显示函数，将数据写入数码管；4. 编写按键扫描函数，检测按键状态。
include <TM1637.h>// 定义CLK和DIO引脚define CLK 2define DIO 3TM1637 tm1637(CLK, DIO);void setup() {// 初始化TM1637tm1637.init();// 设置显示亮度（07）tm1637.setBrightness(5);}void loop() {// 显示数字09for (int i = 0; i < 10; i++) {tm1637.display(i);delay(1000);}}五、模块应用场景1. 时间显示：制作时钟、计时器等，实时展示时间信息；2. 温度显示：配合温度传感器，实时监测环境温度；3. 电压/电流显示：用于电子秤、电源等设备，显示电压或电流值；4. 计数器：用于运动会、比赛等场合，记录选手成绩或得分；5. 智能家居：作为家居设备的一部分，显示各种传感器数据。
74vcx16245低压cmos 16位双向3态总线收发器说明书
1/14November 2003s 3.6V TOLERANT INPUTS AND OUTPUTSsHIGH SPEED:t PD =2.5ns (MAX.)at V CC =3.0to 3.6V t PD =3.2ns (MAX.)at V CC =2.3to 2.7V t PD =5.7ns (MAX.)at V CC =1.8VsPOWER DOWN PROTECTION ON INPUTS AND OUTPUTSsSYMMETRICAL OUTPUT IMPEDANCE:|I OH |=I OL =24mA (MIN)at V CC =3.0V |I OH |=I OL =18mA (MIN)at V CC =2.3V |I OH |=I OL =6mA (MIN)at V CC =1.8V sOPERATING VOLTAGE RANGE:V CC (OPR)=1.8V to 3.6VsPIN AND FUNCTION COMPATIBLE WITH 74SERIES 16240sLATCH-UP PERFORMANCE EXCEEDS 300mA (JESD 17)sESD PERFORMANCE:HBM >2000V (MIL STD 883method 3015);MM >200VDESCRIPTIONThe 74VCX16245is a low voltage CMOS 16BIT BUS TRANSCEIVER (3-STATE)fabricated with sub-micron silicon gate and five-layer metal wiring C 2MOS technology.It is ideal for low power and very high speed 1.8to 3.6V applications;it can be interfaced to 3.6V signal environment for both inputs and outputs.This IC is intended for two-way asynchronous communication between data buses;the direction of data transmission is determined by DIR input.The two enable inputs nG can be used to disable the device so that the buses are effectively isolated.All inputs and outputs are equipped with protection circuits against static discharge,giving them 2KV ESD immunity and transient excess voltage.All floating bus terminals during High Z State must be held HIGH or LOW.74VCX16245LOW VOLTAGE CMOS 16-BIT BUS TRANSCEIVER(3-STATE)WITH 3.6V TOLERANT INPUTS ANDOUTPUTSORDER CODESPACKAGE TUBE T &RTSSOP 74VCX16245TTR TFBGA74VCX16245LBRPIN CONNECTIONOb s o l e t e P r o d uc t (s ) - r od u c t (s ) O b s o le t e P r o d u c t (s ) - o l e t e P r o d74VCX16245INPUT AND OUTPUT EQUIVALENT CIRCUITPIN CONNECTION(top view for TSSOP,top through view for BGA)2/14O b s ol e te Pr o du ct(s)-74VCX162453/14PIN DESCRIPTIONTRUTH TABLEX:Don‘t CareZ:High Impedance IEC LOGIC SYMBOLSPIN N°FOR TSSOP PIN N°FOR TFBGA SYMBOL NAME AND FUNCTION 1A31DIR Directional Control 2,3,5,6,8,9,11,12A1,B2,B1,C2,C1,D2,D1,E21B1to1B8Data Inputs/Outputs13,14,16,17,19,20,22,23E1,F2,F1,G2,G1,H2,H1,J12B1to2B8Data Inputs/Outputs 24J32DIR Directional Control25J42G Output Enable Input36,35,33,32,30,29,27,26E6,F5,F6,G5,G6,H5,H6,J62A1to2A8Data Inputs/Outputs47,46,44,43,41,40,38,38A6,B5,B6,C5,C6,D5,D6,E51A1to1A8Data Inputs/Outputs 48A41G Output Enable Input4,10,15,21,28,34,39,45D3,D4,E3,E4,F3,F4GND Ground(0V) 7,18,31,42C3,G3,C4,G4V CC Positive Supply VoltageA2,A5,B3,B4,H3,H4,J2,J5N.C.No ConnectINPUTS FUNCTION OUTPUTG DIR A BUS B BUS YnL L OUTPUT INPUT A=BL H INPUT OUTPUT B=AH X Z Z ZO b s ol e te Pr o du ct(s)-u ct(s)Ob s o l e t e P r o d uc t (s ) - O b s o l e t e P r od u c t (s ) 74VCX162454/14ABSOLUTE MAXIMUM RATINGSAbsolute Maximum Ratings are those values beyond which damage to the device may occur.Functional operation under these conditions isnot implied1)I O absolute maximum rating must be observed 2)V O <GNDRECOMMENDED OPERATING CONDITIONS1)V IN from 0.8V to 2V at V CC =3.0VSymbol ParameterValue Unit V CC Supply Voltage -0.5to +4.6V V I DC Input Voltage-0.5to +4.6V V O DC Output Voltage (OFF State)-0.5to +4.6V V O DC Output Voltage (High or Low State)(note 1)-0.5to V CC +0.5V I IK DC Input Diode Current-50mA I OK DC Output Diode Current (note 2)-50mA I ODC Output Current±50mA I CC or I GND DC V CC or Ground Current per Supply Pin±100mA P DPower Dissipation (for TSSOP)400mW T stg Storage Temperature-65to +150°C T LLead Temperature (10sec -for TSSOP)300°CSymbol ParameterValue Unit V CC Supply Voltage 1.8to 3.6V V I Input Voltage-0.3to 3.6VV OOutput Voltage (OFF State)0to 3.6VV OOutput Voltage (High or Low State)0to V CCVI OH ,I OL High or Low Level Output Current (V CC =3.0to 3.6V)±24mA I OH ,I OL High or Low Level Output Current (V CC =2.3to 2.7V)±18mA I OH ,I OL High or Low Level Output Current (V CC =1.8V)±6mAT op Operating Temperature-55to 125°Cdt/dvInput Rise and Fall Time (note 1)0to 10ns/VO b s o l e t e P r o d u c t (s ) - O b s o l e t e P r o d u c t (s )Ob s o l e t e P r o d uc t (s ) - O b s o l e t e P r od u c t (s ) 74VCX162455/14DC SPECIFICATIONS (2.7V <V CC <3.6V unless otherwise specified)SymbolParameterTest ConditionValueUnitV CC (V)-40to 85°C -55to 125°C Min.Max.Min.Max.V IH High Level Input Voltage2.7to3.62.02.0VV IL Low Level Input Voltage0.80.8V OHHigh Level Output Voltage2.7to3.6I O =-100µA V CC -0.2V CC -0.2V2.7I O =-12mA 2.2 2.23.0I O =-18mA 2.4 2.4I O =-24mA 2.22.2V OLLow Level OutputVoltage2.7to3.6I O =100µA 0.20.2V2.7I O =12mA0.40.43.0I O =18mA 0.40.4I O =24mA0.550.55I I Input Leakage Current2.7to3.6V I =0to 3.6V±5±5µAI off Power Off Leakage CurrentV I or V O =0to 3.6V 1010µAI OZ High Impedance Output Leakage Current2.7to3.6V I =V IH or V IL V O =0to 3.6V±10±10µAI CCQuiescent Supply Current2.7to3.6V I =V CC or GND 2020µA V I or V O =V CC to3.6V±20±20∆I CCI CC incr.per Input2.7to3.6V IH =V CC -0.6V750750µAO b s o l e t e P r o d u c t (s ) - O b s o l e t e P r o d u c t (s )Ob s o l e t e P r o d uc t (s ) - O b s o l e t e P r od u c t (s ) 74VCX162456/14DC SPECIFICATIONS (2.3V <V CC <2.7V unless otherwise specified)DC SPECIFICATIONS(1.8V <V CC <2.3V unless otherwise specified)SymbolParameterTest ConditionValueUnitV CC (V)-40to 85°C -55to 125°C Min.Max.Min.Max.V IH High Level Input Voltage2.3to 2.71.61.6VV IL Low Level Input Voltage0.70.7V OHHigh Level Output Voltage2.3to 2.7I O =-100µA V CC -0.2V CC -0.2V2.3I O =-6mA 2.0 2.0I O =-12mA 1.8 1.8I O =-18mA 1.71.7V OLLow Level OutputVoltage2.3to 2.7I O =100µA 0.20.2V2.3I O =12mA0.40.4I O =18mA0.60.6I I Input Leakage Current2.3to 2.7V I =0to 3.6V±5±5µAI off Power Off Leakage CurrentV I or V O =0to 3.6V 1010µAI OZ High Impedance Output Leakage Current2.3to 2.7V I =V IH or V IL V O =0to 3.6V±10±10µAI CCQuiescent Supply Current2.3to 2.7V I =V CC or GND 2020µAV I or V O =V CC to3.6V±20±20Symbol ParameterTest ConditionValueUnitV CC (V)-40to 85°C -55to 125°C Min.Max.Min.Max.V IH High Level Input Voltage1.8to2.30.7VCC 0.7VCC VV ILLow Level Input Voltage0.2VCC 0.2VCC VV OH High Level Output Voltage1.8I O =-100µA V CC -0.2V CC -0.2VI O =-6mA 1.41.4V OL Low Level Output Voltage1.8I O =100µA0.20.2VI O =6mA 0.30.3I IInput Leakage Current1.8V I =0to 3.6V±5±5µAI offPower Off Leakage Current0V I or V O =0to 3.6V 1010µA I OZ High Impedance Output Leakage Current1.8V I =V IH or V IL V O =0to 3.6V ±10±10µAI CCQuiescent Supply Current1.8V I =V CC or GND 2020µAV I or V O =V CC to3.6V±20±20O b s o l e t e P r o d u c t (s ) - O b s o l e t e P r o d u c t (s )Ob s o l e t e P r o d uc t (s ) - O b s o l e t e P r od u c t (s ) 74VCX162457/14DYNAMIC SWITCHING CHARACTERISTICS (T a =25°C,Input t r =t f =2.0ns,C L =30pF,R L =500Ω)1)Number of outputs defined as "n".Measured with "n-1"outputs switching from HIGH to LOW or LOW to HIGH.The remaining output ismeasured in the LOW state.2)Number of outputs defined as "n".Measured with "n-1"outputs switching from HIGH to LOW or LOW to HIGH.The remaining output is measured in the HIGH state.3)Parameters guaranteed by design.AC ELECTRICAL CHARACTERISTICS (C L =30pF,R L =500Ω, Input t r =t f =2.0ns )1)Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-ing in the same direction,either HIGH or LOW (t OSLH =|t PLHm -t PLHn |,t OSHL =|t PHLm -t PHLn |)2)Parameter guaranteed by designCAPACITIVE CHARACTERISTICS1)C PD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.(Refer to Test Circuit).Average operating current can be obtained by the following equation.I CC(opr)=C PD x V CC x f IN +I CC /16(per circuit)SymbolParameterTest ConditionValue UnitV CC (V)T A =25°C Min.Typ.Max.V OLPDynamic Low Voltage Quiet Output (note 1,3)1.8V IL =0V V IH =V CC 0.25V2.50.63.30.8V OLVDynamic Low Voltage Quiet Output (note 1,3)1.8V IL =0V V IH =V CC -0.25V2.5-0.63.3-0.8V OHVDynamic High Voltage Quiet Output (note 2,3)1.8V IL =0V V IH =V CC1.5V2.5 1.93.32.2Symbol ParameterTest ConditionValueUnitV CC (V)-40to 85°C -55to 125°C Min.Max.Min.Max.t PLH t PHLPropagation Delay Time1.8 1.5 5.7 1.57.0ns2.3to 2.7 1.03.2 1.04.03.0to 3.60.8 2.50.8 3.4t PZL t PZHOutput Enable Time1.8 1.57.5 1.59.0ns2.3to 2.7 1.0 4.9 1.0 6.03.0to 3.60.8 3.80.84.7t PLZ t PHZOutput Disable Time1.8 1.5 5.5 1.5 6.8ns2.3to 2.7 1.0 4.2 1.0 5.03.0to 3.60.83.70.84.6t OSLH t OSHL Output To OutputSkew Time (note1,2)1.80.50.5ns2.3to 2.70.50.53.0to 3.60.50.5Symbol ParameterTest Condition ValueUnitV CC (V)T A =25°C Min.Typ.Max.C IN Input Capacitance 1.8,2.5or 3.3V IN =0or V CC 4pF C OUT Output Capacitance1.8,2.5or3.3V IN =0or V CC 8pF C PDPower Dissipation Capacitance (note 1)1.8,2.5or3.3f IN =10MHz V IN =0or V CC28pFO b s o l e t e P r o d u c t (s ) - O b s o l e t e P r o d u c t (s )Ob s o l e t e P r o d uc t (s ) - O b s o l e t e P r od u c t (s ) 74VCX162458/14TEST CIRCUITC L =30pF or equivalent (includes jig and probe capacitance)R L =R1=500Ω or equivalentR T =Z OUT of pulse generator (typically 50Ω)WAVEFORM SYMBOL VALUESTESTSWITCH t PLH ,t PHLOpen t PZL ,t PLZ (V CC =3.0to 3.6V)6V t PZL ,t PLZ (V CC =2.3to 2.7V or 1.8V)2V CC t PZH ,t PHZGNDSymbol V CC3.0to 3.6V 2.3to 2.7V1.8V V IH2.7V V CC V CCV M 1.5VV CC /2V CC /2V X V OL +0.3V V OL +0.15V V OL +0.15V V YV OH -0.3VV OH -0.15VV OH -0.15VO b s o l e t e P r o d u c t (s ) - O b s o l e t e P r o d74VCX16245 WAVEFORM1:PROPAGATION DELAYS(f=1MHz;50%duty cycle)WAVEFORM2:OUTPUT ENABLE AND DISABLE TIME(f=1MHz;50%duty cycle)9/14Ob s o l e t e P r o d uc t (s ) - O b s o l e t e P r od u c t (s ) 14/14Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIESAustralia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.O b s o l e t e P r o d u c t (s ) - O b s o l e t e P r o d u c t (s )。
74VHC373MTCX资料
TL F 1155574VHC373 74VHCT373 Octal D-Type Latch with TRI-STATE OutputsNovember199574VHC373 74VHCT373Octal D-Type Latch with TRI-STATE OutputsGeneral DescriptionThe VHC VHCT373is an advanced high speed CMOS octalD-type latch with TRI-STATE output fabricated with silicongate CMOS technology It achieves the high speed opera-tion similar to equivalent Bipolar Schottky TTL while main-taining the CMOS low power dissipation This8-bit D-typelatch is controlled by a latch enable input(LE)and an outputenable input(OE) The latches appear transparent to datawhen latch enable(LE)is HIGH When LE is low the datathat meets the setup time is latched When the OE input ishigh the eight outputs are in a high impedance stateAn input protection circuit ensures that0V–7V can be ap-plied to the input pins without regard to the supply voltageThis device can be used to interface5V to3V systems andtwo supply systems such as battery back up This circuitprevents device destruction due to mismatched supply andinput voltagesFeaturesY High Noise ImmunityVHC V NIH e V NIL e28%V CC(Min)VHCT V IH e2 0V V IL e0 8VY Power Down ProtectionVHC Inputs OnlyVHCT Inputs and OutputsY Low NoiseVHC V OLP e0 6V(typ)VHCT V OLP e0 8V(typ)Y Low Power DissipationI CC e4m A(Max) T a e25 CY Balanced Propagation Delays t PLH j t PHLY Pin and Function Compatible with74HC HCT373CommercialPackagePackage DescriptionNumber74VHC373M M20B20-Lead Molded JEDEC SOIC74VHC373SJ M20D20-Lead Molded EIAJ SOIC74VHC373MSC MSC2020-Lead Molded EIAJ Type1SSOP74VHC373MTC MTC2020-Lead Molded JEDEC Type1TSSOP74VHC373N N20A20-Lead Molded DIP74VHCT373M M20B20-Lead Molded JEDEC SOIC74VHCT373SJ M20D20-Lead Molded EIAJ SOIC74VHCT373MTC MTC2020-Lead Molded JEDEC Type1TSSOP74VHCT373N N20A20-Lead Molded DIPNote Surface mount packages are also available on Tape and Reel Specify by appending the suffix letter‘‘X’’to the ordering code EIAJ Type1SSOP available on Tape and Reel only order MSCXLogic SymbolIEEE IECTL F 11555–1Connection DiagramPin Assignment forDIP SSOP TSSOP and SOICTL F 11555–2Pin Names DescriptionD0–D7Data InputsLE Latch Enable InputOE Output Enable InputO0–O7TRI-STATE OutputsTRI-STATE is a registered trademark of National Semiconductor CorporationC1995National Semiconductor Corporation RRD-B30M125 Printed in U S AFunctional DescriptionThe VHC VHCT373contains eight D-type latches with TRI-STATE standard outputs When the Latch Enable(LE)input is HIGH data on the D n inputs enters the latches In this condition the latches are transparent i e a latch output will change state each time its D input changes When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW tran-sition of LE The TRI-STATE standard outputs are con-trolled by the Output Enable(OE)input When OE is LOW the standard outputs are in the2-state mode When OE is HIGH the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches Truth TableInputs Outputs LE OE D n O nX H X ZH L L LH L H HL L X O0H e HIGH Voltage LevelL e LOW Voltage LevelZ e High ImpedanceX e ImmaterialO0e Previous O0before HIGH to Low transition of Latch EnableLogic DiagramTL F 11555–3 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays2Absolute Maximum Ratings(Note1) Supply Voltage(V CC)b0 5V to a7 0V DC Input Voltage(V IN)b0 5V to a7 0V DC Output Voltage(V OUT)VHC b0 5V to V CC a0 5V VHCT b0 5V to a7 0V Input Diode Current(I IK)b20mA Output Diode Current(VHC)g20mA(VHCT)b20mA DC Output Current(I OUT)g25mA DC V CC GND Current(I CC)g75mA Storage Temperature(T STG)b65 C to a150 C Lead Temperature(T L)(Soldering 10sec)260 C V OUT l V CC only if output is in H or Z state Note1 Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired The databook specifications should be met with-out exception to ensure that the system design is reliable over its power supply temperature and output input load-ing variables National does not recommend operation out-side databook specificationsRecommended Operating ConditionsSupply Voltage(V CC)VHC2 0V to a5 5V VHCT4 5V to a5 5V Input Voltage(V IN)0V to a5 5V Output Voltage(V OUT)0V to V CC Operating Temperature(T OPR)74VHC VHCT b40 C to a85 C Input Rise and Fall Time(t r t f)V CC e3 3V g0 3V(VHC only)0E100ns V V CC e5 0g0 5V0E20ns VDC Characteristics for’VHC Family DevicesSymbol Parameter V CC(V)74VHC74VHCUnits Conditions T A e a25 CT A e b40 Cto a85 CMin Typ Max Min MaxV IH High Level2 01 501 50VInput Voltage3 0b5 50 7V CC0 7V CCV IL Low Level2 00 500 50VInput Voltage3 0b5 50 3V CC0 3V CCV OH High Level2 01 92 01 9V IN e V IH I OH e b50m A Output3 02 93 02 9V or V ILVoltage4 54 44 54 43 02 582 48V I OH e b4mA4 53 943 80I OH e b8mAV OL Low Level2 00 00 10 1V IN e V IH I OL e50m A Output3 00 00 10 1V or V ILVoltage4 50 00 10 13 00 360 44V I OL e4mA4 50 360 44I OL e8mAI OZ TRI-STATE5 5g0 25g2 5m A V IN e V IH or V ILOutput Off-V OUT e V CC or GND State CurrentI IN Input Leakage0b5 5g0 1g1 0m A V IN e5 5or GNDCurrentI CC Quiescent5 54 040 0m A V IN e V CC or GNDSupplyCurrent3DC Characteristics for’VHC Family DevicesSymbol Parameter V CC(V)74VHCUnits Conditions T A e a25 CTyp LimitsV OLP Quiet Output Maximum Dynamic V OL5 00 60 9V C L e50pF V OLV Quiet Output Minimum Dynamic V OL5 0b0 6b0 9V C L e50pF V IHD Minimum High Level Dynamic Input Voltage5 03 5V C L e50pF V ILD Maximum Low Level Dynamic Input Voltage5 01 5V C L e50pF Parameter guaranteed by designDC Characteristics for’VHCT Family DevicesSymbol Parameter V CC(V)74VHCT74VHCTUnits Conditions T A e a25 CT A e b40 Cto a85 CMin Typ Max Min MaxV IH High Level Input Voltage4 52 02 0V5 52 02 0V IL Low Level Input Voltage4 50 80 8V5 50 80 8V OH High Level Output Voltage4 53 153 653 15V V IN e V IH I OH e b50m A4 52 52 4V or V IL I OH e b8mA V OL Low Level Output Voltage4 50 00 10 1V V IN e V IH I OL e50m A4 50 360 44V or V IL I OL e8mAI OZ TRI-STATE Output Off-State5 5g0 25g2 5m A V IN e V IH or V ILCurrent V OUT e V CC or GND I IN Input Leakage Current0–5 5g0 1g1 0m A V IN e5 5V or GND I CC Quiescent Supply Current5 54 040 0m A V IN e V CC or GNDI CCT Maximum I CC Input5 51 351 50mA V IN e3 4VOther Inputs e V CC or GNDI OPD Output Leakage Current0 0a0 5a0 5m A V OUT e5 5V(Power Down State)DC Characteristics for’VHCT Family DevicesSymbol Parameter V CC(V)74VHCTUnits Conditions T A e a25 CTyp LimitsV OLP Quiet Output Maximum Dynamic V OL5 00 81 2V C L e50pF V OLV Quiet Output Minimum Dynamic V OL5 0b0 8b1 2V C L e50pF V IHD Minimum High Level Dynamic Input Voltage5 02 0V C L e50pF V ILD Maximum Low Level Dynamic Input Voltage5 00 8V C L e50pF Parameter guaranteed by design4AC Electrical Characteristics for’VHC Family DevicesSymbol Parameter V CC(V)74VHC74VHCUnits Conditions T A e a25 CT A e b40 Cto a85 CMin Typ Max Min Maxt PLH Propagation3 3g0 37 011 01 013 0nsC L e15pFDelay Timet PHL9 514 51 016 5CL e50pF (LE to O n)5 0g0 54 97 21 08 5nsC L e15pF6 49 21 010 5C L e50pFt PLH Propagation3 3g0 37 311 41 013 5ns C L e15pFDelay Timet PHL9 814 91 017 0CL e50pF(D to O n)5 0g0 55 07 21 08 5C L e15pF6 59 21 010 5C L e50pFt PZL TRI-STATE3 3g0 37 311 41 013 5nsR L e1k X C L e15pFOutputt PZH9 814 91 017 0CL e50pF Enable Time5 0g0 55 58 11 09 5nsC L e15pF7 010 11 011 5C L e50pFt PLZ TRI-STATE3 3g0 39 513 21 015 0ns R L e1k X C L e50pFOutputt PHZ5 0g0 56 59 21 010 5C L e50pF DisableTimet OSLH Output to3 3g0 31 51 5ns (Note1)C L e50pFOutputt OSHL5 0g0 51 01 0C L e50pF SkewC IN Input41010pF V CC e OpenCapacitanceC OUT Output6pF V CC e5 0VCapacitanceC PD Power27pF (Note2)DissipationCapacitanceNote1 Parameter guaranteed by design t OSLH e l t PLH max b t PLH min l t OSHL e l t PHL max b t PHL min lNote2 C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load Average operating current can be obtained by the equation I CC(opr )e C PD V CC f IN a I CC 8(per Latch) The total C PD when n pcs of the Latch operates can be calculated by the equation C PD(total)e14a13nAC Operating Requirements for’VHC Family DevicesSymbol Parameter V CC(V)74VHC74VHCUnits Conditions T A e a25 CT A e b40 Cto a85 CMin Typ Max Min Maxt W(H)Minimum3 3g0 35 05 0ns Pulse Width5 0g0 55 05 0(LE)t S Minimum3 3g0 34 04 0ns Set-Up Time5 0g0 54 04 0t H Minimum3 3g0 31 01 0ns Hold Time5 0g0 51 01 05AC Electrical Characteristics for’VHCT Family DevicesSymbol Parameter V CC(V)74VHCT74VHCTUnits Conditions T A e a25 CT A e b40 Cto a85 CMin Typ Max Min Maxt PLH Propagation5 0g0 57 712 31 013 5nsC L e15pFDelay Timet PHL8 513 31 014 5CL e50pF (LE to O n)t PLH Propagation5 0g0 55 18 51 09 5nsC L e15pFDelay Timet PHL5 99 51 010 5CL e50pF(D to O n)t PZL TRI-STATE5 0g0 56 310 91 012 5nsR L e1k X C L e15pFOutputt PZH7 111 91 013 5CL e50pF Enable Timet PLZ TRI-STATE5 0g0 56 811 21 012 0ns R L e1k X C L e50pFOutput t PHZDisableTimet OSLH Output to5 0g0 51 01 0ns (Note1)Output t OSHLSkewC IN Input41010pF V CC e OpenCapacitanceC OUT Output9pF V CC e5 0VCapacitanceC PD Power(Note2)Dissipation27pFCapacitanceNote1 Parameter guaranteed by design t OSLH e l t PLH max b t PLH min l t OSHL e l t PHL max b t PHL min lNote2 C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load Average operating current can be obtained by the equation I CC(opr )e C PD V CC f IN a I CC 8(per F F)AC Operating Requirements for’VHCT Family DevicesSymbol Parameter V CC(V)74VHCT74VHCTUnits Conditions T A e a25 CT A e b40 Cto a85 CMin Typ Max Min Maxt W(H)Minimum5 0g0 56 56 5nsPulse Width(LE)t S Minimum5 0g0 51 51 5nsSet-Up Timet H Minimum5 0g0 53 53 5nsHold Time6Ordering InformationThe device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as followsTL F 11555–578Physical Dimensions inches(millimeters)20-Lead Small Outline Integrated Circuit JEDEC SOIC(M)Order Number74VHC373M 74VHC373MX 74VHCT373M or74VHCT373MXNS Package Number M20B20-Lead Plastic EIAJ SOIC(SJ)Order Number74VHC373SJ 74VHC373SJX 74VHCT373SJ or74VHCT373SJXNS Package Number M20D9Physical Dimensions millimeters(Continued)20-Lead Shrink Small Outline EIAJ SSOP Type I(MSC)Order Number74VHC373MSCXNS Package Number MSC2010Physical Dimensions millimeters(Continued)20-Lead Plastic JEDEC TSSOP Type I(MTC)Order Number74VHC373MTC 74VHC373MTCX 74VHCT373MTC or74VHCT373MTCXNS Package Number MTC201174V H C 373 74V H C T 373O c t a l D -T y p e L a t c h w i t h T R I -S T A T E O u t p u t s Physical Dimensions inches (millimeters)(Continued)20-Lead (0 300 Wide)Molded Dual-in-Line Package Order Number 74VHCT373N NS Package Number N20A LIFE SUPPORT POLICYNATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein1 Life support devices or systems are devices or2 A critical component is any component of a life systems which (a)are intended for surgical implantsupport device or system whose failure to perform can into the body or (b)support or sustain life and whosebe reasonably expected to cause the failure of the life failure to perform when properly used in accordancesupport device or system or to affect its safety or with instructions for use provided in the labeling caneffectiveness be reasonably expected to result in a significant injuryto the userNational SemiconductorNational Semiconductor National Semiconductor National Semiconductor CorporationEurope Hong Kong Ltd Japan Ltd 1111West Bardin Road Fax (a 49)0-180-530858613th Floor Straight Block Tel 81-043-299-2309。
TM1637驱动数码管教学内容
T M1637驱动数码管TM1637是一种带键盘扫描接口的LED(发光二极管显示器)驱动控制专用电路，内部集成有MCU数字接口，数据锁存器，LED高压驱动，键盘扫描等电路。
采用功率CMOS工艺，显示模式(8段×6位)，支持共阳数码管输出，键扫描(8×2bit)，增强型抗干扰按键识别电路，辉度调节电路(占空比8级可调)，两线串行接口(CLK,DIO)，振荡方式：内置RC振荡(450Khz+-5%)，内置上电复位电路，内置自动消隐电路。
引脚功能：当传输数据时，当SCL高电平时，DIO由高变低则代表开始信号，当SCL 高电平时，DIO由低变高则代表停止信号，只有当SCL低电平时DIO上的数据才可以发生改变，在SCL高电平时DIO上的数据要保持不变，此时数据发送出去，当正确传输8位数据后TM1637会第九个时钟在DIO管脚上给出一个ACK 信号，把DIO拉低。
传输时序类似于I2C通信。
传输数据是低位在前高位在后。
传输过程：下面仅是数码管驱动程序：(注有待改进)驱动的下面这种数码管，普通也行，只是看不到1s的闪烁效果。
/*********************************** Describe: TM1673控制芯片，可以设置时间的倒计时(定时不准，可以自己校准)，四个数码管0xc0,0xc1,0xc2,0xc3 **** Time: 2015.05.14**** Author: zys********************************/#include <reg52.h>#include<intrins.h>sbit CLK = P0^0; //时钟信号sbit DIO = P0^1; //数据/地址数据//共阴极数码管unsigned char code SEGData[]={0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d,0x07,0x7f,0x6f};//1-9unsigned char code SEGDataDp[]={0xbf,0x86,0xdb,0xcf,0xe6,0xed,0xfd,0x87,0xff,0xef}; //有小数点只用于地址0xc1 unsigned char dpFlag = 0; //控制第二个数码管的dp的显示void TM1637_start( void );void TM1637_stop( void );void TM1637_write1Bit(unsigned char mBit);void TM1637_write1Byte(unsigned char mByte);void TM1637_writeCammand(unsigned char mData);void TM1637_writeData(unsigned char addr, unsigned char mData);void time_set(char hour, char min);void time_judge( void );void time_display( void );void timer0_init( void );void delay_140us( void );void delay_1ms(unsigned int i);unsigned int countTime = 0;unsigned char time, sec;struct {char shi;char ge;}Hour;struct {char shi;char ge;}Min;/*********************************************************** ********** 主函数****************************************************************/ void main( void ){timer0_init();time_set(5, 0); //设置5小时倒计时while(1){time_display(); //显示时间if(countTime <= 10){dpFlag = 0;}elseif(countTime <= 20){dpFlag = 1;}else{countTime = 0;time_judge();}}}/******************************************************************** * 名称 : void time_set(char hour, char min)* 功能 : 设置时间* 输入 : char hour, char min* 输出 : 无**************************************************************/void time_set(char hour, char min){if((hour < 0) || (min<0)){hour = 0;min = 0;}Hour.shi = hour/10;Hour.ge = hour%10;Min.shi = min/10;Min.ge = min%10;}/************************************************************** 名称 : time_judge( void )* 功能 : 判断时间变化* 输入 : void* 输出 : 无**************************************************************/void time_judge( void ){if(++sec == 60) //60秒{sec = 0;if((Hour.shi || Hour.ge || Min.shi || Min.ge) && (--Min.ge <= -1)){Min.ge = 9;if((Hour.shi) ||(Hour.ge) && (--Min.shi <= -1)){Min.shi = 5;if(Hour.shi && (--Hour.ge <= -1)){Hour.ge = 9;if(--Hour.shi <= -1){Hour.shi = 0;}}elseif((!Hour.shi) && (--Hour.ge <= -1)){Hour.ge = 0;}}elseif((!Hour.shi) && (!Hour.ge) && (--Min.shi <= -1)){Min.shi = 0;}}elseif(((!Hour.shi) && (!Hour.ge) && (!Min.shi) ) && (Min.ge <= -1)){Min.ge = 0;}}}/********************************************************************* 名称 : void time_display( void )* 功能 : 显示时间* 输入 : void* 输出 : 无**************************************************************/void time_display( void ){TM1637_writeCammand(0x44);TM1637_writeData(0xc0, SEGData[Hour.shi]);if(dpFlag)TM1637_writeData(0xc1, SEGDataDp[Hour.ge]); //小数点标志为1则用小数点那个数组elseTM1637_writeData(0xc1, SEGData[Hour.ge]);TM1637_writeData(0xc2, SEGData[Min.shi]);TM1637_writeData(0xc3, SEGData[Min.ge]);TM1637_writeCammand(0x8a);}/********************************************************************* 名称 : void TM1637_start( void )* 功能 : start信号* 输入 : void* 输出 : 无**************************************************************/void TM1637_start( void ){CLK = 1;DIO = 1;delay_140us();DIO = 0;delay_140us();CLK = 0;delay_140us();}/******************************************************************** * 名称 : void TM1637_stop( void )* 功能 : stop信号* 输入 : void* 输出 : 无**************************************************************/void TM1637_stop( void ){CLK = 0;delay_140us();DIO = 0;delay_140us();CLK = 1;delay_140us();DIO = 1;delay_140us();}/******************************************************************** * 名称 : void TM1637_write1Bit(unsigned char mBit )* 功能 : 写1bit* 输入 : unsigned char mBit* 输出 : 无**************************************************************/void TM1637_write1Bit(unsigned char mBit ){CLK = 0;delay_140us();if(mBit)DIO = 1;elseDIO = 0;delay_140us();CLK = 1;delay_140us();}/******************************************************************** * 名称 : void TM1637_write1Byte(unsigned char mByte)* 功能 : 写1byte* 输入 : unsigned char mByte* 输出 : 无**************************************************************/void TM1637_write1Byte(unsigned char mByte){char loop = 0;for(loop = 0; loop < 8; loop++){TM1637_write1Bit((mByte>>loop)&0x01); //取得最低位}CLK = 0;delay_140us();DIO = 1;delay_140us();CLK = 1;delay_140us();while(DIO == 1); //获得应答位}/******************************************************************** * 名称 : void TM1637_writeCammand(unsigned char mData)* 功能 : 写指令1byte* 输入 : unsigned char mData* 输出 : 无**************************************************************/void TM1637_writeCammand(unsigned char mData){TM1637_start();TM1637_write1Byte(mData); //数据TM1637_stop();}/********************************************************************* 名称 : void TM1637_writeData(unsigned char addr, unsigned char mData)* 功能 : 固定地址写数据1byte* 输入 : unsigned char addr, unsigned char mData* 输出 : 无**************************************************************/void TM1637_writeData(unsigned char addr, unsigned char mData){TM1637_start();TM1637_write1Byte(addr); //地址TM1637_write1Byte(mData); //数据TM1637_stop();}/********************************************************************* 名称 : void timer0_init()* 功能 : 定时50ms，实际运行中由于指令运行造成的延时，实际时间肯定大于50ms * 输入 : 无* 输出 : 无**************************************************************/void timer0_init( void ){TMOD=0X01;TH0=(65535-50000)/256;TL0=(65535-50000)%256;ET0=1;EA=1;TR0=1;}/********************************************************************* 名称 :* 功能 : 定时50ms，实际运行中由于指令运行造成的延时，实际时间肯定大于50ms * 输入 : 无* 输出 : 无**************************************************************/void timer0_isr() interrupt 1{TH0=(65535-50000)/256; //50msTL0=(65535-50000)%256; //countTime++;}精品文档/********************************************************************* 名称 : Delay_1ms(unsigned int i)* 功能 : 延时子程序，延时时间为 140us* 输入 :* 输出 : 无**************************************************************/void delay_140us( void ){int i;for(i=0; i<20; i++)_nop_();}/********************************************************************* 名称 : Delay_1ms(unsigned int i)* 功能 : 延时子程序，延时时间为 1ms * x* 输入 : x (延时一毫秒的个数)* 输出 : 无***********************************************************************/ /*void Delay_1ms(unsigned int i)//1ms延时{unsigned char x,j;for(j=0;j<i;j++)for(x=0;x<=148;x++);}*/收集于网络，如有侵权请联系管理员删除。
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© 2005 Fairchild Semiconductor Corporation DS500065October 1997Revised June 200574VCX16373 Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs74VCX16373Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and OutputsGeneral DescriptionThe VCX16373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applica-tions. The device is byte controlled. The flip-flops appear to be transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state.The 74VCX16373 is designed for low voltage (1.2V to 3.6V) V CC applications with I/O compatibility up to 3.6V.The 74VCX16373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain-ing low CMOS power dissipation.Featuress 1.2V to 3.6V V CC supply operation s 3.6V tolerant inputs and outputs s t PD (I n to O n )3.0 ns max for 3.0V to 3.6V V CCs Power-off high impedance inputs and outputs s Support live insertion and withdrawal (Note 1)s Static Drive (I OH /I OL )r 24 mA @ 3.0V V CCs Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 300 mA s ESD performance:Human body model ! 2000V Machine model ! 200Vs Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary)Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.Ordering Code:Note 2: Ordering Code “G” indicates Trays.Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.Logic SymbolOrder Number Package Number Package Description74VCX16373G (Note 2)(Note 3)BGA54A (Preliminary)54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide74VCX16373MTD (Note 3)MTD4848-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 274V C X 16373Connection DiagramsPin Assignment for TSSOPPin Assignment for FBGA(Top Thru View)Pin DescriptionsFBGA Pin AssignmentsTruth TablesH HIGH Voltage Level L LOW Voltage LevelX Immaterial (HIGH or LOW, inputs may not float)Z High ImpedanceO 0 Previous O 0 before HIGH-to-LOW of Latch EnablePin NamesDescriptionOE n Output Enable Input (Active LOW)LE n Latch Enable InputI 0–I 15Inputs O 0–O 15Outputs NCNo Connect123456A O 0NC OE 1LE 1NC I 0B O 2O 1NC NC I 1I 2C O 4O 3V CC V CC I 3I 4D O 6O 5GND GND I 5I 6E O 8O 7GND GND I 7I 8F O 10O 9GND GND I 9I 10G O 12O 11V CC V CC I 11I 12H O 14O 13NC NC I 13I 14JO 15NCOE 2LE 2NCI 15InputsOutputs LE 1OE 1I 0–I 7O 0–O 7X H X Z HL L L H L H H LL XO 0 InputsOutputs LE 2OE 2I 8–I 15O 8–O 15X H X Z H L L L H L H H LLX O 074VCX16373Functional DescriptionThe 74VCX16373 contains sixteen edge D-type latches with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LE n ) input is HIGH, data on the I n enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each timeits I input changes. When LE n is LOW, the latches store information that was present on the I inputs a setup time preceding the HIGH-to-LOW transition on LE n . The 3-STATE outputs are controlled by the Output Enable (OE n ) input. When OE n is LOW the standard outputs are in the 2-state mode. When OE n is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.Logic DiagramPlease note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 474V C X 16373Absolute Maximum Ratings (Note 4)Recommended Operating Conditions (Note 6)Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Rat-ings. The “Recommended Operating Conditions ” table will define the condi-tions for actual device operation.Note 5: I O Absolute Maximum Rating must be observed.Note 6: Floating or unused inputs must be held HIGH or LOW.DC Electrical CharacteristicsSupply Voltage (V CC ) 0.5V to 4.6V DC Input Voltage (V I ) 0.5V to 4.6V Output Voltage (V O )Outputs 3-STATED 0.5V to 4.6V Outputs Active (Note 5)0.5V to V CC 0.5VDC Input Diode Current (I IK ) V I 0V 50 mA DC Output Diode Current (I OK )V O 0V 50 mA V O ! V CC50 mA DC Output Source/Sink Current (I OH /I OL )r 50 mA DC V CC or GND Current per Supply Pin (I CC or GND)r 100 mAStorage Temperature Range (T STG )65q C to 150q CPower SupplyOperating 1.2V to 3.6V Input Voltage 0.3V to 3.6V Output Voltage (V O )Output in Active States 0.0V to V CC Output in “OFF ” State 0.0V to 3.6VOutput Current in I OH /I OL V CC 3.0V to 3.6V r 24 mA V CC 2.3V to 2.7V r 18 mA V CC 1.65V to 2.3V r 6 mA V CC 1.4V to 1.6V r 2 mA V CC 1.2Vr 100 mA Free Air Operating Temperature (T A ) 40q C to 85q CMinimum Input Edge Rate ('t/'V)V IN 0.8V to 2.0V, V CC 3.0V10 ns/VSymbol ParameterConditionsV CC Min MaxUnits(V)V IHHIGH Level Input Voltage2.7 -3.6 2.0V2.3 - 2.7 1.61.65 - 2.30.65 u V CC 1.4 - 1.60.65 u V CC 1.20.65 u V CCV ILLOW Level Input Voltage2.7 -3.60.8V 2.3 - 2.70.71.65 - 2.30.35 u V CC 1.4 - 1.60.35 u V CC 1.20.15 x V CCV OHHIGH Level Output VoltageI OH 100 P A 2.7 - 3.6V CC 0.2VI OH 12 mA 2.7 2.2I OH 18 mA 3.0 2.4I OH 24 mA 3.0 2.2I OH 100 P A 2.3 - 2.7V CC 0.2I OH 6 mA 2.3 2.0I OH 12 mA 2.3 1.8I OH 18 mA 2.3 1.7I OH 100 P A 1.65 - 2.3V CC 0.2I OH 6 mA 1.65 1.25I OH 100 P A 1.4 - 1.6V CC 0.2I OH 2 mA 1.4 1.05I OH 100 P A1.2V CC 0.274VCX16373DC Electrical Characteristics (Continued)Note 7: Outputs disabled or 3-STATE only.AC Electrical Characteristics (Note 8)Symbol ParameterConditionsV CC Min Max Units(V)V OLLOW Level Output VoltageI OL 100 P A 2.7 - 3.60.2VI OL 12 mA 2.70.4I OL 18 mA 3.00.4I OL 24 mA 3.00.55I OL 100 P A 2.3 - 2.70.2I OL 12 mA 2.30.4I OL 18 mA 2.30.6I OL 100 P A 1.65 - 2.30.2I OL 6 mA 1.650.3I OL 100 P A 1.4 - 1.60.2I OL 2 mA 1.40.35I OL 100 P A1.20.05I I Input Leakage Current 0 d V I d 3.6V 1.2 - 3.6r 5.0P A I OZ 3-STATE Output Leakage 0 d V O d 3.6V 1.2 - 3.6r 10.0P A V I V IH or V IL I OFF I Power-OFF Leakage Current 0 d (V I , V O ) d 3.6V 010.0P A I CC Quiescent Supply Current V I V CC or GND1.2 - 3.620.0P A V CC d (V I , V O ) d 3.6V (Note 7) 1.2 - 3.6r 20.0'I CCIncrease in I CC per InputV IH V CC 0.6V2.7 -3.6750P ASymbol ParameterConditionsV CC T A 40q C to 85q C, UnitsFigure (V)Min Max Numbert PHL , t PLHPropagation Delay C L 30 pF, R L 500:3.3 r 0.30.8 3.0nsFigures 1, 2LE to O n2.5 r 0.2 1.03.91.8 r 0.15 1.57.8C L 15 pF, R L 2k :1.5 r 0.1 1.015.6nsFigures 7, 81.2 1.539.0t PHL , t PLHPropagation Delay C L 30 pF, R L 500:3.3 r 0.30.8 3.0nsFigures 1, 2I n to O n2.5 r 0.2 1.03.41.8 r 0.15 1.5 6.8C L 15 pF, R L 2k :1.5 r 0.1 1.013.6nsFigures 7, 81.2 1.534.0t PZL , t PZHOutput Enable TimeC L 30 pF, R L 500: 3.3 r 0.30.8 3.5nsFigures 1, 3, 42.5 r 0.2 1.0 4.61.8 r 0.151.59.2C L 15 pF, R L 2k :1.5 r 0.1 1.018.4nsFigures 7, 9, 101.2 1.546.0t PLZ , t PHZOutput Disable TimeC L 30 pF, R L 500:3.3 r 0.30.8 3.5nsFigures 1, 3, 42.5 r 0.2 1.03.81.8 r 0.151.5 6.8C L 15 pF, R L 2k :1.5 r 0.1 1.013.6nsFigures 7, 9, 101.2 1.534.0T SSetup TimeC L 30 pF, R L 500:3.3 r 0.3 1.5nsFigures 1, 62.5 r 0.2 1.51.8 r 0.152.5C L 15 pF, R L 2k :1.5 r 0.1 3.0nsFigures 6, 71.26.0 674V C X 16373AC Electrical Characteristics (Continued)Note 8: For C L 50P F, add approximately 300 ps to the AC maximum specification.Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t OSHL ) or LOW-to-HIGH (t OSLH ).Dynamic Switching CharacteristicsCapacitanceSymbol ParameterConditionsV CC T A 40q C to 85q C, UnitsFigure (V)Min MaxNumber T HHold TimeC L 30 pF, R L 500:3.3 r 1.0 1.0nsFigures 1, 62.5 r 0.2 1.01.8 r 0.151.0C L 15 pF, R L 2k :1.5 r 0.1 1.2nsFigures 6, 71.2 3.6T WPulse WidthC L 30 pF, R L 500:3.3 r 0.3 1.5nsFigures 1, 42.5 r 0.2 1.51.8 r 0.154.0C L 15 pF, R L 2k :1.5 r 0.1 4.0nsFigures 4, 71.28.0t OSHL Output to Output Skew C L 30 pF, R L 500:3.3 r 0.30.5nst OSLH(Note 9)2.5 r 0.20.51.8 r 0.150.75C L 15 pF, R L 2k :1.5 r 0.1 1.51.21.5Symbol ParameterConditionsV CC T A 25q C Units(V)Typical V OLPQuiet Output Dynamic Peak V OLC L 30 pF, V IH V CC , V IL 0V1.80.25V2.50.63.30.8V OLVQuiet Output Dynamic Valley V OLC L 30 pF, V IH V CC , V IL 0V1.8 0.25V2.5 0.63.30.8V OHVQuiet Output Dynamic Valley V OHC L 30 pF, V IH V CC , V IL 0V1.8 1.5V2.5 1.93.32.2Symbol ParameterConditionsT A 25q C Units Typical C IN Input Capacitance V CC 1.8V, 2.5V or 3.3V, V I 0V or V CC 6.0pF C OUT Output CapacitanceV I 0V or V CC , V CC 1.8V, 2.5V or 3.3V 7.0pF C PDPower Dissipation CapacitanceV I 0V or V CC , f 10 MHz,20.0pFV CC 1.8V, 2.5V or 3.3V74VCX16373AC Loading and Waveforms (V CC 3.3V r 0.3V to 1.8V r 0.15V)FIGURE 1. AC Test CircuitFIGURE 2. Waveform for Inverting andNon-Inverting FunctionsFIGURE 3. 3-STATE Output HIGH Enable andDisable Times for Low Voltage LogicFIGURE 4. 3-STATE Output LOW Enable and Disable Times for Low Voltage LogicFIGURE 5. Propagation Delay, Pulse Width andt rec WaveformsFIGURE 6. Setup Time, Hold Time and Recovery Time for Low Voltage Logic TEST SWITCH t PLH , t PHL Opent PZL , t PLZ 6V at V CC 3.3 r 0.3V;V CC x 2 at V CC 2.5 r 0.2V; 1.8V r 0.15Vt PZH , t PHZGNDSymbol V CC3.3V r 0.3V2.5V r 0.2V 1.8V r 0.15VV mi 1.5V V CC /2V CC /2V mo 1.5V V CC /2V CC /2V X V OL 0.3V V OL 0.15V V OL 0.15V V YV OH 0.3VV OH 0.15VV OH 0.15V 874V C X 16373AC Loading and Waveforms (V CC1.5 r 0.1V to 1.2V)FIGURE 7. AC Test CircuitFIGURE 8. Waveform for Inverting and Non-Inverting FunctionsFIGURE 9. 3-STATE Output High Enable and Disable Times for Low Voltage LogicFIGURE 10. 3-STATE Output Low Enable and Disable Times for Low Voltage LogicTEST SWITCH t PLH , t PHL Opent PZL , t PLZ V CC x 2 at V CC 1.5 r 0.1Vt PZH , t PHZGNDSymbol V CC 1.5V r 0.1V V mi V CC /2V mo V CC /2V X V OL 0.1V V YV OH 0.1V74VCX16373 Physical Dimensionsinches (millimeters) unless otherwise noted54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm WidePackage Number BGA54A(Preliminary)1074V C X 16373 L o w V o l t a g e 16-B i t T r a n s p a r e n t L a t c h w i t h 3.6V T o l e r a n t I n p u t s a n d O u t p u t sPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm WidePackage Number MTD48Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。