CD4025C中文资料

TL F 5955CD4023M CD4023C Triple 3-Input NAND Gate CD4025M CD4025C Triple 3-Input NOR Gate

February 1988

CD4023M CD4023C Triple 3-Input NAND Gate CD4025M CD4025C Triple 3-Input NOR Gate

General Description

These triple gates are monolithic complementary MOS (CMOS)integrated circuits constructed with N-and P-chan-nel enhancement mode transistors All inputs are protected against static discharge with diodes to V DD and V SS

Features

Y Wide supply voltage range 3 0V to 15V Y High noise immunity

0 45V DD (typ )

Y 5V–10V parametric ratings Y

Low power

Connection Diagrams

Dual-In-Line Packages

CD4023M CD4023C

TL F 5955–1

Top View

CD4025M CD4025C

TL F 5955–2

Top View

Order Number CD4023or CD4025

C 1995National Semiconductor Corporation RRD-B30M105 Printed in U S A

Absolute Maximum Ratings(Note1)

If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Voltage at Any Pin V SS b to V DD a0 3V Operating Temperature Range

CD4023M CD4025M b55 C to a125 C CD4023C CD4025C b40 C to a85 C Storage Temperature Range b65 C to a150 C Power Dissipation(P D)

Dual-In-Line700mW Small Outline500mW Operating V DD Range V SS a3 0V to V SS a15V Lead Temperature

(Soldering 10seconds)260 C

DC Electrical Characteristics CD4023M CD4025M

Limits

Symbol Parameter Conditions b55 C a25 C a125 C Units

Min Max Min Typ Max Min Max

I L Quiescent Device V DD e5 0V0 050 0010 053 0m A

Current V DD e10V0 10 0010 16 0m A

P D Quiescent Device V DD e5 0V0 250 0050 2515m W Dissipation Package V DD e10V1 00 011 060m W

V OL Output Voltage V DD e5 0V V I e V DD I O e0A0 0500 050 05V Low Level V DD e10V V I e V DD I O e0A0 0500 050 05V

V OH Output Voltage V DD e5 0V V I e V SS I O e0A4 954 955 04 95V High Level V DD e10V V I e V SS I O e0A9 959 95109 95V

V NL Noise Immunity V DD e5 0V V O e3 6V I O e0A1 51 52 251 4V (All Inputs)V DD e10V V O e7 2V I O e0A3 03 04 52 9V

V NH Noise Immunity V DD e5 0V V O e0 95V I O e0A1 41 52 251 5V (All Inputs)V DD e10V V O e2 9V I O e0A2 93 04 53 0V

I D N Output Drive Current V DD e5 0V V O e0 4V V I e V DD0 50 401 00 28mA

N-Channel(4025)(Note2)V DD e10V V O e0 5V V I e V DD1 10 92 50 65mA

I D P Output Drive Current V DD e5 0V V O e2 5V V I e V SS b0 62b0 5b2 0b0 35mA

P-Channel(4025)(Note2)V DD e10V V O e9 5V V I e V SS b0 62b0 5b1 0b0 35mA

I D N Output Drive Current V DD e5 0V V O e0 4V V I e V DD0 310 250 50 175mA

N-Channel(4023)(Note2)V DD e10V V O e0 5V V I e V DD0 630 50 60 35mA

I D P Output Drive Current V DD e5 0V V O e2 5V V I e V SS b0 31b0 25b0 5b0 175mA

P-Channel(4023)(Note2)V DD e10V V O e9 5V V I e V SS b0 75b0 6b1 2b0 4mA

I I Input Current10pA

Note1 ‘‘Absolute Maximum Ratings’’are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the devices should be operated at these limits The tables of‘‘Recommended Operating Conditions’’and‘‘Electrical Characteristics’’provide conditions for actual device operation

Note2 I D N and I D P are tested one output at a time

2