fpga测占空比技术文档

方波占空比测量
龙树东
一、设计要求：1、能测量方波占空比。

2、范围5%—95%。

二、设计达到的参数：1、测量占空比范围为DDS输出的20%—80%。

2、频率范围为3hz—100khz。

3、误差：频率低的情况下没有误差频率到8k以上小数点第一位有跳动。

三、测量数据：
设计原理：被测信号和标准时钟经过D触发器得到一与被测信号等脉宽且与标准时钟同相的信号，用标准时钟对D触发器输出的信号的高低电平分别计数，运用公式算出占空比：占空比=高电平计数/（高电平计数+低电平计数）。

附件：
分频器模块：
module div_clk(reset,clk,clk_1mhz,clk_1khz,clk_12864);
input reset,clk;
output reg clk_1mhz,clk_1khz,clk_12864;
reg[31:0] counter1,counter2,counter3;
always@(posedge clk or negedge reset)
begin
if(!reset)
begin
counter1<=0;counter2<=0;counter3<=0;
clk_1mhz<=0;clk_1khz<=0;clk_12864<=0;
end
else begin
if(counter1==1) begin counter1<=0;clk_1mhz<=~clk_1mhz; end
else begin counter1<=counter1+1; end
if(counter2==24999) begin counter2<=0;clk_1khz<=~clk_1khz; end
else begin counter2<=counter2+1; end
end
end
endmodule
D触发器模块：
module D_chufaqi(clk, gatein, gateout);
input clk;
input gatein;
output gateout;
reg gateout;
always @(posedge clk)
begin
gateout <= gatein;
end
endmodule
计数器模块：
module cnt(
clk,
rst_n,
catin,
dat_out
);
input clk,rst_n,catin;
output [23:0] dat_out;
//首先对脉冲输入进行同步处理
reg syn1;
reg syn2;
always @ (posedge clk)
begin
syn1 <= catin;
syn2 <= syn1;
end
reg [23:0] ratio;
wire catin_pos;
//获得输入脉冲的上升沿
assign catin_pos = syn2 & (~syn1);
//计算高低电平宽度
reg [23:0] Pon_reg,Poff_reg;
always @ (negedge rst_n or posedge clk)
begin
if(!rst_n)
begin
Pon_reg <= 24'b0;
Poff_reg <= 24'b0;
end
else if(catin_pos)
begin
ratio=1+1000*Pon_reg/(Poff_reg+Pon_reg);
Pon_reg <= 24'b0;
Poff_reg <= 24'b0;
end
else if(syn1)
begin
Pon_reg <= Pon_reg + 1'b1;
end
else
begin
Poff_reg <= Poff_reg + 1'b1;
end
end
reg [5:0] cnt;
reg [7:0] ge,shi,bai,qian;
always @ (ratio)
if(cnt==20) begin
cnt<=0;
// qian <=ratio/1000%10+"0";
bai <=ratio/100%10+"0";
shi <=ratio/10%10+"0";
ge <=ratio%10+"0";
end
else begin
cnt<=cnt+1;
end
assign dat_out={bai[7:0],shi[7:0],ge[7:0]};
endmodule
12864液晶显示模块：
/***********************
12864底层文件
************************/
module lcd_12864(clk_r,rst_n,en,rs,rw,dat,lcd_data);
input clk_r,rst_n;
input [23:0] lcd_data;
output [7:0] dat;
output rs,rw,en;
reg e;
reg rs;
//reg clk_r,clk_o; //分频后的时钟
reg [7:0] dat;
reg [7:0] dat1;
reg [7:0] dat2;
reg [1:0] cnt;
reg [15:0] count; //分频计数器
reg [6:0] i; //状态机变量
/*always @(posedge clk) //分频部分
if(!rst_n) count = 0;
else begin
count = count + 1'b1;
if(count == 16'h000f)
clk_r=~clk_r;
end
*/
always @(posedge clk_r or negedge rst_n )
if(!rst_n) begin
i <=0;
rs<=0;
e <=0;
dat<=0;
end
else
case(i)
0: begin rs<=0; dat<=8'h30; i<=i+1'b1; end //lcd初始化
1: begin rs<=0; dat<=8'h0c; i<=i+1'b1; end
2: begin rs<=0; dat<=8'h6; i<=i+1'b1; end
3: begin rs<=0; dat<=8'h81; i<=i+1'b1; end
4: begin rs<=1; dat<=8'hd3; i<=i+1'b1; end //玉
5: begin rs<=1; dat<=8'hf1; i<=i+1'b1; end
6: begin rs<=1; dat<=8'hc1; i<=i+1'b1; end //林
7: begin rs<=1; dat<=8'hd6; i<=i+1'b1; end
8: begin rs<=1; dat<=8'hca; i<=i+1'b1; end //师
9: begin rs<=1; dat<=8'ha6; i<=i+1'b1; end
10: begin rs<=1; dat<=8'hb7; i<=i+1'b1; end //范
11: begin rs<=1; dat<=8'hb6; i<=i+1'b1; end
12: begin rs<=1; dat<=8'hd1; i<=i+1'b1; end //学
13: begin rs<=1; dat<=8'ha7; i<=i+1'b1; end
14: begin rs<=1; dat<=8'hd4; i<=i+1'b1; end //院
15: begin rs<=1; dat<=8'hba; i<=i+1'b1; end
16: begin rs<=0; dat<=8'h90; i<=i+1'b1; end //显示第二行17: begin rs<=1; dat<=8'hb5; i<=i+1'b1; end //电
18: begin rs<=1; dat<=8'he7; i<=i+1'b1; end
19: begin rs<=1; dat<=8'hd7; i<=i+1'b1; end //子
20: begin rs<=1; dat<=8'hd3; i<=i+1'b1; end
21: begin rs<=1; dat<=8'hb4; i<=i+1'b1; end //创
22: begin rs<=1; dat<=8'hb4; i<=i+1'b1; end
23: begin rs<=1; dat<=8'hd0; i<=i+1'b1; end //新
24: begin rs<=1; dat<=8'hc2; i<=i+1'b1; end
25: begin rs<=1; dat<=8'hca; i<=i+1'b1; end //实
26: begin rs<=1; dat<=8'hb5; i<=i+1'b1; end
27: begin rs<=1; dat<=8'hd1; i<=i+1'b1; end //验
28: begin rs<=1; dat<=8'he9; i<=i+1'b1; end
29: begin rs<=1; dat<=8'hca; i<=i+1'b1; end //室
30: begin rs<=1; dat<=8'hd2; i<=i+1'b1; end
31: begin e<=0; rs<=0; dat<=(8'h88+1); i<=i+1'b1; end //定位第三行，重新把en拉低32: begin rs<=1; dat<=8'hd5; i<=i+1'b1; end //占
33: begin rs<=1; dat<=8'hbc; i<=i+1'b1; end
34: begin rs<=1; dat<=8'hbf; i<=i+1'b1; end //空
35: begin rs<=1; dat<=8'hd5; i<=i+1'b1; end
36: begin rs<=1; dat<=8'hb1; i<=i+1'b1; end //比
37: begin rs<=1; dat<=8'hc8; i<=i+1'b1; end
38: begin rs<=1; dat<=8'ha1; i<=i+1'b1; end //:
39: begin rs<=1; dat<=8'hc3; i<=i+1'b1; end
40: begin rs<=1; dat<=lcd_data[23:16]; i<=i+1'b1; end
41: begin rs<=1; dat<=lcd_data[15 :8]; i<=i+1'b1; end
42: begin rs<=1; dat<="."; i<=i+1'b1; end //%
43: begin rs<=1; dat<=lcd_data[7 :0]; i<=i+1'b1; end //%
44: begin rs<=1; dat<=8'ha3; i<=i+1'b1; end //%
45: begin rs<=1; dat<=8'ha5; i<=i+1'b1; end
46:
begin rs<=0; dat<=8'h00;
if(cnt!=2'h2)
begin
e<=0; cnt<=cnt+1'b1; i<=1'b0;
end
else begin
e<=1; i<=6'd31;
end
end
default: i<=1'b0;
endcase
assign en=clk_r|e;
assign rw=0;
Endmodule
综合模块：。