STPCC0366BTC3资料

®
STPC CONSUMER-S
PC Compatible Embeded Microprocessor
ADVANCED DATA
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29/10/99
Figure 1.Logic Diagram
s POWERFUL x86PROCESSOR
s 64-BIT 66MHz SDRAM UMA CONTROLLER s VGA &SVGA CRT CONTROLLER s 2D GRAPHICS ENGINE s VIDEO INPUT PORT
s
VIDEO PIPELINE -UP-SCALER
-VIDEO COLOR SP ACE CONVERTER -CHROMA &COLOUR KEY SUPPORT s
TV OUTPUT
-3-LINE FLICKER FILTER
-CCIR 601/656SCAN CONVERTER
-NTSC /PAL COMPOSITE,RGB,S-VIDEO s PCI MASTER /SLAVE CONTROLLER s ISA MASTER /SLAVE CONTROLLER s
INTEGRA TED PERIPHERAL CONTROLLER -DMA CONTROLLER
-INTERRUPT CONTROLLER -TIMER /COUNTERS
s OPTIONAL 16-BIT LOCAL BUS INTERFACE s EIDE CONTROLLER s I C INTERFACE
s POWER MANAGEMENT UNIT s
3.3V OPERA TION
STPC CONSUMER-S OVERVIEW
The STPC Consumer-S integrates a standard 5th generation x86core,a Synchronous DRAM con-troller,a graphics subsystem,a video input port,video pipeline,and support logic including PCI,ISA,and IDE controllers to provide a single con-sumer orientated PC compatible subsystem on a single device.
The device is based on a tightly coupled Unified Memory Architecture (UMA),sharing the same memory array between the CPU main memory and the graphics and video frame buffers.
The STPC Consumer-S is packaged in a 388Plastic Ball Grid Array (PBGA).
PBGA388
x86Core
Host I/F SDRAM CTRL
SVGA GE VIP
PCI m/s
LB CTR PCI Bus
ISA m/s IPC
PCI m/s ISA Bus CRTC
Cursor
Monitor
TV
IDE I/F
PMU
W.dog
Video Pipeline
C Key K Key LUT
Local Bus
Encoder
TVO
STPC CONSUMER-S
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s X86Processor core
s Fully static 32-bit 5-stage pipeline,x86processor fully PC compatible.
s Can access up to 4GB of external memory.s 8Kbyte unified instruction and data cache with write back and write through capability .s Parallel processing integral floating point unit,with automatic power down.
s Fully static design for dynamic clock control.s Low power and system management modes.s SDRAM Controller s 64-bit data bus.
s Up to 66MHz SDRAM clock speed.
s Integrated system memory,graphic frame memory and video frame memory.s Supports 2MB up to 128MB memory.s Supports 8MB,16M,and 32MB DIMMs.s Supports buffered,non buffered,and registered DIMMs
s 4-line write buffers for CPU to DRAM and PCI to DRAM cycles.
s 4-line read prefetch buffers for PCI masters.s Programmable latency
s Programmable timing for DRAM parameters.s Supports -8,-10,-12,-13,-15memory parts s Supports 1MB up to 8MB memory hole.s 32-bit accesses not supported.s Autoprecharge not supported.s Power down not supported.s FPM and EDO not supported.
s Graphics Controller
s 64-bit windows accelerator .
s Compatibility to VGA &SVGA standards.s Hardware acceleration for text,bitblts,transparent blts and fills.
s Up to 64x 64bit graphics hardware cursor.s Up to 4MB long linear frame buffer.s
8-,16-,and 24-bit pixels.
s CRT Controller
s Integrated 135MHz triple RAMDAC allowing for 1024x 768x 75Hz display .s 8-,16-,24-bit pixels.
s Interlaced or non-interlaced output.
s Video Input port
s Accepts video inputs in CCIR 601mode.s Optional 2:1decimator
s Stores captured video in off setting area of the onboard frame buffer.
s Video pass through to the onchip PAL/NTSC encoder for full screen video images.s
HSYNC and B/T generation or lock onto external video timing source.
s Video Pipeline
s Two-tap interpolative horizontal filter.s Two-tap interpolative vertical filter.s Color space conversion.s Programmab le window size.
s
Chroma and color keying for integrated video overlay .
s TV Output
s Programmab le two tap filter with gamma correction or three tap flicker filter.
s Progressive to interlaced scan converter.s NTSC-M,PAL-M,P AL-B,D,G,H,I,PAL-N easy programmable video outputs.
s CCIR601encoding with programmab le color subcarrier frequencies.s Line skip/insert capability
s Interlaced or non-interlaced operation mode.s 625lines/50Hz or 525lines/60Hz 8bit multiplexed CB-Y -CR digital input.
s CVBS and R,G,B simultaneous analog outputs through 10-bit DACs.
s Cross color reduction by specific trap filtering on luma within CVBS flow.
s
Power down mode available on each DAC.
STPC CONSUMER-S
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s PCI Controller
s Fully compliant with PCI 2.1specification.s
Integrated PCI arbitration interface.Up to 3masters can connect directly.External P AL allows for greater than 3masters.s Translation of PCI cycles to ISA bus.
s Translation of ISA master initiated cycle to PCI.
s Support for burst read/write from PCI master.s
PCI clock is 1/3or 1/2Host clock.
s ISA master/slave controller
s Generates the ISA clock from either 14.318MHz oscillator clock or PCI clock s Supports programmable extra wait state for ISA cycles
s Supports I/O recovery time for back to back I/O cycles.
s Fast Gate A20and Fast reset.
s Supports the single ROM that C,D,or E.blocks shares with F block BIOS ROM.s Supports flash ROM.
s Supports ISA hidden refresh.
s
Buffered DMA &ISA master cycles to reduce bandwidth utilization of the PCI and Host bus.NSP compliant.
s Integrated Peripheral Controller
s 2X8237/A T compatible 7-channel DMA controller.
s 2X8259/A T compatible interrupt Controller.16interrupt inputs -ISA and PCI.
s Three 8254compatible Timer/Counters.s Co-processor error support logic.s Supports external RTC.
s Local Bus interface
s Multiplxed with ISA interface.s Low latency bus s 22-bit address bus.
s 16-bit data bus with word steering capability .s Programmable timing (Host clock granularity)s 2Programmab le Flash Chip Select.s 5Programmab le I/O Chip Select.s Supports 32-bit Flash burst.
s 2-level hardware key protection for Flash boot block protection.
s
Supports 2banks of 8MB flash devices with boot block shadowed to 0x000F0000.
s IDE Interface
s Supports PIO and Bus Master IDE s Supports up to Mode 5Timings s Transfer Rates to 22MBytes/sec s Supports up to 4IDE devices
s Concurrent channel operation (PIO &DMA modes)-4x 32-Bit Buffer FIFO per channel s Support for PIO mode 3&4.s Support for DMA mode 1&2.
s Support for 11.1/16.6MB/s,I/O Channel Ready PIO data transfers.
s Supports 13.3/16.6MB/s DMA data transfers s Bus Master with scatter/gather capability s Multi-word DMA support for fast IDE drives s Individual drive timing for all four IDE devices s Supports both legacy &native IDE modes s Supports hard drives larger than 528MB s Support for CD-ROM and tape peripherals s Backward compatibility with IDE (A TA-1).s Power Management
s Four power saving modes:On,Doze,Standby ,Suspend.
s Programmab le system activity detector s Supports SMM.
s Supports STOPCLK.
s Supports IO trap &restart.
s Independent peripheral time-out timer to monitor hard disk,serial &parallel ports.
s
Supports RTC,interrupts and DMAs wake-up
GENERAL DESCRIPTION
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1GENERAL DESCRIPTION
At the heart of the STPC Consumer-S is an ad-vanced 64-bit processor block,dubbed the 5ST86.The 5ST86includes a 486processor core along with a 64-bit SDRAM controller,advanced 64-bit accelerated graphics and video controller,a high speed PCI local-bus controller and Industry standard PC chip set functions (Interrupt control-ler,DMA Controller,Interval timer and ISA bus).The STPC Consumer-S makes use of a tightly coupled Unified Memory Architecture (UMA),where the same memory array is used for CPU main memory and graphics frame-buffer.This means a reduction in total system memory for sys-tem performances that are equal to that of a com-parable frame buffer and system memory based system,and generally much better,due to the higher memory bandwidth allowed by attaching the graphics engine directly to the 64-bit proces-sor host interface running at the speed of the proc-essor bus rather than the traditional PCI bus.
The 64-bit wide memory array provides the sys-tem with 528MB/s peak bandwidth.This allows for higher resolution screens and greater color depth.The ‘standard’PC chipset functions (DMA,inter-rupt controller,timers,power management logic)are integrated together with the x86processor core;additional functions such as communica-tions ports are accessed by the STPC Consumer-S via internal ISA bus.
The PCI bus is the main data communication link to the STPC Consumer-S chip.The STPC Con-sumer-S translates appropriate host bus I/O and Memory cycles onto the PCI bus.It also supports generation of Configuration cycles on the PCI bus.The STPC Consumer-S,as a PCI bus agent (host bridge class),fully complies with PCI specification 2.1.The chip-set also implements the PCI manda-tory header registers in Type 0PCI configuration space for easy porting of PCI aware system BI-OS.The device contains a PCI arbitration function for three external PCI devices.
The STPC Consumer-S has two functionnal blocks sharing the same balls :The ISA /IPC /IDE block and the Local Bus /IDE block (see Ta-ble 3).Any board with the STPC Consumer-S should be built using only one of these two config-urations.
At reset,the configuration is done by ‘strap op-tions’which initialises the STPC Consumer-S to the right settings.It is a set of pull-up or pull-down resistors on the memory data bus,checked on re-set,which auto-configure the STPC Consumer-S.
GRAPHICS FUNCTIONS
Graphics functions are controlled through the on-chip SVGA controller and the monitor display is produced through the 2D graphics display engine.This Graphics Engine is tuned to work with the host CPU to provide a balanced graphics system with a low silicon area cost.It performs limited graphics drawing operations which include hard-ware acceleration of text,bitblts,transparent blts and fills.The results of these operations change the contents of the on-screen or off-screen frame buffer areas of DRAM memory.The frame buffer can occupy a space up to 4Mbytes anywhere in the physical main memory and always starts from the bottom of the main physical memory.
The graphics resolution supported is a maximum of 1280x1024in 65536colours and 1024x768in true color at 75Hz refresh rate and is VGA and SVGA compatible.Horizontal timing fields are VGA compatible while the vertical fields are ex-tended by one bit to accommodate above display resolution.
VIDEO FUNCTIONS
The STPC Consumer-S provides several addition-al functions to handle MPEG or similar video streams.The Video Input Port accepts an encod-ed digital video stream in one of a number of in-dustry standard formats,decodes it,optionally decimates it,and deposits it into an off screen area of the frame buffer.An interrupt request can be generated when an entire field or frame has been captured.The video output pipeline incorpo-rates a video-scaler and color space converter function and provisions in the CRT controller to display a video window.While repainting the screen the CRT controller fetches both the video as well as the normal non-video frame buffer in two separate internal FIFOs.The video stream can be color-space converted (optionally)and smooth scaled.Smooth interpolative scaling in both horizontal and vertical direction are imple-mented.Color and Chroma key functions are also implemented to allow mixing video stream with non-video frame buffer.
The video output passes directly to the RAMDAC for monitor output or through another optional color space converter (RGB to 4:2:2YCrCb)to the programmable anti-flicker filter.The flicker filter is configured as either a two line filter with gamma correction (primarily designed for DOS type text)or a 3line flicker filter (primarily designed for Win-dows type displays).The fliker filter is optional and can be software disabled for use with large screen area’s of video.
GENERAL DESCRIPTION
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The Video output pipeline of the STPC Consumer-S interfaces directly to the internal digital TV en-coder.It takes a 24bit RGB non-interlaced pixel stream and converts to a multiplexed 4:2:2YCrCb 8bit output stream,the logic includes a progres-sive to interlaced scan converter and logic to in-sert appropriate CCIR656timing reference codes into the output stream.It facilitates the high quality display of VGA or full screen video streams re-ceived via the Video input port to standard NTSC or PAL televisions.
The digital PAL/NTSC encoder outputs interlaced or non-interlaced video in PAL-B,D,G,H,I PAL-N,PAL-M or NTSC-M standards and “NTSC-4.43”is also possible.
The four frame (for PAL)or 2frame (for NTSC)burst sequences are internally generated,subcar-rier generation being performed numerically with CKREF as reference.Rise and fall times of syn-chronisation tips and burst envelope are internally controlled according to the relevant ITU-R and SMPTE recommendations.
Video output signals are directed to four analog output pins through internal D/A converters giving,simultaneous R,G,B and composite CVBS out-puts.
IDE INTERFACE
An industry standard EIDE (ATA 2)controller is built into the STPC Consumer-S.The IDE port is capable of supporting a total of four devices.POWER MANAGEMENT
The STPC Consumer-S core is compliant with the Advanced Power Management (APM)specifica-tion to provide a standard method by which the BIOS can control the power used by personal computers.The Power Management Unit module (PMU)controls the power consumption providing a comprehensive set of features that control the power usage and supports compliance with the United States Environmental Protection Agency’s Energy Star Computer Program.The PMU pro-vides following hardware structures to assist the software in managing the power consumption by the system.
-System Activity Detection.-Three power down timers.
-Doze timer for detecting lack of system activity for short durations.
-Stand-by timer for detecting lack of system activ-ity for medium durations
-Suspend timer for detecting lack of system activ-ity for long durations.
-House-keeping activity detection.
-House-keeping timer to cope with short bursts of house-keeping activity while dozing or in stand-by state.
-Peripheral activity detection.
-Peripheral timer for detecting lack of peripheral activity
-SUSP#modulation to adjust the system perform-ance in various power down states of the system including full power on state.
-Power control outputs to disable power from dif-ferent planes of the board.
Lack of system activity for progressively longer period of times is detected by the three power down timers.These timers can generate SMI in-terrupts to CPU so that the SMM software can put the system in decreasing states of power con-sumption.Alternatively,system activity in a power down state can generate SMI interrupt to allow the software to bring the system back up to full power on state.The chip-set supports up to three power down states:Doze state,Stand-by state and Sus-pend mode.These correspond to decreasing lev-els of power savings.
POWER DOWN
Power down puts the STPC Consumer-S into sus-pend mode.The processor completes execution of the current instruction,any pending decoded in-structions and associated bus cycles.During the suspend mode,internal clocks are stopped.Re-moving power down,the processor resumes in-struction fetching and begins execution in the in-struction stream at the point it had stopped.Be-cause of the static nature of the core,no internal data is lost.
GENERAL DESCRIPTION
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Figure 2.Functionnal description.
x86Core
Host I/F SDRAM I/F
SVGA GE VIP
PCI m/s
Local Bus I/F
PCI BUS
ISA m/s
IPC
82C206
PCI m/s
ISA Bus
CRTC
HW Cursor
Monitor
TV
-Pixel formating -Scaler
-Colour Space
IDE I/F
PMU watch-
Video Pipeline
Colour Key Chroma Key
LUT
Local Bus
NTSC/PAL Encoder
TVO
-CSC -FF -CCIR
CC IR Input
GENERAL DESCRIPTION
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Figure 3.Typical Application
STPC Consumer-S
ISA
PCI
4x 16-bit SDRAMs
Super I/O
2x EIDE
Flash
Keyboard /Mouse Serial Ports Parallel Port Floppy
Monitor
TV
Video
SVGA
CCIR601CCIR656
S-VHS RGB PAL NTSC
IRQ
DMA.REQ
DMA.ACK
DMUX
DMUX
MUX
MUX
RTC
GENERAL DESCRIPTION 8/51
Update History for Video controller chapter
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1.1UPDATE HISTORY FOR VIDEO CONTROLLER CHAPTER
The following changes have been made to the General Description Chapter on 29/10/99.
Section Change Text
1
Removed
“The STPC Consumer-S has in addition to the 5ST86a TFT output,a Local Bus interface,a WatchDog and a JTAG interface.”
PIN DESCRIPTION
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2PIN DESCRIPTION
2.1INTRODUCTION
The STPC Consumer-S integrates most of the functionalities of the PC architecture.As a result,many of the traditional interconnections between the host PC microprocessor and the peripheral devices are totally internal to the STPC Consum-er-S.This offers improved performance due to the tight coupling of the processor core and these pe-ripherals.As a result many of the external pin con-nections are made directly to the on-chip peripher-al functions.
Figure 2.1shows the STPC Consumer-S external interfaces.It defines the main busses and their function.Table 2.1describes the physical imple-mentation listing signals type and their functionali-ty.Table 2.2provides a full pin listing and descrip-tion of pins.Table 2.5provides a full listing of pin locations of the STPC Consumer-S package by physical connection.
Note:Several interface pins are multiplexed with other functions,refer to Table 2.3and Table 2.4for further details
Table 2.1.Signal Description
Group name
Qty
System Clocks &Resets 11Memory Interface 95PCI interface 60
ISA 7989IDE
34Local Bus 49
Video Input 11TV Output
8VGA Monitor interface 8Grounds 71V DD
29Analog specific V CC /V DD 6Total Pin Count
388
Figure 2.1.STPC Consumer-S External Interfaces
PCI
x86SDRAM VGA
VIP
TV
SYS
ISA/IDE/LB
958118601189
STPC CONSUMER-S
Table2.2.Definition of Signal Pins
Signal Name Dir Description Qty BASIC CLOCKS AND RESETS
SYSRSTI#I System Power Good Input1 SYSRSTO#O System Reset Output1 XTALI I14.3MHz Crystal Input1 XTALO I/O14.3MHz Crystal Output-External Oscillator Input1 HCLK I/O Host Clock(Test)1 DEV_CLK O24MHz Peripheral Clock(floppy drive)1 DCLK I/O27-135MHz Graphics Dot Clock1
MEMORY INTERFACE
MCLKI I Memory Clock Input1 MCLKO O Memory Clock Output1
CS#[3:0]O DIMM Chip Select4
MA[11:0]O Memory Row&Column Address12
MD[63:0]I/O Memory Data64 RAS#[1:0]O Row Address Strobe2 CAS#[1:0]O Column Address Strobe2 MWE#O Write Enable1 DQM[7:0]O Data Input/Output Mask8
PCI INTERFACE
PCI_CLKI I33MHz PCI Input Clock1
PCI_CLKO O33MHz PCI Output Clock(from internal PLL)1
AD[31:0]I/O PCI Address/Data32 CBE#[3:0]I/O Bus Commands/Byte Enables4 FRAME#I/O Cycle Frame1 IRDY#I/O Initiator Ready1 TRDY#I/O Target Ready1 LOCK#I PCI Lock1 DEVSEL#I/O Device Select1 STOP#I/O Stop Transaction1 PAR I/O Parity Signal Transactions1 SERR#O System Error1 PCIREQ#[2:0]I PCI Request3
PCI_GNT#[2:0]O PCI Grant3
PCI_INT[3:0]I PCI Interrupt Request4 VDD5I5V Power Supply for PCI ESD protection4
ISA CONTROL
ISA_CLK O ISA Clock Output-Multiplexer Select Line For IPC1
ISA_CLK2X O ISA Clock x2Output-Multiplexer Select Line For IPC1 OSC14M O ISA bus synchronisation clock1
LA[23:17]O Unlatched Address7
SA[19:0]I/O Latched Address20
SD[15:0]I/O Data Bus16 ALE O Address Latch Enable1 MEMR#,MEMW#I/O Memory Read and Memory Write2 SMEMR#,SMEMW#O System Memory Read and Memory Write2
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Table2.2.Definition of Signal Pins
Signal Name Dir Description Qty IOR#,IOW#I/O I/O Read and Write2 MCS16#,IOCS16#I Memory/IO Chip Select162 BHE#O System Bus High Enable1 ZWS#I Zero Wait State1 REF#O Refresh Cycle.1 MASTER#I Add On Card Owns Bus1 AEN O Address Enable1 IOCHCK#I I/O Channel Check.1 IOCHRDY I/O I/O Channel Ready(ISA)-Busy/Ready(IDE)1 ISAOE#O ISA/IDE Selection1 GPIOCS#I/O General Purpose Chip Select1 IRQ_MUX[3:0]I Time-Multiplexed Interrupt Request4 DREQ_MUX[1:0]I Time-Multiplexed DMA Request2 DACK_ENC[2:0]O Encoded DMA Acknowledge3 TC O ISA Terminal Count1 RTCAS O Real Time Clock Address Strobe1 RMRTCCS#I/O ROM/RTC Chip Select1 KBCS#I/O Keyboard Chip Select1 RTCRW#I/O RTC Read/Write1 RTCDS I/O RTC Data Strobe1
LOCAL BUS
PA[21:0]O Address Bus22 PD[15:0]I/O Data Bus16 PRD1#,PRD0#O Peripheral Read Control2 PWR1#,PWR0#O Peripheral Write Control2 PRDY#I Data Ready1 FCS1#,FCS0#O Flash Chip Select2 IOCS#[3:0]O I/O Chip Select4
IDE CONTROL
DA[2:0]O Address Bus3 DD[15:0]I/O Data Bus16 PCS3#,PCS1#,SCS3#,SCS1#O Primary&Secondary Chip Selects4 DIORDY O Data I/O Ready1 PIRQ,SIRQ I Primary&Secondary Interrupt Request2 PDRQ,SDRQ I Primary&Secondary DMA Request2 PDACK#,SDACK#O Primary&Secondary DMA Acknowledge2 PDIOR#,SDIOR#O Primary&Secondary I/O Channel Read2 PDIOW#,SDIOW#O Primary&Secondary I/O Channel Write2
MONITOR INTERFACE
RED,GREEN,BLUE O Analog Red,Green,Blue3 VSYNC O Vertical Sync1 HSYNC O Horizontal Sync1 VREF_DAC I DAC Voltage reference1 RSET I Resistor Set1 COMP I Compensation1
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2.2SIGNAL DESCRIPTIONS 2.2.1BASIC CLOCKS AND RESETS
SYSRSTI#System Reset/Power good.This input is low when the reset switch is depressed.Other-wise,it reflects the power supply’s power good signal.This input is asynchronous to all clocks,and acts as a negative active reset.The reset cir-cuit initiates a hard reset on the rising edge of this signal.
SYSRSTO#Reset Output to System.This is the system reset signal and is used to reset the rest of the components (not on Host bus)in the system.The ISA bus reset is an externally inverted buff-ered version of this output and the PCI bus reset is an externally buffered version of this output.XTALI 14.3MHz Crystal Input
XTALO 14.3MHz Crystal Output.These pins are connected to the 14.318MHz crystal to provide the reference clock for the internal frequency syn-thesizer to generate all the other clocks.
A 14.318MHz Series Cut Crystal should be con-nected between these two pins.Balance capaci-tors of 15pF should also be added.In the event of an external quarzt oscillator providing the master
clock signal to the STPC Consumer-S device,the TTL signal should be provided on XTALO.HCLK Host Clock.This clock supplies the CPU and the host related blocks.This clock can e dou-bled inside the CPU and is intended to operate in the range of 25to 100MHz.This clock in generat-ed internally from a PLL but can be driven directly from the external system.
DCLK Dot Clock /Pixel clock.This clock supplies the display controller,the video pipeline,the ram-dac,and the TV output logic.Its value is depend-ent on the selected display mode.
Its frequency can be as high as 135MHz.This sig-nal is either driven by the internal PLL either by an external oscillator.The direction can be controlled by a strap option or an internal register bit.DEV_CLK 24MHz Peripheral Clock.This 24MHZ signal is provided as a convenience for the system integration of a Floppy Disk driver function in an external chip.
VIDEO INPUT VCLK I 27-33MHz Video Input Port Clock
1VIN I CCIR 601or 656YUV Video Data Input
8VCS
I/O Composite Synch or Horizontal line SYNC output 1ODD_EVEN
I/O
Frame Synchronisation
1
ANALOG TV OUTPUT
RED_TV,GREEN_TV,BLUE_TV O Analog RGB or S-VHS outputs 3CVBS O Analog video composite output
1IREF1_TV I Reference current of 9bit DAC for CVBS 1VREF1_TV I Reference voltage of 9bit DAC for CVBS 1IREF2_TV I Reference current of 8bit DAC for R,G,B 1VREF2_TV I Reference voltage of 8bit DAC for R,G,B 1VSSA_TV I Analog Vss for DAC 1VDDA_TV I Analog Vdd for DAC 1
MISCELLANEOUS SPKRD O Speaker Device Output
1SCL I/O I C Interface -Clock /Can be used for VGA DDC[1]signal 1SDA
I/O I C Interface -Data /Can be used for VGA DDC[0]signal 1SCAN_ENABLE
I Reserved (Test pin)1
Table 2.2.Definition of Signal Pins
Signal Name
Dir Description
Qty
2.2.2MEMORY INTERFACE
MCLKO Memory Clock Output.This clock is driv-ing the DIMMs on board and is generated from an internal PLL.The default value is66MHz.
MCLKI Memory Clock Input.This clock is driving the SDRAM controller,the graphics engine and display controller.This input should be a buffered version of the MCLKO signal with the track lengths between the buffer and the pin matched with the track lengths between the buffer and the DIMMs.
CS#[3:0]Chip Select These signals are used to disable or enable device operation by masking or enabling all SDRAM inputs except MCLK,CKE, and DQM.
MA[11:0]Memory Address.Multiplexed row and column address lines.
MD[63:0]Memory Data.This is the64-bit memory data bus.MD[40-0]are read by the device strap option registers during rising edge of SYSRSTI#.
RAS#[1:0]Row Address Strobe.These signals enable row access and precharge.Row address is latched on rising edge of MCLK when RAS#is low.
CAS#[1:0]Column Address Strobe.These sig-nals enable column access.Column address is latched on rising edge of MCLK when CAS#is low.
MWE#Write Enable.Write enable specifies whether the memory access is a read(MWE#=H) or a write(MWE#=L).
DQM#[7:0]Data Mask.Makes data output Hi-Z after the clock and masks the SDRAM outputs. Blocks SDRAM data input when DQM active.2.2.3PCI INTERFACE
PCI_CLKI33MHz PCI Input Clock.This signal is the PCI bus clock input and should be driven from the PCI_CLKO pin.
PCI_CLKO33MHz PCI Output Clock.This is the master PCI bus clock output.
AD[31:0]PCI Address/Data.This is the32-bit multiplexed address and data bus of the PCI.This bus is driven by the master during the address phase and data phase of write transactions.It is driven by the target during data phase of read transactions.
CBE#[3:0]Bus Commands/Byte Enables.These are the multiplexed command and byte enable signals of the PCI bus.During the address phase they define the command and during the data phase they carry the byte enable information. These pins are inputs when a PCI master other than the STPC Consumer-S owns the bus and outputs when the STPC Consumer-S owns the bus.
FRAME#Cycle Frame.This is the frame signal of the PCI bus.It is an input when a PCI master owns the bus and is an output when STPC Consumer-S owns the PCI bus.
IRDY#Initiator Ready.This is the initiator ready signal of the PCI bus.It is used as an output when the STPC Consumer-S initiates a bus cycle on the PCI bus.It is used as an input during the PCI cy-cles targeted to the STPC Consumer-S to deter-mine when the current PCI master is ready to complete the current transaction.
TRDY#Target Ready.This is the target ready sig-nal of the PCI bus.It is driven as an output when the STPC Consumer-S is the target of the current bus transaction.It is used as an input when STPC Consumer-S initiates a cycle on the PCI bus.
LOCK#PCI Lock.This is the lock signal of the PCI bus and is used to implement the exclusive bus operations when acting as a PCI target agent.
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DEVSEL#I/O Device Select.This signal is used as an input when the STPC Consumer-S initiates a bus cycle on the PCI bus to determine if a PCI slave device has decoded itself to be the target of the current transaction.It is asserted as an output either when the STPC Consumer-S is the target of the current PCI transaction or when no other de-vice asserts DEVSEL#prior to the subtractive de-code phase of the current PCI transaction.
STOP#Stop Transaction.Stop is used to imple-ment the disconnect,retry and abort protocol of the PCI bus.It is used as an input for the bus cy-cles initiated by the STPC Consumer-S and is used as an output when a PCI master cycle is tar-geted to the STPC Consumer-S.
PAR Parity Signal Transactions.This is the parity signal of the PCI bus.This signal is used to guar-antee even parity across AD[31:0],CBE#[3:0], and PAR.This signal is driven by the master dur-ing the address phase and data phase of write transactions.It is driven by the target during data phase of read transactions.(Its assertion is identi-cal to that of the AD bus delayed by one PCI clock cycle)
SERR#System Error.This is the system error sig-nal of the PCI bus.It may,if enabled,be asserted for one PCI clock cycle if target aborts a STPC Consumer-S initiated PCI transaction.Its asser-tion by either the STPC Consumer-S or by another PCI bus agent will trigger the assertion of NMI to the host CPU.This is an open drain output.
PCIREQ#[2:0]PCI Request.This pin are the three external PCI master request pins.They indi-cates to the PCI arbiter that the external agents desire use of the bus.
PCI_GNT#[2:0]PCI Grant.These pins indicate that the PCI bus has been granted to the master requesting it on its PCIREQ#.
PCI_INT[3:0]PCI Interrupt Request.These are the PCI bus interrupt signals.
VDD55V Power Supply.These power pins are necessary for5V ESD protection.In case the PCI bus is used in3.3V only,these pins can be con-nected to3.3V.2.2.4ISA INTERFACE
ISA_CLK,ISA_CLKX2ISA Clock x1,x2.These pins generate the Clock signal for the ISA bus and a Doubled Clock signal.They are also used as the multiplexor control lines for the Interrupt Controller Interrupt input lines.ISA_CLK is generated from either PCICLK/4or OSC14M/2.
OSC14M ISA bus synchronisation clock Output. This is the buffered14.318Mhz clock for the ISA bus.
LA[23:17]Unlatched Address.When the ISA bus is active,these pins are ISA Bus unlatched ad-dress for16-bit devices.When ISA bus is ac-cessed by any cycle initiated from PCI bus,these pins are in output mode.When an ISA bus master owns the bus,these pins are in input mode.
SA[19:0]ISA Address Bus.System address bus of ISA on8-bit slot.These pins are used as an in-put when an ISA bus master owns the bus and are outputs at all other times.
SD[15:0]I/O Data Bus.These pins are the exter-nal databus to the ISA bus.
ALE Address Latch Enable.This is the address latch enable output of the ISA bus and is asserted by the STPC Consumer-S to indicate that LA23-17,SA19-0,AEN and SBHE#signals are valid. The ALE is driven high during refresh,DMA mas-ter or an ISA master cycles by the STPC Consum-er-S.ALE is driven low after reset.
MEMR#Memory Read.This is the memory read command signal of the ISA bus.It is used as an in-put when an ISA master owns the bus and is an output at all other times.
The MEMR#signal is active during refresh.
MEMW#Memory Write.This is the memory write command signal of the ISA bus.It is used as an in-put when an ISA master owns the bus and is an output at all other times.
SMEMR#System Memory Read.The STPC Con-sumer-S generates SMEMR#signal of the ISA bus only when the address is below one megabyte or the cycle is a refresh cycle.
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