scan_atpg_basics

scan_atpg_basics
ATPG Basics: The ATPG Process ATPG Basics: The ATPG Process Fault Selection
Fault Observe Point Assessment
Fault Excitation
Vector Generation
Fault Simulation
Fault Dropping
Figure 1.The ATPG Process
ATPG Basics: Combinational Stuck-At Fault
ATPG Basics: Combinational Stuck-At Fault
GOOD CIRCUIT
X
stuck-at-01000
00
1
force to a 1
a
b c
d
e
Figure 2.
Combinational Stuck-at Fault
detected good !~bad
1100
BAD CIRCUIT
1000
10
1000
ATPG Basics: Fault Effective Circuit
ATPG Basics: Fault Effective Circuit
e
Figure 3.Stuck-at Fault Effective Circuit
1e 0X
stuck-at-0force to a 1
a b c d e
Detectable
ab 00011011z 1110
nand c
d
ab 00011011z 1000
nor
ATPG Basics: Fault Masking
ATPG Basics: Fault Masking
Figure 4.
Fault masking
GOOD CIRCUIT
X
stuck-at-010X
01
force to a 1
a
b
c
e
not detected good = bad
110X
BAD CIRCUIT
10X
11
011X
ATPG Basics: The Delay Fault
ATPG Basics: The Delay Fault
Figure 5.The Delay Fault
A B
C Z
D E F
Delay Model Element
Insufficient Transistor Doping
Capacitive or Resistive Wire Delay from Opens Slow Gate Output Slow Gate Input
Delay from Strong Driver
Delay from Extra Load and Metal Defects
Resistive Bridge
Effect of Delay Fault
Delay of Transition Occurrence
Changing of Edge-Rate
1
“Ideal” Signal
Added Rise Delay Added Fall Delay
Edge-Rate Layover
The Delay Fault Model is an added delay
to net, nodes, wires, gates and other circuit elements
ATPG Basics: The Current-based Fault
ATPG Basics: The Current-based Fault
Figure 6.
The Current Fault
A B
C Z
D E F
Leakage Fault Model
Leakage from Metastability
Capacitive or Resistive Delay Extends Current
Internal Gate Leakage
Leakage from Bridge
Leakage from Bridge
Flow Time
Resistive Bridge
Effect of a Current Fault is to add extra current flow or to extend flow time
The Current Fault Model is an added Leakage to net, nodes, wires, gates and other circuit elements I(t)
t
ATPG Basics: Stuck-At ATPG tutorial
ATPG Basics: Stuck-At ATPG tutorial
faultlist 1 BIT ADDER with CARRY
A
B S
C
e f
a b
r
t
s
c
a b e f r t s c 16 faults
@@@@@@@@000
00000a b e f r t s c @@@@@@@@11
111111 Figure 7.
Stuck-At Fault ATPG
1 BIT ADDER with CARRY A B
S
C
e f
a
b
r t
s
c
1
Exercise the Fault
Sensitize the Detect Path
1
1
1
11
1
1. Set up the path to pass the opposite of e SA0which is e = 1
2. Exercise by setting e equal to1
3. Detect by observing S for wrong value during fault simulation X
ATPG Basics: Stuck Fault Equivalence
ATPG Basics: Stuck Fault Equivalence
faultlist a b e f r t s c 16 faults
@@@@@@@@00000000a b e f r t s c @@@@@@@@11111111 Figure 8.
Fault Equivalence Example
GOOD - 1 BIT ADDER with CARRY
A
B
S
C
e f
a b r t s
c
Fault Equivalence Table
b a 1. Any fault that requires a logi
c 1 on the output of an AND-gate will 2. Similar analysis exists for all other gate-level elements 3. If one fault is detecte
d all equivalent faults ar
e detected 4. Fault selection only needs to target one o
f the equivalent faults
a z z
z AND INV OR
a@0 = b@0 = z@0a@1 = z@0 : a@0 = z@1a@1 = b@1 = z@1
also place 1’s on inputs r t
e
a’a b
ATPG Basics: Stuck-At Fault Simulation tutorial
ATPG Basics: Stuck-At Fault Simulation tutorial
faultlist 16 faults
Figure 9.
Fault Simulation example
GOOD - 1 BIT ADDER with CARRY
A
B
S
C
e f
a b
r t
s
c
“t” S@1 - 1 BIT ADDER with CARRY
A
B
S
C
e f
a b
r t
s
c
“t” S@0 - 1 BIT ADDER with CARRY
A
B
S
C
e f
a b
r t
s
c
GND
+
VDD
1. Create multiple copies of the netlist for each fault.
2. Apply same vectors to each copy.
3. Compare each copy to good simulation (expected response).
4. Fault is detected if Bad circuit and Good circuit differ at a detect point.
5. Measurement is faults detected divided by total number of vectors.(8/16 = 50%)
a b e f r t s c @@@@@@@@00000000a b e f r t s c @@@@@@@@11111111 ATPG Basics: Transition Delay Fault ATPG
ATPG Basics: Transition Delay Fault ATPG
faultlist S@T1a b e f r t s c 16 faults
@@@@@@@@000
00000a b e f r t s c @@@@@@@@11
111111 Figure 10.Transition Delay Fault ATPG
S@T21 BIT ADDER with CARRY
A
B S
C
e f
a b
r t
s c
1 BIT ADDER with CARRY A B
S
C
e f a b
r t
s
c
10
Exercise the Fault
Sensitize the Detect Path
1
10
1
111
1. Set up the path to pass the opposite of e S@0which is e = 1
2. Pre-fail by setting e equal to 04. Detect by observing S for wrong value during timing 1 BIT ADDER with CARRY A
B S
C
e f
a b
r t
s c
01
Pre-Fail the Fault
3. Exercise by setting e equal to 1 some The Transition Delay Faultlist is Identical to the DC Faultlist but the Goal is to Detect
a Logic Transition within a given time period
time period later simulation
X
ATPG Basics: Path Delay Fault ATPG
ATPG Basics: Path Delay Fault ATPG
faultlist 1 BIT ADDER with CARRY A
B
S@T1 -> S@T2
C e f
a
b
r
t
s
c
a b e f t c 16 faults
@@@@@@000
000a b e f r t s c @@@@@@@@11
11
11
11 Figure 11.
Path Delay Fault ATPG
1 BIT ADDER with CARRY A
B
S
C
e f
a
r t
s
c
0->1
1->0
Exercise the Fault (Path)
Sensitize the Off-Path
1->1
1->1
0->0
1. Set up the path to pass a transition on B-to-S through e, r, and s by
2. Exercise by first setting B equal to 0 - then to 1
3. Detect by observing S for wrong value during fault simulation with respect to a time standard setting the off-path
values for 2 time periods b
x->x r@0
s@0
This is known as a vector-pair
X X
0->1
0->1
1->0
X
X
X
ATPG Basics: Current-based Fault ATPG
ATPG Basics: Current-based Fault ATPG
Figure 12.Current Fault ATPG
faultlist 1 BIT ADDER with CARRY
A
B S
C
e f
a b
r
t
s
c
a b e f r t s c 16 faults
@@@@@@@@000
00000a b e f r t s c @@@@@@@@11
1111111
Exercise the Fault
1. Exercise by setting e equal to1
2. Detect by measuring Current and assess vector by quietness
ATPG Basics: Two Time Frame ATPG
ATPG Basics: Two Time Frame ATPG
Figure 13.Two Time-Frame ATPG
second order cone of logic establishes transition and off path values first order combinational cone contains path and off path logic
Defined Critical Path
establishes the legal next-state
of logic Q
D Gate
Elements 1->0
1->10->01->1
Expect V alue
Transition bit
End of Path
bit establish first state
legal
next-next-state
legal next-state
preset next-state
1. Launch 1st Value:
2. Launch Transition:establish path fail value at clock edge provide pass value at next clock edge
3. Capture Transition:
observe transition value at next clock edge
1
23
1
2
3
3
Propagation Delay Time
Register Setup Time
Slack Time
Launching Register
Capture Register
Other Fan-In
Output Pin
Previous
cycle cone of logic
Previous cycle cone of logic D Q CLK
D Q CLK
D Q CLK D Q CLK a critical timing path in combinational logic
a critical timing path in combinational logic
Scan Test Basics: Scan Testing
Scan Test Basics: Scan Testing
- >100,000 gates
- >500,000 faults
- >3,000 flip-flops
- > 100 sequential depth
- < 200 chip pins
* > 500 gates/pin
* > 2M = 2100
Chip under Test without Scan
- >100,000 gates
- >500,000 faults
- > no effective flip-flops
- > no sequential depth
- < 200 + 3000 chip pins
* > 31.25 gates/pin
* > 2M = 20 = 1
Chip under Test with Full-Scan
Figure 14.Parallel Testing Problem
Scan Test Basics: The Functional Test Problem
Scan Test Basics: The Functional Test Problem
Q
D
input1input2input3clk input5
output2
output1
Combinational & Figure 15.
Sample Non-Scan Circuit
Sequential Logic
QN
input4
input6
Q
D
12
34
Sequential Depth of 4Combinational Width of 626+4 = 1024 Vectors Scan Test Basics: Scan Effective Circuit
Scan Test Basics: Mux D Scan Flip-Flops
Scan Test Basics: Mux D Scan Flip-Flops
Figure 17.Flip-Flop -vs- Scan Flip-Flop
Regular D Flip-Flop
D
Q CLK
QN
D Q
clk
D
Q SDI SE
CLK
QN SDO
D
Scannable D Flip-Flop
Scan Test Basics: Legal Mux D Scan Flip-Flops Scan Test Basics: Legal Mux D Scan Flip-Flops Figure 18.Example Set-Scan Flip-Flops
Set-Scan D Flip-Flop
D Q CLK
QN D Q
clk
SDI SE
SDO
SET D Q SDI SE
CLK
QN D Q
clk
SDO
Set-Scan D Flip-Flop
SET
Scan Test Basics: LSSD and Clocked Scan Scan Test Basics: LSSD and Clocked Scan Figure 19.Alternate Scan Cells
Clocked Scan D Flip-Flop
D Q MCK QN
D Q
mck TMCK tmck SCK
sck
SDI SDO
Level Sensitive Scan D Latch Complex
D Q MCK QN
D Q
mck STCK stck SCK
sck
SDI SDO。