8313配置文件及说明

writereg MBAR 0xFF400000

writemem.l 0xFF400000 0xE0000000 # IMMRBAR = 0xE0000000

writereg MBAR 0xE0000000

writemem.l 0xE0000020 0xFE000000# LBLAWBAR0 - begining at 0xfe000000 writemem.l 0xE0000024 0x80000014# LBLAWAR0 - enable, size = 2MB

#writemem.l 0xE0000028 0xFA000000 # LBLAWBAR1 FPGAbegining at 0xfa000000

#writemem.l 0xE000002C 0x8000000E # LBLAWAR1 - enable, size = 32KB writemem.l 0xE00000A0 0x00000000 # DDRLAWBAR0 - begining at 0x00000000 writemem.l 0xE00000A4 0x80000018 # DDRLAWAR0 - enable, size = 32MB

# DDR Controller Configuration

#1 DDRCDR

writemem.l 0xE0000128 0x73040002

#CLK_CNTL

writemem.l 0xE0002130 0x02000000

#同原0x02000000。[5-7]CLK_ADJST = 010（1/2），or 011（3/4）

# CS0_BNDS

writemem.l 0xE0002000 0x00000001 # 0x00000001 - 0x01FFFFFF ;32MB

# CS0_CONFIG

# [8]AP_0_EN = 1，0？

# [16-17]BA_BITS_CS_0 = 00，01? Number of bank bits for SDRAM on chip select n.

# [21-23]ROW_BITS_CS_0 = b'001' ; 12 row bits

# [29-31]COL_BITS_CS_0 = b'010' ; 9 columns bits

#原0x80840102 不同：[29-31]、[21-23]，

writemem.l 0xE0002080 0x80000001

# TIMING_CFG_3 原0x00000000

# 13-15EXT_REFREC = 001; AUTO REFRESH command period tRFC=72 ns writemem.l 0xE0002100 0x00010000

# TIMING_CFG_1 原0x26256222

# bit 1-3 = 2 tRP=15ns，(tck=7.5) （类似tRP ，为DDR芯片手册上内容）# bit 4-7 = 6 tRAS=42ns，

# bit 9-11 = 2 tRCD=15ns，

# bit 12 - 15 = 0011:2；0100:2.5

# bit 16 - 19 = 2 (10tck) tRFC=72 ns (tck=7.5)

# bit 21 - 23 = 2 tWR=15ns，

# bit 25 - 27 = 2 tRRD=12ns，

# bit 29 - 31 = 1 tWTR=1tck

writemem.l 0xE0002108 0x26232221

# TIMING_CFG_2 原0x0f9028c7

# bit 4-8 =11111 OR 00010 DQS read preamble tRPRE=0.9tck

# bit 16-18=100 010(BL=4) OR 100(BL=8)

# bit 19-21 = b'011' Write command to write data strobe timing adjustment # 3/4 DRAM clock delay

#Write command to first DQS latching transition tDQSS=0.75 writemem.l 0xE000210C 0x0F888C41

# TIMING_CFG_0 原0x00220802

# [9-11]ACT_PD_EXIT = b'001' ; 1 Clocks P46(MT46V8M16P_6T.pdf) # [13-15]PRE_PD_EXIT = b'001' ; 1 Clocks

# [28-31]MRS_CYC = b'0010'=2CLOCKS;tMRD=12

writemem.l 0xE0002104 0x00220002

# temporary disable DDR_SDRAM_CFG 原0x43080000

# [1]SREN = b'1'

# [3]RD_EN = b'0'

# [10]DYN_PWR = b'0'

# [11-12]DBW = b'01' DRAM data bus width：01=32bit，10=16bit # [13]8_BE = b'1' 0=4-beat bursts 1=8-beat bursts

#[14] NCAP = b'0' 0= support concurrent auto-precharge

# [16]2T_EN = b'0'

# [26]x32_EN = b'0'

# [27]PCHB8 = b'0'

# [28]HSE = b'0'

# [30]MEM_HALT = b'0'

# [31]BI = b'0'

writemem.l 0xE0002110 0x420C0000

# DDR_SDRAM_CFG_2 原0x00401000

# [0]FRC_SR = b'0'

# [2] DLL_RST_DIS = b'0'

# [16-19]NUM_PR = b'0001'

# [27]D_INIT = b'0' DRAM data initialization (or 1？！) writemem.l 0xE0002114 0x00001000

#DDR_SDRAM_MODE 原0x44400232

#[0-15] ESDMODE=4000

#[16-31] SDMODE=0023, Burst Length=8, CAS Latency=2 writemem.l 0xE0002118 0x40000023

# DDR_SDRAM_INTERV AL 原0x03200064

# [0-15]REFINT = 2600 Clocks,