TB4005中文资料
常规生化复合定值质控品((正常正常水平))
1 SD
2.3 2.3 2.3 2.3 4.4 4.5 4.5 4.5 2.7 2.7 2.7 2.7 4.3 4.3 4.3 4.3 2.6 2.6 2.6 2.6 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.5 1.6 1.6 1.6 1.5 1.5 1.5 1.5 0.08 0.08 0.08 0.08 0.12 0.12 0.12 0.12
参考值
45.6 46.1 46.1 46.1 87.3 90.9 90.9 90.9 53.1 53.4 53.4 53.4 85.6 85.9 85.9 85.9 51.3 51.0 51.0 51.0 15.3 15.0 15.0 15.0 14.5 14.8 14.8 14.8 20.6 20.7 20.7 20.7 20.5 20.6 20.6 20.6 2.18 2.21 2.21 2.21 2.59 2.60 2.60 2.60
1
重氮盐 重氮盐法
BS-2002 BS-3003 BS-3804 BS-1201
BS-4806 BS-8007 BS-20008 BS-4005 BS-4806 BS-8007 BS-20008 BS-400
5
TB
钒酸盐氧化法
BS-2002 BS-3003 BS-3804 BS-120
1
Ca
偶氮胂 III 法
6
AST
IFCC 法
BS-2002 BS-3003 BS-3804 BS-1201
重氮盐 重氮盐法
BS-200
2
BS-3003 BS-3804 BS-1201
BS-8007 BS-20008 BS-4005 BS-4806 BS-8007 BS-20008 BS-400
T912-B500K-001-10中文资料
® resistance films to achieve the precise ratio performance Caddock Tetrinox® MG 650 Caddock Tetrinox resistance films to achieve thesource precise ratio performance ® resistance and stability required by highly accurate amplifier circuits, reference Caddock's Micronox films are the ofvoltage Preconditioning for Power and Voltage Ratings and stability required by highly accurate amplifier circuits, reference and stability required by highly accurate amplifier circuits,voltage voltage reference MG 655 Now with Extended Resistance Range to 10,000 Megohms and Additional Models circuits a
foxboro工程师手册
I/A’s系统维护手册（工程师手册）编制：何卫兵上海福克斯波罗有限公司二零零二年元月第一章系统概述本手册为上海福克斯波罗有限公司DCS系统I/A维护手册，并作为I/A’s 培训手册的补充。
用户可以结合两本手册来进行系统操作、软件组态及系统维护。
必要时还应参考随机的原版资料及福克斯波罗公司提供的中文培训手册。
本手册针对福克斯波罗制造的I/A’S，采用Solaris 2.5.1操作系统和I/A’s 6.2.1版本应用软件。
整个系统为一个节点，在冗余的节点总线DNBI上挂有：●三台工程师站AW5101、AW5102、AW5103该站作为工程师站，内置256M内存及8GB硬盘，AW5102外挂一台喷墨打印机（电缆长度15米），AW5103配有和MIS系统通讯用的第二以太网卡。
该工作站安放在工程师站内，与I/A机柜（位于电子间）之间的通讯电缆长度为30米。
●四台操作员站WP5101、WP5103、WP5104、WP5105该站内置128M内存及8GB硬盘，并各配有一个21”的CRT。
该工作站安放在主控室内与I/A机柜（位于电子间）之间的通讯电缆长度为30米。
●一台操作员站WP5102该站作为大屏幕操作站，内置128M内存及8GB硬盘，除配有一个21”的CRT外。
还配有一台用于显示大屏幕的以太网卡。
该工作站安放在主控室内，与I/A机柜（位于电子间）之间的通讯电缆长度为30米。
●十一对容错台控制处理站CP4001、CP4002、CP4003、CP4004、CP4005、CP4006、CP4007、CP4008、CP4009、CP4010、CP4011此容错型控制处理站CP40BFT，用于实现DCS系统的数据采集及控制。
该控制处理器安放在电子间内。
现场由十八个装有现场总线组件FBM的现场机柜、十个安装DCS系统辅助装置（包括冗余的24VDC电源、交流继电器、直流继电器、SIMENSE交流接触器、以及相应的I/O端子）的继电器柜、一个DCS系统220VAC配电柜共同构成。
BT152B-400R,118;BT152B-600R,118;BT152B-800R,118;中文规格书,Datasheet资料
BT152B series ThyristorsThyristors BT152B seriesGENERAL DESCRIPTIONQUICK REFERENCE DATAGlass passivated thyristors in a plastic SYMBOL PARAMETERMAX.MAX.MAX.UNIT envelope suitable for surface mounting,intended for use in BT152B-400R 600R 800R applications requiring high V DRM ,Repetitive peak off-state 450650800V bidirectional blocking voltage V RRM voltagescapability and high thermal cycling I T(AV)Average on-state current 131313A performance.Typical applications I T(RMS)RMS on-state current202020A include motor control,industrial and I TSMNon-repetitive peak on-state 200200200Adomestic lighting,heating and static currentswitching.PINNING - SOT404PIN CONFIGURATIONSYMBOLPIN DESCRIPTION 1cathode 2anode 3gate mbanodeLIMITING VALUESLimiting values in accordance with the Absolute Maximum System (IEC 134).SYMBOL PARAMETERCONDITIONSMIN.MAX.UNIT -400R -600R -800R V DRM Repetitive peak off-state -45016501800V voltagesI T(AV)Average on-state current half sine wave; T mb ≤ 103 ˚C -13A I T(RMS)RMS on-state current all conduction angles-20A I TSMNon-repetitive peak half sine wave; T j = 25 ˚C prior to on-state currentsurge t = 10 ms -200A t = 8.3 ms -220A I 2t I 2t for fusingt = 10 ms-200A 2s dI T /dt Repetitive rate of rise of I TM = 50 A; I G = 0.2 A;-200A/μs on-state current after dI G /dt = 0.2 A/μs triggeringI GM Peak gate current -5A V GM Peak gate voltage-5V V RGM Peak reverse gate voltage -5V P GM Peak gate power -20W P G(AV)Average gate power over any 20 ms period -0.5W T stg Storage temperature -40150˚C T jOperating junction -125˚Ctemperature1 Although not recommended, off-state voltages up to 800V may be applied without damage, but the thyristor may switch to the on-state. The rate of rise of current should not exceed 15 A/μs.Thyristors BT152B seriesTHERMAL RESISTANCESSYMBOL PARAMETERCONDITIONSMIN.TYP.MAX.UNIT R th j-mb Thermal resistance-- 1.1K/W junction to mounting base R th j-aThermal resistance minimum footprint, FR4 board -55-K/Wjunction to ambientSTATIC CHARACTERISTICST j = 25 ˚C unless otherwise stated SYMBOL PARAMETER CONDITIONSMIN.TYP.MAX.UNIT I GT Gate trigger current V D = 12 V; I T = 0.1 A -332mA I L Latching current V D = 12 V; I GT = 0.1 A -2580mA I H Holding current V D = 12 V; I GT = 0.1 A -1560mA V T On-state voltage I T = 40 A- 1.4 1.75V V GT Gate trigger voltage V D = 12 V; I T = 0.1 A-0.6 1.5V V D = V DRM(max); I T = 0.1 A; T j = 125 ˚C 0.250.4-V I D , I ROff-state leakage currentV D = V DRM(max); V R = V RRM(max); T j = 125 ˚C-0.21.0mADYNAMIC CHARACTERISTICST j = 25 ˚C unless otherwise stated SYMBOL PARAMETER CONDITIONSMIN.TYP.MAX.UNIT dV D /dt Critical rate of rise of V DM = 67% V DRM(max); T j = 125 ˚C;200300-V/μs off-state voltageexponential waveform gate open circuit t gt Gate controlled turn-on V D = V DRM(max); I G = 0.1 A; dI G /dt = 5 A/μs;-2-μs timeI TM = 40 At qCircuit commutated V D = 67% V DRM(max); T j = 125 ˚C;-70-μsturn-off timeI TM = 50 A; V R = 25 V; dI TM /dt = 30 A/μs;dV D /dt = 50 V/μs; R GK = 100 ΩThyristors BT152B seriesThyristors BT152B seriesThyristors BT152B seriesMECHANICAL DATANotes1. Epoxy meets UL94 V0 at 1/8".MOUNTING INSTRUCTIONS1. Plastic meets UL94 V0 at 1/8".Legal informationDATA SHEET STATUSNotes1.Please consult the most recently issued document before initiating or completing a design.2.The product status of device(s) described in this document may have changed since this document was publishedand may differ in case of multiple devices. The latest product status information is available on the Internet at URL . DOCUMENT STATUS (1)PRODUCT STATUS (2)DEFINITIONObjective data sheet Development This document contains data from the objective specification for product development.Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet ProductionThis document contains the product specification.DEFINITIONSProduct specification ⎯ The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXPSemiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.DISCLAIMERSLimited warranty and liability ⎯ Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give anyrepresentations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or reworkcharges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’aggregate and cumulative liability towards customer for the products described herein shall be limited inaccordance with the Terms and conditions of commercial sale of NXP Semiconductors.Right to make changes ⎯ NXP Semiconductors reserves the right to make changes to informationpublished in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.Suitability for use ⎯ NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severeproperty or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment orapplications and therefore such inclusion and/or use is at the customer’s own risk.Applications ⎯ Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXPSemiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXPSemiconductors product is suitable and fit for thecustomer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.Legal informationNXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third partycustomer(s). NXP does not accept any liability in this respect.Limiting values ⎯ Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or theCharacteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.Terms and conditions of commercial sale ⎯ NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at /profile/terms, unless otherwiseagreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.No offer to sell or license ⎯ Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.Export control ⎯ This document as well as the item(s) described herein may be subject to export controlregulations. Export might require a prior authorization from national authorities.Quick reference data ⎯ The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.Non-automotive qualified products ⎯ Unless this data sheet expressly states that this specific NXPSemiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.In the event that customer uses the product for design-in and use in automotive applications to automotivespecifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXPSemiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.Contact informationFor additional information please visit: For sales offices addresses send e-mail to: salesaddresses@Customer notificationThis data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the content, except for the legal definitions and disclaimers. © NXP B.V. 2011All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.Printed in The Netherlands分销商库存信息:NXPBT152B-400R,118BT152B-600R,118BT152B-800R,118。
TPS40021中文资料
乐器价格表
350
2454
虎丘牌5211香红木3.5寸中胡（配盒）
把
2200
2455
虎丘牌香红木3.5寸铜轸中胡（配盒）
把
2200
2474
敦煌牌90A酸枝木八角筒木轸中胡（配盒）
把
1800
2475
敦煌牌90C酸枝木前方后圆木轸中胡（配盒）
把
2800
胡琴配件
售价
2700
苏式二胡腰托（用于南方二胡）
只
30
2607
2225
虎丘牌T525红木本色二胡(配高级盒)
把
2650
2228
虎丘牌5128-1五级黑檀专业二胡(配高级盒)
把
2650
2216
虎丘牌5131特选红木专业二胡(配高级盒)
把
2850
2219
虎丘牌5133特选紫檀二胡(配高级盒)
把
3800
2240
虎丘牌5135特选紫檀专业二胡(配高级盒)
把
3300
2220
把
820
2400
虎丘牌5602白木板(梆)胡（纸盒）
把
250
2401
虎丘牌5603仿红木板(梆)胡（纸盒）
把
350
2404
虎丘牌5611花梨木板(梆)胡（配盒）
把
430
2409
虎丘牌5621红木专业板(梆)胡（配盒）
把
800
2406
敦煌牌62B酸枝木铜轸板(梆)胡（配盒）
把
680
2408
敦煌牌61A花梨木木轸板(梆)胡（纸盒）
台
350
2804
永美YM6100电子琴((61键)
T912-B500K-002-02中文资料
® resistance films to achieve the precise ratio performance Caddock Tetrinox® MG 650 Caddock Tetrinox resistance films to achieve thesource precise ratio performance ® resistance and stability required by highly accurate amplifier circuits, reference Caddock's Micronox films are the ofvoltage Preconditioning for Power and Voltage Ratings and stability required by highly accurate amplifier circuits, reference and stability required by highly accurate amplifier circuits,voltage voltage reference MG 655 Now with Extended Resistance Range to 10,000 Megohms and Additional Models circuits and precision bridge circuits. the Type
AD404M324VBB-5中文资料
ASCEND Semiconductor 4Mx4 EDO Data sheetDescriptionThe device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable elec-tronic application. lt is packaged in JEDEC standard 26/24-pin plastic SOJ or TSOP(II).Features• Single 3.3V(%) only power supply • High speed t RAC acess time: 50/60ns • Low power dissipation- Active mode : 432/396 mW (Mas) - Standby mode: 0.54 mW (Mas)• Extended - data - out(EDO) page mode access • I/O level: CMOS level (Vcc = 3.3V)• 2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version)• 4 refresh modesh: - RAS only refresh- CAS - before - RAS refresh - Hidden refresh - Self-refresh(S-version)10±Pin Name FunctionA0-A10Address inputs- Row address - Column address - Refresh address DQ1~DQ4Data-in / data-out RAS Row address strobe CAS Column address strobe WE Write enable OE Output enable Vcc Power (+ 3.3V)VssGroundVCC 1DQ12DQ23DQ34DQ45VCC6891011 NC 12 WE 13A0 A117 A218 A319VSS RAS CAS OE A8A7A6A5A4VSSAD404M42VSPin Description Pin Configuration21222324 2526151416 A1026/24-PIN 300mil Plastic SOJA9VCC 1DQ12DQ23DQ34DQ45VCC6891011 NC 12 WE 13A0 A117 A218 A319VSS RAS CAS OE A8A7 A6A5 A4VSSAD404M42VT212223242526151416 A1026/24-PIN 300mil Plastic TSOP (ll)A9A0-A10A0-A10A0-A10WECASNO. 2 CLOCK GENERATORCOLUMN ADDRESS BUFFERS (11)REFRESH CONTROLLERREFRESH COUNTERBUFFERS (11)ADDRESS ROW NO. 1 CLOCK GENERATORA0RASA1A2A3A4A5A6A7A8CONTROLLOGICDATA-IN BUFFERDATA-OUT BUFFEROEDQ1.DQ4.COLUMN DECODER2048SENSE AMPLIFIERSI/O GATING2048x42048x2048x4MEMORY ARRAY2048R O W D E C O D E RVcc VssBlock DiagramA9A10TRUTH TABLENotes: 1. EARLY WRITE only.FUNCTIONRASCAS WE OE ADDRESSESDQ SNotesROW COL STANDBY H X X X X High-Z READL L H L ROW COL Data-Out WRITE: (EARLY WRITE )L L L X ROW COL Data-lnREAD WRITE L L ROW COL Data-Out,Data-ln EDO-PAGE-MODE READ1st Cycle L H L ROW COL Data-Out 2nd CycleL H L n/a COL Data-Out EDO-PAGE MODE WRITE1st CycleL L X ROW COL Data-In 2nd Cycle L L Xn/a COL Data-InEDO-PAGE-MODEREAD-WRITE 1st Cycle L ROW COL Data-Out, Data-In 2nd Cycle L n/a COL Data-Out, Data-In HIDDEN REFRESHREAD L H L ROW COL Data-Out WRITEL L X ROW COL Data-In 1RAS-ONLY REFRESH L H X X ROW n/a High-Z CBR REFRESHLHXXXHigh-ZH X →H L →L H →H L →H L →H L →H L →H L →H L →L H →H L →H L →L H→L H L →→L H L→→H L→Absolute Maximum RatingsRecommended DC Operating ConditionsCapacitanceTa = 25°C, V CC = 3.3V%, f = 1MHz Note: 1. Capacitance measured with effective capacitance measuring method. 2. RAS, CAS = V IH to disable Dout.ParameterSymbol Value Unit Voltage on any pin relative to Vss V T -0.5 to + 4.6V Supply voltage relative to Vss V CC -0.5 to + 4.6V Short circuit output current I OUT 50mA Power dissipation P D 1.0WOperating temperature T OPT 0 to + 70°C Storage temperatureT STG-55 to + 125°CParameter/Condition Symbol3.3 Volt VersionUnitMinTyp MaxSupply VoltageV CC 3.0 3.33.6V Input High Voltage, all inputs V IH 2.0-V CC + 0.3V Input Low Voltage, all inputsV IL-0.3-0.8VParameterSymbol Typ Max Unit Note Input capacitance (Address)C I1 -5pF 1Input capacitance (RAS, CAS, OE, WE)C I2-7pF 1Output capacitance(Data-in, Data-out)C I/O-7pF1, 210±DC Characteristics :(T a = 0 to 70°C, V CC = + 3.3V%, V SS = 0V)Parameter Symbol Test Conditions AD404M42V Unit Notes-5-6Min Max Min MaxOperating current I CC1RAS cyclingCAS, cyclingt RC = min-120-110mA1, 2Standby Current LowpowerS-versionI CC2LVTTL interfaceRAS, CAS = V IHDout = High-Z-0.5-0.5mACMOS interfaceRAS, -0.2VDout = High-Z-0.15-0.15mAStandardpowerversionLVTTL interfaceRAS, CAS = V IHDout = High-Z-2-2mACMOS interfaceRAS,-0.2VDout = High-Z-0.5-0.5mARAS- only refresh current I CC3RAS cycling, CAS = V IHt RC = min-120-110mA1, 2 EDO page mode current I CC4t PC = min-90-80mA1, 3CAS- before- RAS refresh current I CC5t RC = minRAS, CAS cycling-120-110mA1, 2Self- refresh current (S-Version)I CC8 - 550 - 55010±CAS V CC≥CAS V CC≥t RASS100µs≥µADC Characteristics :(T a = 0 to 70°C , V CC = +3.3V %, V SS = 0V)Notes:1. I CC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. I CC max is specified at the output open condition.2. Address can be changed once or less while RAS = V IL .3. For I CC4, address can be changed once or less within one EDO page mode cycle time.Parameter Symbol Test Conditions AD404M42VUnitNotes-5-6Min MaxMin MaxInput leakage current I LI + 0.3V -55-55Output leakage current I LO + 0.3V Dout = Disable -55-55Output high Voltage V OH I OH = -2mA 2.4- 2.4-V Output low voltage V OLI OL = +2mA-0.4-0.4V10±0V Vin V CC ≤≤µA 0V Vout V CC ≤≤µAAC Characteristics(T a = 0 to + 70°C , V cc = 3.3V %, V ss = 0V) *1, *2, *3, *4Test conditions• Output load: one TTL Load and 100pF (V CC = 3.3V %)• Input timing reference levels:V IH = 2.0V, V IL = 0.8V (V CC = 3.3V %)• Output timing reference levels:V OH = 2.0V, V OL = 0.8V10±10±10±Read, Write, Read- Modify- Write and Refresh Cycles (Common Parameters)ParameterSymbol AD404M42V UnitNotes-5-6Min MaxMin MaxRandom read or write cycle time t RC 84-104-ns RAS precharge timet RP 30-40-ns CAS precharge time in normal mode t CPN 10-10-ns RAS pulse width t RAS 50100006010000ns 5CAS pulse width t CAS 8100001010000ns 6Row address setup time t ASR 0-0-ns Row address hold time t RAH 8-10-ns Column address setup time t ASC 0-0-ns 7Column address hold time t CAH 8-10-ns RAS to CAS delay timet RCD 12371445ns 8RAS to column address delay time t RAD 10251230ns 9Column address to RAS lead time t RAL 25-30-ns RAS hold time t RSH 8-10-ns CAS hold timet CSH 38-40-ns CAS to RAS precharge time t CRP 5-5-ns 10OE to Din delay time t OED 12-15-ns Transition time (rise and fall)t T 150150ns 11Refresh periodt REF -32-32ms Refresh period (S- Version)t REF -128-128ms CAS to output in Low- Z t CLZ 0-0-ns CAS delay time from Din t DZC 0-0-ns OE delay time from Dint DZO-0-nsRead CycleWrite Cycle Parameter SymbolAD404M42V Unit Notes-5-6Min Max Min MaxAccess time from RAS t RAC-50-60ns12 Access time from CAS t CAC-14-15ns13, 14 Access time from column address t AA-25-30ns14, 15 Access time from OE t OEA-12-15nsRead command setup time t RCS0-0-ns7 Read command hold time to CAS t RCH0-0-ns10, 16 Read command hold time to RAS t RRH0-0-ns16 Output buffer turn-off time t OFF012015ns17 Output buffer turn-off time from OE t OEZ012015ns17Parameter SymbolAD404M42V Unit Notes -5-6Min Max Min MaxWrite command setup time t WCS0-0-ns7, 18 Write command hold time t WCH8-10-nsWrite command pulse width t WP8-10-nsWrite command to RAS lead time t RWL13-15-nsWrite command to CAS lead time t CWL8-10-nsData-in setup time t DS0-0-ns19 Data-in hold time t DH8-10-ns19 WE to Data-in delay t WED10-10-nsRead- Modify- Write CycleRefresh Cycle Parameter SymbolAD404M42V Unit Notes-5-6Min Max Min MaxRead-modify- write cycle time t RWC108-133-nsRAS to WE delay time t RWD64-77-ns18 CAS to WE dealy time t CWD26-32-ns18 Column address to WE delay time t AWD39-47-ns18 OE hold time from WE t OEH8-10-nsParameter SymbolAD404M42VUnit Notes -5-6Min Max Min MaxCAS setup time (CBR refresh) t CSR5-5-nsCAS hold time (CBR refresh)t CHR8-10-ns10 RAS precharge to CAS hold time t RPC5-5-ns7 RAS pulse width (self refresh)t RASS100-100-RAS precharge time (self refresh)t RPS90-110-nsCAS hold time (CBR self refresh)t CHS-50--50-nsWE setup time t WSR0-0-nsWE hold time t WHR10-10-nsµsEDO Page Mode CycleEDO Page Mode Read Modify Write CycleParameterSymbol AD404M42VUnit Notes-5-6Min MaxMin MaxEDO page mode cycle timet PC 20-25-ns EDO page mode CAS precharge time t CP 10-10-ns EDO page mode RAS pulse width t RASP 5010560105ns 20Access time from CAS precharge t CPA -30-35ns 10, 14RAS hold time from CAS precharge t CPRH 30-35-ns OE high hold time from CAS high t OEHC 5-5-ns OE high pulse widtht OEP 10-10-ns Data output hold time after CAS low t COH 5-5-ns Output disable delay from WEt WHZ 310310ns WE pulse width for output disable whenCAS hight WPZ7-7-nsParameterSymbol AD404M42V Unit Notes -5-6Min MaxMin MaxEDO page mode read- modify- write cycle CAS precharge to WE delay timet CPW 45-55-ns 10EDO page mode read- modify- write cycle timet PRWC56-68-nsNotes :1. AC measurements assume t T = 2ns.2. An initial pause of 100 is required after power up, and it followed by a minimum of eightinitialization cycles (RAS - only refresh cycle or CAS - before - RAS refresh cycle). If the internal refresh counter is used, a minimun of eight CAS - before - RAS refresh cycles are required.3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device.4. All the V CC and V SS pins shall be supplied with the same voltages.5. t RAS (min) = t RWD (min)+t RWL (min)+t T in read-modify-write cycle.6. t CAS (min) = t CWD (min)+t CWL (min)+t T in read-modify-write cycle.7. t ASC (min), t RCS (min), t WCS (min), and t RPC are determined by the falling edge of CAS .8. t RCD (max) is specified as a reference point only, and t RAC (max) can be met with the t RCD (max) limit.Otherwise, t RAC is controlled exclusively by t CAC if t RCD is greater than the specified t RCD (max) limit. 9. t RAD (max) is specified as a reference point only, and t RAC (max) can be met with the t RAD (max) limit.Otherwise, t RAC is controlled exclusively by t AA if t RAD is greater than the specified t RAD (max) limit. 10. t CRP , t CHR , t RCH , t CPA and t CPW are determined by the rising edge of CAS .11. V IH (min) and V IL (max) are reference levels for measuring timing or input signals. Therefore, transitiontime is measured between V IH and V IL .12. Assumes that t RCD tRCD (max) and t RAD t RAD (max). If t RCD or t RAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 13. Assumes that (max) and (max).14. Access time is determined by the maximum of t AA , t CAC , t CPA . 15. Assumes that (max) and (max). 16. Either t RCH or t RRH must be satisfied for a read cycle.17. t OFF (max) and t OEZ (max) define the time at which the output achieves the open circuit condition (highimpedance). t OFF is determined by the later rising edge of RAS or CAS.18. t WCS , t RWD , t CWD , and t AWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If (min), the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If (min),(min), (min) and (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data output (at access time) is indeterminate.19. These parameters are referenced to CAS separately in an early write cycle and to WE edge in adelayed write or a read-modify-write cycle.20. t RASP defines RAS pulse width in EDO page mode cycles.µs ≤≤t RCD t RCD ≥t RADt RAD ≤t RCD t RCD ≤t RAD t RAD ≥t WCS t WCS ≥t RWD t RWD ≥t CWDt CWD ≥t AWD t AWD ≥t CPW t CPW≥Timing Waveforms• Read Cyclet RC t RASt RPtCRPtCPNtRRHtRCHt OEZ t OFF tOEA tCACt AAtRACt CLZD OUTtRCS t ASR tRAH tASC tCAH tRAD t RALtCAStRSH tRCDt TtCSHRASCASADDRESSWEDQ1~DQ4Note : = don’t care OEt OFFRowColumn= Invalid Dout•Early Write CycletRC t RASt RPt WCHt DSt DHt WCS t RALtCAStRSH tRCDt TtCSHRASCASWEDQ1~DQ4tCRPtASRtRAH tASCtCAH ADDRESSColumnRowtCPND INtRADt RAL• Delayed Write CycletRC t RASt RPt RWL t RCSt CAStRSH tRCDt TtCSHRASCAStASR tRAH tCAHADDRESSColumnRow tASC D INDQ1~DQ4WEtCRPtCPNt DHt DSt OEHt OEDOEt DSOPENt WPt CWL• Read - Modify - Write CycletRWC t RASt RPtRWDt WPtRADtRWL tCAStCWL tRCDt TtCPNRASCASWEtCRP t ASRtRAHtASCtCAHADDRESS Column RowDQ1~DQ4t DHt DSOEtRCStAWD tCWD D INt OEDt OEHt OEZt OEA t CAC t RACt AADQ1~DQ4D OUTOPENtDZCtDZO• EDO Page Mode Read CycletRASPtCPRHt RCStCAStRSH tRCDt OEAtCSHRASCAStASRtRAHtCAHADDRESStCASWEtCRPt CPOEDQ1~DQ4OPENtOEPD OUT 1t PCt CPtCAStCPNtCRPtRADtCAHtASCt ASCtCAHt ASCt RAL Row Column 1t OEAt OEHCtRRH tRCHt RACt AAt AAt AA t CPA t CPA t OEZt OFFt OFFt CACt OEZt CAC t CACt COHD OUT NWE OE Column 2Column N Rowt RPD OUT 2• EDO Page Mode Early Write CycletRASPtRPt WCSt CAStRSH tRCDRASCAStASRtRAHtCAHADDRESStCASWEt CPDQ1~DQ4t PCt CPt CAStCPNtCRP tCAH tASCtASC tCAH tASC Row Column 1t DS WE Column 2Column Nt WCH t WCS t WCH t WCS t WCHt DH t DS t DH t DS t DHD IN 1D IN 2D IN Nt TtCSH• EDO Page Mode Read-Early-Write Cyclet RASPtCPRHt RCStCAStRSH tRCDt OEAtCSHRASCAStASRtRAHtCAHADDRESStCASWEtCRPt CPOEDQ1~DQ4OPENtWEDt PCt CPtCAStCPNtCRPtRADtRAHtASCt ASCtCAHt ASCt RAL Row Column 1tWCStRCHt RACt AAt AAt CPA t DHt WHZt CACt CACt COHWE OE Column 2Column N Rowt RPt CAL tWCHDataDoutput 2Data Input NDataDoutput 1t DStCSH• EDO Page Mode Read-Modify-Write Cyclet RASPt CPRHt RCStCASt WP RASCASt ASRtRAHtCAHADDRESSt CASWEtRCDCPDQ1~DQ4tPRWCt CPtCAStCRPtRADtCAHtASCt ASCtCAH tASC Row Column 1tRWLtRCSt OEDt DZOt CAC WE OEt RPt RAL D OUT 2D OUT ND OUT 1tTt Column NColumn 2Column 1tRWD tAWD tCWDtCWLtRCStCWDtAWD tCPW tCWL tCPW tAWD tCWDtCWL t OEDt OEDt OEHt OEHt OEHt CAC t CAC t OEA t AAt RACt OEZt OEAt AA t CPAt OEZt OEAt AA t CPAt OEZ t DSt DHt WP t DSt DHt WP t DSt DHOPENOPENOPEN D IN 1D IN ND IN 2DQ1~DQ4t DZCt DZOt DZCt DZCt DZO• Read Cycle with WE Controlled Disablet WPZt RCStCAStRCDt TtCSHRASCASt ASRtRAHtCAHADDRESSColumnRow tASCD DQ1~DQ4WEt OEZt DSt WHZOEt RCH t OEA t CACt AAt RACt CLZOUTtRADRASADDRESSt RC t CRPt ASRt RAHt Tt RPCROWt OFFCAS t RASt RPOPENt CRPDQ1~DQ4RASt CSRt WSRt RPt T t RPCt OFFCAS t RASt RPOPENt CRPDQ1~DQ4t RPCt CHRt RASt RPt RCt RCt CHRt CSRt WHRt WSRt WHRWECAS-Before-RAS Refresh CycleRASWEt RPCt OFFt CSRt CHSt WSRCASt RASS t RPSOPENDQ1~DQ4t WHRHigh lmpedance• Hidden Refresh Cyclet RPt RASRASt RCDt CRPADDRESSWEt CHRt CASt RSHt RAHt ASRt ASCt CAHt RAL ROW t RCHt OEZCASDQ1~DQ4t Tt RCSD t RASt RASt RPt RPt RC t RCt RCt RADt RRHt OFF t OFFt OEA t CACt AAt RACCOlumnOUTOE(READ)(REFRESH)(REFRESH)Ordering informationAD404M42VSA-5• AD• Ascend Memory Product • 40 • Device Type• 4M4 • Density and Organization • 2• Refresh Rate, 2: 2K Refresh • V• T: 5V, V: 3.3V• S • Package Type (S : SOJ, T : TSOP II)• A• Version• 5• Speed (5: 50 ns, 6: 60 ns)Part Number Access time PackageAD404M42VSA-5AD404M42VSA-6AD404M42VTA-5AD404M42VTA-650 ns 60 ns 50 ns 60 ns300mil 26/24-Pin Plastic SOJTSOP IIPackaging information • 300 mil, 26/24-Pin Plastic SOJ• 300 mil, 26/24-Pin TSOP II。
TDA2050-TB5-T中文资料
UNISONIC TECHNOLOGIES CO., LTDTDA2050 LINEAR INTEGRATED CIRCUIT32W HI-FI AUDIO POWER AMPLIFIERDESCRIPTIONThe UTC TDA2050 is a monolithic integrated circuit with high power capability and is designed to use as an class AB audio amplifier. It can deliver typically 50W music power into 4Ω load over 1 sec at V S =22.5V, f = 1KHz.The device is most suitable for both Hi-Fi and high class TV sets on the strength of its high supply voltage and very low harmonic and crossover distortion.FEATURES* High output power (50W Music Power IEC 268.3 Rules) * High operating supply voltage (50V) * Single or split supply operations * Very low distortion* Short circuit protection (OUT to GND) * Thermal shutdown*Pb-free plating product number: TDA2050LORDERING INFORMATIONOrdering Number Normal Lead Free Plating Package PackingTDA2050-TB5-T TDA2050L-TB5-TTO-220BTubePIN CONFIGURATION*TAB CONNECTED TO PIN 3OUTPUT +V S -V SINVERTING INPUT NON INVERTING INPUTBLOCK DIAGRAMABSOLUTE MAXIMUM RATINGSPARAMETER SYMBOL RATINGS UNITSupply Voltage V S ±25 V Input Voltage V IN V SDifferential Input Voltage V IN(DIFF) ±15℃ Output Peak Current (internally limited) I OUT 5℃ Power Dissipation T C = 75℃ P D 25 WJunction Temperature T J +125℃ Storage Temperature T STG -40 ~ +150 ℃ Note:1.Absolute maximum ratings are those values beyond which the device could be permanently damaged.Absolute maximum ratings are stress ratings only and functional device operation is not implied.2.The device is guaranteed to meet performance specification within 0℃~70℃ operating temperature range and assured by design from –40℃~85℃.THERMAL DATAPARAMETERSYMBOLRATINGS UNITThermal Resistance junction-case θJC3 ℃/WELECTRICAL CHARACTERISTICS(Refer to the Test Circuit, V S = ±18V, Ta = 25℃, f = 1 kHz, unless otherwise specified.)PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITSupply Voltage V S ±4.5 ±25VQuiescent Drain Current I DV S = ±4.5VV S = ±25V18 21 50 90 mA Input Bias Current I B V S = ±22V 0.4 0.5µA Input Offset Voltage V IN(OS) V S = ±22V ±15mV Input Offset Current I IN(OS) V S = ±22V ±200nAD = 0.5%R L = 4ΩR L = 8Ω R L = 8Ω, V S = ±22V24 22 27 18 25 RMS Output PowerD = 10%R L = 4ΩR L = 8Ω R L = 8Ω, V S = ±22V 35 22 32Music Power IEC268.3 RULES P O D = 10%, T = 1s, V S = ±22.5V, R L = 4Ω50 W R L = 4Ω f = 1kHz, P O = 0.1 ~ 24W f = 100Hz ~ 10kHz, P O = 0.1 ~ 18W 0.03 0.50.5Total Harmonic Distortion THD R L = 8Ω, V S = ±22V f = 1kHz, P O = 0.1 ~ 20W f = 100Hz ~ 10kHz, P O = 0.1 ~ 15W 0.02 0.5%Slew Rate SR 5 8 V/µs Open Loop Voltage Gain G V 80 dB Closed Loop Voltage Gain G V 30 30.5 31 dB Power Bandwidth (-3dB) B W R L = 4Ω, V IN = 200mV 20 ~ 80000 HzTotal Input Noise e NCurve AB = 22Hz ~ 22kHz4 5 10 µV Input Resistance (pin 1) R IN 500 k ΩSupply Voltage Rejection SVR R S = 22K Ω, f =100Hz, V RIPPLE =0.5Vrms 45 dBP O = 28W, R L = 4Ω 65Efficiency η P O = 25W, R L = 8Ω, V S = ±22V 67%TYPICAL APPLICATION CIRCUITFOR SPLIT SUPPLY APPLICATION SUGGESTIONSR LV INFigure.1 Split Supply Typical Application CircuitThe following table demonstrates the recommended values of the external components are those shown on above circuit. Different values can be used.RECOMMENDED VALUECOMPONENT PURPOSETYPICAL LARGER SMALLERR1 Input Impedance 22k ΩIncrease of Input Impedance Decrease of InputImpedanceR2 Feedback Resistor 680Ω Decrease of Gain* Increase of Gain R3 22k Ω Increase of Gain Decrease of Gain* R4 Frequency Stability 2.2Ω Danger of Oscillations C1 Input Decoupling DC 1µF Higher Low-frequency cut-offC2Inverting Input DCDecoupling22µF Increase of Switch ON/OFF Noise Higher Low-frequency cut-off C3, C4 Supply Voltage Bypass 100nF Danger of Oscillations C5, C6 Supply Voltage Bypass 220µF Danger of Oscillations C7 Frequency Stability 0.47µF Danger of Oscillations* The gain must be higher than 24dBTYPICAL APPLICATION CIRCUIT(CONT.)FOR SINGLE SUPPLY APPLICATION SUGGESTIONSR L C21000μFFigure.2 Single Supply Typical Application CircuitThe following table demonstrates the recommended values of the external components are those shown on above circuit. Different values can be used.RECOMMENDED VALUECOMPONENT PURPOSETYPICAL LARGER SMALLER R1, R2, R3 Biasing Resistor 22kΩR4 FeedbackResistor22kΩIncrease of Gain Decrease of Gain*R5 680ΩDecrease of Gain*Increase of GainR6 FrequencyStability 2.2ΩDanger of OscillationsC1 Input Decoupling DC 2.2µF Higher Low-frequency cut-offC2 Supply VoltageRejection100µFWorse Turn-off TransientWorse Turn-on DelayC3 Supply Voltage Bypass1000µF Danger of Oscillations Worse of Turn-off TransientC4 Inverting Input DCDecoupling22µFIncrease of Switch ON/OFFHigher Low-frequency cut-offC5 Supply Voltage Bypass100nF Danger of OscillationsC6 FrequencyStability 0.47µF Danger of Oscillations C7 Output DC Decoupling1000µF Higher Low-frequency cut-off * The gain must be higher than 24dBNOTE: If the supply voltage is lower than 40V and the load is 8Ω(or more), a lower value of C2(i.e. 22µF) can be used.C7 can be larger than 1000µF only if the supply voltage does not exceed 40V.TYPICAL CHARACTERISTICS (Split Supply Test Circuit, unless otherwise specified )P O (W )V S (V)152025301050Output Power vs. Supply VoltageP O (W )V S(V)15202530105Output Power vs. Supply VoltageI D (m A )V S (V)35404550302520Quiescent Current vs. Supply Voltage P D (W )P O (W)152********Total Power Dissipation and Efficiencyvs. Output Power 55m (%)3530405060201007080P D (W )P O (W)12162024840Total Power Dissipation and Efficiencyvs. Output Power m (%)2830405060201007080354040603540。
各类2020年垂直盘PMR区分和最新叠瓦盘SMR及其性能参数表
2020年各类最新叠Brand Series Market Model SMR/PMR CapacityRPMDisk/HeadSeagate Barracuda Desktop ST500DM009PMR500 GB72001/1 Seagate Barracuda Desktop ST1000DM010PMR 1 TB72001/2 Seagate Barracuda Desktop ST2000DM005SMR 2 TB54001/2 Seagate Barracuda Desktop ST2000DM006PMR 2 TB72003/6 Seagate Barracuda Desktop ST2000DM007PMR 2 TB72002/4 Seagate Barracuda Desktop ST2000DM008SMR 2 TB72001/2 Seagate Barracuda Desktop ST3000DM007SMR 3 TB54002/3 Seagate Barracuda Desktop ST4000DM004SMR 4 TB54002/4 Seagate Barracuda Desktop ST6000DM003SMR 6 TB54003/6 Seagate Barracuda Desktop ST8000DM004SMR8 TB54004/8 Seagate Barracuda Pro Enthusiast ST2000DM009PMR 2 TB72002/4 Seagate Barracuda Pro Enthusiast ST4000DM006PMR 4 TB72004/7 Seagate Barracuda Pro Enthusiast ST6000DM004PMR 6 TB72006/12 Seagate Barracuda Pro Enthusiast ST8000DM005PMR8 TB72006/12 Seagate Barracuda Pro Enthusiast ST8000DM0004PMR8 TB72007/14 Seagate Barracuda Pro Enthusiast ST10000DM001PMR+TDMR10 TB72008/13 Seagate Barracuda Pro Enthusiast ST10000DM0004PMR10 TB72007/14 Seagate Barracuda Pro Enthusiast ST12000DM001PMR+TDMR12 TB72008/15 Seagate Barracuda Pro Enthusiast ST12000DM0007PMR12 TB72008/16 Seagate Barracuda Pro Enthusiast ST14000DM001PMR+TDMR14 TB72008/16 Seagate IronWolf NAS ST1000VN002PMR 1 TB59001/2 Seagate IronWolf NAS ST2000VN004PMR 2 TB59002/4 Seagate IronWolf NAS ST3000VN007PMR 3 TB59003/6 Seagate IronWolf NAS ST4000VN008PMR 4 TB59003/6 Seagate IronWolf NAS ST6000VN001PMR 6 TB54004/8Seagate IronWolf NAS ST6000VN0033PMR 6 TB72005/10 Seagate IronWolf NAS ST8000VN004PMR8 TB72005/10 Seagate IronWolf NAS ST8000VN0022PMR8 TB72006/12 Seagate IronWolf NAS ST10000VN0004PMR10 TB72008/16 Seagate IronWolf NAS ST10000VN0008PMR+TDMR10 TB72008/13 Seagate IronWolf NAS ST12000VN0007PMR12 TB72008/16 Seagate IronWolf NAS ST12000VN0008PMR+TDMR12 TB72008/15 Seagate IronWolf NAS ST14000VN0008PMR+TDMR14 TB72008/16 Seagate IronWolf NAS ST14000VN0008PMR+TDMR14 TB72009/18 Seagate IronWolf NAS ST16000VN001PMR+TDMR16 TB72009/18Seagate IronWolf Pro EnterpriseNASST2000NE0025PMR 2 TB72002/4Seagate IronWolf Pro EnterpriseNASST4000NE0025PMR 4 TB72004/7Seagate IronWolf Pro EnterpriseNASST4000NE001PMR 4 TB72003/6Seagate IronWolf Pro EnterpriseNASST6000NE0021PMR 6 TB72006/12Seagate IronWolf Pro EnterpriseNASST6000NE0023PMR 6 TB72006/12Seagate IronWolf Pro EnterpriseNASST6000NE000PMR 6 TB72004/8Seagate IronWolf Pro EnterpriseNASST8000NE0021PMR8 TB72006/12Seagate IronWolf Pro EnterpriseNASST8000NE001PMR8 TB72005/10Seagate IronWolf Pro EnterpriseNASST8000NE0004PMR8 TB72007/14Seagate IronWolf Pro EnterpriseNASST10000NE0004PMR10 TB72007/14Seagate IronWolf Pro EnterpriseNASST10000NE0004PMR10 TB72008/16Seagate IronWolf Pro EnterpriseNASST10000NE0008PMR+TDMR10 TB72008/13Seagate IronWolf Pro EnterpriseNASST12000NE0007PMR12 TB72008/16Seagate IronWolf Pro EnterpriseNASST12000NE0008PMR+TDMR12 TB72008/15Seagate IronWolf Pro EnterpriseNASST14000NE0008PMR+TDMR14 TB72008/16Seagate IronWolf Pro EnterpriseNASST14000NE0008PMR+TDMR14 TB72009/18Seagate IronWolf Pro EnterpriseNASST16000NE000PMR+TDMR16 TB72009/18Seagate SkyHawk Surveillance ST1000VX005PMR 1 TB59001/2 Seagate SkyHawk Surveillance ST2000VX008PMR 2 TB59002/4 Seagate SkyHawk Surveillance ST2000VX012SMR 2 TB54001/2 Seagate SkyHawk Surveillance ST2000VX015SMR 2 TB54001/2 Seagate SkyHawk Surveillance ST2000VP001SMR 2 TB54001/2 Seagate SkyHawk Surveillance ST3000VX009SMR 3 TB54002/4 Seagate SkyHawk Surveillance ST3000VX010PMR 3 TB59003/6 Seagate SkyHawk Surveillance ST4000VX005SMR 4 TB54002/4 Seagate SkyHawk Surveillance ST4000VX013SMR 4 TB54002/4 Seagate SkyHawk Surveillance ST4000VX007PMR 4 TB59003/6 Seagate SkyHawk Surveillance ST4000VP001SMR 4 TB54002/4 Seagate SkyHawk Surveillance ST6000VX001SMR 6 TB54004/8 Seagate SkyHawk Surveillance ST6000VP001SMR 6 TB54004/8 Seagate SkyHawk Surveillance ST6000VP000SMR 6 TB54004/8 Seagate SkyHawk Surveillance ST6000VX0023PMR 6 TB72005/10 Seagate SkyHawk Surveillance ST8000VX002SMR8 TB54004/8 Seagate SkyHawk Surveillance ST8000VX008SMR8 TB54004/8 Seagate SkyHawk Surveillance ST8000VP001SMR8 TB54004/8 Seagate SkyHawk Surveillance ST8000VX0022PMR8 TB72006/12 Seagate SkyHawk Surveillance ST8000VX004PMR8 TB72005/10 Seagate SkyHawk AI AI Surveillance ST6000VE000PMR 6 TB72004/8 Seagate SkyHawk AI AI Surveillance ST8000VE000PMR8 TB72005/10 Seagate SkyHawk AI AI Surveillance ST8000VE0004PMR8 TB72007/14 Seagate SkyHawk AI AI Surveillance ST10000VE0004PMR10 TB72007/14 Seagate SkyHawk AI AI Surveillance ST10000VE0008PMR+TDMR10 TB72008/13 Seagate SkyHawk AI AI Surveillance ST12000VE0008PMR+TDMR12 TB72008/15 Seagate SkyHawk AI AI Surveillance ST12000VE0008PMR+TDMR12 TB72009/16Seagate SkyHawk AI AI Surveillance ST14000VE0008PMR+TDMR14 TB72008/16 Seagate SkyHawk AI AI Surveillance ST14000VE0008PMR+TDMR14 TB72009/18 Seagate SkyHawk AI AI Surveillance ST16000VE000PMR+TDMR16 TB72009/18 Seagate Exos 5E8Enterprise ST8000AS0003SMR8 TB59804/8 Seagate Exos 7E2Enterprise ST1000NM0008PMR 1 TB72002/2 Seagate Exos 7E2Enterprise ST2000NM0008PMR 2 TB72002/4 Seagate Exos 7E8 512n Enterprise ST1000NM000A PMR 1 TB72002/2 Seagate Exos 7E8 512n Enterprise ST2000NM000A PMR 2 TB72002/3 Seagate Exos 7E8 512n Enterprise ST3000NM000A PMR 3 TB72003/6 Seagate Exos 7E8 512n Enterprise ST4000NM000A PMR 4 TB72003/6 Seagate Exos 7E8 512n Enterprise ST6000NM002A PMR 6 TB72005/10 Seagate Exos 7E8 512e Enterprise ST2000NM001A PMR 2 TB72002/3 Seagate Exos 7E8 512e Enterprise ST4000NM002A PMR 4 TB72003/6 Seagate Exos 7E8 512e Enterprise ST6000NM021A PMR 6 TB72004/8 Seagate Exos 7E8 512e Enterprise ST8000NM000A PMR8 TB72005/10 Seagate Exos 7E8 4Kn Enterprise ST2000NM002A PMR 2 TB72002/3 Seagate Exos 7E8 4Kn Enterprise ST4000NM001A PMR 4 TB72003/6 Seagate Exos 7E8 4Kn Enterprise ST6000NM022A PMR 6 TB72004/8 Seagate Exos 7E8 4Kn Enterprise ST8000NM002A PMR8 TB72005/10 Seagate Exos X10 512e Enterprise ST8000NM0206PMR8 TB72007/14 Seagate Exos X10 4Kn Enterprise ST8000NM0136PMR8 TB72007/14 Seagate Exos X10 512e Hyperscale ST8000NM0016PMR8 TB72007/14 Seagate Exos X10 4Kn Hyperscale ST8000NM0006PMR8 TB72007/14 Seagate Exos X10 512e Enterprise ST10000NM0086PMR10 TB72007/14 Seagate Exos X10 4Kn Enterprise ST10000NM0146PMR10 TB72007/14 Seagate Exos X10 512e Hyperscale ST10000NM0016PMR10 TB72007/14 Seagate Exos X10 4Kn Hyperscale ST10000NM0006PMR10 TB72007/14Seagate Exos X12Enterprise ST12000NM0007PMR12 TB72008/16 Seagate Exos X14Enterprise ST10000NM0478PMR+TDMR10 TB72008/13 Seagate Exos X14Enterprise ST12000NM0008PMR+TDMR12 TB72008/15 Seagate Exos X14Enterprise ST14000NM0008PMR+TDMR14 TB72008/16 Seagate Exos X16 512e Hyperscale ST10000NM001G PMR+TDMR10 TB72009/14 Seagate Exos X16 512e Hyperscale ST12000NM001G PMR+TDMR12 TB72009/16 Seagate Exos X16 512e Hyperscale ST14000NM001G PMR+TDMR14 TB72009/16 Seagate Exos X16 512e Hyperscale ST16000NM001G PMR+TDMR16 TB72009/18 Seagate Exos X16 4Kn Hyperscale ST10000NM009G PMR+TDMR10 TB72009/14 Seagate Exos X16 4Kn Hyperscale ST12000NM007G PMR+TDMR12 TB72009/16 Seagate Exos X16 4Kn Hyperscale ST14000NM010G PMR+TDMR14 TB72009/16 Seagate Exos X16 4Kn Hyperscale ST16000NM008G PMR+TDMR16 TB72009/18 WD Blue Desktop WD5000AZLX PMR500 GB72001/2 WD Blue Desktop WD5000AZRZ PMR500 GB54001/2 WD Blue Desktop WD10EZEX PMR 1 TB72001/2 WD Blue Desktop WD10EZRZ PMR 1 TB54001/2 WD Blue Desktop WD20EZRZ PMR 2 TB54002/4 WD Blue Desktop WD20EZAZ SMR 2 TB54001/2 WD Blue Desktop WD30EZRZ PMR 3 TB54003/6 WD Blue Desktop WD40EZRZ PMR 4 TB54003/6 WD Blue Desktop WD60EZRZ PMR 6 TB54005/6 WD Blue Desktop WD60EZAZ SMR 6 TB54003/6 WD Black Enthusiast WD5003AZEX PMR500 GB72001/1 WD Black Enthusiast WD1003FZEX PMR 1 TB72001/2 WD Black Enthusiast WD2003FZEX PMR 2 TB72003/6 WD Black Enthusiast WD4004FZWZ PMR 4 TB72005/10 WD Black Enthusiast WD4005FZBX PMR 4 TB72005/10 WD Black Enthusiast WD6002FZWZ PMR 6 TB72005/10 WD Black Enthusiast WD6003FZBZ PMR 6 TB72005/10 WD Red NAS WD10EFRX PMR 1 TB54001/2 WD Red NAS WD20EFRX PMR 2 TB54002/4 WD Red NAS WD20EFAX SMR 2 TB54001/2 WD Red NAS WD30EFRX PMR 3 TB54003/6 WD Red NAS WD30EFAX SMR 3 TB54002/3 WD Red NAS WD40EFRX PMR 4 TB54004/8 WD Red NAS WD40EFAX SMR 4 TB54002/4 WD Red NAS WD60EFRX PMR 6 TB54005/10 WD Red NAS WD60EFAX SMR 6 TB54003/6 WD Red NAS WD80EFAX PMR8 TB54005/10 WD Red NAS WD100EFAX PMR10 TB54007/14 WD Red NAS WD101EFAX PMR10 TB54006/12 WD Red NAS WD120EFAX PMR12 TB54008/16WD Red NAS WD140EFFX PMR+TDMR14 TB54009/18 WD Red Pro Enterprise WD2002FFSX PMR 2 TB72002/4 WD Red Pro Enterprise WD4003FFBX PMR 4 TB72003/6 WD Red Pro Enterprise WD6003FFBX PMR 6 TB72004/8 WD Red Pro Enterprise WD8003FFBX PMR8 TB72005/10 WD Red Pro Enterprise WD101KFBX PMR10 TB72007/14 WD Red Pro Enterprise WD102KFBX PMR10 TB72006/12 WD Red Pro Enterprise WD121KFBX PMR12 TB72008/16 WD Red Pro Enterprise WD141KFGX PMR+TDMR14 TB72009/18 WD Purple Surveillance WD10PURZ PMR 1 TB54001/2 WD Purple Surveillance WD20PURZ PMR 2 TB54002/4 WD Purple Surveillance WD30PURZ PMR 3 TB54003/6 WD Purple Surveillance WD40PURZ PMR 4 TB54004/8 WD Purple Surveillance WD60PURZ PMR 6 TB54005/10 WD Purple AI Surveillance WD82PURZ PMR8 TB72005/10 WD Purple AI Surveillance WD101PURZ PMR10 TB72007/14 WD Purple AI Surveillance WD102PURZ PMR10 TB72006/12 WD Purple AI Surveillance WD121PURZ PMR12 TB72008/16 WD Purple AI Surveillance WD140PURZ PMR+TDMR14 TB72009/18 WD Gold Enterprise WD1005FBYZ PMR 1 TB72001/2 WD Gold Enterprise WD2005FBYZ PMR 2 TB72002/4 WD Gold Enterprise WD4003FRYZ PMR 4 TB72003/6 WD Gold Enterprise WD6003FRYZ PMR 6 TB72004/8 WD Gold Enterprise WD8004FRYZ PMR8 TB72005/10 WD Gold Enterprise WD102KRYZ PMR10 TB72006/12 WD Gold Enterprise WD121KRYZ PMR12 TB72008/16 WD Gold Enterprise WD141KRYZ PMR+TDMR14 TB72009/18 Ultrastar DC HA210Enterprise HUS722T1TALE604PMR 1 TB72001/2 Ultrastar DC HA210Enterprise HUS722T2TALE604PMR 2 TB72002/4 Ultrastar DC HC310 512n Enterprise HUS726T4TALA6L4PMR 4 TB72003/6 Ultrastar DC HC310 4Kn Enterprise HUS726T4TALE6L4PMR 4 TB72003/6 Ultrastar DC HC310 512n Enterprise HUS726T6TALA6L4PMR 6 TB72004/8 Ultrastar DC HC310 4Kn Enterprise HUS726T6TALE6L4PMR 6 TB72004/8 Ultrastar DC HC320Enterprise HUS728T8TALE6L4PMR8 TB72005/10 Ultrastar DC HC330Enterprise WUS721010ALE6L4PMR10 TB72006/12 Ultrastar DC HC510 512e Enterprise HUH721008ALE604PMR8 TB72007/14 Ultrastar DC HC510 4Kn Enterprise HUH721008ALN604PMR8 TB72007/14 Ultrastar DC HC510 512e Enterprise HUH721010ALE604PMR10 TB72007/14 Ultrastar DC HC510 4Kn Enterprise HUH721010ALN604PMR10 TB72007/14 Ultrastar DC HC520 512e Enterprise HUH721212ALE604PMR12 TB72008/16 Ultrastar DC HC520 4Kn Enterprise HUH721212ALN604PMR12 TB72008/16 Ultrastar DC HC530Enterprise WUH721414ALE604PMR+TDMR14 TB72009/18 Ultrastar DC HC620 512e Enterprise HSH721414ALE6M4SMR14 TB72008/16 Ultrastar DC HC620 4Kn Enterprise HSH721414ALN6M SMR14 TB72008/16 Ultrastar DC HC620 512e Enterprise HSH721415ALE6M4SMR15 TB72008/16 Ultrastar DC HC620 4Kn Enterprise HSH721415ALN6M SMR15 TB72008/16 Toshiba P300Desktop HDWD105PMR500 GB72001/1 Toshiba P300Desktop HDWD110PMR 1 TB72001/2 Toshiba P300Desktop HDWD120PMR 2 TB72002/4 Toshiba P300Desktop HDWD130PMR 3 TB72003/6 Toshiba P300Desktop HDWD240SMR 4 TB54002/4 Toshiba P300Desktop HDWD260SMR 6 TB54003/6Toshiba X300Enthusiast HDWE140PMR 4 TB72004/8 Toshiba X300Enthusiast HDWE150PMR 5 TB72005/10 Toshiba X300Enthusiast HDWE160PMR 6 TB72006/12 Toshiba X300Enthusiast HDWE180PMR8 TB72006/12 Toshiba X300Enthusiast HDWR11A PMR10 TB72007/14 Toshiba X300Enthusiast HDWR21C PMR12 TB72008/16 Toshiba X300Enthusiast HDWR21E PMR14 TB72009/18 Toshiba N300NAS HDWQ140PMR 4 TB72004/8 Toshiba N300NAS HDWN160PMR 6 TB72006/12 Toshiba N300NAS HDWN180PMR8 TB72006/12 Toshiba N300NAS HDWG11A PMR10 TB72007/14 Toshiba N300NAS HDWG21C PMR12 TB72008/16 Toshiba N300NAS HDWG21E PMR14 TB72009/18 Toshiba V300Video Stream HDWU105PMR500 GB57001/1 Toshiba V300Video Stream HDWU110PMR 1 TB57001/2 Toshiba V300Video Stream HDWU120PMR 2 TB57002/4 Toshiba V300Video Stream HDWU130PMR 3 TB59403/6 Toshiba S300Surveillance HDWT140PMR 4 TB54004/8 Toshiba S300Surveillance HDWT240SMR 4 TB54002/4 Toshiba S300Surveillance HDWT150PMR 5 TB54005/10 Toshiba S300Surveillance HDWT360PMR 6 TB72006/12 Toshiba S300Surveillance HDWT380PMR8 TB72006/12 Toshiba S300Surveillance HDWT31A PMR10 TB72007/14 Toshiba MG04ACA-N Enterprise MG04ACA100N PMR 1 TB72001/2 Toshiba MG04ACA-N Enterprise MG04ACA200N PMR 2 TB72002/4 Toshiba MG04ACA-N Enterprise MG04ACA400N PMR 4 TB72004/8 Toshiba MG04ACA 4Kn Enterprise MG04ACA200A PMR 2 TB72002/4 Toshiba MG04ACA 512e Enterprise MG04ACA200E PMR 2 TB72002/4 Toshiba MG04ACA 4Kn Enterprise MG04ACA300A PMR 3 TB72003/6 Toshiba MG04ACA 512e Enterprise MG04ACA300E PMR 3 TB72003/6 Toshiba MG04ACA 4Kn Enterprise MG04ACA400A PMR 4 TB72004/8 Toshiba MG04ACA 512e Enterprise MG04ACA400E PMR 4 TB72004/8 Toshiba MG04ACA 4Kn Enterprise MG04ACA500A PMR 5 TB72005/10 Toshiba MG04ACA 512e Enterprise MG04ACA500E PMR 5 TB72005/10 Toshiba MG04ACA 4Kn Enterprise MG04ACA50DA PMR 5 TB72006/10 Toshiba MG04ACA 512e Enterprise MG04ACA50DE PMR 5 TB72006/10 Toshiba MG04ACA 4Kn Enterprise MG04ACA600A PMR 6 TB72006/12 Toshiba MG04ACA 512e Enterprise MG04ACA600E PMR 6 TB72006/12 Toshiba MG05ACA 4Kn Enterprise MG05ACA800A PMR8 TB72006/12 Toshiba MG05ACA 512e Enterprise MG05ACA800E PMR8 TB72006/12 Toshiba MG06ACA 4Kn Enterprise MG06ACA600A PMR 6 TB72005/10 Toshiba MG06ACA 512e Enterprise MG06ACA600E PMR 6 TB72005/10 Toshiba MG06ACA 4Kn Enterprise MG06ACA800A PMR8 TB72006/12 Toshiba MG06ACA 512e Enterprise MG06ACA800E PMR8 TB72006/12 Toshiba MG06ACA 4Kn Enterprise MG06ACA10TA PMR10 TB72007/14 Toshiba MG06ACA 512e Enterprise MG06ACA10TE PMR10 TB72007/14 Toshiba MG07ACA 4Kn Enterprise MG07ACA12TA PMR12 TB72008/16 Toshiba MG07ACA 512n Enterprise MG07ACA12TE PMR12 TB72008/16 Toshiba MG07ACA 4Kn Enterprise MG07ACA14TA PMR14 TB72009/18 Toshiba MG07ACA 512n Enterprise MG07ACA14TE PMR14 TB72009/18 Toshiba MG08ACA 4Kn Enterprise MG08ACA16TA PMR+TDMR16 TB72009/18 Toshiba MG08ACA 512n Enterprise MG08ACA16TE PMR+TDMR16 TB72009/18最新叠瓦盘SMR和垂直盘PMR区分及其性能参数表Cap./Disk Density Cache Speed Helium/AirL/ULCycleWorkloadPower-OnPower Op1 TB625 Gb/in²32 MB210 MB/s Air30000055 TB/Y 2400hrs/Y5.3 W1 TB625 Gb/in²64 MB210 MB/s Air30000055 TB/Y 2400hrs/Y5.3 W2 TB1203 Gb/in²256MB190 MB/s Air30000055 TB/Y2400hrs/Y3.7 W1 TB625 Gb/in²64 MB210 MB/s Air30000055 TB/Y 2400hrs/Y8 W1 TB625 Gb/in²64 MB210 MB/s Air30000055 TB/Y 2400hrs/Y8 W2 TB1188 Gb/in²256MB220 MB/s Air30000055 TB/Y2400hrs/Y5.1 W2 TB1203 Gb/in²256MB185 MB/s Air30000055 TB/Y2400hrs/Y3.7 W2 TB1203 Gb/in²256MB190 MB/s Air30000055 TB/Y2400hrs/Y3.7 W2 TB1203 Gb/in²256MB185 MB/s Air30000055 TB/Y2400hrs/Y5.3 W2 TB1203 Gb/in²256MB190 MB/s Air30000055 TB/Y2400hrs/Y5.3 W1 TB651 Gb/in²128MB195 MB/s Air600000180 TB/Y8760hrs/Y6.7 W1.33 TB732 Gb/in²128MB214 MB/s Air600000180 TB/Y8760hrs/Y6.7 W1.33 TB732 Gb/in²256MB214 MB/s Air600000180 TB/Y8760hrs/Y9.0 W1.33 TB732 Gb/in²256MB214 MB/s Air600000180 TB/Y8760hrs/Y9.0 W1.43 TB867 Gb/in²256MB220 MB/s Helium300000300 TB/Y8760hrs/Y6.8 W1.75 TB1058 Gb/in²256MB250 MB/s Helium300000300 TB/Y8760hrs/Y6.9 W1.43 TB867 Gb/in²256MB220 MB/s Helium300000300 TB/Y8760hrs/Y7.8 W1.75 TB1058 Gb/in²256MB250 MB/s Helium300000300 TB/Y8760hrs/Y6.9 W1.5 TB923 Gb/in²256MB250 MB/s Helium300000300 TB/Y8760hrs/Y7.8 W1.75 TB1058 Gb/in²256MB250 MB/s Helium300000300 TB/Y8760hrs/Y6.9 W1 TB625 Gb/in²64 MB180 MB/s Air600000180 TB/Y 8760hrs/Y3.76 W1 TB613 Gb/in²64 MB180 MB/s Air600000180 TB/Y 8760hrs/Y4.3 W1 TB613 Gb/in²64 MB180 MB/s Air600000180 TB/Y 8760hrs/Y4.8 W1.33 TB810 Gb/in²64 MB180 MB/s Air600000180 TB/Y 8760hrs/Y4.8 W1.5 TB900 Gb/in²256MB190 MB/s Air600000180 TB/Y8760hrs/Y5.3 W1.33 TB732 Gb/in²256MB210 MB/s Air600000180 TB/Y8760hrs/Y8.1 W1.6 TB930 Gb/in²256MB210 MB/s Air600000180 TB/Y8760hrs/Y8.8 W1.33 TB732 Gb/in²256MB210 MB/s Air600000180 TB/Y8760hrs/Y8.8 W1.5 TB923 Gb/in²256MB210 MB/s Helium600000180 TB/Y8760hrs/Y7.8 W1.75 TB1058 Gb/in²256MB220 MB/s Helium600000180 TB/Y8760hrs/Y7.8 W1.5 TB923 Gb/in²256MB210 MB/s Helium600000180 TB/Y8760hrs/Y7.8 W1.75 TB1058 Gb/in²256MB220 MB/s Helium600000180 TB/Y8760hrs/Y7.8 W1.75 TB1058 Gb/in²256MB220 MB/s Helium600000180 TB/Y8760hrs/Y7.8 W1.78 TB1028 Gb/in²256MB210 MB/s Helium600000180 TB/Y8760hrs/Y7.3 W1.78 TB1028 Gb/in²256MB210 MB/s Helium600000180 TB/Y8760hrs/Y7.3 W1 TB651 Gb/in²128MB195 MB/s Air600000300 TB/Y8760hrs/Y6.5 W1.33 TB732 Gb/in²128MB214 MB/s Air600000300 TB/Y8760hrs/Y8.5 W1.6 TB930 Gb/in²256MB214 MB/s Air600000300 TB/Y8760hrs/Y9.0 W1.33 TB732 Gb/in²256MB214 MB/s Air600000300 TB/Y8760hrs/Y8.1 W1.33 TB732 Gb/in²256MB214 MB/s Air600000300 TB/Y8760hrs/Y8.1 W1.6 TB930 Gb/in²256MB214 MB/s Air600000300 TB/Y8760hrs/Y8.1 W1.33 TB732 Gb/in²256MB214 MB/s Air600000300 TB/Y8760hrs/Y8.78 W1.6 TB930 Gb/in²256MB214 MB/s Air600000300 TB/Y8760hrs/Y9.2 W1.43 TB867 Gb/in²256MB214 MB/s Helium600000300 TB/Y8760hrs/Y7.4 W1.43 TB867 Gb/in²256MB214 MB/s Helium600000300 TB/Y8760hrs/Y7.8 W1.5 TB923 Gb/in²256MB250 MB/s Helium600000300 TB/Y8760hrs/Y7.8 W1.75 TB1058 Gb/in²256MB250 MB/s Helium600000300 TB/Y8760hrs/Y7.8 W1.5 TB923 Gb/in²256MB250 MB/s Helium600000300 TB/Y8760hrs/Y7.8 W1.75 TB1058 Gb/in²256MB250 MB/s Helium600000300 TB/Y8760hrs/Y7.6 W1.75 TB1058 Gb/in²256MB250 MB/s Helium600000300 TB/Y8760hrs/Y7.9 W1.78 TB1028 Gb/in²256MB255 MB/s Helium600000300 TB/Y8760hrs/Y7.6 W1.78 TB1028 Gb/in²256MB255 MB/s Helium600000300 TB/Y8760hrs/Y7.6 W1 TB625 Gb/in²64 MB180 MB/s Air300000180 TB/Y 8760hrs/Y5.6 W1 TB613 Gb/in²64 MB180 MB/s Air300000180 TB/Y 8760hrs/Y5.6 W2 TB1186 Gb/in²256MB180 MB/s Air600000180 TB/Y8760hrs/Y2 TB1186 Gb/in²256MB180 MB/s Air600000180 TB/Y8760hrs/Y2 TB1186 Gb/in²256MB180 MB/s Air600000180 TB/Y8760hrs/Y1.5 TB900 Gb/in²256MB180 MB/s Air600000180 TB/Y8760hrs/Y3.5 W1 TB613 Gb/in²64 MB180 MB/s Air300000180 TB/Y 8760hrs/Y5.6 W2 TB1186 Gb/in²256MB180 MB/s Air600000180 TB/Y8760hrs/Y2 TB1186 Gb/in²256MB180 MB/s Air600000180 TB/Y8760hrs/Y1.33 TB810 Gb/in²64 MB180 MB/s Air300000180 TB/Y 8760hrs/Y5.5 W2 TB1186 Gb/in²256MB180 MB/s Air600000180 TB/Y8760hrs/Y1.5 TB900 Gb/in²256MB180 MB/s Air600000180 TB/Y8760hrs/Y5.0 W1.5 TB900 Gb/in²256MB180 MB/s Air600000180 TB/Y8760hrs/Y5.0 W1.5 TB900 Gb/in²256MB180 MB/s Air600000180 TB/Y8760hrs/Y5.0 W1.33 TB732 Gb/in²256MB210 MB/s Air300000180 TB/Y8760hrs/Y9.0 W2 TB1186 Gb/in²256MB180 MB/s Air600000180 TB/Y8760hrs/Y2 TB1186 Gb/in²256MB180 MB/s Air600000180 TB/Y8760hrs/Y2 TB1186 Gb/in²256MB180 MB/s Air600000180 TB/Y8760hrs/Y1.33 TB732 Gb/in²256MB210 MB/s Air300000180 TB/Y8760hrs/Y9.0 W1.6 TB930 Gb/in²256MB210 MB/s Air300000180 TB/Y8760hrs/Y8.73 W1.6 TB930 Gb/in²256MB235 MB/s Air300000550 TB/Y8760hrs/Y1.6 TB930 Gb/in²256MB235 MB/s Air300000550 TB/Y8760hrs/Y8.73 W1.43 TB867 Gb/in²256MB235 MB/s Helium300000550 TB/Y8760hrs/Y7.2 W1.43 TB867 Gb/in²256MB235 MB/s Helium300000550 TB/Y8760hrs/Y7.2 W1.75 TB1058 Gb/in²256MB250 MB/s Helium300000550 TB/Y8760hrs/Y6.9 W1.75 TB1058 Gb/in²256MB250 MB/s Helium300000550 TB/Y8760hrs/Y6.9 W1.78 TB1028 Gb/in²256MB250 MB/s Helium300000550 TB/Y8760hrs/Y6.71 W1.75 TB1058 Gb/in²256MB250 MB/s Helium300000550 TB/Y8760hrs/Y6.9 W1.78 TB1028 Gb/in²256MB250 MB/s Helium300000550 TB/Y8760hrs/Y6.71 W1.78 TB1028 Gb/in²256MB250 MB/s Helium300000550 TB/Y8760hrs/Y6.71 W2 TB1203 Gb/in²256MB190 MB/s Air300000180 TB/Y8760hrs/Y5.3 W1 TB651 Gb/in²128MB185 MB/s Air600000550 TB/Y8760hrs/Y7.0 W1 TB651 Gb/in²128MB185 MB/s Air600000550 TB/Y8760hrs/Y7.0 W1.33 TB732 Gb/in²256MB225 MB/s Air600000550 TB/Y8760hrs/Y9.91 W1.33 TB732 Gb/in²256MB225 MB/s Air600000550 TB/Y8760hrs/Y9.91 W1.33 TB732 Gb/in²256MB225 MB/s Air600000550 TB/Y8760hrs/Y10.77 W1.33 TB732 Gb/in²256MB225 MB/s Air600000550 TB/Y8760hrs/Y10.77 W1.33 TB732 Gb/in²256MB225 MB/s Air600000550 TB/Y8760hrs/Y12.91 W1.6 TB930 Gb/in²256MB226 MB/s Air600000550 TB/Y8760hrs/Y9.83 W1.6 TB930 Gb/in²256MB226 MB/s Air600000550 TB/Y8760hrs/Y10.89 W1.6 TB930 Gb/in²256MB226 MB/s Air600000550 TB/Y8760hrs/Y11.67 W1.6 TB930 Gb/in²256MB249 MB/s Air600000550 TB/Y8760hrs/Y12.81 W1.6 TB930 Gb/in²256MB226 MB/s Air600000550 TB/Y8760hrs/Y9.83 W1.6 TB930 Gb/in²256MB226 MB/s Air600000550 TB/Y8760hrs/Y10.89 W1.6 TB930 Gb/in²256MB226 MB/s Air600000550 TB/Y8760hrs/Y11.67 W1.6 TB930 Gb/in²256MB249 MB/s Air600000550 TB/Y8760hrs/Y12.81 W1.43 TB867 Gb/in²256MB249 MB/s Helium600000550 TB/Y8760hrs/Y8.4 W1.43 TB867 Gb/in²256MB249 MB/s Helium600000550 TB/Y8760hrs/Y8.4 W1.43 TB867 Gb/in²256MB249 MB/s Helium600000550 TB/Y8760hrs/Y8.4 W1.43 TB867 Gb/in²256MB249 MB/s Helium600000550 TB/Y8760hrs/Y8.4 W1.43 TB867 Gb/in²256MB249 MB/s Helium600000550 TB/Y8760hrs/Y8.4 W1.43 TB867 Gb/in²256MB249 MB/s Helium600000550 TB/Y8760hrs/Y8.4 W1.43 TB867 Gb/in²256MB249 MB/s Helium600000550 TB/Y8760hrs/Y8.4 W1.43 TB867 Gb/in²256MB249 MB/s Helium600000550 TB/Y8760hrs/Y8.4 W1.5 TB923 Gb/in²256MB261 MB/s Helium600000550 TB/Y8760hrs/Y7.8 W1.75 TB1058 Gb/in²256MB245 MB/s Helium600000550 TB/Y8760hrs/Y9.8 W1.75 TB1058 Gb/in²256MB245 MB/s Helium600000550 TB/Y8760hrs/Y10 W1.75 TB1058 Gb/in²256MB261 MB/s Helium600000550 TB/Y8760hrs/Y10 W1.78 TB1028 Gb/in²256MB245 MB/s Helium600000550 TB/Y8760hrs/Y9.5 W1.78 TB1028 Gb/in²256MB245 MB/s Helium600000550 TB/Y8760hrs/Y9.5 W1.78 TB1028 Gb/in²256MB245 MB/s Helium600000550 TB/Y8760hrs/Y10 W1.78 TB1028 Gb/in²256MB261 MB/s Helium600000550 TB/Y8760hrs/Y10 W1.78 TB1028 Gb/in²256MB245 MB/s Helium600000550 TB/Y8760hrs/Y9.5 W1.78 TB1028 Gb/in²256MB245 MB/s Helium600000550 TB/Y8760hrs/Y9.5 W1.78 TB1028 Gb/in²256MB245 MB/s Helium600000550 TB/Y8760hrs/Y10 W1.78 TB1028 Gb/in²256MB261 MB/s Helium600000550 TB/Y8760hrs/Y10 W500 GB32 MB150 MB/s Air300000 3.3 W 500 GB64 MB150 MB/s Air300000 3.3 W 1 TB64 MB150 MB/s Air300000 6.8 W 1 TB64 MB150 MB/s Air300000 3.3 W1 TB64 MB147 MB/s Air300000 4.1 W2 TB256180 MB/s Air300000 4.1 W 1 TB64 MB147 MB/s Air300000 4.1 W 1.33 TB64 MB175 MB/s Air300000 4.5 W1.2 TB64 MB170 MB/s Air300000 5.3 W2 TB256180 MB/s Air300000 4.8 W 1 TB64 MB150 MB/s Air300000 6.8 W 1 TB64 MB150 MB/s Air300000 6.8 W 667 GB64 MB164 MB/s Air3000009.5 W 800 GB128128 MB/s Air3000009.1 W 800 GB256256 MB/s Air3000009.1 W 1.2 TB128227 MB/s Air3000009.1 W 1.2 TB256227 MB/s Air3000009.1 W 1 TB64 MB144 MB/s Air600000180 TB/Y 3.3 W1 TB64 MB147 MB/s Air600000180 TB/Y 4.1 W2 TB256180 MB/s Air600000180 TB/Y 4.1 W1 TB64 MB147 MB/s Air600000180 TB/Y 4.1 W2 TB256180 MB/s Air600000180 TB/Y 4.8 W1 TB64 MB150 MB/s Air600000180 TB/Y 4.5 W2 TB256180 MB/s Air600000180 TB/Y 4.8 W1.2 TB64 MB175 MB/s Air600000180 TB/Y 5.3 W2 TB256180 MB/s Air600000180 TB/Y 4.8 W 1.6 TB256198 MB/s Air600000180 TB/Y8.8 W 1.43 TB256210 MB/s Helium600000180 TB/Y 5.7 W 1.67 TB256215 MB/s Air600000180 TB/Y8.4 W 1.5 TB256196 MB/s Helium600000180 TB/Y 6.3 W1.56 TB512210 MB/s Helium600000180 TB/Y 6.5 W 1 TB64 MB164 MB/s Air600000300 TB/Y7.8 W 1.33 TB256217 MB/s Air600000300 TB/Y7.2 W 1.5 TB256238 MB/s Air600000300 TB/Y7.2 W 1.6 TB256235 MB/s Air600000300 TB/Y8.8 W 1.43 TB256240 MB/s Helium600000300 TB/Y 5.7 W 1.67 TB256265 MB/s Air600000300 TB/Y8.4 W 1.5 TB256240 MB/s Helium600000300 TB/Y 6.0 W 1.56 TB512255 MB/s Helium600000300 TB/Y 6.2 W 1 TB64 MB110 MB/s Air300000180 TB/Y 3.3 W 1 TB64 MB145 MB/s Air300000180 TB/Y 4.4 W 1 TB64 MB145 MB/s Air300000180 TB/Y 4.4 W 1 TB64 MB150 MB/s Air300000180 TB/Y 5.1 W 1.2 TB64 MB175 MB/s Air300000180 TB/Y 5.3 W 1.6 TB256245 MB/s Air300000360 TB/Y8.6 W 1.43 TB256245 MB/s Helium300000360 TB/Y 6.3 W 1.67 TB256265 MB/s Air300000360 TB/Y9.0 W 1.5 TB256245 MB/s Helium300000360 TB/Y 6.6 W 1.56 TB512255 MB/s Helium300000360 TB/Y 6.0 W 1 TB128184 MB/s Air6000008.1 W 1 TB128200 MB/s Air6000008.1 W 1.33 TB256255 MB/s Air6000007.0 W 1.5 TB256255 MB/s Air6000007.0 W 1.6 TB256255 MB/s Air6000008.8 W 1.67 TB256262 MB/s Air6000009.2 W 1.5 TB256255 MB/s Helium600000 6.9 W 1.56 TB512267 MB/s Helium600000 6.0 W 1 TB128184 MB/s Air6000008.1 W 1 TB128200 MB/s Air6000008.1 W 1.33 TB256255 MB/s Air6000007.0 W 1.33 TB256255 MB/s Air6000007.0 W 1.5 TB256255 MB/s Air6000007.0 W 1.5 TB256255 MB/s Air6000007.0 W 1.6 TB256255 MB/s Air6000008.8 W 1.67 TB256262 MB/s Air6000009.2 W 1.13 TB256249 MB/s Helium600000 6.8 W 1.13 TB256249 MB/s Helium600000 6.8 W 1.43 TB256249 MB/s Helium600000 6.8 W 1.43 TB256249 MB/s Helium600000 6.8 W 1.5 TB256255 MB/s Helium600000 6.9 W 1.5 TB256255 MB/s Helium600000 6.9 W 1.56 TB512267 MB/s Helium600000 6.0 W 1.75 TB512255 MB/s Helium600000 6.4 W 1.75 TB512255 MB/s Helium600000 6.4 W 1.86 TB512255 MB/s Helium600000 6.4 W 1.86 TB512255 MB/s Helium600000 6.4 W 1 TB64 MB Air300000 6.4 W 1 TB64 MB Air300000 6.4 W 1 TB64 MB Air300000 5.8 W 1 TB64 MB Air300000 6.4 W2 TB 128MB185 MB/s Air60000055 TB/Y2400hrs/Y4.11 W2 TB 128MB185 MB/s Air60000055 TB/Y2400hrs/Y4.46 W。
发那科数控系统的编程与操作
第一节指令详解一、FANUC系统准备功能表表4-1 FANUC 0iMATE-TB数控系统常用G代码（A类）一览表..数控车床编程与操作- 102 - 102二、FANUC 0i MATE-TB编程规则1．小数点编程：在本系统中输入的任何坐标字（包括X、Z、I、K、U、W、R等）在其数值后须加小数点。
即X100须记作X100.0。
否则系统认为所坐标字数值为100×0.001mm＝0.1mm。
2．绝对方式与增量方式：FANUC-0T数控车系统中用U或W表示增量方式。
在程序段出现U即表示X方向的增量值，出现W即表示Z方向的增量值。
同时允许绝对方式与增量混合编程。
注意与使用G90和G91表示增量的系统有所区别。
3．进给功能：系统默认进给方式为转进给。
4．程序名的指定：本系统程序名采用字母O后跟四位数字的格式。
子程序文件名遵循同样的命名规则。
通常在程序开始指定文件名。
程序结束须加M30或M02指令。
5．G指令简写模式：系统支持G指令简写模式。
三、常用准备功能代码详解1．直线插补（G01）格式：G01 X（U）Z（W） F说明：基本用法与其它各系统相同。
此处主要介绍G01指令用于回转体类工件的台阶和端面交接处实现自动倒圆角或直角。
⑴圆角自动过渡：——格式：G01 X R FG01 Z R F——说明：X轴向Z轴过渡倒圆（凸弧）R值为负，Z轴向X轴过渡倒圆（凹弧）R值为正。
..数控车床编程与操作- 104 - 104——程序示例：O4001 N10 T0101N20 G0 X0 Z1. S500 M03 N30 G1Z0 F0.2 N40 G1 X20. R-5. N50 G1 Z-25. R3. N60 G1 X30.5 N70 G28 X120. Z100. N80 M30⑵ 直角自动过渡：——程式：G01 X C FG01 Z C F——说明：倒直角用指令C ，其符号设置规则同倒圆角。
——程序示例： O4002N10 T0101N20 G0 X0 Z1. S500 M03 N30 G1Z0 F0.2 N40 G1 X20. C-2. N50 G1 Z-25. R3. N60 G1 X30.5 N70 G28 X120. Z100. N80 M30提示：自动过渡倒直角和圆角指令在用于精加工编程时会带来方便，但要注意符号的正负要准确，否则会发生不正确的动作。
铁路信号电缆 一般规定
序号
项目
单位
指标
试验方法
换算公式
1
1.1
1.2
直流电阻20℃时
每根导体直流电阻不大于
工作线对导体电阻不平衡不大于
Ω
23.5
0.02
GB3048.4
L/1000
2
绝缘电阻不小于
MΩ
3000
GB3048.6
1000/L
3
3.1
3.2
3.3
电容
对线组工作电容不大于
星形四线组工作电容不大于
任一绝缘线芯对连接到地
PTY22 37×1.0 TB/T 2476.2
5技术要求与试验方法
5.1导体
导体应采用符合GB 3953规定的软圆铜线，其标称直径为1.0mm，试验方法应符合GB4909.2规定。
5.2绝缘
5.2.1绝缘应采用聚乙烯塑料，并制成红、绿、白、蓝四种颜色。
5.2.2绝缘标称厚度为0.6mm，允许偏差为±0.1mm，试验方法应符合GB2951.2规定。
四芯电缆ea1、ea2Байду номын сангаас标为最大值
PF
330
1300
GB5441.3
L/500
6
6.1
6.2
绝缘耐压50Hz 2min
线芯间
线芯对其余线芯接地
V
1000
1800
GB3048.8
注：工作线对导体电阻不平衡，即星形四线组工作线对的两根导体的电阻之差与其电阻之和的比值。
5.7电缆的机械物理特性除应符合本标准第5.5条的规定外，应进行低温卷绕或低温拉伸试验，试验温度为－15±2℃，其技术要求和试验方法应符合GB2951.12或GB2951.13的规定。
MX25L4005AM2C-12G中文资料
MX25L4005A4M-BIT [x 1] CMOS SERIAL FLASH FEATURESGENERAL• Serial Peripheral Interface (SPI) compatible -- Mode 0 and Mode 3• 4,194,304 x 1 bit structure• 128 Equal Sectors with 4K byte each- Any Sector can be erased individually•8 Equal Blocks with 64K byte each- Any Block can be erased individually• Single Power Supply Operation- 2.7 to 3.6 volt for read, erase, and program operations• Latch-up protected to 100mA from -1V to Vcc +1V• Low Vcc write inhibit is from 1.5V to 2.5VPERFORMANCE• High Performance- Fast access time: 85MHz serial clock (15pF + 1TTL Load) and 66MHz serial clock (30pF + 1TTL Load)- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)- Fast erase time: 60ms(typ.) and 120ms(max.)/sector (4K-byte per sector) ; 1s(typ.) and 2s(max.)/block (64K-byte per block)• Low Power Consumption- Low active read current: 12mA(max.) at 85MHz, 8mA(max.) at 66MHz and 4mA(max.) at 33MHz- Low active programming current: 15mA (max.)- Low active erase current: 15mA (max.)- Low standby current: 10uA (max.)- Deep power-down mode 1uA (typical)• Minimum 100,000 erase/program cycles• 10 years data retentionSOFTWARE FEATURES• Input Data Format- 1-byte Command code•Block Lock protection- The BP0~BP2 status bit defines the size of the area to be software protected against Program and Erase instructions • Auto Erase and Auto Program Algorithm- Automatically erases and verifies data at selected sector- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first)•Status Register Feature•Electronic Identification- JEDEC 2-byte Device ID- RES command, 1-byte Device IDHARDWARE FEATURES• SCLK Input- Serial clock input• SI Input- Serial Data Input• SO Output- Serial Data Output• WP# pin- Hardware write protectionGENERAL DESCRIPTIONThe MX25L4005A is a CMOS 4,194,304 bit serial Flash memory, which is configured as 524,288 x 8 internally. The MX25L4005A feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). SPI access to the device is enabled by CS# input.The MX25L4005A provide sequential read operation on whole chip.After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or byte /sector/block locations will be executed. Program command is executed on page (256 bytes) basis, and erase command is executes on chip or sector(4K-bytes) or block(64K-bytes).To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit.When the device is not in operation and CS# is high, it is put in standby mode and draws less than 10uA DC current.The MX25L4005A utilize MXIC's proprietary memory cell, which reliably stores memory contents even after 100,000program and erase cycles.PIN CONFIGURATIONSSYMBOL DESCRIPTION CS#Chip SelectSI Serial Data Input SO Serial Data Output SCLK Clock InputHOLD#Hold, to pause the device without deselecting the device WP#Write ProtectionVCC + 3.3V Power Supply GNDGroundPIN DESCRIPTION8-PIN SOP (150/200mil)*8-LAND SON (6x5mm), WSON (6x5mm), USON (4x4mm)CS#SO WP#GNDVCC HOLD#SCLK SIC S #S O W P #G ND V C C H O L D #S C L K S I8-PIN PDIP (300mil)• HOLD# pin-pause the chip without diselecting the chip • PACKAGE- 8-pin SOP (150mil)- 8-pin SOP (200mil)- 8-pin PDIP (300mil)- 8-land SON (6x5mm, 1.0mm package height), which is not recommended for new design - 8-land WSON (6x5mm, 0.8mm package height)- 8-land USON (4x4mm) in development - All Pb-free devices are RoHS CompliantCS#SO WP#GNDVCC HOLD#SCLK SINote: 8-land SON is not recommended for new designBLOCK DIAGRAMDATA PROTECTIONThe MX25L4005A are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.•Power-on reset and tPUW: to avoid sudden power switch by system power supply transition, the power-on reset and tPUW (internal timer) may protect the Flash.• Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary.• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. The WEL bit will return to reset stage under following situation:- Power-up- Write Disable (WRDI) command completion- Write Status Register (WRSR) command completion- Page Program (PP) command completion- Sector Erase (SE) command completion- Block Erase (BE) command completion- Chip Erase (CE) command completion•Software Protection Mode (SPM): by using BP0-BP2 bits to set the part of Flash protected from data change.•Hardware Protection Mode (HPM): by using WP# going low to protect the BP0-BP2 bits and SRWD bit from data change.•Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command (RES).Table 1. Protected Area SizesStatus bit Protect level4Mb BP2BP1BP00000 (none)None001 1 (1 block)Block 7010 2 (2 blocks)Block 6-7 011 3 (4 blocks)Block 4-7 100 4 (8 blocks)All101 5 (All)All110 6 (All)All1117 (All)AllHOLD FEATUREHOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation of write status register, programming, or erasing in progress.The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal is being low( if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low), see Figure 1. Figure 1. Hold Condition OperationThe Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low.Table 2. COMMAND DEFINITIONCOMMAND WREN WRDI RDID RDSR WRSR READ Fast Read (byte)(write(write(read ident-(read status(write status(read data)(fast read Enable)disable)ification)register)register)data)1st06 Hex04 Hex9F Hex05 Hex01 Hex03 Hex0B Hex2nd AD1AD13rd AD2AD24th AD3AD35th xAction sets the reset the output the to read out to write new n bytes(WEL)(WEL)manufacturer the status values to the read outwrite write ID and 2-byte register status register untilenable enable device ID CS# goeslatch bit latch bit highCOMMAND SE BE CE PP DP RDP RES REMS (Read (byte)(Sector(Block(Chip(Page(Deep(Release(Read Electronic Erase)Erase)Erase)Program)Power from Deep Electronic ManufacturerDown)Power-down)ID)& Device ID) 1st20 Hex52 or60 or 02 Hex B9 Hex AB Hex AB Hex90 HexD8 Hex C7 Hex2nd AD1AD1AD1x x3rd AD2AD2AD2x x4th AD3AD3AD3x ADD(1)5thAction Output themanufacturerID and deviceID(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.(2) It is not recommended to adopt any other code which is not in the above command definition table.Table 3. Memory OrganizationBlockSector 12707F000h 07FFFFh……..…….……..112070000h 070FFFh 11106F000h 06FFFFh……..…….……..96060000h 060FFFh 9505F000h 05FFFFh……..…….……..80050000h 050FFFh 7904F000h 04FFFFh……..…….……..64040000h 040FFFh 6303F000h 03FFFFh……..…….……..48030000h 030FFFh 4702F000h 02FFFFh……..…….……..32020000h 020FFFh 3101F000h 01FFFFh……..…….……..16010000h 010FFFh 1500F000h 00FFFFh……..…….……..3003000h 003FFFh 2002000h 002FFFh 001000h 001FFFh 000000h 000FFFh10Address Range7654321DEVICE OPERATION1.Before a command is issued, status register should be checked to ensure device is ready for the intended operation.2.When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.3.When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS# rising edge.4.Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The difference of SPI mode 0 and mode 3 is shown as Figure 2.Figure 2. SPI Modes Supported5.For the following instructions: RDID, RDSR, READ, FAST_READ, RES and REMS the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP and DP the CS# must go high exactly at the byte boundary;otherwise, the instruction will be rejected and not executed.6.During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase.Note:CPOL indicates clock polarity of SPI master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which SPI mode is supported.SCLKMSBCPHAshift inshift outSI 01CPOL0(SPI mode 0)(SPI mode 3)1SO SCLKMSBCOMMAND DESCRIPTION(1) Write Enable (WREN)The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE, BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit.The sequence of issuing WREN instruction is: CS# goes low-> sending WREN instruction code-> CS# goes high. (see Figure 11)(2) Write Disable (WRDI)The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.The sequence of issuing WRDI instruction is: CS# goes low-> sending WRDI instruction code-> CS# goes high. (see Figure 12)The WEL bit is reset by following situations:- Power-up- Write Disable (WRDI) instruction completion- Write Status Register (WRSR) instruction completion- Page Program (PP) instruction completion- Sector Erase (SE) instruction completion- Block Erase (BE) instruction completion- Chip Erase (CE) instruction completion(3) Read Identification (RDID)The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID of second-byte ID is as followings: 13(hex) for MX25L4005A.The sequence of issuing RDID instruction is: CS# goes low-> sending RDID instruction code -> 24-bits ID data out on SO -> to end RDID operation can use CS# to high at any time during data out. (see Figure. 13)While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.(4) Read Status Register (RDSR)The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress.The sequence of issuing RDSR instruction is: CS# goes low-> sending RDSR instruction code-> Status Register data out on SO (see Figure. 14)The definition of the status register bits is as below:WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle.WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction.BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area(as defined in table 1) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed)SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP# pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP2, BP1, BP0) are read only.bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0SRWD BP2BP1BP0WEL WIPStatus00the level of the level of the level of(write enable(write in progress Register Write protected protected protected latch)bit) Protect block block block1= status(note 1)(note 1)(note 1)1=write enable1=write operation register write0=not write0=not in write disable enable operationNote:1. See the table "Protected Area Sizes".2. The endurance cycles of protect bits are 100,000 cycles; however, the tW time out spec of protect bits is relaxedas tW = N x 15ms (N is a multiple of 10,000 cycles, ex. N = 2 for 20,000 cycles) after 10,000 cycles on those bits.(5) Write Status Register (WRSR)The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP2, BP1, BP0) bits to define the protected area of memory (as shown in table 1). The WRSR also can set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#) pin signal. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered.The sequence of issuing WRSR instruction is: CS# goes low-> sending WRSR instruction code-> Status Register data on SI-> CS# goes high. (see Figure 15)The WRSR instruction has no effect on b6, b5, b1, b0 of the status register.The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing,and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset.Table 4. Protection ModesNote:1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).Software Protected Mode (SPM):-When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and can change the valuesof SRWD, BP2, BP1, BP0. The protected area, which is defined by BP2, BP1, BP0, is at software protected mode (SPM).-When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP2,BP1, BP0. The protected area, which is defined by BP2, BP1, BP0, is at software protected mode (SPM).Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status Register and not be executed.ModeStatus register condition Software protection mode(SPM)Status register can be written in (WEL bit is set to "1") and the SRWD, BP0-BP2bits can be changedWP# and SRWD bit status MemoryWP#=1 and SRWD bit=0, or WP#=0 and SRWD bit=0, or WP#=1 and SRWD=1The protected area cannot be program or erase.The protected area cannot be program or erase.WP#=0, SRWD bit=1The SRWD, BP0-BP2 ofstatus register bits cannot be changedHardware protection mode (HPM)Hardware Protected Mode (HPM):-When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP2, BP1, BP0 and hardware protected mode by the WP# to against data modification.Note: to exit the hardware protected mode requires WP# driving high once the hardware protected mode is entered. If the WP# pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP2, BP1, BP0.(6) Read Data Bytes (READ)The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached.The sequence of issuing READ instruction is: CS# goes low-> sending READ instruction code-> 3-byte address on SI -> data out on SO-> to end READ operation can use CS# to high at any time during data out. (see Figure. 16)(7) Read Data Bytes at Higher Speed (FAST_READ)The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached.The sequence of issuing FAST_READ instruction is: CS# goes low-> sending FAST_READ instruction code-> 3-byte address on SI-> 1-dummy byte address on SI->data out on SO-> to end FAST_READ operation can use CS# to high at any time during data out. (see Figure. 17)While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.(8) Sector Erase (SE)The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see table 3) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.Address bits [Am-A12] (Am is the most significant address) select the sector address.The sequence of issuing SE instruction is: CS# goes low -> sending SE instruction code-> 3-byte address on SI -> CS# goes high. (see Figure 19)The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.(9) Block Erase (BE)The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (see table 3) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.The sequence of issuing BE instruction is: CS# goes low -> sending BE instruction code-> 3-byte address on SI -> CS# goes high. (see Figure 20)The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page.(10) Chip Erase (CE)The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the sector (see table 3) is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.The sequence of issuing CE instruction is: CS# goes low-> sending CE instruction code-> CS# goes high. (see Figure 20)The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP2, BP1, BP0 all set to "0".(11) Page Program (PP)The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7-A0 (The eight least significant address bits) should be set to 0. If the eight least significant address bits (A7-A0) are not all 0, all transmitted data going beyond the end of the current page are programmed from the start address of the same page (from the address A7-A0 are all 0). If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at the requested address of the page without effect on other address of the same page.The sequence of issuing PP instruction is: CS# goes low-> sending PP instruction code-> 3-byte address on SI-> at least 1-byte on data on SI-> CS# goes high. (see Figure 18)The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed.The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed.(12) Deep Power-down (DP)The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/ Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep power-down mode. It's different from Standby mode.The sequence of issuing DP instruction is: CS# goes low-> sending DP instruction code-> CS# goes high. (see Figure 22) Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction. (RES instruction to allow the ID been read out). When Power-down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.(13) Release from Deep Power-down (RDP), Read Electronic Signature (RES)The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max), as specified in Table 6. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new deisng, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress.The sequence is shown as Figure 23,24.The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction.The RDP instruction is for releasing from Deep Power Down Mode.。
TBBP530产品概述_20080714
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第 2 章 DBBP530 产品概述 ......................................................................................................8 2.1 电气及机械规格 ............................................................................................................ 8 2.2 环境适应性 ................................................................................................................... 8 2.3 安全 ............................................................................................................................. 8 2.4 电磁兼容性 ................................................................................................................... 9 2.5 硬件结构 ...................................................................................................................... 9 2.5.1 硬件组成 ............................................................................................................ 9 2.5.2 硬件逻辑框图 .................................................................................................... 11 2.6 软件结构 .................................................................................................................... 11 2.7 各模块功能概述 .......................................................................................................... 12 2.7.1 主控板 .............................................................................................................. 12 2.7.2 基带处理板（BBP）和基带处理及接口板（BBI）................................................ 13 2.7.3 扩展传输板（UTRP） ....................................................................................... 13 2.7.4 电源环境接口单元（UPEU）和环境接口单元（UE IU） ....................................... 13 2.7.5 风扇模块（FA N） ............................................................................................. 14 2.7.6 防雷板（UE LP、UFLP）................................................................................... 14 2.7.7 星卡时钟单元板（USCU） ................................................................................ 14
热处理调控氧化石墨烯薄膜层间距与离子筛分
第61卷 第1期厦门大学学报(自然科学版)V o l .61 N o .1 2022年1月J o u r n a l o f X i a m e nU n i v e r s i t y (N a t u r a l S c i e n c e )J a n .2022h t t p :ʊjx m u .x m u .e d u .c n d o i :10.6043/j.i s s n .0438-0479.202103015热处理调控氧化石墨烯薄膜层间距与离子筛分林玲鑫,刘 畅,马鹏飞,曹留烜*(厦门大学能源学院,福建厦门361102)摘要:采用热处理方法,通过改变热处理时间和温度来调控氧化石墨烯(G O )薄膜的层间距,并考察了C s +㊁K +㊁N a+㊁L i +㊁S r 2+㊁M g 2+和Al 3+离子在不同层间距的G O 薄膜中的渗透性.结果发现:热处理后得到的G O 薄膜在湿润状态下的层间距范围为0.57~1.31n m ,当薄膜层间距在0.55n m 左右时,水分子很难在薄膜中输运;此外,在不同层间距的G O 薄膜中离子渗透性除了与离子水合直径有关之外,还与离子所带电荷以及离子脱水作用有关.该方法实现了L i +/M g 2+和N a +/S r 2+的分离,为离子的精确筛分㊁促进如盐湖提锂以及核废液处理等提供了参考.关键词:氧化石墨烯薄膜;层间距;热处理;离子渗透中图分类号:T B 332 文献标志码:A 文章编号:0438-0479(2022)01-0042-07收稿日期:2021-03-15 录用日期:2021-05-27*通信作者:c a o l i u x u a n @x m u .e d u .c n引文格式:林玲鑫,刘畅,马鹏飞,等.热处理调控氧化石墨烯薄膜层间距与离子筛分[J ].厦门大学学报(自然科学版),2022,61(1):42-48. C i t a t i o n :L I NLX ,L I UC ,M APF ,e t a l .H e a t t r e a t m e n t r e g u l a t e s t h e i n t e r l a y e r s p a c i n g o f t h e g r a ph e n e o x i d em e m b r a n e a n d i o n s i e v i n g[J ].JX i a m e nU n i vN a t S c i ,2022,61(1):42-48.(i nC h i n e s e ) 氧化石墨烯(G O )在海水淡化[1-3]㊁气体和离子筛分[4-8]㊁生物传感器[9]和超级电容器[10]等领域显示出巨大的潜力.G O 表面具有丰富的羧基㊁羟基㊁羰基和环氧基等[11],这使其具有带负电的表面电荷和亲水性.G O 薄膜是由G O 片层堆叠而成,片层间形成的通道为分子和离子的输运提供了空间[12].G O 薄膜在实现水快速输运的同时还能根据自身的层间距实现分子筛分[5-6,13]和离子筛分[1,14-19],从而引起广泛关注.G O 薄膜独特的筛分性能由薄膜的层间距决定,具有良好亲水性的G O 薄膜在干燥状态下的层间距约0.8n m [19-20],当其浸没于液体时,薄膜的片层间能插入2~3层水分子,导致薄膜发生溶胀,层间距增大至1.4n m 左右[19,21-22],导致其分离性能和筛分效果严重衰减.研究者们通过改变G O 薄膜的外环境来缩小薄膜的层间距,从而提高膜的分离性能,包括利用高浓度的钾离子插层[23-24],利用环氧树脂机械性地控制薄膜在溶液中的肿胀性质[25],施加外部压力机械压缩[26],调节p H ㊁盐浓度和压力等方法[27].此外,还可通过调控G O 表面官能团的密度来控制层间距,如可以在G O 悬浊液制备过程中通过改变氧化剂的量来调控氧化程度[17],还能通过添加还原剂[28]㊁γ射线辐照法㊁紫外线(U V )辐照[29]和热处理方法[3,30-33]等进行调控.Y a n g 等[34]使用的还原剂还原法,虽然能够调控层间距,但是G O 薄膜在H I 蒸汽中仅暴露5m i n,层间距立即从湿润状态下的1.15n m 降低至0.37n m ,很难实现对薄膜层间距的精细调控.Z h a n g 等[35-36]使用的γ射线辐照方法对G O 薄膜的还原程度也很高,但很难实现对薄膜层间距的精细调控.而热处理方法具有操作简单,可连续且精确调控G O 薄膜层间距等突出优点.如:K i m 等[32]采用不同的热处理条件将G O 层间距精确控制在0.37~0.8n m 范围内,用于实现K +㊁A l 3+㊁S O 42-和F e (C N )63-的筛分;H u 等[31]通过改变热处理温度和时间来调控G O 薄膜层间距,大大提高了M g 2+/C a 2+㊁M g 2+/S r 2+㊁K +/C a 2+和K +/F e3+的分离系数.N a +㊁C s +和S r2+是核燃料后处理产生的高放废液的重要组成部分.目前对高放废液最成熟的处理技术是固化后地质处置,而从高放废液中分离出C s+和S r 2+可以大大提高地质处置库的利用率以及安全性[37-38].锂作为 推动世界进步的能源金属 在新能源㊁航天航空等重要领域有着广泛的应用.约有80%的锂资源蕴含在盐湖卤水之中,实现L i +/M g 2+分离引起了众多研究者的关注.本研究通过热处理方法来调控G O 薄膜的层间距,系统地分析了在不同热处理温度和时间条件下得到的G O 薄膜在湿润状态下层间距的变化,并探究不Copyright©博看网 . All Rights Reserved.第1期林玲鑫等:热处理调控氧化石墨烯薄膜层间距与离子筛分h t t p :ʊjx m u .x m u .e d u .c n 同离子(C s +㊁K +㊁N a +㊁L i +㊁S r 2+㊁M g 2+和Al 3+)在不同层间距的G O 薄膜中的渗透性变化及渗透机理,实现了L i +/M g 2+以及Na +/S r 2+的分离.1 实验部分1.1 试剂与材料石墨粉(纯度为98.5%),购于北京百灵威科技有限公司;N a N O 3(纯度为99.0%),购于国药集团化学试剂有限公司;去离子水,电阻率>18.2M Ω㊃c m ,取于D i r e c t -Q 3型纯水机;多孔纤维素膜(孔径为0.2μm ),购于上海羽令过滤器材有限公司.浓H 2S O 4(纯度为98.5%),K M n O 4(纯度为99.0%),H 2O 2(纯度为30.0%),C s C l ㊁N a C l ㊁K C l ㊁L i C l ㊁M g C l 2㊁S r C l 2和A l C l 3均为分析纯,购于厦门绿茵试剂玻仪有限公司.1.2 仪器设备D H J F -4005低温恒温搅拌反应浴(郑州长城科工贸有限公司),D i r e c t -Q 3纯水机(精艺兴业科技有限公司),T G 16-W S 高速离心机(湖南湘仪实验室仪器开发有限公司),T F H -1200-80-440新版实验级助力管式炉(科幂仪器);定制的有刻度的渗透装置250m L(如图1所示),K e i t h l e y 6487电流计,M S -01H 和M S 2-P 1H 磁力搅拌器;R i ga k uU l t i m aⅣ多晶X 射线衍射(X R D )仪,J C 200J C 1接触角测量仪,S U P R A55S A P P H I R E 场发射扫描电子显微镜(S E M )/能谱(E D S )仪,I D S p e cA R C T I C 拉曼光谱仪,P r o d i g y 7电感耦合等离子体发射光谱仪(I C P -O E S ),N e x l O N350X 电感耦合等离子体发射质谱仪(I C P -M S ).图1 渗透装置示意图F i g .1S c h e m a t i c d i a gr a mo f i n f i l t r a t i o n d e v i c e 1.3 G O 薄膜的制备采用改良H u m m e r s 法[39]实现石墨粉的氧化和剥离,制备G O 悬浊液(实验中的反应时间是通过多次预实验得到的)步骤如下.1)设置低温恒温搅拌反应浴程序:-10ħ,13h;0ħ,1h ;35ħ,12h ;0ħ,3h .2)预氧化:称取4g 石墨粉和4g N a N O 3,量取192m L 浓H 2S O 4,一起加入到三口烧瓶中,在-10ħ下放置12h .3)氧化:保持-10ħ的温度不变,缓慢加入48g K M n O 4(添加时间约为50m i n ),此时,石墨开始发生氧化,样品由黑色变成黄褐色;将温度提升到0ħ,以约400r /m i n 的速度磁力搅拌1h;再将温度提升到至35ħ,维持搅拌速度不变继续反应12h,保证反应充分.4)去除多余的M n O 4-:维持搅拌速度不变,将温度降低至0ħ,量取160m L 去离子水缓慢加入到三口烧瓶中(滴加时间约为20m i n );量取400m L 去离子水和50m LH 2O 2,将两者充分混合后缓慢滴入三口烧瓶中(滴加时间约为50m i n );当观察到样品呈现亮黄色时,再维持搅拌0.5~1.0h 后即完成反应.5)洗酸㊁除去样品中的杂质离子:将得到的样品倒出静置12h 后,取下层沉淀物;往下层沉淀物中加入适量的去离子水后(按每500m L 沉淀物加70m L去离子水的比例)超声处理1h ,再进行多次离心(11000r /m i n ,35m i n /次,离心12~13次),直至离心后样品上清液的p H 值接近7;离心后得到的下层沉淀物即G O 悬浊液,对其进行低温㊁遮光保存.6)G O 悬浊液浓度的标定:称取一定量的G O 悬浊液,将其放置于烘箱或冷冻干燥机中进行干燥;称量干燥后的质量,对比干燥前后的质量进行计算,即可得到G O 悬浊液的浓度.将制备好的G O 悬浊液通过真空过滤法制备成G O 薄膜:清洗干净流动相过滤器上的珐琅滤芯和上层配套玻璃装置,并加入适量的去离子水使珐琅滤芯保持适度湿润;将多孔纤维素底膜平铺到珐琅滤芯上,盖好上层配套玻璃装置,用夹子夹稳,加入一定量已知浓度的G O 悬浊液,连接并启动循环水式多用真空泵,开始真空抽滤;观察到薄膜成型,薄膜表面没有水光,则G O 薄膜过滤完成;将薄膜取出,在55ħ的恒温鼓风干燥箱下干燥0.5~1.0h,即获得实验可用的片层排列致密的G O 薄膜.G O 薄膜的厚度取决于过滤的G O 悬浊液的浓度和体积.因此,为了制备厚度相同的G O 薄膜,必须保持每次所使用的G O 悬浊液的浓度和体积一致.1.4 热处理调控层间距通过热处理来调控G O 薄膜的层间距.为了减小薄膜的厚度误差,热处理使用的G O 薄膜均从同一片面积较大的G O 薄膜上裁剪得到.热处理方法如下:将制备好的G O 薄膜放入60ħ的恒温鼓风干燥箱中干燥㊃34㊃Copyright©博看网 . All Rights Reserved.厦门大学学报(自然科学版)2022年h t t p :ʊjx m u .x m u .e d u .c n 24h ;设置管式炉的加热程序后(升温速率为5ħ/m i n,热处理温度为140~170ħ,热处理时间为0.5~2.0h,气氛为N 2,降温方式为自然降温)将G O 薄膜放入管式炉中;当加热程序完成,管式炉温度降为常温后,取出热还原氧化石墨烯薄膜(T r G O )备用.将在不同温度下热处理2.0h 得到的薄膜分别记为T r G O -140ħ㊁T r G O -150ħ㊁T r G O -160ħ和T r G O -170ħ.除非另有说明,否则实验中使用的热处理时间均为2.0h .1.5 离子渗透性实验配制浓度分别为0.01和1m o l /L 的C s C l ㊁N a C l㊁K C l ㊁L i C l ㊁S r C l 2㊁M g C l 2和A l C l 3的混合溶液.将T r G O 薄膜在渗透装置中夹紧,在渗透装置的一侧溶液池中加入一定体积的配制好的1m o l /L 电解质溶液,另一侧加入相同体积的0.01m o l /L 同种电解质溶液,则离子会从高浓度往低浓度迁移.为了加快扩散速度,使用电极将装置与电流计连接成闭合回路,沿着高浓度往低浓度的方向施加电压.为了防止溶液池中不同位置的溶液浓度在扩散时分布不均匀,以及防止薄膜表面出现严重的离子浓度极化,在溶液池中加入磁转子,并在整个扩散过程中维持溶液的搅拌.2 结果与讨论2.1 T r G O 薄膜的表征热处理能够还原G O 片层上的含氧官能团,利用E D S 分析G O 和T r G O 薄膜中碳和氧元素的质量分数,如表1所示.可以看出:G O 薄膜中碳和氧的质量分数分别为64.8%和35.2%,表明经过多次高速离心可以很好地将G O 悬浊液中的杂质离子洗去,并且高含氧量表明制备的G O 具有丰富的含氧官能团;经热处理后,薄膜发生还原,随着热处理温度的提高,薄膜的含碳量逐渐升高而含氧量不断降低.表1 G O 和T r G O 薄膜中碳和氧元素的质量分数T a b .1 C a r b o n a n d o x y g e n e l e m e n t c o m po s i t i o n o f G Oa n dT r G Om e m b r a n e s样品ω(C )/%ω(O )/%G O64.835.2T r G O -140ħ68.431.6T r G O -150ħ70.629.4T r G O -160ħ73.726.3T r G O -170ħ77.722.3G O 薄膜中的含氧官能团会影响其亲水性.使用接触角测量仪对薄膜的水接触角进行表征,如图2所示.由于G O 薄膜表面含有丰富的含氧官能团,所以其水接触角较小,为33.22ʎ,具有良好的亲水性.随着热处理温度的不断提高,薄膜的水接触角不断变大,亲水性不断降低,进一步证明薄膜表面的含氧官能团在逐渐减少,与E D S 分析的结论一致.图2 G O 和T r G O 薄膜的水接触角F i g .2W a t e r c o n t a c t a n gl e s o f G Oa n dT r G Om e m b r a n e s G O 薄膜的层间距是影响离子在薄膜中输运的关键因素之一.通过X R D 表征G O 薄膜在热处理前后层间距的变化.由于离子渗透实验是在溶液环境中进行的,所以需要表征薄膜在湿润状态下的层间距.如图3(a )所示:干燥状态下G O 薄膜的特征衍射峰位于10.28ʎ,经热处理后特征衍射峰往右移动.T r G O -140ħ㊁T r G O -150ħ㊁T r G O -160ħ和T r G O -170ħ薄膜的特征衍射峰分别位于11.20ʎ㊁11.96ʎ㊁13.02ʎ和16.00ʎ.根据布拉格公式2d s i n θ=n λ(其中d 为层间距,n =1,λ=0.154n m )可计算出干燥状态下G O ㊁T r G O -140ħ㊁T r G O -150ħ㊁T r G O -160ħ和T r G O -170ħ薄膜的层间距分别为0.86,0.79,0.74,0.68和0.55n m.可以看出,随着热处理温度的升高,薄膜的层间距不断减小,这为筛分小分子和小离子提供了可能.G O 片层表面拥有丰富的含氧官能团,能与水分子结合从而使薄膜层间距增大.因此,湿润状态下G O ㊁T r G O -140ħ㊁T r G O -150ħ和T r G O -160ħ层间距均有所增大,分别为1.64,1.31,1.19和0.91n m.而T r G O -170ħ薄膜在湿润状态下的特征衍射峰的位置变化不大,层间距从0.55n m 变化至0.57n m ,层间距基本不变.这证明当T r G O 薄膜层间距为0.55n m 时,水分子很难进入层间,此时液体和离子的渗透率很低.采用X R D 表征获得的G O 和T r G O 薄膜的层间距包括G O 片层的厚度[40].因此在湿润状态下,G O ㊁T r G O -140ħ㊁T r G O -150ħ㊁T r G O -160ħ和T r G O -170ħ薄膜中可用于离子输运的有效层间距分别为1.30,0.97,0.85,0.57和0.23n m.以热处理温度160ħ为例,考察热处理时间㊃44㊃Copyright©博看网 . All Rights Reserved.第1期林玲鑫等:热处理调控氧化石墨烯薄膜层间距与离子筛分h t t p :ʊjx m u .x m u .e d u .c n (0.5,1.0,1.5和2.0h )对G O 薄膜层间距的影响.将不同热处理时间得到的薄膜分别记为T r G O -160ħ-0.5h ㊁T r G O -160ħ-1.0h ㊁T r G O -160ħ-1.5h 和T r G O -160ħ-2.0h .如图3(b)所示,随着热处理时间的延长,薄膜层间距逐渐减小,上述薄膜在湿润状态下可用于离子输运的有效层间距分别为0.95,0.87,0.65和0.57n m.因此可以通过调控热处理时间和温度来得到多种尺寸的层间距.实线为干燥状态,虚线为湿润状态;图中括号内容为干燥状态下薄膜的层间距/湿润状态下薄膜的层间距.图3 G O 和热处理时间为2.0h 的T r G O 薄膜(a ),以及不同热处理时间下的T r G O -160ħ薄膜(b )的X R D 谱图F i g.3X R D p a t t e r n s o f G Oa n dT r G Om e m b r a n e sw i t h h e a t t r e a t m e n t t i m e o f 2.0h (a ),a n dT r G O -160ħm e m b r a n e sw i t h d i f f e r e n t h e a t t r e a t m e n t t i m e (b) 图4为G O 薄膜的拉曼谱图,可以看出G O 薄膜和T r G O 薄膜的拉曼光谱均在1351和1592c m -1附近出现D 峰和G 峰.D 峰和G 峰的强度比(I D /I G )是表征缺陷的重要参数.根据实验数据计算出G O ㊁T r G O -140ħ㊁T r G O -150ħ㊁T r G O -160ħ和T r G O -170ħ薄膜的I D /I G 值分别为0.73,0.78,0.83,0.89和0.96,表明G O 薄膜的缺陷和无序度随着热处理温度的升高而升高.图4 G O 和T r G O 薄膜的拉曼谱图F i g .4R a m a n s pe c t r a of G Oa n dT r G Om e m b r a n e s G O 和T r G O 薄膜的表面形貌相似,均呈现出褶皱状态(图5(a )),这是石墨烯基膜的特点[41].G O 薄膜截面如图5(b)所示,可以看出薄膜由片层堆叠而成,厚度为759.2n m ,且由真空过滤法制备的G O 薄膜厚度较为均匀.使用具有相同厚度的G O 薄膜在不同温度下进行热处理,可以看出随着热处理温度的升高,薄膜的厚度逐渐减小.如图5(c )~(f )所示,T r G O -140ħ㊁T r G O -150ħ㊁T r G O -160ħ和T r G O -170ħ薄膜的厚度分别为664.6,620.4,569.7和476.8n m.与G O 薄膜相比,T r G O 薄膜厚度减小的比例与层间距减小的比例一致,即薄膜厚度减小归因于薄膜层间距减小.2.2 离子渗透率实验选择T r G O -140ħ㊁T r G O -160ħ和T r G O -160ħ-1.5h 薄膜,研究C s +㊁K +㊁N a +㊁L i +㊁S r 2+㊁M g 2+和A l3+在不同层间距中的离子渗透性.如图6所示,这7种离子的水合直径均小于T r G O -140ħ薄膜的有效层间距(0.97n m ),因此离子都能发生渗透.离子水合直径越小,离子渗透率越大.与一价阳离子相比,多价阳离子的水合直径较大,相同时间内进入薄膜的离子数量相对较少,因此S r 2+和M g 2+的渗透性略低;而A l 3+的水合直径接近于T r G O -140ħ薄膜有效层间距的极限值,因此A l3+的渗透性明显小于其他离子.由于M g 2+和Al 3+的水合直径均大于T r G O -160ħ-1.5h ㊃54㊃Copyright©博看网 . All Rights Reserved.厦门大学学报(自然科学版)2022年h t t p :ʊjx m u .x m u .e d u .cn 图5 G O 和T r G O 薄膜的S E M 图F i g .5S E Mi m a ge s of G Oa n dT r G Om e m b r a n es 灰色区域的上限表示检测极限为100μg/L ,箭头在灰色区域表示离子发生截留.图6 离子的渗透性分析F i g .6I o n p e r m e a b i l i t y a n a l ys i s 薄膜的有效层间距(0.65n m ),所以不发生渗透,但仍能观察到有少量的S r 2+(水合直径为0.824n m )渗透.T r G O -160ħ薄膜的有效层间距虽仅有0.57n m ,但还能检测到一价阳离子的渗透.这是因为离子会发生脱水效应,在通过层间距比水合直径小的薄膜时,可以通过脱水使得水合直径减小,从而在薄膜中发生渗透.但离子脱水与离子的水合自由能有关,而水合自由能由离子带电荷数决定,带电荷数越多的离子水合自由能越高,脱水越困难.本研究中所用离子的水合自由能最大的是A l 3+,因此,在有效层间距接近或小于水合直径时,可以明显观察到A l 3+渗透性降低甚至发生截留,S r 2+和M g 2+同理.而一价阳离子的水合自由能较低,可以通过离子脱水进入到比水合直径小的层间距中,因此在T r G O -160ħ薄膜中还能观察到一价阳离子的渗透.此外,还比较了不同层间距对L i +/M g 2+和Na +/S r 2+的选择性,即两种离子的渗透率比值.在T r G O -140ħ薄膜中,N a +㊁L i +㊁M g 2+和S r 2+都能在发生渗透,因此L i +/M g 2+和Na +/S r 2+的选择性较小,接近1;但随着薄膜层间距的不断减小,L i +/M g 2+和Na +/S r 2+的选择性逐渐变大.在T r G O -160ħ-1.5h 薄膜中,N a +/S r 2+的选择性为175;而在L i +/M g 2+渗透中M g 2+被截留,只有L i +渗透.在T r G O -160ħ薄膜中,只有N a +和L i +的渗透,从而实现L i +/M g 2+以及N a +/S r2+的筛分.这为盐湖提锂㊁高放废液的处理提供了新方法.3 结 论通过改良H u m m e r s 法制备了G O 悬浊液,再经真空过滤法制备成G O 薄膜,通过改变热处理的时间和温度来调控薄膜的层间距,所制备的G O 薄膜在湿润条件下的层间距为1.64n m ,经热处理后薄膜在湿润状态下的层间距范围为0.57~1.31n m.干燥条件下当薄膜层间距接近0.55n m 时,水已经很难进入,因此其湿润状态下的层间距几乎不发生改变.离子的渗透性实验发现:离子在薄膜中的输运不仅依赖于薄膜的层间距和离子水合直径,还与离子所带电荷数和离子脱水作用有关.据此实现了L i +/M g 2+和Na +/㊃64㊃Copyright©博看网 . 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h u m m e r s m e t h o d [J ].S c i e n t i f i cR e po r t s ,2016,6:36143.[40] L E ESE ,J A N G J ,K I MJ ,e t a l .T u n a b l e s i e v i n g o f s m a l l g a sm o l e c u l e s u s i n g h o r i z o n t a l g r a ph e n e o x i d em e m b r a n e [J ].JM e m b S c i ,2020,610:118178.[41] S C H U S T E R W ,M I K L E RH ,K O M A R E KKL .T r a n s i t i o nm e t a l -c h a l c o g e n s ys t e m s ,Ⅶ:t h ei r o n -s e l e n i u m p h a s e d i a gr a m [J ].M o n a t s hC h e m C h e m M o n ,1979,110(5):1153-1170.H e a t t r e a t m e n t r e g u l a t e s t h e i n t e r l a y e r s p a c i n g of t h eg r a ph e n e o xi d em e m b r a n e a n d i o n s i e v i n gL I NL i n g x i n ,L I UC h a n g ,M AP e n gf e i ,C A OL i u x u a n *(C o l l eg e o f E n e r g y ,X i a m e nU n i v e r s i t y,X i a m e n 361102,C h i n a )A b s t r a c t :T h e h e a t t r e a t m e n t m e t h o dw a s u s e d t o c o n t r o l t h e i n t e r l a y e r s p a c i n g o f t h e G Om e m b r a n e b y c h a n g i n gt h e h e a t t r e a t m e n t t i m e a n d t e m p e r a t u r e ,a n d t h e p e r m e a b i l i t y o f C s +,K +,N a +,L i +,S r 2+,M g 2+a n dA l 3+i nG O m e m b r a n e sw i t hd i f f e r e n t i n t e r l a ye r s p a c i n g w a s i n v e s t i g a t e d .T h e i n t e r l a y e r s p a c i n g of t h eG Om e m b r a n e s o b t a i n e d a f t e r h e a t t r e a t m e n t i n t h ew e t s t a t ew a s 0.57-1.31n m .W h e n t h e i n t e r l a y e r s p a c i ng w a s a b o u t 0.55n m ,i t w a s d i f f i c u l t f o rw a t e rm o l e c u l e s t o t r a n s po r t i n t h em e m b r a n e .I t w a s f o u n d t h a t t h e i o n p e r m e a b i l i t y o f G Om e m b r a n e s w i t h d i f f e r e n t i n t e r l a y e r s p a c i n g w a s r e l a t e d n o t o n l y t o t h e h yd r a t i o n d i a me t e r of t h e i o n s ,b u t a l s o t o t h e c h a rg e a n d th e d e h y d r a ti o no f t h e i o n s .W e h a v e a c h i e v e d t h e s e p a r a t i o no f L i +/M g 2+a n dN a +/S r 2+,w h i c h p r o v i d e s a r e f e r e n c e f o r p r e c i s e s i e v i n g o f i o n s ,p r o m o t i o n o f l i t h i u me x t r a c t i o n f r o ms a l t l a k e s ,a n d n u c l e a rw a s t e l i qu i d t r e a t m e n t .K e yw o r d s :g r a p h e n e o x i d em e m b r a n e ;i n t e r l a y e r s p a c i n g ;h e a t t r e a t m e n t ;i o n p e r m e a b i l i t y (责任编辑:曾礼娜)㊃84㊃Copyright©博看网 . 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VHF-4005专业四路VHF无线麦克风系统用户手册说明书
VHF-4005 Professional Quad VHF Wireless Microphone System o w n e r’s m a n u a lWelcomeAnd thank you for purchasing the VHF-4005 from VocoPro, your ultimate choice in Karaoke entertainment! With years of experience in the music entertainment business, VocoPro is a leading manufacturer of Karaoke equipment, and has been providing patrons of bars, churches, schools, clubs and individual consumers the opportunity to sound like a star with full-scale club models, in-home systems and mobile units. All our products offer solid performance and sound reliability, and to reinforce our commitment to customer satisfaction, we have customer service and technical support professionals ready to assist you with your needs. We have provided some contact information for you below.VocoPro1728 Curtiss CourtLa Verne, CA 91750Toll Free: 800-678-5348TEL: 909-593-8893FAX: 909-593-8890VocoPro Company Email DirectoryCustomer Service & General Information****************Tech Support***********************Remember Our WebsiteBe sure to visit the VocoPro website for the latest information on new products, packages and promos. And while you're there don't forget to check out our Club VocoPro for Karaoke news and events, chat rooms, club directories and evena KJ Service directory!We look forward to hearing you sound like a PRO, with VocoPro, the singer’s ultimate choice.FOR YOUR RECORDSPlease record the model number and serial number below, for easy reference, in case of loss or theft. These numbers are located on the rear panel of the unit. Space is also provided for other relevant informationModel NumberSerial NumberDate of PurchasePlace of PurchaseCONNECTING POWERConnect the AC power adapter to the power input jack on the far right of the back panel on the VHF-4005 .CONNECTING AUDIO OUTPUTUSING THE XLR OUTPUTS:The XLR outputs allow you to connect each channel to the mixer independently . This gives you more control over the volume on individual microphone channels when connected to a mixer .You’ll need:• VHF-4005• (4) XLR patch cables (not included)• An input device, such as a mixer or amplifier (not included)TO CONNECT THE XLR OUTPUTS:1 . Ensure the main power switch is turned off .2 . Connect one end of an XLR cable to the CH .1output of the VHF-4000 .3 . Connect the other end of the XLR cable to thedesired input on your mixer .Note: To avoid confusion, it’s recommended that the XLR jacks are attached correspondingly (e.g. CH.1 to CH.1, CH.2 to CH. 2, etc. illustration is for clarity not accuracy).4 . Repeat steps 2 and 3 until all the XLR outputsare connected .USING THE 1/4” MIXED OUTPUT:The 1/4” mixed output is useful if you have limited inputs available on your mixer . All four microphone signals are mixed together in this single output .You’ll need:• VHF-4005• (1) 1/4” patch cables (included)• An input device, such as a mixer or amplifier (not included) .TO CONNECT THE 1/4” MIXED OUTPUT:1 . Ensure the main power switch is turned off .2 . Connect one end of a 1/4” cable to the 1/4”mixed output on the rear panel of the VHF-4005 .3 . Connect the other end of the 1/4” cable to thedesired input on your mixer or amplifier .Getting ConnectedVHF-4005 Rear PanelVHF-4005 Rear PanelMixerMixerVHF-4005 Rear Panel11VHF-4005 Owner’s Manual © VocoPro 2014v1.1119。
某地5层底框结构条形基础商住楼结构施工图
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40A Bridge Rectifiers
40A Bridge Rectifiers
Features
• Low reverse leakage current • Low power loss • High efficiency
• Electrically isolated epoxy case for maximum heat dissipation • Case to terminal isolated voltage 2500V • RoHS compliant
Mechanical Data
Case: Molded plastic with heat sink, available in both low profile and standard case Terminals: Plated faston lugs Polarity: As marked on case Mounting Torque: 20 in. – lbs. max. Weight:
21 grams
Maximum Ratings And Electrical Characteristics (T amb =25˚C)
Symbols
Parameter
TB 4005
TB 401
TB 402
TB 404
TB 406
TB 408
TB 410
Unit
Conditions
V RRM Maximum Repetitive Peak Reverse Voltage 50 100 200 400 600 800 1000 V V RMS Maximum RMS Voltage 35 70 140 280 420 560 700 V V DC Maximum DC Blocking Voltage 50
100
200
400
600
800
1000
V
I F(AV) Maximum Average Forward Rectified Current
40 A T A =60˚C
I FSM Peak Forward Surge Current 400 A
8.3ms single half
sine-wave
superimposed on rated load (JEDEC Method)
V F Maximum Instantaneous
Forward Voltage Drop per leg 1.1 V I F =20A 5.0 T C =25°C
I R Maximum DC Reverse Current at Rated DC Blocking Voltage per leg
500 µA
T C =125°C
I²t
Rating for Fusing (1ms<t<8.3ms)
664 A²S
TB35
TB4005 – TB410
Fig.1- Derating Curve Output Rectified Current
Ambient Temperature (°C)
Symbols Parameter
TB 4005TB 401 TB 402 TB 404 TB
406 TB 408 TB 410
Unit Conditions C J Typical Junction Capacitance 400 pF
V R =4V, f=1MHz
R θJC Typical Thermal Resistance per leg
2.1
˚C/W Note 1
V ISO RMS Isolation Voltage from Case to Leads
2500 V T J ,T STG
Operating and Storage Temperature Range
-65 to 150
˚C
Note:
1. Thermal resistance junction to case, mounted on heatsink.
2. Single Phase, half wave, 60 Hz, resistive or inductive load. For capacitive load, derate current by 20%.
Rating and characteristic curves
Fig.2-Max Non-Repetitive Peak Forward Surge Current
Number of Cycles at 60Hz
P e a k F o r w a r d S u r g e C u r r e n t (A )
A v e r a g e F o r w a r d C u r r e n t (A )
TB4005 – TB410
Fig.3- Typical Instantaneous Forward Characteristics,
per leg
Instantaneous Forward Voltage (V)
I n s t a n t a n e o u s F o r w a r d C u r r e n t (
A )
Fig.5-Typical Junction Capacitance per leg
Reverse Voltage (V)
J u n c t i o n C a p a c i t a n c e (
p F )
Fig.4-Typical Reverse Leakage Characteristics
per leg
Percent of Rated Peak Reverse Voltage (%)
I n s t a n t a n e o u s R e v e r s e C u r r e n t (µA )
TB4005 – TB410
Dimensions in mm
How to contact us。