WED3EG6418S-D4中文资料

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MEMORY存储芯片TMS32C6414TBGLZWA8中文规格书

TMS570LS3135,TMS570LS2135,TMS570LS2125SPNS164C–APRIL2012–REVISED APRIL20155.9Thermal Resistance CharacteristicsTable5-2shows the thermal resistance characteristics for the QFP-PGE mechanical package.Table5-3shows the thermal resistance characteristics for the BGA-ZWT mechanical package.Table5-2.Thermal Resistance Characteristics(PGE Package)°C/WJunction-to-free air thermal resistance,Still air using JEDEC2S2P testRΘJA39boardRΘJB Junction-to-board thermal resistance26.3RΘJC Junction-to-case thermal resistance 6.7ΨJT Junction-to-package top,Still air0.10Table5-3.Thermal Resistance Characteristics(ZWT Package)°C/WJunction-to-free air thermal resistance,Still air(includes5x5thermal viaRΘJA18.8cluster in2s2p PCB connected to1st ground plane)RΘJB Junction-to-board thermal resistance14.1RΘJC Junction-to-case thermal resistance7.1Junction-to-package top,Still air(includes5x5thermal via cluster in2s2pΨJT0.33PCB connected to1st ground plane)SpecificationsTMS570LS3135,TMS570LS2135,TMS570LS2125SPNS164C–APRIL2012–REVISED APRIL2015 5.10Output Buffer Drive StrengthsTable5-4.Output Buffer Drive StrengthsLOW-LEVEL OUTPUT CURRENT,I OL for V I=V OLmaxor SIGNALSHIGH-LEVEL OUTPUT CURRENT,I OH for V I=V OHminFRAYTX2,FRAYTX1,FRAYTXEN1,FRAYTXEN2,MIBSPI5CLK,MIBSPI5SOMI[0],MIBSPI5SOMI[1],MIBSPI5SOMI[2],MIBSPI5SOMI[3],MIBSPI5SIMO[0],MIBSPI5SIMO[1],MIBSPI5SIMO[2],MIBSPI5SIMO[3],8mA TMS,TDI,TDO,RTCK,SPI4CLK,SPI4SIMO,SPI4SOMI,nERROR,N2HET2[1],N2HET2[3],All EMIF Outputs and I/Os,All ETM OutputsMIBSPI3SOMI,MIBSPI3SIMO,MIBSPI3CLK,MIBSPI1SIMO,MIBSPI1SOMI,MIBSPI1CLK, 4mAnRSTAD1EVT,CAN1RX,CAN1TX,CAN2RX,CAN2TX,CAN3RX,CAN3TX,DMM_CLK,DMM_DATA[0],DMM_DATA[1],DMM_nENA,DMM_SYNC,GIOA[0-7],GIOB[0-7],LINRX,LINTX,2mA zero-dominantMIBSPI1NCS[0],MIBSPI1NCS[1-3],MIBSPI1NENA,MIBSPI3NCS[0-3],MIBSPI3NENA,MIBSPI5NCS[0-3],MIBSPI5NENA,N2HET1[0-31],N2HET2[0],N2HET2[2],N2HET2[4],N2HET2[5],N2HET2[6],N2HET2[7],N2HET2[8],N2HET2[9],N2HET2[10],N2HET2[11],N2HET2[12],N2HET2[13],N2HET2[14],N2HET2[15],N2HET2[16],N2HET2[18],SPI2NCS[0],SPI2NENA,SPI4NCS[0],SPI4NENAECLK,selectable8mA/2mA SPI2CLK,SPI2SIMO,SPI2SOMIThe default output buffer drive strength is8mA for these signals.Table5-5.Selectable8mA/2mA ControlSIGNAL CONTROL BIT ADDRESS8mA2mAECLK SYSPC10[0]0xFFFF FF7801SPI2CLK SPI2PC9[9](1)0xFFF7F66801SPI2SIMO SPI2PC9[10](1)0xFFF7F66801SPI2SOMI SPI2PC9[11](1)0xFFF7F66801(1)Either SPI2PC9[11]or SPI2PC9[24]can change the output strength of the SPI2SOMI pin.In case of a32-bit write where these two bitsdiffer,SPI2PC9[11]determines the drive strength.SpecificationsTMS570LS3135,TMS570LS2135,TMS570LS2125SPNS164C–APRIL2012–REVISED APRIL20155.11Input TimingsFigure5-2.TTL-Level InputsTable5-6.Timing Requirements for Inputs(1)MIN MAX UNIT t pw Input minimum pulse width t c(VCLK)+10(2)ns(1)t c(VCLK)=peripheral VBUS clock cycle time=1/f(VCLK)(2)The timing shown in Figure5-2is only valid for pins used in GPIO mode.5.12Output TimingsTable5-7.Switching Characteristics for Output Timings versus Load Capacitance(C L)PARAMETER MIN MAX UNITCL=15pF 2.5CL=50pF4Rise time,t r nsCL=100pF7.2CL=150pF12.5 8mA low EMI pins(see Table5-4)CL=15pF 2.5CL=50pF4Fall time,t f nsCL=100pF7.2CL=150pF12.5CL=15pF 5.6CL=50pF10.4Rise time,t r nsCL=100pF16.8CL=150pF23.2 4mA low EMI pins(see Table5-4)CL=15pF 5.6CL=50pF10.4Fall time,t f nsCL=100pF16.8CL=150pF23.2 2mA-z low EMI pins CL=15pF8(see Table5-4)CL=50pF15Rise time,t r nsCL=100pF23CL=150pF33CL=15pF8CL=50pF15Fall time,t f nsCL=100pF23CL=150pF33 Specifications。

12864中文资料

12864液晶名称含义12864是128*64点阵液晶模块的点阵数简称，业界约定俗成的简称。

基本参数液晶屏类型 STN FSTN模块显示效果：黄绿底黑字蓝底白字白底黑字视角6点钟12点钟驱动方式 1/64 DUTY 1/9 BIAS背光LED白色LED黄绿色控制器KS0108或兼容ST7920 T6963C数据总线 8 位并口/6800 方式串口温度特性工作温度：-20℃~+70℃ 储藏温度：-30℃~+80℃点阵格式 128 x 64基本用途：该点阵的屏显成本相对较低，适用于各类仪器，小型设备的显示领域。

基本用途：该点阵的屏显成本相对较低，适用于各类仪器，小型设备的显示领域。

液晶模组使用注意事项1 当您在你的产品设计中使用本液晶模组，注意液晶的视角与你的产品用途相一致。

2 液晶屏是玻璃为基础的，跌落或与硬物撞击会引起液晶屏破裂或粉碎。

尤其是边角处。

3 尽管在液晶表面的偏振片有抑制反光的表层，应当小心不要划伤表面，一般推荐在液晶表面采用透明塑胶材料的保护屏。

4 如果液晶模组储藏在低于规定的温度以下，液晶材料会凝结而性能恶化。

如果液晶模组储藏在高于规定的温度以上，液晶材料的分子排列方向会转变为液态，可能无法恢复到原来的状态。

超出温度和湿度范围，会引起偏振片剥落或起泡。

因此，液晶模组应储藏在规定的温度范围。

5 如液晶表面遇口水或滴水，应立即擦除，避免长时间过后引起色彩变化或留下污点。

水蒸气会引起ITO电极腐蚀。

6 如果需要清洁液晶屏表面，应该用棉或软布轻快地擦拭，仍不能清除时，呵气之后再擦拭。

7 液晶模组的驱动应遵照规定的额定指标，避免故障及永久损坏。

对液晶材料施加直流电压，会引起液晶材料迅速恶化，应该确保提供交流波形的M信号的连续应用。

特别是，在电源开关时应遵照供电顺序，避免驱动锁存及直流直接加至液晶屏。

8 机械注意事项：a) 液晶模组是在高精度下调试安装的。

避免外力撞击，不要对其改变或修改。

b) 不要篡改金属框的任何突出部分。

MEMORY存储芯片TMS320C6414TZLZ中文规格书

TMS320C6414, TMS320C6415, TMS320C6416FIXED-POINT DIGITAL SIGNAL PROCESSORSSPRS146N − FEBRUARY 2001 − REVISED MAY 2005 bootmodeThe C6414/15/16 device resets using the active-low signal RESET. While RESET is low, the device is held in reset and is initialized to the prescribed reset state. Refer to reset timing for reset timing characteristics and states of device pins during reset. The release of RESET starts the processor running with the prescribed device configuration and boot mode.The C6414/C6415/C6416 has three types of boot modes:D Host bootIf host boot is selected, upon release of RESET, the CPU is internally “stalled” while the remainder of the device is released. During this period, an external host can initialize the CPU’s memory space as necessary through the host interface, including internal configuration registers, such as those that control the EMIF or other peripherals. For the C6414 device, the HPI peripheral is used for host boot. For the C6415/C6416 device, the HPI peripheral is used for host boot if PCI_EN = 0, and the PCI peripheral is used for host boot if PCI_EN = 1. Once the host is finished with all necessary initialization, it must set the DSPINT bit in the HPIC register to complete the boot process. This transition causes the boot configuration logic to bring the CPU out of the “stalled” state. The CPU then begins execution from address 0. The DSPINT condition is not latched by the CPU, because it occurs while the CPU is still internally “stalled”. Also, DSPINT brings the CPU out of the “stalled” state only if the host boot process is selected. All memory may be written to and read by the host. This allows for the host to verify what it sends to the DSP if required. After the CPU is out of the “stalled” state, the CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received.D EMIF boot (using default ROM timings)Upon the release of RESET, the 1K-Byte ROM code located in the beginning of CE1 is copied to address 0 by the EDMA using the default ROM timings, while the CPU is internally “stalled”. The data should be stored in the endian format that the system is using. In this case, the EMIF automatically assembles consecutive 8-bit bytes to form the 32-bit instruction words to be copied. The transfer is automatically done by the EDMA as a single-frame block transfer from the ROM to address 0. After completion of the block transfer, the CPU is released from the “stalled” state and starts running from address 0.D No bootWith no boot, the CPU begins direct execution from the memory located at address 0. Note: operation is undefined if invalid code is located at address 0.resetA hardware reset (RESET) is required to place the DSP into a known good state out of power-up. The RESETsignal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core and I/O voltages have reached their proper operating conditions. As a best practice, reset should be held low during power-up.Prior to deasserting RESET (low-to-high transition), the core and I/O voltages should be at their proper operating conditions and CLKIN should also be running at the correct frequency.TMS320C6414, TMS320C6415, TMS320C6416FIXED-POINT DIGITAL SIGNAL PROCESSORSSPRS146N − FEBRUARY 2001 − REVISED MAY 2005absolute maximum ratings over operating case temperature range (unless otherwise noted)†Supply voltage ranges:CV DD (see Note 1)− 0.3 V to 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DV DD (see Note 1)−0.3 V to 4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage ranges:(except PCI), V I −0.3 V to 4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (PCI), V IP [C6415 and C6416 only]−0.5 V to DV DD + 0.5 V . . . . . . . . . . . . . . . . . . . . . Output voltage ranges:(except PCI), V O −0.3 V to 4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (PCI), V OP [C6415 and C6416 only]−0.5 V to DV DD + 0.5 V . . . . . . . . . . . . . . . . . . . . Operating case temperature ranges, T C :(default)0_C to 90_C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (A version) [A-5E0, A-6E3]−40_C to105_C . . . . . . . . . . . . . . . . . . . Storage temperature range, T stg −65_C to 150_C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTE 1:All voltage values are with respect to V SS .recommended operating conditions MINNOM MAX UNIT CV DDSupply voltage, Core (-5E0 device)‡ 1.14 1.2 1.26V CV DDSupply voltage, Core (A-5E0 device)‡ 1.19 1.25 1.31V CV DDSupply voltage, Core (-6E3, A-6E3, -7E3 devices)‡ 1.36 1.4 1.44V DV DDSupply voltage, I/O 3.14 3.3 3.46V V SSSupply ground 000V V IHHigh-level input voltage (except PCI)2V V ILLow-level input voltage (except PCI)0.8V V IPInput voltage (PCI) [C6415 and C6416 only]−0.5DV DD + 0.5V V IHPHigh-level input voltage (PCI) [C6415 and C6416 only]0.5DV DD DV DD + 0.5V V ILPLow-level input voltage (PCI) [C6415 and C6416 only]−0.50.3DV DD V V OSMaximum voltage during overshoot/undershoot −1.0§ 4.3§V Operating case tem-Default 090_C T COperating case tem perature A version (C6414/15/16GLZA-5E0 and GLZA-6E3 only)–40105_C ‡Future variants of the C641x DSPs may operate at voltages ranging from 0.9 V to 1.4 V to provide a range of system power/performance options.TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.2 V, 1.25 V, 1.3 V, 1.35 V, 1.4 V with ± 3% tolerances) by implementing simple board changes such as reference resistor values or input pin configuration modifications. Examples of such supplies include the PT4660, PT5500, PT5520, PT6440, and PT6930 series from Power Trends, a subsidiary of T exas Instruments. Not incorporating a flexible supply may limit the system’s ability to easily adapt to future versions of C641x devices.§The absolute maximum ratings should not be exceeded for more than 30% of the cycle period.。

(完整word版)12864中文字库说明书ST7920

12864C-1液晶中文显示模块(一)概述 (3)(一)(二)外形尺寸1 方框图 (3)2 外型尺寸图 (4)(二)(三)模块的接口 (4)(三)(四)硬件说明 (5)(五) 指令说明 (7)(四)(五)读写操作时序 (8)(五)(六)交流参数 (11)(六)(七)软件初始化过程 (12)(七)(八)应用举例 (13)(八)(九)附录1半宽字符表 (20)2 汉字字符表 (21)一、概述12864C-1是一种具有4位/8位并行、2线或3线串行多种接口方式，内部含有国标一级、二级简体中文字库的点阵图形液晶显示模块；其显示分辨率为128×64, 内置8192个16*16点汉字，和128个16*8点ASCII字符集.利用该模块灵活的接口方式和简单、方便的操作指令，可构成全中文人机交互图形界面。

可以显示8×4行16×16点阵的汉字. 也可完成图形显示.低电压低功耗是其又一显著特点。

由该模块构成的液晶显示方案与同类型的图形点阵液晶显示模块相比，不论硬件电路结构或显示程序都要简洁得多，且该模块的价格也略低于相同点阵的图形液晶模块。

基本特性:●●低电源电压（VDD:+3.0--+5.5V）●●显示分辨率:128×64点●●内置汉字字库，提供8192个16×16点阵汉字(简繁体可选)●●内置 128个16×8点阵字符●●2MHZ时钟频率●●显示方式：STN、半透、正显●●驱动方式：1/32DUTY，1/5BIAS●●视角方向：6点●●背光方式：侧部高亮白色LED，功耗仅为普通LED的1/5—1/10●●通讯方式：串行、并口可选●●内置DC-DC转换电路，无需外加负压●●无需片选信号，简化软件设计●●工作温度: 0℃ - +55℃ ,存储温度: -20℃ - +60℃二、方框图3、外形尺寸图三、模块接口说明*注释1：如在实际应用中仅使用串口通讯模式，可将PSB接固定低电平，也可以将模块上的J8和“GND”用焊锡短接。

计算机硬件指标

③显存容量
显存容量决定了显示芯片能处理的数据量。除显存频率和位宽外，影响显卡性能的一个非常重要的指标就是显存的容量。从理论上讲，显存容量越大，显卡性能就越好。
⑵显示器的性能参数
显示器作为最重要的输出设备，其性能好坏直接影响到用户的使用和身体健康。根据显示器成像原理，可分为CRT显示器、LCD（液晶）显示器和等离子显示器（PD），目前用户常用的是CRT显示器和LCD（液晶）显示器。
BIOS惠普68CPC Ver. F.02
制造日期06/09/2011
内存：
DIMM 0:海力士DDR3 1333MHz 2GB
制造日期2010年01月
型号AD HMT125S6BFR8C-H9 N0
序列号:BD43B222
DIMM 3:金士顿DDR3 1333MHz 2GB
制造日期2011年04月
CPU的接口是指CPU与主板插槽接触的部位。
⑹制造工艺
CPU的制造工艺一般是指CPU内部主要电子元件之间所间隔的距离，其单位通常为nm(纳米)，生产工艺越先进，连接线越细，CPU内部功耗和发热量越小，其集成度越高。
主板：
⑴主板的结构
主板上的主要结构元素有以下几点：
①主板的接口
目前大多数主板的接口一般有IDE接口、SATA接口、软驱接口等。
④可扩充性
主板的扩充能力主要体现在有足够的扩展槽、内存插槽、CPU插槽及硬盘、光驱接口、USB接口等。
内存：
内存的主要性能参数有容量、工作电压、存取时间、工作频率、数据宽度等。
⑴容量
计算机中内存容量越大，计算机运行速度也就越快。但内存容量的增加受到主板芯片支持能力和内存插槽数量的制约。因此在扩充内存容量时，要了解所使用的主板所支持的最大内存容量和空闲的内存插槽数量。

W3HG128M64EEUXXXD4MG资料

W3HG128M64EEU-D4ADVANCED*White Electronic Designs1GB – 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMMDESCRIPTIONThe W3HG128M64EEU is a 128Mx64 Double Data Rate2 SDRAM memory module based on 1Gb DDR2 SDRAM components. The module consists of eight 128Mx8, in FBGA package mounted on a 200 pin SO-DI MM FR4 substrate.* T his product is under development, is not qualiﬁ ed or characterized and is subject to change or cancellation without notice.NOTE: C onsult factory for availability of:• Vendor source control options • Industrial temperature optionFEATURES200-pin, Small-Outline DIMM (SO-DIMM), RawCard "B" Fast data transfer rates: PC2-6400*, PC2-5300*,PC2-4200 and PC2-3200 Utilizes 800*, 667*, 533 and 400 Mb/s DDR2SDRAM components V CC = V CCQ = 1.8V ± 0.1V V CCSPD = 1.7V to 3.6VJEDEC standard 1.8V I/O (SSTL_18-compatible) Differential data strobe (DQS, DQS#) option Four-bit prefetch architectureDLL to align DQ and DQS transitions with CK Multiple internal device banks for concurrentoperation Supports duplicate output strobe (RDQS/RDQS#) Programmable CAS# latency (CL): 3, 4, 5* and 6* Adjustable data-output drive strength On-Die Termination (ODT)Posted CAS# latency: 0, 1, 2, 3 and 4 Serial Presence Detect (SPD) with EEPROM 64ms: 8,192 cycle refresh Gold edge contacts Single Rank RoHS Compliant JEDEC Package option• 200 Pin (SO-D IMM)• PCB – 29.20mm (1.150") TYPOPERATING FREQUENCIESPC2-6400*PC2-5300*PC2-4200PC2-3200Clock Speed 400MHz 333MHz 266MHz 200MHz CL-t RCD -t RP6-6-65-5-54-4-43-3-3* Consult factory for availabilityW3HG128M64EEU-D4ADVANCEDWhite Electronic DesignsPIN NAMESSYMBOLDESCRIPTION A0 - A13Address inputODT0On-Die Termination CK0, CK0#Differential Clock Inputs CK1, CK1#Differential Clock inputs CKE0Clock Enable input CS0#Chip selectRAS#, CAS#, WE#Command Inputs BA0 - BA2Bank Address Inputs DM0 - DM7Input Data Mask DQ0 - DQ63Data Input/Output DQS0 - DQS7DQS0#-DQS7#Data StrobeSCL Serial Clock for Presence Detect SA0-SA1Presence Detect Address Inputs SDA Serial Presence Detect Data V CC Power SupplyV REF SSTL_18 reference voltage V SS GroundV CCSPD Serial EEPROM Power Supply NCNo ConnectPIN CONFIGURATIONPIN#SYMBOL PIN#SYMBOL PIN#SYMBOL PIN#SYMBOL1V REF51DQS2101A1151DQ422V SS 52DM2102A0152DQ463V SS53V SS 103V CC 153DQ434DQ454V SS 104V CC 154DQ475DQ055DQ18105A10/AP 155V SS 6DQ556DQ22106BA1156V SS 7DQ157DQ19107BA0157DQ488V SS 58DQ23108RAS#158DQ529V SS 59V SS 109WE#159DQ4910DM060V SS 110CS0#160DQ5311DQS0#61DQ24111V CC 161V SS 12V SS 62DQ28112V CC 162V SS 13DQS063DQ25113CAS#163NC 14DQ664DQ29114ODT0164CK115V SS65V SS 115NC 165V SS 16DQ766V SS 116A13166CK1#17DQ267DM3117V CC 167DQS6#18V SS 68DQS3#118V CC 168V SS 19DQ369NC 119NC 169DQS620DQ1270DQS3120NC 170DM621V SS 71V SS 121V SS 171V SS 22DQ1372V SS 122V SS 172V SS 23DQ873DQ26123DQ32173DQ5024V SS74DQ30124DQ36174DQ5425DQ975DQ27125DQ33175DQ5126DM176DQ31126DQ37176DQ5527V SS 77V SS 127V SS 177V SS 28V SS 78V SS 128V SS 178V SS 29DQS1#79CKE0129DQS4#179DQ5630CK080NC 130DM4180DQ6031DQS181V CC 131DQS4181DQ5732CK0#82V CC 132V SS 182DQ6133V SS 83NC 133V SS 183V SS 34V SS 84NC 134DQ38184V SS 35DQ1085BA2135DQ34185DM736DQ1486NC 136DQ39186DQS7#37DQ1187V CC137DQ35187V SS 38DQ1588V CC 138V SS 188DQS739V SS 89A12139V SS 189DQ5840V SS 90A11140DQ44190V SS 41V SS 91A9141DQ40191DQ5942V SS 92A7142DQ45192DQ6243DQ1693A8143DQ41193V SS 44DQ2094A6144V SS 194DQ6345DQ1795V CC 145V SS 195SDA 46DQ2196V CC 146DQS5#196V SS 47V SS 97A5147DM5197SCL 48V SS 98A4148DQS5198SA049DQS2#99A3149V SS 199V CCSPD 50NC 100A2150V SS 200SA1White Electronic DesignsW3HG128M64EEU-D4ADVANCED FUNCTIONAL BLOCK DIAGRAMW3HG128M64EEU-D4ADVANCEDWhite Electronic DesignsRECOMMENDED DC OPERATING CONDITIONSAll voltages referenced to V SSParameter Symbol Min Max Units Notes Supply VoltageV CC 1.7 1.9V -I/O Reference VoltageV REF 0.49 x V CC 0.51 x V CC V 1I/O Termination Voltage (system)V TT V REF - 40V REF + 40mV 2NOTE:1. V REF is expected to equal V CCQ /2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on V REF may not exceed±1 percent of the DC value. Peak-to-peak AC noise on V REF may not exceed ±2 percent of V REF (DC). This measurement is to be taken at the nearest V REF bypass capacitor.2. V TT is not applied directly to the device. V TT is a system supply for signal termination resistors, is expected to be set equalto V REF and must track variations in the DC level of V REF .ABSOLUTE MAXIMUM DC CHARACTERISTICSSymbol ParameterMin Max Units V CC V CC Supply Voltage Relative to V SS -0.5 2.3V V IN , V OUT Voltage on any Pin Relative to V SS -0.5 2.3V T STG Storage Temperature-55100°C T CASE DDR2 SDRAM Device Operating Temperature*085°C T OPR Operating Temperature (Ambient)065°C I IInput Leakage Current; Any input 0V ≤ V IN ≤ V CC ; V REF input 0V ≤ V IN ≤0.95V; (All other pins not under test = 0V)Command/Address, RAS#, CAS#, WE# S#, CKE-4040µACK, CK#-2020DM-55I OZ Output Leakage Current; 0V ≤ V OUT ≤ V CC Q; DQs and ODT are disabledDQ, DQS, DQS#-55µA I VREFV REF Leakage Current; V REF = Valid V REF level-1616µA* T CASE speciﬁ es as the temperature at the top center of the memory devices.CAPACITANCET A = 25°C, f = 100MHz, V CC = 1.8V, V REF = V SSParameterSymbol Max Unit Input Capacitance (A0-A12)C IN135pF Input Capacitance (RAS#,CAS#,WE#)C IN235pF Input Capacitance (CKE0)C IN331pF Input Capacitance (CK0, CK0#)C IN415pF Input Capacitance (CS0#)C IN531pF Input Capacitance (DQS0#-DQS17#)C IN66pF Input Capacitance (BA0-BA1)C IN735pF Data input/output Capacitance (DQ0-DQ63)C OUT 6pFNOTE:* These capacitance values are based on worst case component values in conjunction with the circuit boards associated parasitic net capacitance.W3HG128M64EEU-D4ADVANCED White Electronic DesignsDDR2 I CC SPECIFICATIONS AND CONDITIONSDDR2 SDRAM components onlyV CC = +1.8V ± 0.1VParameter Symbol Condition806665534403Units Operating one devicebank active-precharge current;I CC0t CK = t CK (I CC), t RC = t RC (I CC), t RAS = t RAS MIN (I CC); CKE is HIGH, CS# isHIGH between valid commands; Address bus inputs are SWITCHING;Data bus inputs are SWITCHING.TBD800640640mAOperating one devicebank active-read-precharge current;I CC1I OUT = 0mA; BL = 4, CL = CL(I CC), AL = 0; t CK = t CK (I CC), t RC = t RC (I CC),t RAS = t RAS MIN (I CC), t RCD = t RCD (I CC); CKE is HIGH, CS# is HIGHbetween valid commands; Address bus inputs are SWITCHING; Datapattern is same as I CC4W.TBD1,160760760mAPrecharge power-down current;I CC2PAll device banks idle; t CK = t CK (I CC); CKE is LOW; Other control andaddress bus inputs are STABLE; Data bus inputs are FLOATING.TBD564040mAPrecharge quiet standby current;I CC2QAll device banks idle; t CK = t CK (I CC); CKE is HIGH, CS# is HIGH; Othercontrol and address bus inputs are STABLE; Data bus inputs areFLOATING.TBD480328280mAPrecharge standby current;I CC2NAll device banks idle; t CK = t CK (I CC); CKE is HIGH, CS# is HIGH; Othercontrol and address bus inputs are SWITCHING; Data bus inputs areSWITCHING.TBD520360280mAActive power-down current;I CC3PAll device banks open; t CK = t CK (I CC); CKE is LOW;Other control and address bus inputs are STABLE;Data bus inputs are FLOATING.Fast PDN ExitMR[12] = 0TBD320240200mASlow PDN ExitMR[12] = 1TBD808080mAActive standby current;I CC3N All device banks open; t CK = t CK(I CC), t RAS = t RAS MAX (I CC), t RP = t RP(I CC);CKE is HIGH, CS# is HIGH between valid commands; Other control andaddress bus inputs are SWITCHING; Data bus inputs are SWITCHING.TBD560400320mAOperating burst write current;I CC4WAll device banks open, Continuous burst writes; BL = 4, CL = CL (I CC),AL = 0; t CK = t CK (I CC), t RAS = t RAS MAX (I CC), t RP = t RP (I CC); CKE isHIGH, CS# is HIGH between valid commands; Address bus inputs areSWITCHING; Data bus inputs are SWITCHING.TBD1,4401,040960mAOperating burst read current;I CC4RAll device banks open, Continuous burst reads, I OUT = 0mA; BL = 4, CL= CL (I CC), AL = 0; t CK = t CK (I CC), t RAS = t RAS MAX (I CC), t RP = t RP (I CC);CKE is HIGH, CS# is HIGH between valid commands; Address businputs are SWITCHING; Data bus inputs are SWITCHING.TBD1,6401,1601,080mABurst refresh current;I CC5t CK = t CK (I CC); Refresh command at every t RFC (I CC) interval; CKEis HIGH, CS# is HIGH between valid commands; Other control andaddress bus inputs are SWITCHING; Data bus inputs are SWITCHING.TBD2,1602,0001,920mASelf refresh current;I CC6CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputsare FLOATING; Data bus inputs are FLOATING.TBD564040mAOperating device bank interleave read current; I CC7All device banks interleaving reads, I OUT= 0mA; BL = 4, CL = CL (I CC),AL = t RCD (I CC)-1 x t CK (I CC); t CK = t CK (I CC), t RC = t RC(I CC), t RRD = t RRD(I CC),t RCD = t RCD(I CC); CKE is HIGH, CS# is HIGH between valid commands;Address bus inputs are STABLE during DESELECTs; Data bus inputsare SWITCHINGTBD2,7202,3602,360mANote:• I CC speciﬁ cation is based on MICRON components. Other DRAM manufacturers speciﬁ cation may be different.W3HG128M64EEU-D4ADVANCEDWhite Electronic DesignsAC OPERATING CONDITIONSV CC = +1.8V ±0.1VC l o c kAC Characteristics Symbol806665534403Units NotesParameterMinMaxMin Max Min Max Min Max Clock cycle timeCL = 6t CK (6)3,0008,000------ps CL = 5t CK (5)3,0008,0003,0008,000----ps 16, 22, 36, 38CL = 4t CK (4)3,0008,0003,7508,0003,7508,0005,0008,000ps CL = 3tCK (3)--5,0008,0005,0008,0005,0008,000psCK high-level width tCH AVG 0.480.520.480.520.480.520.480.52t CK 45CK low-level width tCL AVG0.480.520.480.520.480.520.480.52tCKHalf clock periodtHP MIN (t CH,t CL)MIN (t CH,t CL)MIN (t CH,t CL)MIN (t CH,t CL)ps46C l o c k (A b s o l u t e )Absolute tCk tCK abstCKAVG+(MIN)+tJITPER (MIN)tCKAVG+(MAX)+t JITPER (MAX)tCKAVG+(MIN)+t JITPER (MIN)tCKAVG+(MAX)+t JITPER (MAX)tCKAVG+(MIN)+t JITPER (MIN)tCKAVG+(MAX)+t JITPER (MAX)tCKAVG+(MIN)+t JITPER (MIN)tCKAVG+(MAX)+tJITPER (MAX)psAbsolute CK high-level widthtCH abstCKAVG (MIN)*t CH AVG+t JIT DTY(MIN)tCKAVG (MAX)*t CH AVG+t JIT DTY(MAX)tCKAVG (MIN)*t CH AVG+t JIT DTY(MIN)tCKAVG (MAX)*t CH AVG+t JIT DTY(MAX)tCKAVG (MIN)*t CH AVG+t JIT DTY(MIN)tCKAVG (MAX)*t CH AVG+t JIT DTY(MAX)tCKAVG (MIN)*t CH AVG+t JIT DTY(MIN)tCKAVG (MAX)*t CHAVG+t JIT DTY(MAX)psAbsolute CK low-level widthtCL abstCKAVG (MIN)*tCLAVG(MIN)+t JIT DTY(MIN)t CKAVG (MAX)*tCLAVG (MAX)+t JIT DTY(MIN)t CKAVG (MIN)*t CLAVG (MIN)+t JIT DTY(MIN)t CKAVG (MAX)*t CLAVG (MAX)+t JIT DTY(MIN)t CKAVG (MIN)*t CLAVG (MIN)+t JIT DTY(MIN)t CKAVG (MAX)*t CLAVG (MAX)+t JIT DTY(MIN)t CKAVG(MIN)*t CLAVG(MIN)+tJIT DTY(MIN)tCKAVG(MAX)*t CLAVG(MAX)+t JITDTY(MIN)psC l o c k j i t t e rClock jitter - period tJIT PER-125125-125125-125125-125125ps 39Clock jitter - half period tJIT DUTY -125125-125125-125125-150150ps 40Clock jitter - cycle to cycle tJIT CC250250250250ps 41Cumulative jitter error, 2 cycles t ERR 2per -175175-175175-175175-175175ps 42Cumulative jitter error, 3 cycles t ERR 3per -225225-225225-225225-225225ps 42Cumulative jitter error, 4 cycles t ERR 4per -250250-250250-250250-250250ps 42Cumulative jitter error, 5cycles t ERR 5per-250250-250250-250250-250250ps 42, 48Cumulative jitter error, 6-10 cycles t ERR 6-10per -350350-350350-350350-350350ps 42, 48Cumulative jitter error, 11-50 cyclest ERR 11-50per -450450-450450-450450-450450ps42Note:• AC speciﬁ cation is based on MICRON components. Other DRAM manufactures speciﬁ cation may be different.W3HG128M64EEU-D4ADVANCEDWhite Electronic DesignsAC OPERATING CONDITIONS (continued)V CC = +1.8V ±0.1VD a t aAC Characteristics Symbol806665534403Units Notes ParameterMin Max Min Max Min Max Min Max tQHS-340-340-400-450ps 47DQ output access time from CK/CK#tAC -450+450-450+450-500+500-600+600ps 43Data-out high-impedance window from CK/CK#tHZtAC (MAX)tAC (MAX)tAC (MAX)tAC (MAX)ps 8, 9, 43Data-out low-impedance window from CK/CK#tLZ1tAC (MIN)tAC (MAX)tAC (MIN)tAC (MAX)tAC (MIN)tAC (MAX)tAC (MIN)tAC (MAX)ps 8, 10, 43Data-out low-impedance window from CK/CK#tLZ 22*t AC(MIN)tAC (MAX)2*t AC(MIN)tAC (MAX)2*t AC(MIN)tAC (MAX)2*t AC(MIN)tAC (MAX)ps 8, 10, 43DQ and DM input setup time relative to DQS tDS a300300350400ps 7, 15,19DQ and DM input hold time relative to DQS tDH a 300300350400ps 7, 15, 19DQ and DM input setup time relative to DQS tDS b100100100150ps 7, 15, 19DQ and DM input hold time relative to DQS tDH b175175225275ps7, 15,19DQ and DM input pulse width (for each input)t DIPW0.350.350.350.35tCK37Data hold skew factortQHS340340400450ps 47DQ–DQS hold, DQS to ﬁ rst DQ to go nonvalid, per accesstQHtHP-tQHStHP-tQHStHP-tQHStHP-tQHSps 15, 17, 47Data valid output window (DVW)t DVWt QH - tDQSQ t QH - tDQSQ t QH - tDQSQ t QH- tDQSQns15, 17D a t a S t r o b eDQS input high pulse width t DQSH 0.350.350.350.35t CK 37DQS input low pulse widthtDQSL0.350.350.350.35tCK37DQS output access time from CK/CK#t DQSCK -400+400-400+400-450+450-500+500ps40DQS falling edge to CK rising – setup time t DSS 0.20.20.20.2t CK 37DQS falling edge from CK rising – hold timetDSH0.20.20.20.2tCK37Note:• AC speciﬁ cation is based on MICRON components. Other DRAM manufactures speciﬁ cation may be different.W3HG128M64EEU-D4ADVANCEDWhite Electronic DesignsAC OPERATING CONDITIONS (continued)V CC = +1.8V ±0.1VD a t a S t r o b eAC Characteristics Symbol806665534403Units Notes ParameterMinMax MinMax MinMax MinMax DQS–DQ skew, DQS to last DQ valid, per group, per accesstDQSQ 240240300350ps15, 17DQS read preamble tRPRE 0.9 1.10.9 1.10.9 1.10.9 1.1tCK33, 37, 43DQS read postamble t RPST0.40.60.40.60.40.60.40.6tCK33, 34, 37, 43DQS write preamble setup time tWPRE S 0000ps12, 13,DQS write preamble tWPRE 0.350.350.250.25tCK 37DQS write postambletWPST 0.40.60.40.60.40.60.40.6t CK 11, 37Positive DQS latching edge to associated clock edge tDQSS- 0.25 0.25- 0.25 0.25- 0.25 0.25- 0.25 0.25tCK 37Write command to ﬁ rst DQS latching transition WL-tDQSSWL+tDQSSWL-tDQSSWL+tDQSSWL-tDQSSWL+tDQSSWL-tDQSSWL+tDQSStCK C o m m a n d a n d A d d r e s sAddress and control input pulse width for each input t IPW0.60.60.60.6tCK37Address and control input setup time t IS a 400400500600ps 6, 19Address and control input hold time tIH a 400400500600ps 6, 19Address and control input setup time t IS b200200250350ps6, 19Address and control input hold time tIH b2752753754756, 19CAS# to CAS# command delayt CCD2222tCK37ACTIVE to ACTIVE (same bank) command tRC54555555ns 31, 37ACTIVE bank a to ACTIVE bank b command t RRD (x8)7.57.57.57.5ns 25, 37ACTIVE to READ or WRITE delay tRCD 12151515ns 37Four Bank Activate period tFAW(x8)37.537.537.537.5ns28, 37ACTIVE to PRECHARGE command tRAS 4070,0004070,0004070,0004070,000ns 18, 31,37Internal READ to precharge command delay tRTP 7.57.57.57.5ns 21, 25. 37Write recovery timet WR15151515ns 25, 37Auto precharge write recovery + precharge time tDALtWR + tRPtWR + tRPtWR + tRPtWR + tRPns 20Internal WRITE to READ command delay t WTR 7.57.57.510ns 25, 37PRECHARGE command period tRP12151515ns 29, 37PRECHARGE ALL command period t RPAtRP + tCKtRP + tCKtRP + tCKtRP + tCKns29LOAD MODE command cycle timet MRD 2222tCK37Note:• AC speciﬁ cation is based on MICRON components. Other DRAM manufactures speciﬁ cation may be different.W3HG128M64EEU-D4ADVANCEDWhite Electronic DesignsAC OPERATING CONDITIONS (continued)V CC = +1.8V ±0.1VAC Characteristics Symbol806665534403Units Notes ParameterMinMaxMinMaxMinMaxMinMaxR e f r e s hCKE low to CK,CK# uncertainty tDELAYtIS + tCK + tIH tIS + tCK + tIH tIS + tCK + tIH tIS + tCK + tIHns 26REFRESH to ACTIVE or REFRESH to REFRESH command intervaltRFC 127.570,000127.570,000127.570,000127.570,000ns 14, 37Average periodic refresh interval (commercial)tREFI 7.87.87.87.8µs 14, 37Average periodic refresh interval (industrial)tREFI IT 3.9 3.93.93.9µs 14, 37S e l f R e f r e s hExit self refresh to non-READ command tXSNR t RFC(MIN) + 10t RFC(MIN) + 10t RFC(MIN) + 10t RFC(MIN) + 10nsExit self refresh to READ command tXSRD200200200200tCK37Exit self refresh timing reference tISXR t IS t ISt ISt ISps 6, 27O D TODT turn-on delay t AOND 22222222tCK37ODT turn-on tAOND tAC (MIN)tAC (MAX) + 700)t AC (MIN)tAC (MAX) + 700)t AC (MIN)tAC (MAX) + 1,000)t AC (MIN)tAC (MAX) + 1,000)ps23, 43ODT turn-off delay tAOFD2.52.52.52.52.52.52.52.5tCK35, 37ODT turn-off tAOFtAC (MIN)tAC (MAX + 600)t AC (MIN)tAC (MAX + 600)t AC (MIN)tAC (MAX + 600)t AC (MIN)tAC (MAX + 600)ps 24, 44ODT turn-on (power-down mode)t AONPDtAC (MIN) + 2,000 2 x tCK +tAC (MAX) + 1,000t AC (MIN) + 2,000 2 x tCK +t AC (MAX) + 1,000t AC (MIN) + 2,000 2 x tCK +t AC (MAX) + 1,000t AC (MIN) + 2,0002 x tCK +tAC (MAX)+ 1,000psODT turn-off (power-down mode)t AOFPDtAC (MIN)+ 2,000 2.5 xtCK +tAC (MAX) + 1,000tAC (MIN)+ 2,000 2.5 xtCK +tAC (MAX) + 1,000tAC (MIN)+ 2,000 2.5 xtCK +tAC (MAX) + 1,000tAC (MIN)+ 2,000 2.5 xtCK +tAC (MAX)+ 1,000psODT to power-down entry latency tANPD 3333t CK 37ODT power-down exit latency tAXPD8888tCK37ODT enable from MRS command tMOD 12121212ns37, 49P o w e r D o w nExit active power-down to READ command, MR[bit12=0]t XARD2222tCK37Exit active power-down to READ command, MR[bit12=1]tXARDS 7 - AL 7 - AL 6 - AL 6 - AL 37Exit precharge power-down to any non-READ command.t XP 2222t CK 37CKE minimum high/low timetCKE3333tCK32, 37Note:• AC speciﬁ cation is based on MICRON components. Other DRAM manufactures speciﬁ cations may be different.W3HG128M64EEU-D4ADVANCED* White Electronic DesignsNotes:1. All voltages referenced to VSS.2. Tests for AC timing, I CC, and electrical AC and DC characteristics may be conductedat nominal reference / supply voltage levels, but the related speciﬁ cations anddevice operation are guaranteed for the full voltage range speciﬁ ed. ODT is disabled for all measurements that are not ODT-speciﬁ c.3. Outputs measured with equivalent load:4. AC timing and I CC tests may use a V IL-to-V IH swing of up to 1.0V in the testenvironment and parameter speciﬁ cations are guaranteed for the speciﬁ ed AC input levels under normal use conditions. The slew rate for the input signals used to test the device is 1.0V/ns for signals in the range between V IL (AC) and V IH (AC). Slew rates less than 1.0V/ns require the timing parameters to be derated as speciﬁ ed.5. The AC and DC input level speciﬁ cations are as deﬁ ned in the SSTL_18 standard(i.e., the receiver will effectively switch as a result of the signal crossing the AC inputlevel and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level).6. There are two sets of values listed for Command/Address: t ISa, t IHa and t ISb, t IHb. Thet ISa, t IHa values (for reference only) are equivalent to the baseline values of t ISb, t IHb at V REF when the slew rate is 1V/ns. The baseline values, t ISb, t IHb, are the JEDEC deﬁ ned values, referenced from the logic trip points. t ISb is referenced from V IH (AC) for a rising signal and V IL (AC) for a falling signal, while t IHb is referenced from V IL (DC) for a rising signal and V IH (DC) for a falling signal. If the Command/Address slew rate is not equal to 1 V/ns, then the baseline values must be derated.7. The values listed are for the differential DQS strobe (DQS and DQS#) with adifferential slew rate of 2 V/ns (1 V/ns for each signal). There are two sets of values listed: t DSa. t DHa and t DSb, t DHb. The t DSa, t DHa values (for reference only) are equivalent to the baseline values of t DSb, t DHb at V REF when the slew rate is 2V/ns, differentially. The baseline values, t DSb, t DHb, are the JEDEC-deﬁ ned values, referenced from the logic trip points. t DSb is referenced from V IH (AC) for a rising signal and V IL (AC) for a falling signal, while t DSb is referenced from V IL (DC) for a rising signal and V IH (DC) for a falling signal. If the differential DQS slew rate is not equal to 2 V/ns, then the baseline values must be derated. If the DQS differential strobe feature is not enabled, then the DQS strobe is single-ended, the baseline values not applicable, and timing is not referenced to the logic trip points. Single-ended DQS data timing is referenced to DQS crossing V REF.8. t HZ and t LZ transitions occur in the same access time windows as valid datatransitions. These parameters are not referenced to a speciﬁ c voltage level, butspecify when the device output is no longer driving (t HZ) or begins driving (t LZ).9. This maximum value is derived from the referenced test load. t HZ (MAX) will prevailover t DQSCK (MAX) + t RPST (MAX) condition.10. t LZ (MIN) will prevail over a t DQSCK (MIN) + t RPRE (MAX) condition11. The intent of the "Don’t Care" state after completion of the postamble is the DQS-driven signal should either be high, low or High-Z and that any signal transitionwithin the input switching region must follow valid input requirements. That is if DQS transitions high (above V IH DC(min) then it must not transition low (below V IH(DC) prior to t DQSH(min).12. This is not a device limit. The device will operate with a negative value, but systemperformance could be degraded due to bus turnaround.13. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITEcommand. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was inprogress, DQS could be HIGH during this time, depending on t DQSS.14. The refresh period is 64ms (commercial) or 32ms (industrial). This equates to anaverage refresh rate of 7.8125µs (commercial) or 3.9607µs (industrial). However, a REFRESH command must be asserted at least once every 70.3µs or t RFC (MAX).To ensure all rows of all banks are properly refreshed, 8,192 REFRESH commands must be issued every 64ms.15. Referenced to each output group: x4 = DQS with DQ0–DQ3; x8 = DQS withDQ0–DQ7; x16 = LDQS with DQ0–DQ7; and UDQS with DQ8–DQ15.16. CK and CK# input slew rate is referenced at 1 V/ns (2 V/ns if measureddifferentially).17. The data valid window is derived by achieving other speciﬁ cations - t HP. (t CK/2),t DQSQ, and t QH (t QH = t HP - t QHS). The data valid window derates in directproportion to the clock duty cycle and a practical data valid window can be derived.18. READs and WRITEs with auto precharge are allowed to be issued beforet RAS(MIN) is satisﬁ ed since t RAS lockout feature is supported in DDR2 SDRAM.19. V IL/V IH DDR2 overshoot/undershoot.20. t DAL = (nWR) + (t RP/t CK). Each of these terms, if not already an integer, should berounded up to the next integer. t CK refers to the application clock period; nWR refers with t WR programmed to four clocks would have t DAL = 4 + (15ns/3.75ns) clocks =4 + (4) clocks = 8 clocks.21. The minimum internal READ to PRECHARGE time. This is the time from the last4-bit prefetch begins to when the PRECHARGE command can be issued. A 4-bit prefetch is when the READ command internally latches the READ so that data will output CL later. This parameter is only applicable when t RTP/(2x t CK) > 1, such as frequencies faster than 533 MHz when tRTP = 7.5ns. If tRTP/ (2x t CK) ≤ 1, then equation AL + BL/2 applies. tRAS (MIN) also has to be satisﬁ ed as well. The DDR2 SDRAM will automatically delay the internal PRECHARGE command until t RAS(MIN) has been satisﬁ ed.22. Operating frequency is only allowed to change during self refresh mode, prechargepower-down mode, and system reset condition.23. t DAL = (nWR) + (t RP/t CK): For each of the terms above, if not already an integer,round to the next highest integer. t CK refers to the application clock period;AC Operation Condition Notes: nWR refers to the t WR parameter stored in theMR[11,10,9]. Example: For -533Mb/s at t CK = 3.75 ns with t WR programmed to four clocks. t DAL = 4 + (15 ns/3.75 ns) clocks = 4 +(4) clocks = 8 clocks.24. ODT turn-off time t AOF (MIN) is when the device starts to turn off ODT resistance.ODT turn off time t AOF (MAX) is when the bus is in high-Z. Both are measured from t AOFD.25. This parameter has a two clock minimum requirement at any t CK.26. t DELAY is calculated from t IS + t CK + t IH so that CKE registration LOW isguaranteed prior to CK, CK# being removed in a system RESET condition.27. t ISXR is equal to t IS and is used for CKE setup time during self refresh exit.28. No more than 4 bank ACTIVE commands may be issued in a given t FAW(min)period. t RRD(min) restriction still applies. The t FAW(min) parameter applies to all 8 bank DDR2 devices, regardless of the number of banks already open or closed. 29. t RPA timing applies when the PRECHARGE(ALL) command is issued, regardlessof the number of banks already open or closed. If a single-bank PRECHARGEcommand is issued, t RP timing applies. t RPA(MIN) applies to all 8-bank DDR2devices.30. Value is minimum pulse width, not the number of clock registrations.31. This is applicable to Read cycles only. Write cycles generally require additional timedue to t WR during auto precharge.32. t CKE (MIN) of 3 clocks means CKE must be registered on three consecutivepositive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of t IS + 2 x t CK + t IH.33. This parameter is not referenced to a speciﬁ c voltage level, but speciﬁ ed when thedevice output is no longer driving (t RPST) or beginning to drive (t RPRE).34. When DQS is used single-ended, the minimum limit is reduced by 100ps.35. The half-clock of t AOFD's 2.5 t CK assumes a 50/50 clock duty cycle. This half-clockvalue must be derated by the amount of half-clock duty cycle error. For example, if the clock duty cycle was 47/53, t AOFD would actually be 2.5 - 0.03, or 2.47 for t AOF (MIN) and 2.5 + 0.03 or 2.53 for t AOF (MAX).36. The clock’s t CK AVG is the average clock over any 200 consecutive clocks and。

MEMORY存储芯片MT48G4M32LFFC-10IT中文规格书

Temperature-Controlled Refresh ModeDuring normal operation, temperature-controlled refresh (TCR) mode disabled, the de-vice must have a REFRESH command issued once every t REFI, except for what is al-lowed by posting (see REFRESH Command section). This means a REFRESH commandmust be issued once every 0.975μs if T C is greater than 105°C, once every 1.95μs if T C isgreater than 95°C, once every 3.9μs if T C is greater than 85°C, and once every 7.8μs if T Cis less than or equal to 85°C, regardless of which Temperature Mode is selected(MR4[2]). TCR mode is disabled by setting MR4[3] = 0 while TCR mode is enabled bysetting MR4[3] = 1. When TCR mode is enabled (MR4[3] = 1), the Temperature Modemust be selected where MR4[2] = 0 enables the Normal Temperature Mode whileMR4[2] = 1 enables the Extended Temperature Mode.When TCR mode is enabled, the device will register the externally supplied REFRESHcommand and adjust the internal refresh period to be longer than t REFI of the normaltemperature range, when allowed, by skipping REFRESH commands with the propergear ratio. TCR mode has two Temperature Modes to select between the normal tem-perature range and the extended temperature range; the correct Temperature Modemust be selected so the internal control operates correctly. The DRAM must have thecorrect refresh rate applied externally; the internal refresh rate is determined by theDRAM based upon the temperature.Normal Temperature ModeREFRESH commands should be issued to the device with the refresh period equal tot REFI of normal temperature range (–40°C to 85°C). The system must guarantee that theT C does not exceed 85°C when t REFI of the normal temperature range is used. The de-vice may adjust the internal refresh period to be longer than t REFI of the normal tem-perature range by skipping external REFRESH commands with the proper gear ratiowhen T C is below 85°C. The internal refresh period is automatically adjusted inside theDRAM, and the DRAM controller does not need to provide any additional control. Extended Temperature ModeREFRESH commands should be issued to the device with the refresh period equal tot REFI of extended temperature range (85°C to 125°C). The system must guarantee thatthe T C does not exceed 125°C. Even though the external refresh supports the extendedtemperature range, the device may adjust its internal refresh period to be equal to orlonger than t REFI of the normal temperature range (–40°C to 85°C) by skipping externalREFRESH commands with the proper gear ratio when T C is equal to or below 85°C. Theinternal refresh period is automatically adjusted inside the DRAM, and the DRAM con-troller does not need to provide any additional control.Table 47: Normal t REFI Refresh (TCR Enabled)Fine Granularity Refresh ModeMode Register and Command Truth TableThe REFRESH cycle time (t RFC) and the average refresh interval (t REFI) can be pro-grammed by the MRS command. The appropriate setting in the mode register will set asingle set of REFRESH cycle times and average refresh interval for the device (fixedmode), or allow the dynamic selection of one of two sets of REFRESH cycle times andaverage refresh interval for the device (on-the-fly mode [OTF]). OTF mode must be ena-bled by MRS before any OTF REFRESH command can be issued.Table 48: MRS DefinitionThere are two types of OTF modes (1x/2x and 1x/4x modes) that are selectable by pro-gramming the appropriate values into the mode register. When either of the two OTFmodes is selected, the device evaluates the BG0 bit when a REFRESH command is is-sued, and depending on the status of BG0, it dynamically switches its internal refreshconfiguration between 1x and 2x (or 1x and 4x) modes, and then executes the corre-sponding REFRESH operation.Table 49: REFRESH Command Truth Tablet REFI and t RFC ParametersThe default refresh rate mode is fixed 1x mode where REFRESH commands should beissued with the normal rate; that is, t REFI1 = t REFI(base) (for T C≤ 85°C), and the dura-tion of each REFRESH command is the normal REFRESH cycle time (t RFC1). In 2xmode (either fixed 2x or OTF 2x mode), REFRESH commands should be issued to thedevice at the double frequency (t REFI2 = t REFI(base)/2) of the normal refresh rate. In 4xmode, the REFRESH command rate should be quadrupled (t REFI4 = t REFI(base)/4). PerFigure 84: TCR Mode Example1Controller85°C T C 95°C T C 85°C REFRESHExternal t REFI3.9μs Internal t REFI 3.9μs Internal t REFI 7.8μs REFRESH REFRESH REFRESH REFRESH REFRESH REFRESHREFRESH REFRESHREFRESH REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH Note: 1.TCR enabled with Extended Temperature Mode selected.。

W3EG6466S-BD4中文资料

White Electronic DesignsW3EG6466S-AD4-BD4PRELIMINARY*512MB – 2x32Mx64 DDR SDRAM UNBUFFERED, w/PLLDESCRIPTIONThe W3EG 6466S is a 2x32Mx64 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components. The module consists of sixteen 32Mx8 components as eight 64Mx8 stacked DDR SDRAMs in 66 pin TSOP packages mounted on a 200 pin FR4 substrate.Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.* T his product is under development, is not qualiﬁ ed or characterized and is subject to change without notice.FEATURESDDR200, DDR266 and DDR333• JEDEC design speciﬁ cations Double-data-rate architecture Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8)Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Dual RankPower supply: 2.5V ± 0.20VJEDEC standard 200 pin SO-DIMM package• Package height options: AD4: 35.5mm (1.38") BD4: 31.75mm (1.25")NOTE: C onsult factory for availability of:• RoHS compliant products • Vendor source control options • Industrial temperature optionOPERATING FREQUENCIESDDR333 @CL=2.5DDR266 @CL=2DDR266 @CL=2.5DDR200 @CL=2Clock Speed 166MHz 133MHz 133MHz 100MHz CL-t RCD -t RP2.5-3-32-2-22.5-3-32-2-2White Electronic DesignsW3EG6466S-AD4-BD4PRELIMINARYPIN NAMESA0 – A12A CC ress input (Multiplexed)BA0-BA1Bank Select A CC ress DQ0-DQ63Data Input/OutputDQS0-DQS7Data Strobe Input/Output CK0Clock Input CK0#Clock inputCKE0-CKE1Clock Enable input CS0#-CS1#Chip select Input RAS#Row A CC ress Strobe CAS#Column A CC ress Strobe WE#Write Enable DQM0-DQM7Data-In Mask V CC Power Supply V SS GroundV REF Power Supply for Reference V CCSPD Serial EEPROM Power Supply SDA Serial data I/O SCL Serial clockSA0-SA2A CC ress in EEPROM V CCID V CC Identiﬁ cation Flag NCNo Connect* Not UsedPIN CONFIGURATIONPin Symbol Pin Symbol Pin Symbol Pin Symbol 1V REF 51V SS 101A9151DQ422V REF 52V SS 102A8152DQ463V SS 53DQ19103V SS 153DQ434V SS 54DQ23104V SS 154DQ475DQ055DQ24105A7155V CC 6DQ456DQ28106A6156V CC 7DQ157V CC 107A5157V CC 8DQ558V CC 108A4158NC 9V CC 59DQ25109A3159V SS 10V CC 60DQ29110A2160NC 11DQS061DQS3111A1161V SS 12DQM062DQM3112A0162V SS 13DQ263V SS 113V CC 163DQ4814DQ664V SS 114V CC 164DQ5215V SS 65DQ26115A10/AP 165DQ4916V SS 66DQ30116BA1166DQ5317DQ367DQ27117BA0167V CC 18DQ768DQ31118RAS#168V CC 19DQ869V CC 119WE#169DQS620DQ1270V CC 120CAS#170DQM621V CC 71NC 121CS0#171DQ5022V CC 72NC 122CS1#172DQ5423DQ973NC 123NC 173V SS 24DQ1374NC 124NC 174V SS 25DQS175V SS 125V SS 175DQ5126DQM176V SS 126V SS 176DQ5527V SS 77DQS8127DQ32177DQ5628V SS 78DQM8128DQ36178DQ6029DQ1079NC 129DQ33179V CC 30DQ1480NC 130DQ37180V CC 31DQ1181V CC 131V CC 181DQ5732DQ1582V CC 132V CC 182DQ6133V CC 83NC 133DQS4183DQS734V CC 84NC 134DQM4184DQM735CK085NC 135DQ34185V SS 36V CC 86NC 136DQ38186V SS 37CK0#87V SS 137V SS 187DQ5838V SS 88V SS 138V SS 188DQ6239V SS 89NC 139DQ35189DQ5940V SS 90V SS 140DQ39190DQ6341DQ1691NC 141DQ40191V CC 42DQ2092V CC 142DQ44192V CC 43DQ1793V CC 143V CC 193SDA 44DQ2194V CC 144V CC 194SA045V CC 95CKE1145DQ41195SCL 46V CC 96CKE0146DQ45196SA147DQS297NC 147DQS5197V CCSPD 48DQM298NC 148DQM5198SA249DQ1899A12149V SS 199V CCID 50DQ22100A11150V SS200NCWhite Electronic Designs W3EG6466S-AD4-BD4PRELIMINARY FUNCTIONAL BLOCK DIAGRAMWhite Electronic DesignsW3EG6466S-AD4-BD4PRELIMINARYABSOLUTE MAXIMUM RATINGSParameterSymbol Value Units Voltage on any pin relative to V SS V IN , V OUT -0.5 to 3.6V Voltage on V CC supply relative to V SS V CC , V CCQ -1.0 to 3.6V Storage Temperature T STG -55 to +150°C Power Dissipation P D 16W Short Circuit CurrentI OS50mANote:Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.DC CHARACTERISTICS0°C ≤ T A ≤ 70°C, V CC = 2.5V ± 0.2VCAPACITANCET A = 25°C, f = 1MHz, V CC = 3.3V, V REF =1.4V ± 200mVParameter Symbol Min Max Unit Supply Voltage V CC 2.3 2.7V Supply Voltage V CCQ 2.3 2.7V Reference Voltage V REF V CCQ/2 - 50mV V CCQ/2 + 50mV V Termination Voltage V TT V REF - 0.04V REF + 0.04V Input High Voltage V IH V REF + 0.15V CCQ + 0.3V Input Low Voltage V IL -0.3V REF - 0.15V Output High Voltage V OH V TT + 0.76—V Output Low VoltageV OL—V TT - 0.76VParameterSymbol Max Unit Input Capacitance (A0-A12)C IN150pF Input Capacitance (RAS#, CAS#, WE#)C IN250pF Input Capacitance (CKE0, CKE1)C IN326pF Input Capacitance (CK0,CK0#)C IN4 5.5pF Input Capacitance (CS0#, CS1#)C IN526pF Input Capacitance (DQM0-DQM8)C IN613pF Input Capacitance (BA0-BA1)C IN750pF Data input/output capacitance (DQ0-DQ63)(DQS)C OUT13pFWhite Electronic Designs W3EG6466S-AD4-BD4PRELIMINARYI DD SPECIFICATIONS AND TEST CONDITIONS0°C ≤ T A ≤ 70°C, V CCQ = 2.5V ±0.2V, V CC = 2.5V ±0.2VDDR333@CL=2.5DDR266@CL=2, 2.5DDR200@CL=2 Parameter Symbol Conditions Max Max Max UnitsOperating Current I DD0One device bank; Active - Precharge;t RC=t RC(MIN); t CK=t CK(MIN); DQ,DM and DQSinputs changing once per clock cycle; Addressand control inputs changing once every twocycles.160014401360mAOperating Current I DD1One device bank; Active-Read-Precharge;Burst = 2; t RC=t RC(MIN);t CK=t CK(MIN); Iout =0mA; Address and control inputs changingonce per clock cycle.180016401560mAPrecharge Power-Down Standby Current I DD2PAll device banks idle; Power- down mode;t CK=t CK(MIN); CKE=(low)484848mAIdle Standby Current I DD2F CS# = High; All device banks idle;t CK=t CK(MIN); CKE = high; Address and othercontrol inputs changing once per clock cycle.Vin = Vref for DQ, DQS and DM.400320320mAActive Power-Down Standby Current I DD3POne device bank active; Power-down mode;t CK(MIN); CKE=(low)560480480mAActive Standby Current I DD3N CS# = High; CKE = High; One devicebank; Active-Precharge; t RC=t RAS(MAX);t CK=t CK(MIN); DQ, DM and DQS inputschanging twice per clock cycle; Address andother control inputs changing once per clockcycle.880720720mAOperating Current I DD4R Burst = 2; Reads; Continous burst; Onedevice bank active;Address and control inputschanging once per clock cycle; t CK=t CK(MIN);Iout = 0mA.216018401840mAOperating Current I DD4W Burst = 2; Writes; Continous burst; Onedevice bank active; Address and control inputschanging once per clock cycle; t CK=t CK(MIN);DQ,DM and DQS inputs changing twice perclock cycle.216018001800mAAuto Refresh Current I DD5t RC=t RC(MIN)224020002000mA Self Refresh Current I DD6CKE ≤ 0.2V484848mAOperating Current I DD7A Four bank interleaving Reads (BL=4) with autoprecharge with t RC=t RC (MIN); t CK=t CK(MIN);Address and control inputs change onlyduring Active Read or Write commands.312029602720mA* For DDR333 consult factoryWhite Electronic Designs W3EG6466S-AD4-BD4PRELIMINARYI DD1 : OPERATING CURRENT : ONE BANK1. Typical Case : V CC=2.5V, T=25°C2. Worst Case : V CC=2.7V, T=10°C3. Only one bank is accessed with t RC (min), BurstMode, Address and Control inputs on NOP edgeare changing once per clock cycle. I OUT = 0mA4. Timing Patterns :• DDR200 (100 MHz, CL=2) : t CK=10ns, CL2, BL=4, t RCD=2*t CK, t RAS=5*t CKRead : A0 N R0 N N P0 N A0 N - repeat thesame timing with random address changing;50% of data changing at every burst• DDR266 (133MHz, CL=2.5) : t CK=7.5ns,CL=2.5, BL=4, t RCD=3*t CK, t RC=9*t CK, t RAS=5*t CKRead : A0 N N R0 N P0 N N N A0 N - repeatthe same timing with random addresschanging; 50% of data changing at every burst • DDR266 (133MHz, CL=2) : t CK=7.5ns, CL=2, BL=4, t RCD=3*t CK, t RC=9*t CK, t RAS=5*t CKRead : A0 N N R0 N P0 N N N A0 N - repeatthe same timing with random addresschanging; 50% of data changing at every burst • DDR333 (166MHz, CL=2.5) : t CK=6ns, BL=4, t RCD=10*t CK, t RAS=7*t CKRead : A0 N N R0 N P0 N N N A0 N - repeatthe same timing with random addresschanging; 50% of data changing at every burst I DD7A : OPERATING CURRENT : FOUR BANKS1. Typical Case : V CC=2.5V, T=25°C2. Worst Case : V CC=2.7V, T=10°C3. Four banks are being interleaved with t RC (min),Burst Mode, Address and Control inputs on NOPedge are not changing. Iout=0mA4. Timing Patterns :• DDR200 (100 MHz, CL=2) : t CK=10ns, CL2, BL=4, t RRD=2*t CK, t RCD=3*t CK, Read withAutoprechargeRead : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0- repeat the same timing with random addresschanging; 100% of data changing at everyburst• DDR266 (133MHz, CL=2.5) : t CK=7.5ns,CL=2.5, BL=4, t RRD=3*t CK, t RCD=3*t CKRead with AutoprechargeRead : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 NA1 R0 - repeat the same timing with randomaddress changing; 100% of data changing atevery burst• DDR266 (133MHz, CL=2) : t CK=7.5ns, CL2=2, BL=4, t RRD=2*t CK, t RCD=2*t CKRead : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 NA1 R0 - repeat the same timing with randomaddress changing; 100% of data changing atevery burst• DDR333 (166MHz, CL=2.5) : t CK=6ns,BL=4, t RRD=3*t CK, t RCD=3*t CK, Read withAutoprechargeRead : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 NA1 R0 - repeat the same timing with randomaddress changing; 100% of data changing atevery burstDETAILED TEST CONDITIONS FOR DDR SDRAM I DD1 & I DD7ALegend : A = Activate, R = Read, W = Write, P = Precharge, N = NOPA (0-3) = Activate Bank 0-3R (0-3) = Read Bank 0-3White Electronic Designs W3EG6466S-AD4-BD4PRELIMINARYDDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED ACOPERATING CONDITIONSAC CHARACTERISTICS335262265/202UNITS NOTES PARAMETER SYMBOL MIN MAX MIN MAX MIN MAXAccess window of DQs from CK/CK#t AC-0.70+0.70-0.75+0.75-0.75+0.75nsCK high-level width t CH0.450.550.450.550.450.55t CK26 CK low-level width t CL0.450.550.450.550.450.55t CK26 Clock cycle time CL = 2.5t CK (2.5)6137.5137.513ns39, 44CL = 2t CK (2)7.5137.5137.5/1013ns39, 44 DQ and DM input hold time relative to DQS t DH0.450.50.5ns23, 27 DQ and DM input setup time relative to DQS t DS0.450.50.5ns23, 27 DQ and DM input pulse width (for each input)t DIPW 1.75 1.75 1.75ns27 Access window of DQS from CK/CK#t DQSCK-0.60+0.60-0.75+0.75-0.75+0.75nsDQS input high pulse width t DQSH0.350.350.35t CKDQS input low pulse width t DQSL0.350.350.35t CKDQS-DQ skew, DQS to last DQ valid, per group, per access t DQSQ0.40.50.5ns22, 23 Write command to ﬁ rst DQS latching transition t DQSS0.75 1.250.75 1.250.75 1.25t CKDQS falling edge to CK rising - setup time t DSS0.200.200.20t CKDQS falling edge from CK rising - hold time t DSH0.200.200.20t CKHalf clock period t HP t CH,t CL t CH,t CL t CH,t CL ns8 Data-out high-impedance window from CK/CK#t HZ+0.70+0.75+0.75ns16, 36 Data-out low-impedance window from CK/CK#t LZ-0.70-0.75-0.75ns16, 36 Address and control input hold time (fast slew rate)t IHF0.750.900.90ns12 Address and control input setup time (fast slew rate)t ISF0.750.90.900ns12 Address and control input hold time (slow slew rate)t IHS0.811ns12 Address and control input setup time (slow slew rate)t ISS0.811ns12 Address and Control input pulse width (for each input)t IPW 2.2 2.2 2.2nsLOAD MODE REGISTER command cycle time t MRD121515nsWhite Electronic Designs W3EG6466S-AD4-BD4PRELIMINARYDDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED ACOPERATING CONDITIONS (Continued)AC CHARACTERISTICS335262265/202UNITS NOTES PARAMETER SYMBOL MIN MAX MIN MAX MIN MAXDQ-DQS hold, DQS to ﬁ rst DQ to go non-valid, per access t QH t HP - t QHS t HP - t QHS t HP - t QHS ns22, 23 Data hold skew factor t QHS0.750.750.75nsACTIVE to PRECHARGE command t RAS4270,00040120,00040120,000ns31, 47 ACTIVE to READ with Auto precharge command t RAP151520nsACTIVE to ACTIVE/AUTO REFRESH command period t RC606065nsAUTO REFRESH command period t RFC727575ns42 ACTIVE to READ or WRITE delay t RCD151520ns PRECHARGE command period t RP151520nsDQS read preamble t RPRE0.9 1.10.9 1.10.9 1.1t CK37 DQS read postamble t RPST0.40.60.40.60.40.6t CK37 ACTIVE bank a to ACTIVE bank b command t RRD121515nsDQS write preamble t WPRE0.250.250.25t CKDQS write preamble setup time t WPRES000ns18, 19 DQS write postamble t WPST0.40.60.40.60.40.6t CK17 Write recovery time t WR151515nsInternal WRITE to READ command delay t WTR111t CKData valid output window NA t QH -t DQSQ t QH -t DQSQ t QH -t DQSQ ns22 REFRESH to REFRESH command interval t REFC70.370.370.3µs21 Average periodic refresh interval t REFI7.87.87.8µs21 Terminating voltage delay to VDD t VTD000nsExit SELF REFRESH to non-READ command t XSNR757575nsExit SELF REFRESH to READ command t XSRD200200200t CKWhite Electronic Designs W3EG6466S-AD4-BD4PRELIMINARY Notes1. All voltages referenced to V SS.2. Tests for AC timing, I DD, and electrical AC and DC characteristics may be conductedat nominal reference/supply voltage levels, but the related speciﬁ cations and device operation are guaranteed for the full voltage range speciﬁ ed.3. Outputs measured with equivalent load:Output(V OUT)4. AC timing and I DD tests may use a V IL-to-V IH swing of up to 1.5V in the testenvironment, but input timing is still referenced to V REF (or to the crossing point for CK/CK#), and parameter speciﬁ cations are guaranteed for the speciﬁ ed AC input levels under normal use conditions. The mini-mum slew rate for the input signals used to test the device is 1V/ns in the range between V IL(AC) and V IH(AC).5. The AC and DC input level speciﬁ cations are as deﬁ ned in the SSTL_2 Standard(i.e., the receiver will effectively switch as a result of the signal crossing the ACinput level, and will remain in that state as long as the signal does not ring backabove [below] the DC input LOW [HIGH] level).6. V REF is expected to equal V CCQ/2 of the transmitting device and to track variationsin the DC level of the same. Peak-to-peak noise (non-common mode) on V REF may not exceed ±2 percent of the DC value. Thus, from V CCQ/2, V REF is allowed ±25mV for DC error and an additional ±25mV for AC noise. This measurement is to betaken at the nearest V REF bypass capacitor.7. V TT is not applied directly to the device. V TT is a system supply for signal terminationresistors, is expected to be set equal to V REF and must track variations in the DC level of V REF.8. I DD is dependent on output loading and cycle rates. Speciﬁ ed values are obtainedwith mini-mum cycle time at CL = 2 for 262, 263, and 202, CL = 2.5 for 335 and 265 with the outputs open.9. Enables on-chip refresh and address counters.10. I DD speciﬁ cations are tested after the device is properly initialized, and is averagedat the deﬁ ned cycle rate.11. This parameter is sampled. V CC = +2.5V ±0.2V, V CCQ = +2.5V ±0.2V, V REF = V SS, f= 100 MHz, = 25°C, V OUT(DC) = V CCQ/2, V OUT (peak to peak) T A = 0.2V. DM input is grouped with I/O pins, reﬂ ecting the fact that they are matched in loading.12. For slew rates less than 1 V/ns and greater than or equal to 0.5 V/ns. If slew rateis less than 0.5 V/ns, timing must be derated: t IS has an additional 50ps per each 100mV/ns reduction in slew rate from 500mV/ns, while t IH is unaffected. If slew rate exceeds 4.5 V/ns, functionality is uncertain. For 335, slew rates must be ≥ 0.5 V/ns.13. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point atwhich CK and CK# cross; the input reference level for signals other than CK/CK# is V REF.14. Inputs are not recognized as valid until V REF stabilizes. Exception: during the periodbefore V REF stabilizes, CKE < 0.3 x V CCQ is recognized as LOW.15. The output timing reference level, as measured at the timing reference pointindicated in Note 3, is V TT.16. t HZ and t LZ transitions occur in the same access time windows as valid datatransitions. These parameters are not referenced to a speciﬁ c voltage level, butspecify when the device output is no longer driving (HZ) or begins driving (LZ).17. The intent of the Don’t Care state after completion of the postamble is the DQS-driven signal should either be high, low, or high-Z and that any signal transitionwithin the input switching region must follow valid input requirements. That is, ifDQS transitions high (above V IH DC (MIN) then it must not transition low (below V IH DC) prior to t DQSH (MIN).18. This is not a device limit. The device will operate with a negative value, but systemperformance could be degraded due to bus turnaround.19. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITEcommand. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on t DQSS.20. MIN (t RC or t RFC) for I DD measurements is the smallest multiple of t CK that meetsthe minimum absolute Value for the respective parameter. t RAS (MAX) for I DDmeasurements is the largest multiple of t CK that meets the maximum absolute value for t RAS.21. The refresh period 64ms. This equates to an aver-age refresh rate of 7.8125µs.However, an AUTO REFRESH command must be asserted at least once every70.3µs; burst refreshing or posting by the DRAM controller greater than eightrefresh cycles is not allowed.22. The valid data window is derived by achieving other speciﬁ cations: t HP (t CK/2), t DQSQ,and t QH (t QH = t HP - t QHS). The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55, beyond which functionality is uncertain. Figure 8, Derating Data Valid Window, shows derating curves for duty cycles ranging between 50/50 and 45/55.23. Each byte lane has a corresponding DQS.24. This limit is actually a nominal value and does not result in a fail value. CKE isHIGH during REFRESH command period (t RFC [MIN]) else CKE is LOW (i.e., during standby).25. To maintain a valid level, the transitioning edge of the input must:a. S ustain a constant slew rate from the current AC level through to the target AClevel, V IL(AC) or V IH(AC).b. R each at least the target AC level.After the AC target level is reached, continueto maintain at least the target DC level, V IL(DC) or V IH(DC).26. JEDEC speciﬁ es CK and CK# input slew rate must be ≥ 1V/ns (2V/ns differentially).27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent.If the DQ/ DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to t DS and t DH for each 100mv/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain. For 335, slew rates must be ≥ 0.5 V/ns.28. V CC must not vary more than 4 percent if CKE is not active while any bank is active.29. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to varyby the same amount.30. t HP min is the lesser of t CL minimum and t CH minimum actually applied to the deviceCK and CK# inputs, collectively during bank active.31. READs and WRITEs with auto precharge are not allowed to be issued untilt RAS(MIN) can be satisﬁ ed prior to the internal precharge command being issued. 32. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or2.9V, whichever is less. Any negative glitch must be less than 1/3 of the clock cycleand not exceed either -300mV or 2.2V, whichever is more positive.White Electronic Designs W3EG6466S-AD4-BD4PRELIMINARY33. The voltage levels used are derived from a mini-mum V CC level and the referencedtest load. In practice, the voltage levels obtained from a properly terminated bus will provide signiﬁ cantly different voltage values.34. V IH overshoot: V IH (MAX) = V CCQ + 1.5V for a pulse width ≤ 3ns and the pulse widthcan not be greater than 1/3 of the cycle rate. V IL undershoot: V IL (MIN) = -1.5V for a pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate.35. V CC and V CCQ must track each other.36. t HZ (MAX) will prevail over t DQSCK (MAX) + t RPST (MAX) condition. t LZ (MIN) willprevail over t DQSCK (MIN) + t RPRE (MAX) condition.37. t RPST end point and t RPRE begin point are not referenced to a speciﬁ c voltage levelbut specify when the device output is no longer driving (t RPST), or begins driving(t RPRE).38. During Initialization, V CCQ, V TT, and V REF must be equal to or less than V CC + 0.3V.Alternatively, V TT may be 1.35V maximum during power up, even if V CC/V CCQ are0.0V, provided a minimum of 42 0 of series resistance is used between the V TTsupply and the input pin.39. The current part operates below the slowest JEDEC operating frequency of 83MHz. As such, future die may not reﬂ ect this option.40. Random addressing changing and 50 percent of data changing at every transfer.41. Random addressing changing and 100 percent of data changing at every transfer.42. CKE must be active (high) during the entire time a refresh command is executed.That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tREF later.43. I DD2N speciﬁ es the DQ, DQS, and DM to be driven to a valid high or low logic level.I DD2Q is similar to I DD2F except I DD2Q speciﬁ es the address and control inputs toremain stable. Although I DD2F, I DD2N, and I DD2Q are similar, I DD2F is “worst case.”44. Whenever the operating frequency is altered, not including jitter, the DLL is requiredto be reset. This is followed by 200 clock cycles.45. Leakage number reﬂ ects the worst case leakage possible through the module pin,not what each memory device contributes.46. When an input signal is HIGH or LOW, it is deﬁ ned as a steady state logic HIGH orLOW.47. The 335 speed grade will operate with t RAS (MIN) = 40ns and t RAS (MAX) =120,000ns at any slower frequency.White Electronic DesignsW3EG6466S-AD4-BD4PRELIMINARYPACKAGE DIMENSIONS FOR AD4ORDERING INFORMATION FOR AD4Part Number SpeedHeight*W3EG6466S335AD4166MHz/333Mbps, CL=2.535.5 (1.38)W3EG6466S262AD4133MHz/266Mbps, CL=235.5 (1.38)W3EG6466S265AD4133MHz/266Mbps, CL=2.535.5 (1.38)W3EG6466S202AD4100MHz/200Mbps, CL=235.5 (1.38)NOTES:• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) • V endor speciﬁ c part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is tobe replaced with the respective vendors code. Consult factory for qualiﬁ ed sourcing options. (M = Micron, S = Samsung & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option* ALL DIMENSIONS ARE IN MILIMETERS AND (INCHES)White Electronic DesignsW3EG6466S-AD4-BD4PRELIMINARYPACKAGE DIMENSIONS FOR BD4ORDERING INFORMATION FOR BD4Part Number SpeedHeight*W3EG6466S335BD4166MHz/333Mbps, CL=2.531.75 (1.25)W3EG6466S262BD4133MHz/266Mbps, CL=231.75 (1.25)W3EG6466S265BD4133MHz/266Mbps, CL=2.531.75 (1.25)W3EG6466S202BD4100MHz/200Mbps, CL=231.75 (1.25)NOTES:• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) • V endor speciﬁ c part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is tobe replaced with the respective vendors code. Consult factory for qualiﬁ ed sourcing options. (M = Micron, S = Samsung & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option* ALL DIMENSIONS ARE IN MILIMETERS AND (INCHES)White Electronic Designs W3EG6466S-AD4-BD4PRELIMINARYDocument Title512MB – 64Mx64 DDR SDRAM UNBUFFERED, w/PLLRevision HistoryRev #History Release Date StatusRev A Created7-21-02Advanced8-04Preliminary Rev 00.1 Upated I DD specs.0.2 Added AD4 and BD4 package options0.3 Added document title page0.4 Removed "ED" from part number0.5 Moved from advanced to preliminary11-04Preliminary Rev 1 1.0 Upated I DD and CAP specs.1.1 Added AC specs1-05Preliminary Rev 2 2.1 Added lead-free and RoHS notes2.2 Added source control notes2.3 Added industrial temperature options。

配置

网卡瑞昱 RTL8168E PCI-E Gigabit Ethernet NIC / 华硕
100台
电脑型号 X86 兼容台式电脑
操作系统 Windows XP 专业版 32位 SP3 ( DirectX 9.0c )
处理器 AMD Athlon(速龙) II X4 640பைடு நூலகம்四核
主板华硕 M4A87T PLUS (ATI RX780/RX790(AMD 770/870) 芯片组)
50台
电脑型号 X86 兼容台式电脑
操作系统 Windows XP 专业版 32位 SP3 ( DirectX 9.0c )
处理器 AMD Athlon(速龙) II X4 640 四核
主板华硕 M4A87T PLUS (ATI RX780/RX790(AMD 770/870) 芯片组)
内存 2 GB ( 宇瞻 DDR2 800MHz )
显卡 Nvidia Geforce 9600 GT ( 512 MB / 七彩虹 )
显示器瀚视奇 HSD2275 Hanns.G HH241 ( 23.4 英寸 ) （钢化玻璃）
声卡瑞昱 ALC662 @ 英特尔 ICH10 高保真音频
网卡瑞昱 RTL8168E PCI-E Gigabit Ethernet NIC / 华硕
内存制造日期宇瞻 2011 年 10 月
主板制造日期华硕 2011 年 05 月 31 日
显卡制造日期镭风 2011 年 05 月 09 日
显示器制造日期 HannsG 2011 年 09 月
电脑型号精英 P43T-A2 台式电脑
操作系统 Windows XP 专业版 32位 SP3 ( DirectX 9.0c )

W78E58中文

W78E58B规格书8位微控制器目录:1.概述 (3)2.特性 (3)3.管脚配置 (4)4.管脚描述 (5)5.方块图 (7)6.功能描述 (8)6.1 RAM (8)6.2 定时器0，1，2 (8)6.3 时钟 (9)6.4 晶体振荡器 (9)6.5 外部时钟 (9)6.6 电源管理 (9)6.7 减少EMI辐射 (9)6.8 复位 (9)6.9 I/O口4 (11)6.10 INT2/INT3 (12)6.11 P4口基地址寄存器 (14)6.12 在线编程（ISP）模式 (15)6.13 在线编程控制寄存器（CHPCON） (17)6.14 F04KBOOT 模式（从LDROM启动） (18)7.保密位 (22)7.1 锁止位 (22)禁止 (22)7.2 MOVC7.3 加密 (22)8.电气特性 (23)8.1 绝对最大额定值 (23)8.2 DC特性 (23)出版日期: December 22, 20048.3 AC特性 (25)8.3.1时钟输入波形 (25)8.3.2程序读取周期 (26)8.3.3数据读取周期 (26)8.3.4数据写周期 (27)8.3.5端口访问周期 (27)9.时序波形图 (28)9.1 程序读取周期 (28)9.2 数据读周期 (28)9.3 数据写周期 (29)9.4 端口访问周期 (29)10.典型应用电路 (30)10.1 扩展的外部程序存储器和石英晶体 (30)10.2 扩展的外部程序存储器和振荡器 (31)11.封装尺寸 (32)11.1 DIP40 (32)11.2 44 管脚PLCC (33)11.3 44 管脚PQFP (34)12.应用指南 (35)12.1 ISP 软件编程示例： (35)13.文件版本描述 (42)1. 概述W78E58B是具有带ISP功能的Flash EPROM的低功耗8位微控制器；ISP功能的Flash EPROM可用于固件升级。

专业音频处理器 2X4 3X6 4X8（Dante 可选）使用说明书

使用说明书V1.2专业音频处理器2X4/3X6/4X8（Dante可选）目录第1章简介---------------------------------------------3第2章技术参数--------------------------------------------3第3章功能结构---------------------------------------------5第4章上位机软件简介----------------------------------------7第5章软件安装----------------------------------------------7第6章软件界面说明------------------------------------------9第7章功能界面介绍------------------------------------------14第1章简介DAP是数字音频处理的简称，DAP系列产品是一种可以实现多种DSP功能的专业音箱处理器，本系列产品集成压缩器、限幅器、分频器、延时器、均衡器、混音矩阵，可以通过精美直观的Mconsole软件快速地进行调试和监控，为专业音响扩音系统的构建和操作提供了广阔的操作空间。

D4表示配置了4路Dante 网络音频输入和输出接口的功能。

应用场合▲演艺厅▲体育场馆▲专业演出▲礼堂▲多功能厅▲会议系统功能特点▲96k24BIT采样率▲输入7段PEQ，输出7段PEQ，高低通滤波器▲全通滤波器AIIpass▲可配置Dante网络数字音频输入输出▲USB免驱自动连接软件，支持RS232中控控制，支持TCPIP有线和无线控制▲支持手机APP无线控制▲支持多台机器组网联调，远程监控第2章技术参数第3章功能结构前面板过载指示灯0dBu输入信号电平灯-24dBu输入信号电平灯输入编辑与静音灯限幅状态灯0dBu输出信号电平灯-24dBu输出信号电平灯输出编辑与静音灯后面板机器尺寸图上翻键下翻键菜单键回车键旁通键退出键频率Q 值增益输入：长按编辑/短按静音输出：长按编辑/短按静音USB （B 型）连接口液晶显示屏4通道卡侬母输入8通道卡侬公输出电源开关保险丝盒电源插座Dante 接口（可选）TCP/IP 控制网口RS232接口3.1LCD 显示屏功能菜单LCD菜单主界面1、设备名称：用户可以通过控制软件或下位机自定义修改名称。

SAMSUNG SDRAM 64Mb H-die (x4, x8, x16) 数据手册

现货库存、技术资料、百科信息、热点资讯，精彩尽在鼎好!SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAM 64Mb H-die SDRAM SpecificationRevision 1.8August 2004* Samsung Electronics reserves the right to change products or specification without notice.Rev. 1.8 August 2004SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAM Revision HistoryRevision 0.0 (May, 2003)- Target spec releaseRevision 0.1 (July, 2003)- Preliminary spec releaseRevision 0.2 (August, 2003)- Modified IBIS characteristic.Revision 1.0 (September, 2003)- Finalized.Revision 1.1 (September, 2003)- Corrected IBIS Specification.Revision 1.2 (October, 2003)- Deleted speed 7C at x4/x8.Revision 1.3 (October, 2003)- Deleted AC parameter notes 5.Revision 1.4 (November, 2003)- Modified Pin Function description.Revision 1.5 (February, 2004)- Corrected typo.Revision 1.6 (March, 2004)- Modified Pin Description.Revision 1.7 (May, 2004)- Added Note 5. sentense of tRDL parameter.Revision 1.8 (August, 2004)- Modified CLK cycle time(tcc) parameter in AC Characteristics.( If you want use of CL=2 not CL=3, the maximum operating frequency is 100MHz regardless of its speed bin.)Rev. 1.8 August 2004SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAMRev. 1.8 August 2004Part No.Orgainization Max Freq.InterfacePackageK4S640432H-TC(L)7516Mb x 4 133MHz(CL=3)LVTTL54pin TSOP(II)K4S640832H-TC(L)758Mb x 8133MHz(CL=3) K4S641632H-TC(L)604Mb x 16166MHz(CL=3) K4S641632H-TC(L)70143MHz(CL=3) K4S641632H-TC(L)75133MHz(CL=3)The K4S640432H / K4S640832H / K4S641632H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 4 bits, / 4 x 2,097,152 words by 8 bits, / 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG ′s high perfor-mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.• JEDEC standard 3.3V power supply• LVTTL compatible with multiplexed address • Four banks operation• MRS cycle with address key programs -. CAS latency (2 & 3)-. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)• All inputs are sampled at the positive going edge of the system clock • Burst read single-bit write operation• DQM (x4,x8) & L(U)DQM (x16) for masking • Auto & self refresh• 64ms refresh period (4K cycle)GENERAL DESCRIPTIONFEATURESOrdering Information4M x 4Bit x 4 / 2M x 8Bit x 4 / 1M x 16Bit x 4 Banks SDRAMRow & Column address configurationOrganizationRow Address Column Address16Mx4A0~A11A0-A98Mx8A0~A11A0-A84Mx16A0~A11A0-A7SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAM Package Physical Dimension54Pin TSOP(II) Package DimensionRev. 1.8 August 2004SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAMRev. 1.8 August 2004LWE LDQMDQiSamsung Electronics reserves the right to change products or specification without notice.*SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAMRev. 1.8 August 2004123456789101112131415161718192021222324252627545352515049484746454443424140393837363534333231302928PIN CONFIGURATION (Top view)54Pin TSOP (II)(400mil x 875mil)(0.8 mm Pin pitch)PIN FUNCTION DESCRIPTIONPin NameInput FunctionCLK System clock Active on the positive going edge to sample all inputs.CSChip selectDisables or enables device operation by masking or enabling all inputs except CLK, CKE and DQMCKE Clock enableMasks system clock to freeze operation from the next clock cycle.CKE should be enabled at least one cycle prior to new command.Disable input buffers for power down in standby.A 0 ~ A 11AddressRow/column addresses are multiplexed on the same pins.Row address : RA 0 ~ RA 11,Column address : (x4 : CA 0 ~ CA 9, x8 : CA 0 ~ CA 8 , x16 : CA 0 ~ CA 7)BA 0 ~ BA 1Bank select address Selects bank to be activated during row address latch time.Selects bank for read/write during column address latch time.RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low.Enables row access & precharge.CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low.Enables column access.WE Write enableEnables write operation and row tches data in starting from CAS, WE active.DQM Data input/output mask Makes data output Hi-Z, t SHZ after the clock and masks the output.Blocks data input when DQM active.DQ 0 ~ N Data input/output Data inputs/outputs are multiplexed on the same pins.(x4 : DQ 0 ~ 3), (x8 : DQ 0 ~ 7), (x16 : DQ 0 ~ 15)V DD /V SS Power supply/ground Power and ground for the input buffers and the core logic.V DDQ /V SSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise immunity.N.C/RFUNo connection/reserved for future useThis pin is recommended to be left No Connection on the device.x16x8x4x16x8x4V DD DQ0V DDQ DQ1DQ2V SSQ DQ3DQ4V DDQ DQ5DQ6V SSQ DQ7V DD LDQM WE CAS RAS CS BA0BA1A10/AP A0A1A2A3V DD V SS DQ15V SSQ DQ14DQ13V DDQ DQ12DQ11V SSQ DQ10DQ9V DDQ DQ8V SSN.C/RFU UDQM CLK CKE N.C A11A9A8A7A6A5A4V SSV DDN.C V DDQ N.C DQ0V SSQ N.C N.C V DDQ N.C DQ1V SSQ N.C V DD N.C WE CAS RAS CS BA0BA1A10/APA0A1A2A3V DDV SS N.C V SSQ N.C DQ3V DDQ N.C N.C V SSQ N.C DQ2V DDQ N.C V SSN.C/RFU DQM CLK CKE N.C A11A9A8A7A6A5A4V SSV DD DQ0V DDQ N.C DQ1V SSQ N.C DQ2V DDQ N.C DQ3V SSQ N.C V DD N.C WE CAS RAS CS BA0BA1A10/AP A0A1A2A3V DD V SS DQ7V SSQ N.C DQ6V DDQ N.C DQ5V SSQ N.C DQ4V DDQ N.C V SSN.C/RFU DQM CLK CKE N.C A11A9A8A7A6A5A4V SSSDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAMRev. 1.8 August 2004ABSOLUTE MAXIMUM RATINGSParameter Symbol Value Unit Voltage on any pin relative to V SS V IN , V OUT -1.0 ~ 4.6V Voltage on V DD supply relative to V SS V DD , V DDQ-1.0 ~ 4.6V Storage temperature T STG -55 ~ +150°C Power dissipation P D 1W Short circuit currentI OS50mAPermanent device damage may occur if "ASOLUTE MAXIMUM RATINGS" are exceeded.Functional operation should be restricted to recommended operating condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.Note :DC OPERATING CONDITIONSRecommended operating conditions (Voltage referenced to V SS = 0V, T A = 0 to 70°C)Parameter Symbol Min Typ Max Unit NoteSupply voltage V DD , V DDQ3.0 3.3 3.6V Input logic high voltage V IH 2.0 3.0V DD +0.3V 1Input logic low voltage V IL -0.300.8V 2Output logic high voltage V OH 2.4--V I OH = -2mA Output logic low voltage V OL --0.4V I OL = 2mAInput leakage currentI LI-10-10uA31. V IH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns.2. V IL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.3. Any input 0V ≤ V IN ≤ V DDQ .Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.Notes :CAPACITANCE (V DD = 3.3V, T A = 23°C, f = 1MHz, V REF =1.4V ± 200 mV)PinSymbol Min Max Unit Note ClockC CLK 2.5 4.0pF 1RAS, CAS, WE, CS, CKE, DQM C IN 2.5 5.0pF 2AddressC ADD 2.5 5.0pF 2(x4 : DQ0 ~ DQ3), (x8 : DQ0 ~ DQ7), (x16 : DQ0 ~DQ15)C OUT4.06.5pF3SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAMRev. 1.8 August 20041. Measured with outputs open.2. Refresh period is 64ms.3. K4S6404(08)32H-TC4. K4S6404(08)32H-TL5. Unless otherwise noted, input swing IeveI is CMOS(V IH /V IL =V DDQ /V SSQ)Notes :(Recommended operating condition unless otherwise noted, T A = 0 to 70°C for x4, x8)ParameterSymbolTest ConditionVersion Unit Note75Operating current (One bank active)I CC1 Burst length = 1 t RC ≥ t RC (min) I O = 0 mA75mA 1Precharge standby current in power-down modeI CC2P CKE ≤ V IL (max), t CC = 10ns 1mAI CC2PS CKE & CLK ≤ V IL (max), t CC = ∞1Precharge standby current in non power-down mode I CC2NCKE ≥ V IH (min), CS ≥ V IH (min), t CC = 10nsInput signals are changed one time during 20ns15mAI CC2NSCKE ≥ V IH (min), CLK ≤ V IL (max), t CC = ∞Input signals are stable 6Active standby current in power-down mode I CC3P CKE ≤ V IL (max), t CC = 10ns 3mAI CC3PS CKE & CLK ≤ V IL (max), t CC = ∞3Active standby current in non power-down mode (One bank active)I CC3NCKE ≥ V IH (min), CS ≥ V IH (min), t CC = 10nsInput signals are changed one time during 20ns30mAI CC3NSCKE ≥ V IH (min), CLK ≤ V IL (max), t CC = ∞Input signals are stable 25Operating current (Burst mode)I CC4 I O = 0 mA Page burst4Banks Activated t CCD = 2CLKs 115mA 1Refresh current I CC5t RC ≥ t RC (min)135mA 2Self refresh currentI CC6CKE ≤ 0.2VC 1mA 3L400uA4DC CHARACTERISTICS (x4, x8)SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAMRev. 1.8 August 20041. Measured with outputs open.2. Refresh period is 64ms.3. K4S641632H-TC4. K4S641632H-TL5. Unless otherwise noted, input swing IeveI is CMOS(V IH /V IL =V DDQ /V SSQ)Notes :DC CHARACTERISTICS (x16)(Recommended operating condition unless otherwise noted, T A = 0 to 70°C for x16 only)ParameterSymbolTest ConditionVersionUnit Note607075Operating current (One bank active)I CC1 Burst length = 1 t RC ≥ t RC (min) I O = 0 mA140115110mA 1Precharge standby current in power-down modeI CC2P CKE ≤ V IL (max), t CC = 10ns 1mAI CC2PS CKE & CLK ≤ V IL (max), t CC = ∞1Precharge standby current in non power-down mode I CC2NCKE ≥ V IH (min), CS ≥ V IH (min), t CC = 10nsInput signals are changed one time during 20ns15mAI CC2NSCKE ≥ V IH (min), CLK ≤ V IL (max), t CC = ∞Input signals are stable 6Active standby current in power-down mode I CC3P CKE ≤ V IL (max), t CC = 10ns 3mAI CC3PS CKE & CLK ≤ V IL (max), t CC = ∞3Active standby current in non power-down mode (One bank active)I CC3NCKE ≥ V IH (min), CS ≥ V IH (min), t CC = 10nsInput signals are changed one time during 20ns30mAI CC3NSCKE ≥ V IH (min), CLK ≤ V IL (max), t CC = ∞Input signals are stable 25Operating current (Burst mode)I CC4 I O = 0 mA Page burst4Banks Activated t CCD = 2CLKs 160140135mA 1Refresh current I CC5t RC ≥ t RC (min)160140135mA 2Self refresh currentI CC6CKE ≤ 0.2VC 1mA 3L400uA4SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAMRev. 1.8 August 2004AC OPERATING TEST CONDITIONS (V DD = 3.3V ± 0.3V, T A = 0 to 70°C)Parameter Value Unit AC input levels (Vih/Vil)2.4/0.4V Input timing measurement reference level 1.4V Input rise and fall timetr/tf = 1/1ns Output timing measurement reference level 1.4VOutput load conditionSee Fig. 23.3V1200Ω870ΩOutput30pFV OH (DC) = 2.4V, I OH = -2mA V OL (DC) = 0.4V, I OL = 2mAVtt = 1.4V50ΩOutput30pFZ0 = 50Ω(Fig. 2) AC output load circuit(Fig. 1) DC output load circuit Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle timeand then rounding off to the next higher integer.2. Minimum delay is required to complete write.3. All parts allow every cycle column address change.4. In case of row precharge interrupt, auto precharge and read burst stop.5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP .OPERATING AC PARAMETER(AC operating conditions unless otherwise noted)ParameterSymbol VersionUnit Note 607075Row active to row active delay t RRD (min)121415ns 1RAS to CAS delay t RCD (min)182020ns 1Row precharge time t RP (min)182020ns 1Row active time t RAS (min)424945ns 1t RAS (max)100us Row cycle timet RC (min)606865ns 1Last data in to row precharge t RDL (min)2CLK 2,5Last data in to Active delayt DAL (min) 2 CLK + tRP-5Last data in to new col. address delay t CDL (min)1CLK 2Last data in to burst stopt BDL (min)1CLK 2Col. address to col. address delay t CCD (min)1CLK 3Number of valid output dataCAS latency = 32ea4CAS latency = 21SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAMRev. 1.8 August 20041. Parameters depend on programmed CAS latency.2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.3. Assumed input rise and fall time (tr & tf) = 1ns.If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.Notes :DQ BUFFER OUTPUT DRIVE CHARACTERISTICSParameterSymbol Condition Min TypMax Unit Notes Output rise time trh Measure in linear region : 1.2V ~ 1.8V 1.37 4.37Volts/ns 3 Output fall time tfh Measure in linear region : 1.2V ~ 1.8V 1.30 3.8Volts/ns 3 Output rise time trh Measure in linear region : 1.2V ~ 1.8V 2.8 3.9 5.6Volts/ns 1,2 Output fall timetfhMeasure in linear region : 1.2V ~ 1.8V2.02.9 5.0Volts/ns1,21. Rise time specification based on 0pF + 50 Ω to V SS , use these values to design to.2. Fall time specification based on 0pF + 50 Ω to V DD , use these values to design to.3. Measured into 50pF only, use these values to characterize to.4. All measurements done with respect to V SS .Notes :AC CHARACTERISTICS (AC operating conditions unless otherwise noted)ParameterSymbol607075Unit NoteMin Max Min Max Min Max CLK cycle timeCAS latency=3t CC 61000710007.51000ns 1CAS latency=2101010CLK to validoutput delay CAS latency=3t SAC -5-6- 5.4ns 1,2CAS latency=2-6-6-6Output data hold timeCAS latency=3t OH 2.5-3-3-ns 2CAS latency=23-3-3-CLK high pulse width t CH 2.5-3- 2.5-ns 3CLK low pulse width t CL 2.5-3- 2.5-ns 3Input setup time t SS 1.5-2- 1.5-ns 3Input hold time t SH 1-1-0.8-ns 3CLK to output in Low-Z t SLZ1-1-1-ns 2CLK to outputin Hi-ZCAS latency=3t SHZ-5-6- 5.4nsCAS latency=2-6-6-6SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAMRev. 1.8 August 2004I OH Characteristics (Pull-up)Voltage 133MHz Min 133MHz Max (V)I (mA)I (mA)3.45- -1.683.30- -19.113.00-0.35 -51.872.70-3.75-90.442.50-6.65-107.311.95-13.75-137.91.80-17.75-158.341.65-20.55-173.61.50-23.55-188.791.40-26.2-199.011.00-36.25-241.150.20-46.5-351.68IBIS SPECIFICATIONI OL Characteristics (Pull-down)Voltage 133MHz Min 133MHz Max (V)I (mA)I (mA)3.4543.92155.823.30--3.0043.36153.721.9541.20148.401.8040.56146.021.6539.60141.751.5038.40136.081.4037.28131.391.0030.08105.840.8526.6493.660.6521.5275.250.4014.1649.140-100-200-300-400-500-600030.511.522.53.5Voltagem A250200150100500030.511.522.53.5Voltagem A133MHz Pull-up133MHz Pull-downI OH Min (133MHz)I OH Max (133MHz)I OL Min (133MHz)I OL Max (133MHz)SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAMRev. 1.8 August 2004V DD Clamp @ CLK, CKE, CS, DQM & DQV DD (V)I (mA)0.00.00.20.00.40.00.60.00.70.00.80.00.90.01.0 0.231.2 1.341.4 3.021.6 5.061.8 7.352.0 9.832.212.482.415.302.618.31V SS Clamp @ CLK, CKE, CS, DQM & DQV SS (V)I (mA)-2.6-57.23-2.4-45.77-2.2-38.26-2.0-31.22-1.8-24.58-1.6-18.37-1.4-12.56-1.2 -7.57-1.0 -3.37-0.9 -1.75-0.8 -0.58-0.7 -0.05-0.6 0.0-0.4 0.0-0.2 0.0 0.00.0201510500312Voltagem AI (mA)Voltagem AI (mA)Minimum V DD clamp current(Referenced to V DD )Minimum V SS clamp current0-10-20-30-40-30-2-1-50-60SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAMRev. 1.8 August 2004SIMPLIFIED TRUTH TABLE (V=Valid, X=Don ′t care, H=Logic high, L=Logic low)CommandCKEn-1CKEnCSRASCASWEDQMBA 0,1A 10/APA 11,A 9 ~ A 0NoteRegisterMode register set H X L L L L X OP code1,2RefreshAuto refreshH H L L L H X X 3Self refreshEntry L 3ExitL H L H H H X X3H X X X 3Bank active & row addr.H X L L H H X V Row address Read &column address Auto precharge disable H X L H L H X V L Column address 4Auto precharge enable H 4,5Write &column address Auto precharge disable H X L H L L X VL Column address4Auto precharge enableH 4,5Burst stop HX L H H L X X 6Precharge Bank selection H X L L H L X V L XAll banksX H Clock suspend or active power downEntry H L H X X X X XL V V V Exit L H X X X X X Precharge power down modeEntryH L H X X X XXL H H H ExitL HH X X X X L V V V DQMH X V X 7No operation commandHXH X X X XXLHHH1. OP Code : Operand codeA 0 ~ A 11 & BA 0 ~ BA 1 : Program keys. (@ MRS)2. MRS can be issued only at all banks precharge state.A new command can be issued after 2 CLK cycles of MRS.3. Auto refresh functions are as same as CBR refresh of DRAM.The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state.4. BA 0 ~ BA 1 : Bank select addresses.If both BA 0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected.If both BA 0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank B is selected. If both BA 0 is "High" and BA 1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA 0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected. If A 10/AP is "High" at row precharge, BA 0 and BA 1 is ignored and all banks are selected.5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst.New row active of the associated bank can be issued at t RP after the end of burst.6. Burst stop command is valid at every burst length.7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)Notes :。

John Deere 第 4 代显示器兼容性说明书

第 4 代显示器兼容性这是通过软件更新至 19-1 版本所允准的兼容设备，并且可能随着较新的软件更新而更改。

为保证完整性和相应的兼容性，应使用最新版本的机具控制单元软件、第 4 代显示器软件或兼容的农场管理信息软件 (FMIS)。

非当前软件版本将需要更新才能提供支持。

未经批准的软件版本配置将不予支持。

软件更新 19-1 版本仅兼容于 4600 CommandCenter™ v2 处理器。

软件更新 17-2 是与 4600 v1 处理器兼容的最新版本。

服务器序列号如下：v1 = RWG 前缀v2 = PCG 前缀机器兼容性John Deere 大型农用拖拉机John Deere 大型农用拖拉机（包含所有自动检测到的机器的清单）型号年份CommandCenter™ 显示器通用显示器4600 v24200464042409R/9RT/9RX 系列2018 年型及更新型号X---X X9R/9RT/9RX 系列2015 年 - 2017 年*---X X 9R/9RT2012 年 - 2014 年------X X9030/9030T 系列2008 年型 - 更新型号------X X8R/8RT 系列2018 年型 - 更新型号X---X X8R/8RT 系列2014 年中期 - 2017年*---X X8R/8RT 系列2010 年 - 2013 年------X X8030/8030T 系列2006 年型及更新型号------X X7R 系列2018 年型及更新型号X X X X7R 系列2014 年 - 2017 年*---X X 7R 系列2012 年 - 2013 年------X X7J 系列2018 年型及更新型号------X X7030 系列2007 年型及更新型号------X X7030 系列（大型机架）2007 年型及更新型号------X X6030 和 7030 系列（小机架）2006 年型及更新型号------X X6R 系列2018 年型及更新型号X X X X6R 系列2015 年 - 2017 年*---X X6M 系列2013 年型及更新型号------X X6J 系列2018 年型及更新型号------X X5R 系列2019 年型及更新型号------X X*注意：为获得最新精准农业功能，请将出厂配备的机器从 v1 处理器更新为 v2。

布德电子产品说明书

17Use on Bud Cabinet Racks: Series 60, Series 2000, ValuRack, Classic II and Economizer. 12 Gauge Steel. Sold in pairs. Rail mounting hardware included. (Uses #7346 equipment mounting screws - order separately.) Finish: BlackMounting RailsChassisSupport BracketsAttaches to panel mounting rail accessory flange, heavy duty 14 ga. steel. Finish: Black. Sold in pairs. Requires two pairs of panel mounting rails per cabinet rack.Catalog No.Length Weight (Lbs.)Cable Management Bracket SetsHeavy gauge steel bracket mounts in any direction with one screw mounting. Package contains six brackets, six 12˝ Velcro cable straps and all mounting hardware. Management panels occupy 1U (1.75˝)of panel space height, and are available for both 19˝ and 23˝ panel widths. Comes complete with 8˝ Velcro cable straps and all mounting hardware. 1.70˝LengthAdapter Bracketchassis support brackets for use on open rack. Package Catalog No.Est. Weight (Lbs.)Catalog No.Style Size (W × L)Wt. Oz.CMS-2218-BB.75˝ × 18.00˝4.6CableManagement StrapsVelcro cable straps in two styles. Comes in packages of 25 straps. Color: BlackStyle AStyle BCatalog No.18Panel ExtenderHeavy gauge steel brackets extend panels 5.00˝ beyond normal panel mounting rails. Panel mounting holes on EIAuniversal spacing. Finish: Black. Sold in pairs. Includes all mounting hardware.racks. Heavy gauge steel Available in Black. Includes all Cable BracketHeavy gauge steel brackets occupy 1U (1.75˝) of panel space. Finish: Black. Includes all mounting hardware.Cable Management Designed for 19˝ panel width racks. Heavy 18 gauge formed steelpanel, with twelve plastic cable clips. Finish: Black. Includes all mounting hardware. Accessories: Additional plastic cable clips catalog No. CM-1229. Twelve clips per package.Cable Management PanelDesigned for 19˝ panel width racks. Heavy 18 gauge formed steel panel withtwenty-four plastic cable clips and three CM-1220 cable rings. Finish: Black. Includes all mounting hardware. Accessories: Additional plastic cable clips catalog No. CM-1229. Twelve clips per package.Cableway CoverFormed steel covers mount to the front and rear of cableway rings to protect cables and present afinished look to your cabling installation. Finish: Black. Used on 7’ tall open racks. Sold in pairs. Includes all mounting hardware.Equipment Tie Down BracketHeavy gauge steel bracket, in 19˝ panel width, will secure your equipment within open or enclosed cabinet racks. Frontpanels are 1U (1.75˝) high.Black Texture (BT) or Metallic Gray (MG) Includes all mounting hardware.Catalog No.Panel HeightEst. Weight Lbs.PE-1600 3.50˝1Catalog No.Size (W × D)Est. Weight Lbs.Catalog No.Size (W × D)Est. Weight Lbs.Catalog No.Size (H × W)Est. Weight Lbs.CM-12273.50˝ × 19.00˝3Catalog No.Size (W × D)Est. Weight Lbs.CM-12231.75˝ × 3.50˝1See our online rack and accessory selector guide at /rackguide.htmlCable ManagementSnap-in spring steel cableclips available in two sizes.In packages of 3 clips.AdapterMountingBrackets16-gauge steelbrackets used formounting 19˝ wideequipment into open rackswith 23˝ and 24˝ wide panel spaces and enclosed cabinet rackswith 24˝ wide panel spaces. Mounting hole locations conform to EIAspecs. Finish is Black Texture (BT). Comes complete with all mountingAllows for the organizationand protection of cables onslide-mounted equipment.Mounts to panel mountingrail at rear of cabinet rack,and can be used on both theleft and right sides of thecabinet. Wide support arms allow for the use of either ribbon cableStationaryKeyboard/MouseShelfHeavy gauge steel shelfmounts to any 19˝ panelwidth open rack. Comeswith 9.00˝ × 7.00˝ mousetray that can be bolted on to either the left or right hand side of theshelf. Takes up 1U (1.75˝) of panel space. Finish: Black Texture (BT) orMetallic Gray (MG). Includes all mounting hardware.gauge steel shelf mountsto any 19˝ or 23˝ panelwidth open rack. Includes4.00˝ high × 10.50˝ wideintegrated switch box compartment.Finish: BlackTexture (BT) or Metallic Gray (MG). Includes allmounting hardware.Sliding Keyboard/Mouse ShelfSliding keyboard shelf fits19˝ and 23˝ panel widthracks. Mouse pad slides outfrom underneath the shelf ineither the right or left side.Takes up 2U (3.50˝) of panel space. Overalldepth: 12.50˝. Black Texture (BT) orMetallic Gray (MG). Includes all mounting hardware.Catalog No.Size (W × D)Weight Lbs.CM-2220.56˝ × 3.75˝.5See our online rack andaccessory selector guide at/rackguide.html19。

三星 GPRS 移动电话 SGH-D488 说明书

World Wide Web * 本手册中的一些内容可能与手机不同，取决于安装的软件或服务提供商。

Printed in China Code No.: GH68-05995A Chinese. 03/2005. Rev. 1.1无线电发射型号核准证：2004CP1411 (CMII ID)入网许可证号码：02-5827-042446GPRS移动电话SGH-D488用户手册目录安全措施 (7)配件介绍 (9)您的手机 (10)手机部位图 (10)显示屏 (14)外置显示屏 (17)服务指示灯 (18)照相机 (18)内置天线 (19)开始使用 (20)安装/取出SIM卡 (20)安装/取下电池/电池充电 (21)开机和关机 (25)选择功能和选项 (26)基本功能 (28)拨打电话 (28)结束通话 (30)接听来电 (30)拒绝接听 (31)调节音量 (31)通话中访问选项 (32)使用耳机 (40)输入文本 (41)改变文本输入法 (42)使用手写板 (43)智能拼音输入法 (44)中文笔画输入法 (45)智能英文输入法 (48)基本英文输入法 (50)数字输入法 (51)特殊符号输入法 (51)使用功能表 (52)访问功能表 (52)功能表 (53)3目录4电话簿功能表................................................ 59查找 (电话簿 1.1 )................................................ 59增加记录 (电话簿 1.2 )......................................... 61分组查找 (电话簿 1.3 )......................................... 63快速拨号 (电话簿 1.4 )......................................... 63全部复制到话机 (电话簿 1.5 ).............................. 65由红外线发送全部 (电话簿 1.6 )........................... 65全部删除 (电话簿 1.7 )......................................... 67本机号码 (电话簿 2.1 )......................................... 68分组设定 (电话簿 2.2 )......................................... 69存储器状态 (电话簿 2.3 )..................................... 69服务目录 (电话簿 3.1 ).. (70)SIM-AT （SIM 应用工具箱） (71)通话记录....................................................... 72未接来电 (功能 2.1 )............................................ 72已接来电 (功能 2.2 )............................................ 72已拨电话 (功能 2.3 )............................................ 73全部删除 (功能 2.4 )............................................ 73通话时间 (功能 2.5 )............................................ 74通话费用 (功能 2.6 ).. (74)网络服务....................................................... 76呼叫转移 (功能 3.1 )............................................ 76呼叫限制 (功能 3.2 )............................................ 77呼叫等待 (功能 3.3 )............................................ 79网络选择 (功能 3.4 )............................................ 80主叫号码 (功能 3.5 )............................................ 81线路选择 (功能 3.6 ).. (81)声音设定....................................................... 82来电 (功能 4.1 )................................................... 82信息 (功能 4.2 )................................................... 83开/关机 (功能 4.3 )............................................ 83连接指示音 (功能 4.4 )........................................ 84按键音 (功能 4.5 )............................................... 84分钟提示音 (功能 4.6 )........................................ 84安静模式 (功能 4.7 )............................................ 85翻盖铃声 (功能 4.8 )............................................ 85整点报时 (功能 4.9 )............................................ 85通话中提示 (功能 4.10 ) (86)目录5信息............................................................... 87短信息 (功能 5.1 )............................................... 87多媒体信息 (功能 5.2 )........................................ 93WAP 短信 (功能 5.3 )........................................ 103预置信息清单 (功能 5.4 ).................................. 103语音信箱 (功能 5.5 ).......................................... 104小区信息 (功能 5.6 ).......................................... 105设定 (功能 5.7 )................................................. 106存储器状态 (功能 5.8 )...................................... 109娱乐功能..................................................... 110WAP 浏览器 (功能 6.1 )..................................... 110三星乐园 (功能 6.2 ).......................................... 115图铃宝盒 (功能 6.3 ).......................................... 116JAVA 世界 (功能 6.4 )....................................... 119管理目录..................................................... 123新备忘录 (功能 7.1 ).......................................... 123日历 (功能 7.2 )................................................. 125记事本 (功能 7.3 )............................................. 127时钟 (功能 7.4 )................................................. 128闹钟 (功能 7.5 )................................................. 129计算器 (功能 7.6 )............................................. 131换算 (功能 7.7 )................................................. 132定时器 (功能 7.8 )............................................. 133秒表 (功能 7.9 )................................................. 134字典 (功能 7.10 )............................................... 135照相机......................................................... 136拍照 (功能 8.1 )................................................. 136我的相片 (功能 8.2 ).......................................... 141我的相册 (功能 8.3 ).......................................... 141全部删除 (功能 8.4 ).......................................... 141批量删除 (功能 8.5 ).......................................... 142设定 (功能 8.6 )................................................. 142存储器状态 (功能 8.7 )...................................... 143话机设定..................................................... 144显示屏设定 (功能 9.1 )...................................... 144问候语 (功能 9.2 )............................................. 145语言 (功能 9.3 ). (146)目录6保密设定 (功能 9.4 ).......................................... 146自动重拨 (功能 9.5 ).......................................... 149清晰话音 (功能 9.6 ).......................................... 149翻盖接听 (功能 9.7 ).......................................... 149任意键应答 (功能 9.8 )...................................... 150侧键 (功能 9.9 )................................................. 150红外线启动 (功能 9.10)..................................... 150出厂设置 (功能 9.11 )........................................ 151ALS （线路选择）....................................... 152疑难解答..................................................... 153访问密码..................................................... 156话机密码......................................................... 156PIN 码............................................................. 156PIN2码........................................................... 156PUK 码........................................................... 157PUK2码......................................................... 157呼叫限制密码.................................................. 157健康和安全信息........................................... 158电池安全......................................................... 158使用电池的注意事项....................................... 159交通安全......................................................... 160使用环境......................................................... 160电子设备......................................................... 160可能发生危险的环境....................................... 162紧急呼叫......................................................... 162其它重要安全信息.......................................... 163保养和维护..................................................... 164术语解释..................................................... 165快速指南.. (169)安全措施使用无线移动话机前请仔细阅读以下注意事项。

MEMORY存储芯片TMS320C6414TBGLZ8中文规格书

TMS320C6414, TMS320C6415, TMS320C6416FIXED-POINT DIGITAL SIGNAL PROCESSORSSPRS146N − FEBRUARY 2001 − REVISED MAY 2005DEVICE CONFIGURATIONS (CONTINUED)Table 27. PCI_EN and MCBSP2_EN Peripheral Selection (HPI, GP[15:9], PCI, and McBSP2) PERIPHERAL SELECTION†PERIPHERALS SELECTEDPCI_EN Pin [AA4]MCBSP2_ENPin [AF3]HPI GP[15:9]PCIEEPROM(Internal to PCI)McBSP200√√√01√√√10√√‡11√√†The PCI_EN pin must be driven valid at all times and the user must not switch values throughout device operation.The MCBSP2_EN pin must be driven valid at all times and the user can switch values throughout device operation.‡The only time McBSP2 is disabled is when both PCI_EN = 1 and MCBSP2_EN = 0. This configuration enables, at reset, the auto-initialization of the PCI peripheral through the PCI internal EEPROM [provided the PCI EEPROM Auto-Initialization pin (BEA13) is pulled up (EEAI = 1)]. The user can then enable the McBSP2 peripheral (disabling EEPROM) by dynamically changing MCBSP2_EN to a “1” after the device is initialized (out of reset).−If the PCI is disabled (PCI_EN = 0), the HPI peripheral is enabled and GP[15:9] pins can be programmed as GPIO, provided the GPxEN and GPxDIR bits are properly configured.This means all multiplexed HPI/PCI pins function as HPI and all standalone PCI pins (PCBE0 andXSP_CS) are tied-off (Hi-Z). Also, the multiplexed GPIO/PCI pins can be used as GPIO with theproper software configuration of the GPIO enable and direction registers (for more details, seeTable 29).−If the PCI is enabled (PCI_EN = 1), the HPI peripheral is disabled.This means all multiplexed HPI/PCI pins function as PCI. Also, the multiplexed GPIO/PCI pins functionas PCI pins (for more details, see Table 29).−The MCBSP2_EN pin, in combination with the PCI_EN pin, controls the selection of the McBSP2 peripheral and the PCI internal EEPROM (for more details, see Table 27 and its footnotes).other device configurationsTable 28 describes the C6414, C6415, and C6416 devices configuration pins, which are set up via external pullup/pulldown resistors through the specified EMIFB address bus pins (BEA[20:13, 11, 9:7]) and the HD5 pin.For more details on these device configuration pins, see the Terminal Functions table and the Debugging Considerations section.TMS320C6414, TMS320C6415, TMS320C6416FIXED-POINT DIGITAL SIGNAL PROCESSORSSPRS146N − FEBRUARY 2001 − REVISED MAY 2005DEVICE CONFIGURATIONS (CONTINUED)Table 28. Device Configuration Pins (BEA[20:13, 9:7], HD5, and BEA11)CONFIGURATIONPIN NO.FUNCTIONAL DESCRIPTIONBEA20E16Device Endian mode (LEND)0–System operates in Big Endian mode1−System operates in Little Endian mode (default)BEA[19:18][D18,C18]Bootmode [1:0]00–No boot01−HPI boot10−EMIFB 8-bit ROM boot with default timings (default mode)11−ReservedBEA[17:16][B18,A18]EMIFA input clock selectClock mode select for EMIFA (AECLKIN_SEL[1:0])00–AECLKIN (default mode)01−CPU/4 Clock Rate10−CPU/6 Clock Rate11−ReservedBEA[15:14][D17,C17]EMIFB input clock selectClock mode select for EMIFB (BECLKIN_SEL[1:0])00–BECLKIN (default mode)01−CPU/4 Clock Rate10−CPU/6 Clock Rate11−ReservedBEA13B17PCI EEPROM Auto-Initialization (EEAI) [C6415 and C6416 devices only][The C6414 device does not support the PCI peripheral; for proper device operation, do not oppose the internal pulldown (IPD) on the BEA13 pin.]PCI auto-initialization via external EEPROM0−PCI auto-initialization through EEPROM is disabled; the PCI peripheral uses the specified PCI default values (default).1−PCI auto-initialization through EEPROM is enabled; the PCI peripheral is configured through EEPROM provided the PCI peripheral pin is enabled (PCI_EN = 1) and theMcBSP2 peripheral pin is disabled (MCBSP2_EN = 0).Note: If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up.For more information on the PCI EEPROM default values, see the TMS320C6000 DSP Peripheral Component Interconnect (PCI) Reference Guide (literature number SPRU581).BEA11D16UTOPIA Enable (UTOPIA_EN) [C6415 and C6416 devices only][The C6414 device does not support the UTOPIA peripheral; for proper device operation, do not oppose the internal pulldown (IPD) on the BEA11 pin.]UTOPIA peripheral enable (functional)0−UTOPIA peripheral disabled (McBSP1 functions are enabled). [default]This means all multiplexed McBSP1/UTOPIA pins function as McBSP1 and all otherstandalone UTOPIA pins are tied-off (Hi-Z).1−UTOPIA peripheral enabled (McBSP1 functions are disabled).This means all multiplexed McBSP1/UTOPIA pins now function as UTOPIA and all otherstandalone McBSP1 pins are tied-off (Hi-Z).。

MEMORY存储芯片TMS320C6414TGLZA8中文规格书

TMS320C6414, TMS320C6415, TMS320C6416FIXED-POINT DIGITAL SIGNAL PROCESSORSSPRS146N − FEBRUARY 2001 − REVISED MAY 2005 311615141312111098ReservedEnable orNon-EnabledInterrupt WakeEnabledInterrupt Wake PD3PD2PD1R/W-0R/W-0R/W-0R/W-0R/W-0R/W-070 Legend:R/W−x = Read/write reset valueNOTE:The shadowed bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).Figure 10. PWRD Field of the CSR RegisterA delay of up to nine cycles may occur after the instruction that sets the PWRD bits in the CSR before the PDmode takes effect. As best practice, NOPs should be padded after the PWRD bits are set in the CSR to account for this delay.If PD1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction where PD1 took effect. If PD1 mode is terminated by an enabled interrupt, the interrupt service routine will be executed first, then the program execution returns to the instruction where PD1 took effect. In the case with an enabled interrupt, the GIE bit in the CSR and the NMIE bit in the interrupt enable register (IER) must also be set in order for the interrupt service routine to execute; otherwise, execution returns to the instruction where PD1 took effect upon PD1 mode termination by an enabled interrupt.PD2 and PD3 modes can only be aborted by device reset. Table 32 summarizes all the power-down modes.TMS320C6414, TMS320C6415, TMS320C6416FIXED-POINT DIGITAL SIGNAL PROCESSORSSPRS146N − FEBRUARY 2001 − REVISED MAY 2005Table 32. Characteristics of the Power-Down ModesPRWD FIELD (BITS 15−10)POWER-DOWNMODE WAKE-UP METHOD EFFECT ON CHIP’S OPERATION000000No power-down——001001PD1Wake by an enabled interrupt CPU halted (except for the interrupt logic)Power-down mode blocks the internal clock inputs at the010001PD1Wake by an enabled ornon-enabled interruptPower down mode blocks the internal clock inputs at theboundary of the CPU, preventing most of the CPU’s logic fromswitching. During PD1, EDMA transactions can proceedbetween peripherals and internal memory.011010PD2†Wake by a device reset Output clock from PLL is halted, stopping the internal clock structure from switching and resulting in the entire chip being halted. All register and internal RAM contents are preserved. All functional I/O “freeze” in the last state when the PLL clock is turned off.011100PD3†Wake by a device reset Input clock to the PLL stops generating clocks. All register and internal RAM contents are preserved. All functional I/O “freeze” in the last state when the PLL clock is turned off. Following reset, the PLL needs time to re-lock, just as it does following power-up. Wake-up from PD3 takes longer than wake-up from PD2 because the PLL needs to be re-locked, just as it does following power-up.All others Reserved——†When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions, peripherals will not operate according to specifications.C64x power-down mode with an emulatorIf user power-down modes are programmed, and an emulator is attached, the modes will be masked to allow the emulator access to the system. This condition prevails until the emulator is reset or the cable is removed from the header. If power measurements are to be performed when in a power-down mode, the emulator cable should be removed.When the DSP is in power-down mode PD2 or PD3, emulation logic will force any emulation execution command (such as Step or Run) to spin in IDLE. For this reason, PC writes (such as loading code) will fail. A DSP reset will be required to get the DSP out of PD2/PD3.power-supply sequencingTI DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time (>1 second) if the other supply is below the proper operating voltage.power-supply design considerationsA dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and I/Opower up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 11).。

FPGA可编程逻辑器件芯片5SGSED8K2F40C2中文规格书

Media Transceiver Module (MXVR) The DMAx Bit-Swap Enable (BITSWAPENx) bit enables or disables bitswapping of the data that is DMA’ed to and from L1 memory. IfBITSWAPENx is set to 1, the data bits will be swapped on a byte-wise basis as follows:bit 7 => bit 0 and bit 0 => bit 7bit 6 => bit 1 and bit 1 => bit 6bit 5 => bit 2 and bit 2 => bit 5bit 4 => bit 3 and bit 3 => bit 4For example, data value 0x35 when bit-swapped becomes 0xAC. IfBITSWAPEN is set to 0, no bit swapping will take place. Note that bit-swap-ping and byte-swapping may be used in conjunction.The DMAx Two Byte Swap Enable (BY2SWAPENx) bit enables or disables two byte swapping of the data that is DMA'd to/from L1 or L2 memory.If BY2SWAPENx is set to 1, the data byte 0 will be swapped with data byte 1.If BY2SWAPENx is set to 0, two byte swapping will not take place. For exam-ple, data value 0x3586 when two byte swapped becomes 0x8635. Two byte swapping is done by reading and writing the L1 or L2 memory in a different order if two byte swapping is enabled. For example, normally data will be read from/written to L1 or L2 in the following address order: 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, etc. If two byte swapping is enabled, data will be read from/written to L1 or L2 in the following address order: 0x01, 0x00, 0x03, 0x02, 0x05, 0x04, etc. Note that when two byte swap-ping is enabled, the MXVR_DMAx_CURR_ADDR will reflect the normal address incrementing (0x00, 0x01, 0x02, 0x03, etc.) even though the L1 or L2 memory accesses will be occurring in the two byte swapping address order.Note that bit-swapping and two byte-swapping may be used in conjunc-tion. However, two byte-swapping and four byte-swapping may not be used at the same time.ADSP-BF54x Blackfin Processor Hardware ReferenceReset and Power-upReset VectorWhen reset releases, the processor starts fetching and executing instruc-tions from address 0xEF000000. This is the address where the on-chip boot ROM resides.On a hardware reset, the boot kernel initializes the EVT1 register to0xFFA00000. When the booting process completes, the boot kerneljumps to the location provided by the EVT1 vector register. With theexception of the HOSTDP boot modes, the content of the EVT1 register is overwritten by the TARGET ADDRESS field of the first block of the applied boot stream. If the BCODE field of the SYSCR register is set to 1 (no boot option), the EVT1 register is not modified by the boot kernel on software resets. Therefore, programs can control the reset vector for software resets through the EVT1 register. This process is illustrated by the flow chart in Figure17-1.The content of the EVT1 register may be undefined in emulator sessions.ADSP-BF54x Blackfin Processor Hardware Reference。

MEMORY存储芯片N25Q064A13ESF40E中文规格书

easy repair method of the device after placed in the system. One row per bank can berepaired. The repair process is revocable by either doing a reset or power-down or byrewriting a new address in the same bank.WRITE PreambleProgrammable WRITE preamble, t WPRE, can be set to 1t CK or 2t CK via the MR4 register.The 1t CK setting is similar to DDR3. However, when operating in 2t CK WRITE preamblemode, CWL must be programmed to a value at least 1 clock greater than the lowest CWLsetting supported in the applicable t CK range.Some even settings will require addition of 2 clocks. If the alternate longer CWL wasused, the additional clocks will not be required.READ PreambleProgrammable READ preamble t RPRE can be set to 1t CK or 2t CK via the MR4 register.Both the 1t CK and 2t CK DDR4 preamble settings are different from that defined for theDDR3 SDRAM. Both DDR4 READ preamble settings may require the memory controllerto train (or read level) its data strobe receivers using the READ preamble training. READ Preamble TrainingProgrammable READ preamble training can be set to 1t CK or 2t CK. This mode can beused by the memory controller to train or READ level its data strobe receivers. Temperature-Controlled RefreshWhen temperature-controlled refresh mode is enabled, the device may adjust the inter-nal refresh period to be longer than t REFI of the normal temperature range by skippingexternal REFRESH commands with the proper gear ratio. For example, the DRAM tem-perature sensor detected less than 45°C. Normal temperature mode covers the range of-40°C to 85°C, while the extended temperature range covers -40°C to 105°C. Command Address LatencyCOMMAND ADDRESS LATENCY (CAL) is a power savings feature and can be enabledor disabled via the MRS setting. CAL is defined as the delay in clock cycles (t CAL) be-tween a CS_n registered LOW and its corresponding registered command and address.The value of CAL (in clocks) must be programmed into the mode register according tothe t CAL(ns)/t CK(ns) rounding algorithms found in the Converting Time-Based Specifi-cations to Clock-Based Requirements section.Internal V REF MonitorThis mode enables output of internally generated V REFDQ for monitoring on DQ0, DQ1,DQ2, and DQ3. May be used during V REFDQ training and test. While in this mode, R TTshould be set to High-Z. V REF_time must be increased by 10ns if DQ load is 0pF, plus anadditional 15ns per pF of loading. This measurement is for verification purposes and isNOT an external voltage supply pin.Table 24: Truth Table – CKENotes: 1.Current state is defined as the state of the DDR4 SDRAM immediately prior to clockedge n.2.CKE (n) is the logic state of CKE at clock edge n; CKE (n-1) was the state of CKE at theprevious clock edge.MAND (n) is the command registered at clock edge n, and ACTION (n) is a result ofCOMMAND (n); ODT is not included here.4.All states and sequences not shown are illegal or reserved unless explicitly describedelsewhere in this document.5.The state of ODT does not affect the states described in this table. The ODT function isnot available during self refresh.6.During any CKE transition (registration of CKE H->L or CKE H->L), the CKE level must bemaintained until 1 nCK prior to t CKE (MIN) being satisfied (at which time CKE may tran-sition again).7.DESELECT and NOP are defined in the Truth Table – Command table.8.For power-down entry and exit parameters, see the Power-Down Modes section.9.CKE LOW is allowed only if t MRD and t MOD are satisfied.10.The power-down mode does not perform any REFRESH operations.11.X = "Don’t Care" (including floating around V REF) in self refresh and power-down. X al-so applies to address pins.12.The DESELECT command is the only valid command for power-down entry and exit.13.V PP and V REFCA must be maintained during SELF REFRESH operation.14.On self refresh exit, the DESELECT command must be issued on every clock edge occur-ring during the t XS period. READ or ODT commands may be issued only after t XSDLL issatisfied.15.The DESELECT command is the only valid command for self refresh exit.16.Self refresh cannot be entered during READ or WRITE operations. For a detailed list ofrestrictions see the SELF REFRESH Operation and Power-Down Modes sections.17.If all banks are closed at the conclusion of the READ, WRITE, or PRECHARGE command,then precharge power-down is entered; otherwise, active power-down is entered.The figure below is another representative way to view the write leveling procedure. Al-though it shows the clock varying to a static strobe, this is for illustrative purpose only;the clock does not actually change phase, the strobe is what actually varies. By issuingmultiple WL bursts, the DQS strobe can be varied to capture with fair accuracy the timeat which the clock edge arrives at the DRAM clock input buffer.Figure 23: Write Leveling Concept, Example 2CK_tCK_cCK_tCK_cCK_tCK_cDQS_t/DQS_cDRAM Setting for Write Leveling and DRAM TERMINATION Function in that ModeThe DRAM enters into write leveling mode if A7 in MR1 is HIGH. When leveling is fin-ished, the DRAM exits write leveling mode if A7 in MR1 is LOW (see the MR LevelingProcedures table). Note that in write leveling mode, only DQS terminations are activa-ted and deactivated via the ODT pin, unlike normal operation (see DRAM DRAM TER-MINATION Function in Leveling Mode table).Table 25: MR Settings for Leveling ProceduresTable 26: DRAM TERMINATION Function in Leveling Mode8Gb: x4, x8, x16 DDR4 SDRAM Write Leveling。

编译型一体机硬件手册说明书

编译型一体机硬件手册二、HMI 接口及PLC 端子说明1. GC-043系列显控控制器(GC-043-16M4AI-C 为例)PLC 端子序号接口功能① 数字量输入。

其中24V 、0V 为内部输出电压接口。

② 数字量输出。

其中PD 为输出保护，接输出电源正极。

③模拟量输入。

其中NTC 、GND 为冷端热敏电阻接口。

HMI 接口序号接口功能 ① 电源输入接口 ② 485通讯口 ③ U 盘口 ④USB 通讯口①② ③ ④2. GC-050系列显控控制器(GC-050-32MAI-C) PLC端子HMI接口3. GC-070系列显控控制器(GC-070-32MAA-C为例) PLC端子HMI接口三、AIAO规格及接线说明1. GC-043、GC-050系列机型模拟量输入规格及配线图AI0~AI3的可选模式有4种：⚫电压模拟量输入范围：0~5V；⚫电流模拟量输入范围：4~20mA；⚫K型热电偶输入，测温范围：-50℃~ 900℃；⚫T型热电偶输入，测温范围：-250℃~ 400℃；注意事项：1. 电压电流模式下，AI寄存器数据类型为16位无符号整数；2. 温度模式下，AI寄存器数据类型为16位有符号整数，显示值为实际温度的10倍（如显示254，即表示当前测量温度为25.4℃）。

若热电偶或热敏电阻出现断线、测温数值超量程等异常情况，对应通道的AI寄存器显示32767；3. 热电偶模式下，必须在NTC、GND处接入热敏电阻，用以测量冷端温度。

AI30寄存器显示AI0和AI1通道共用的冷端温度测量值，AI31寄存器显示AI2和AI3通道共用的冷端温度测量值。

若冷端热敏电阻测温数值异常，AI30/AI31寄存器显示-32767；4. 安装温度传感器时，热电偶的测温部分要避免接触非测温目标的物体。

同时要尽量减小非屏蔽导线的长度，避免导线外露，以减少外部干扰，降低对测温精度的影响。

●模拟量电压输入Samkoon 控制器B- RB B+A- RA A+250Ω- +250Ω-+●模拟量电流输入Samkoon控制器B-RBB+A-RAA+250Ω250ΩB- RB B+A- RA A+250Ω250ΩSamkoon 控制器●K/T 型热电偶模拟量输入+ +2. GC-070系列机型模拟量输入输出规格及配线图（1）电压/电流模拟量输入GC-070-24MAA-C、GC-070-32MAA-C有4路电压/电流模拟量输入通道AI0~AI3，可选模式有3种：⚫电压模拟量输入范围：0~5V⚫电压模拟量输入范围：0~10V⚫电流模拟量输入范围：4~20mA注意事项：电压电流模式下，AI寄存器数据类型为16位无符号整数。

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1White Electronic Designs Corporation • (602) 437-1520 • Oct. 2002Rev. # 0White Electronic Designs Corp. reserves the right to change products or speciﬁ cations without notice.128MB- 16Mx64 DDR SDRAM UNBUFFERED W/PLLDESCRIPTIONThe WED3DG6418S is a 16Mx64 Double Data Rate SDRAM memory module based on 128Mb DDR SDRAM component. The module consists of eight 16Mx8 DDR SDRAMs in 66 pin TSOP package mounted on a 200 Pin FR4 substrate.Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.FEATURESDouble-data-rate architectureSpeed of 100MHz, 133MHz and 166MHz Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2,5 (clock) Programmable Burst Length (2,4,8)Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detectJEDEC standard 200 pin SO-DIMM package Power Supply: 2.5V ± 0.25V2White Electronic Designs Corporation • (602) 437-1520 • Oct. 2002Rev. # 0White Electronic Designs Corp. reserves the right to change products or speciﬁ cations without notice.PIN CONFIGURATIONSPIN NAMESA0 – A11Address input (Multiplexed)BA0-BA1Bank Select Address DQ0-DQ63 Data Input/Output DQS0-DQS8Data Strobe Input/OutputCK0Clock input CK0#Clock input CKE0 Clock Enable Input CS0#Chip select Input RAS#Row Address Strobe CAS#Column Address StrobeWE#Write Enable DQM0-DQM8Data-In Mask V CC Power Supply (2.5V)V CCQ Power Supply for DQS (2.5V)V SS GroundV REF Power Supply for Reference V CCSPD Serial EEPROM Power Supply(2.3V to 3.6V)SDA Serial data I/O SCL Serial clock SA0-SA2Address in EEPROM V CCID V CC Identiﬁ cation FlagNCNo ConnectPin Symbol Pin Symbol Pin Symbol Pin Symbol 1V REF 51V SS 101A9151DQ422V REF 52V SS 102A8152DQ463V SS 53DQ19103V SS 153DQ434V SS 54DQ23104V SS 154DQ475DQ055DQ24105A7155V CC 6DQ456DQ28106A6156V CC 7DQ157V CC 107A5157V CC 8DQ558V CC 108A4158NC 9V CC 59DQ25109A3159V SS 10V CC 60DQ29110A2160NC 11DQS061DQS3111A1161V SS 12DM062DM3112A0162V SS 13DQ263V SS 113V CC 163DQ4814DQ664V SS 114V CC 164DQ5215V SS 65DQ26115A10/AP 165DQ4916V SS 66DQ30116BA1166DQ5317DQ367DQ27117BA0167V CC 18DQ768DQ31118RAS#168V CC 19DQ869V CC 119WE#169DQS620DQ1270V CC 120CAS#170DM621V CC 71NC 121CSO 171DQ5022V CC 72NC 122NC 172DQ5423DQ973NC 123NC 173V SS 24DQ1374NC 124NC 174V SS 25DQS175V SS 125V SS 175DQ5126DM176V SS 126V SS 176DQ5527V SS 77DQS8127DQ32177DQ5628V SS 78DM8128DQ36178DQ6029DQ1079NC 129DQ33179V CC 30DQ1480NC 130DQ37180V CC 31DQ1181V CC 131V CC 181DQ5732DQ1582V CC 132V CC 182DQ6133V CC 83NC 133DQS4183DQS734V CC 84NC 134DM4184DM735CK085NC 135DQ34185V SS 36V CC 86NC 136DQ38186V SS 37CK0#87V SS 137V SS 187DQ5838V SS 88V SS 138V SS 188DQ6239V SS 89NC 139DQ35189DQ5940V SS 90V SS 140DQ39190DQ6341DQ1691NC 141DQ40191V CC 42DQ2092V CC 142DQ44192V CC 43DQ1793V CC 143V CC 193SDA 44DQ2194V CC 144V CC 194SA045V CC 95NC 145DQ41195SCL 46V CC 96CKE0146DQ45196SA147DQS297NC 147DQS5197V CCSPD 48DM298NC 148DM5198SA249DQ1899NC 149V SS 199V CCID 50DQ22100A11150V SS200NC3White Electronic Designs Corporation • (602) 437-1520 • Oct. 2002Rev. # 0White Electronic Designs Corp. reserves the right to change products or speciﬁ cations without notice.FUNCTIONAL BLOCK DIAGRAMDQ32-39DQM4DQ40-479DQM5DQ48-55DQM6DQ56-63DQM74White Electronic Designs Corporation • (602) 437-1520 • Oct. 2002Rev. # 0White Electronic Designs Corp. reserves the right to change products or speciﬁ cations without notice.Absolute Maximum RatingsParameterSymbol Value Units Voltage on any pin relative to V SSV IN , V OUT -0.5 ~ 3.6V Voltage on V CC supply relative to V SS V CC , V CCQ-1.0 ~ 3.6V Storage Temperature T STG -55 ~ +150°C Power Dissipation P D 8W Short Circuit CurrentI OS50mANote: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.DC CHARACTERISTICS(t A = 0 to 70°C, V CC = 2.5V ± 0.2V)ParameterSymbol Min Max Unit Supply Voltage V CC 2.3 2.7V Supply Voltage V CCQ 2.3 2.7V Reference Voltage V REF V CCQ /2-50mV V CCQ /2+50mV V Termination Voltage V TT V REF -0.04V REF +0.04V Input High Voltage V IH V REF +0.15V CCQ +0.3V Input Low Voltage V IL -0.3V REF +0.15V Output High Voltage V OH V TT +0.76—V Output Low VoltageV OL—V TT -0.76VCAPACITANCE(t A = 23°C, f = 1MHz, V CC = 3.3V, V REF =1.4V ± 200mV)ParameterSymbol Min Max Unit Input Capacitance (A0-A12)C IN 1-34pF Input Capacitance (RAS#,CAS#,WE#)C IN 2-34pF Input Capacitance (CKE0)C IN 3-34pF Input Capacitance (CK0, CK0#)C IN 4-30pF Input Capacitance (CS0#)C IN 5-30pF Input Capacitance (DQM0-DQM8)C IN 6-10pF Input Capacitance (BA0-BA1)C IN 7-45pF Data input/output capacitance (DQ0-DQ63)(DQS)C OUT-10pF5White Electronic Designs Corporation • (602) 437-1520 • Oct. 2002Rev. # 0White Electronic Designs Corp. reserves the right to change products or speciﬁ cations without notice.I DD SPECIFICATIONS AND TEST CONDITIONS(Recommended operating conditions, t A = 0 to 70°C, V CCQ = 2.5V ± 0.2V, V CC = 2.5V ± 0.2V)* Module I DD was calculated on the basis of component I DD and can be different measured according to DQ loading cap.Parameter Symbol ConditionsDDR333@CL=2.5Max DDR266@CL=2, 2.5Max DDR200@CL=2MaxUnitsOperating Current I DD0 One device bank; Active = Precharge;t RC =t RC (MIN); t CK =t CK(MIN); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles.840760680mAOperating Current I DD1One device banks; Active-Read-Precharge; Burst = 2; t RC =t RC (MIN); t CK =t CK(MIN); l OUT =0mA; Address and control inputs changing once per clock cycle.1040960880mAPrecharge Power-Down Standby Current I DD2P All device bank idle; Power-down mode; t CK =t CK (MIN); CKE=(low)242424mAIdle Standby Current I DD2F CS# = High; All device banks idle;t CK =t CK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. V IN = V REF for DQ, DQS and DM.200180160mAActive Power-Down Standby CurrentI DD3P One device bank active; Power-down mode;t CK (MIN); CKE=(low)280280225mAActive Standby Current I DD3N CS# = High; CKE = High; One device bank; Active-Precharge; t RC =t RAS (MAX); t CK =t CK (MIN); DQ, DM and DQS inputschanging twice per clock cycle; Address and other control inputs changing once per clock cycle495440360mAOperating Current I DD4R Burst = 2; Reads; Continous burst; Once device bank active; Address and control inputs changing once per clock cycle; t CK =t CK (MIN); I OUT =0mA12801140960mAOperating Current I DD4W Burst=2; Writes; Continous burst; Once device bank active; Address and control inputs changing once per clock cycle; t CK =t CK (MIN); DQ,DM and DQS inputs changing twice per clock cycle.12161040815mAAuto Refresh Current I DD5t RC =t RC (MIN)152014401315mA Self Refresh Current I DD6CKE £ 0.2V161616mAOperating Current I DD7A Four bank interleaving Reads (BL=4) with auto precharge with t RC =t RC (MIN); t CK =t CK (MIN); Address and control input change only during Active Read or Write commands.264024001920mA6White Electronic Designs Corporation • (602) 437-1520 • Oct. 2002Rev. # 0White Electronic Designs Corp. reserves the right to change products or speciﬁ cations without notice.I DD1 : OPERATING CURRENT: ONE BANK1. Typical Case : V CC =2.5V, T = 25°C 2. Worst Case : V CC = 2.7V, T = 10°C3. Only one bank is accessed with t RC (min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. I OUT = 0mA4. Timing patterns-DDR200 (100Mhz, CL = 2) : t CK = 10ns, CL2, BL = 4, t RCD = 2*t CK , t RAS = 5*t CKRead : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst -DDR266B (133Mhz, CL = 2.5): t CK = 7.5ns, CL = 2.5, BL = 4, t RCD = 3*t CK , t RC = 9*t CK , t RAS = 5*t CKRead : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst-DDR266A (133Mhz, CL = 2) : t CK = 7.5ns, CL = 2, BL = 4, t RCD = 3*t CK , t RC = 9*t CK , t RAS = 5*t CKRead : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst-DDR333 (166MHz, CL = 2.5) : t CK = 6ns, CL = 2.5, BL = 4, t RCD = 10*t CK , t RAS = 7*t CKRead " A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst.I DD7A : OPERATING CURRENT : FOUR BANK OPERATION1. Typical Case : V cc =2.5V, T = 25°C 2. Worst Case : V cc = 2.7V, T = 10°C3. Four banks are being interleaved with t RC (min), Burst Mode, Address and Control inputs on NOP edge are not changing. I OUT = 0mA4. Timing patterns- DDR200 (100Mhz, CL = 2) : t CK = 10ns, CL2, BL = 4, t RRD = 2*t CK , t RCD = 3*t CK , Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst -DDR266B (133Mhz, CL = 2.5) : t CK = 7.5ns, CL = 2.5, BL = 4, t RRD = 2*t CK , t RCD = 3*t CK Read with autoprechargeRead : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst -DDR266A (133Mhz, CL = 2) : t CK = 7.5ns, CL2 = 2, BL = 4, t RRD = 2*t CK , t RCD = 3*t CKRead : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst -DDR333 (166MHz, CL = 2.5) : t CK = 6ns, CL = 2.5, BL = 4, t RRD = 2*t CK , t RCD = 3*t CK , Read with autoprechargeRead : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burstLegend : A = Activate, R = Read, W = Write, P = Precharge, N = NOPDETAILED TEST CONDITIONS FOR DDR SDRAM I DD1 & I DD7A7White Electronic Designs Corporation • (602) 437-1520 • Oct. 2002Rev. # 0White Electronic Designs Corp. reserves the right to change products or speciﬁ cations without notice.ORDER INFORMATIONPart NumberSpeed CAS Latency WED3EG6418S335D4166M Hz/333Mbps CL=2.5WED3EG6418S262D4133MHz/266Mbps CL=2WED3EG6418S265D4133MHz/266Mbps CL=2.5WED3EG6418S202D4100MHz/200Mbps CL=2PACKAGE DIMENSIONSALL DIMENSIONS ARE IN INCHES。