YG801C04中文资料
SC801_04资料
1.5 1.5 Fast - Charge Current = • 88 • 1000 Termination Current = R R 2 1
1
元器件交易网
Parameter VC C , EN to GND VOUT, VPRGM, IPRGM, C P, OVP, STAT, ITERM, BIP to GND Power D i ssi pati on, MLP (D erate 20mW/ °C above 85 °C ) VOUT short to GND Thermal Resi stance, Juncti on to Ambi ent Operati ng Juncti on Temperature IR Reflow Temperature (Solderi ng) 10 seconds Storage Temperature ESD Rati ng (Human Body Model) TR opti on TRT opti on (leadfree leadframe)
IVOUT VBAT
V C C = 0V VPRGM = Logic High VPRGM = Logic Low VPRGM = External Divider VCC = 4.2V - 6.5V
0.1 4.20 4.10 3.0 82 4.16 4.06 2.97 72 38 450 750
1 4.24 4.14 3.03 92 52 550 850
Electrical Characteristics
Unless otherwise noted: VCC = 4.75V - 5.25V
LQH4C100K04中文资料
MP21051MHz, 800mA Synchronous Step-Down ConverterThe Future of Analog IC TechnologyTMTMDESCRIPTIONThe MP2105 is a 1MHz constant frequency,current mode, PWM step-down converter. The device integrates a main switch and a synchronous rectifier for high efficiency without an external Schottky diode. It is ideal for powering portable equipment that runs from a single cell Lithium-Ion (Li+) battery. The MP2105 can supply 800mA of load current from a 2.5V to 6V input voltage. The output voltage can be regulated as low as 0.6V. The MP2105 can also run at 100% duty cycle for low dropout applications.The MP2105 is available in a low profile (1mm) 5-pin, TSOT package.EVALUATION BOARD REFERENCEBoard Number Dimensions EV2105DJ-00A2.0”X x 2.0”Y x 0.5”ZFEATURES• High Efficiency: Up to 95%• 1MHz Constant Switching Frequency • 800mA Available Load Current • 2.5V to 6V Input Voltage Range • Output Voltage as Low as 0.6V • 100% Duty Cycle in Dropout • Current Mode Control • Short Circuit Protection • Thermal Fault Protection • <0.1µA Shutdown Current•Space Saving 5-Pin TSOT23 PackageAPPLICATIONS• Cellular and Smart Phones• Microprocessors and DSP Core Supplies • PDAs • MP3 Players• Digital Still and Video Cameras • Portable Instruments“MPS” and “The Future of Analog IC Technology” are Trademarks of Monolithic Power Systems, Inc.TYPICAL APPLICATIONE F F I C I E N C Y (%)101001000LOAD CURRENT (mA)MP2105-EC01Efficiency vs Load CurrentMP2105 – 1MHz 800mA SYNCHRONOUS STEP-DOWN CONVERTER TMPACKAGE REFERENCE* For Tape & Reel, add suffix –Z (eg. MP2105DJ–Z)For Lead Free, add suffix –LF (eg. MP2105DJ–LF–Z) ABSOLUTE MAXIMUM RATINGS (1) V IN to GND..................................–0.3V to +6.5V V SW to GND...........................–0.3V to V IN +0.3V V FB, V EN to GND..........................–0.3V to +6.5V Junction Temperature.............................+150°C Lead Temperature..................................+260°C Storage Temperature .............–65°C to +150°C Recommended Operating Conditions (2) Supply Voltage V IN.............................2.5V to 6V Output Voltage V OUT..........................0.6V to 6V Operating Temperature.............–40°C to +85°C Thermal Resistance (3)θJA θJCTSOT23-5..............................220....110..°C/W Notes:1) Exceeding these ratings may damage the device.2) The device is not guaranteed to function outside of itsoperating conditions.3) Measured on approximately 1” square of 1 oz copper.ELECTRICAL CHARACTERISTICS (4)V IN = V EN = 3.6V, T A = +25°C, unless otherwise noted.Parameter SymbolCondition MinTypMaxUnits Supply Current V EN = V IN, V FB = 0.65V 440 600 µAShutdown Current V EN = 0V, V IN = 6V 0.10 1 µAIN Undervoltage Lockout Threshold RisingEdge 2.15 2.30 2.40 VIN Undervoltage LockoutHysteresis55 mVT A = +25°C 0.588 0.600 0.612Regulated FB Voltage V FB–40°C ≤ T A≤ +85°C 0.582 0.600 0.618VFB Input Bias Current V FB = 0.65V –50 0.5 +50 nA PFET On Resistance I SW100mA 0.42 ΩNFET On Resistance I SW–100mA 0.26 ΩSW Leakage Current V EN = 0V, V IN = 6V,V SW = 0V or 6V–1 +1 µAPFET Current Limit Duty Cycle = 100%,Current Pulse Width < 1ms1.2 1.62.1 AOscillator Frequency f OSC0.85 1.05 1.25 MHz Thermal Shutdown TripThreshold145 °CEN Trip Threshold –40°C ≤ T A≤+85°C 0.3 0.96 1.5 V EN Input Current V EN = 0V to 6V –1 +1 µA Notes:4) 100% production test at +25°C. Specifications over the temperature range are guaranteed by design and characterization.MP2105 – 1MHz 800mA SYNCHRONOUS STEP-DOWN CONVERTERTMTYPCIAL PERFORMANCE CHARACTERISTICSV IN = 3.3V, V OUT = 1.8V, L1 = 4.7µH, C1 = 4.7µF, C3 = 10µF, T A = +25°C, unless otherwise noted.MP2105-TPC03Load Transient(I OUT =0mA to 500mA step)Light Load Operation(IOUT =0mA)F E E D B AC K V O L T A G E (V )-40+200-20+40+60+80+100-40+200-20+40+60+80+100TEMPERATURE (°C)MP2105-TPC01E F F I C I E N C Y (%)MP2105-TPC04TEMPERATURE (°C)MP2105-TPC02V OUT 100mV/div.I OUT 0.5A/div.V OUT 10mV/div.I L0.2A/div.SW 2V/div.MP2105 – 1MHz 800mA SYNCHRONOUS STEP-DOWN CONVERTERTMTYPCIAL PERFORMANCE CHARACTERISTICS (continued)V IN = 3.3V, V OUT = 1.8V, L1 = 4.7µH, C1 = 4.7µF, C3 = 10µF, T A = +25°C, unless otherwise noted.MP2105-TPC09Short Circuit Protection(No Load)MP2105-TPC07Heavy Load OperationI OUT= 800mAMP2105-TPC10Short Circuit Recovery (No Load)MP2105-TPC08Startup from ShutdownV OUT 10mV/div.I L0.2A/div.L =0SW 2V/div.V OUT 1V/div.I L0.5A/div.V OUT 1V/div.I L0.5A/div.V EN 2V/div.V OUT 1V/div.I L0.5A/div.PIN FUNCTIONSPin # Name DescriptionEN 1Regulator Enable Control Input. Drive EN above 1.5V to turn on the MP2105. Drive EN below0.3V to turn it off (shutdown current < 0.1µA).GND 2 Ground SW 3 Power Switch Output. Inductor connection to drains of the internal PFET and NFET switches. IN 4 Supply Input. Bypass to GND with a 2.2µF or greater ceramic capacitor.FB 5Feedback Input. Connect FB to the center point of the external resistor divider. The feedbackthreshold voltage is 0.6V.MP2105 – 1MHz 800mA SYNCHRONOUS STEP-DOWN CONVERTERTMOPERATIONThe MP2105 is a constant frequency current mode PWM step-down converter. The MP2105 is optimized for low voltage, Li-Ion battery powered applications where high efficiency and small size are critical. The MP2105 uses an external resistor divider to set the output voltage from 0.6V to 6V. The device integrates both a main switch and a synchronous rectifier, which provides high efficiency and eliminatesan external Schottky diode. The MP2105 can achieve 100% duty cycle. The duty cycle D of a step-down converter is defined as:%100V V %100f T D INOUTOSC ON ×≈××= where T ON is the main switch on time, and f OSC is the oscillator frequency (1MHz).INENFBGNDSWMP2105_BD01Figure 1—Functional Block DiagramMP2105 – 1MHz 800mA SYNCHRONOUS STEP-DOWN CONVERTERTMCurrent Mode PWM ControlSlope compensated current mode PWM control provides stable switching and cycle-by-cycle current limit for superior load and line response and protection of the internal main switch and synchronous rectifier. The MP2105 switches at a constant frequency (1MHz) and regulates the output voltage. During each cycle the PWM comparator modulates the power transferred to the load by changing the inductor peak current based on the feedback error voltage. During normal operation, the main switch is turned on for a certain time to ramp the inductor current at each rising edge of the internal oscillator, and switched off when the peak inductor current is above the error voltage. When the main switch is off, the synchronous rectifier will be turned on immediately and stay on until either the next cycle starts. Dropout OperationThe MP2105 allows the main switch to remain on for more than one switching cycle and increases the duty cycle while the input voltage is dropping close to the output voltage. When the duty cycle reaches 100%, the main switch is held on continuously to deliver current to the output up tothe PFET current limit. The output voltage then is the input voltage minus the voltage drop across the main switch and the inductor.Short Circuit ProtectionThe MP2105 has short circuit protection. When the output is shorted to ground, the oscillator frequency is reduced to prevent the inductor current from increasing beyond the PFET current limit. The PFET current limit is also reduced to lower the short circuit current. The frequency and current limit will return to the normal values once the short circuit condition is removed and the feedback voltage reaches 0.6V.Maximum Load CurrentThe MP2105 can operate down to 2.5V input voltage; however the maximum load current decreases at lower input due to large IR drop on the main switch and synchronous rectifier. The slope compensation signal reduces the peak inductor current as a function of the duty cycle to prevent sub-harmonic oscillations at duty cycles greater than 50%. Conversely the current limit increases as the duty cycle decreases.APPLICATION INFORMATIONOutput Voltage SettingThe external resistor divider sets the output voltage (see Figure 3). The feedback resistor R1 also sets the feedback loop bandwidth with the internal compensation capacitor (see Figure 1). Choose R1 around 500k Ω for optimal transient response. R2 is then given by:1V6.0V 1R 2R OUT−=Table 1—Resistor Selection vs. OutputVoltage SettingV OUT R1 R2 1.2V 499k Ω (1%) 499k Ω (1%) 1.5V 499k Ω (1%) 332k Ω (1%) 1.8V 499k Ω (1%) 249k Ω (1%) 2.5V499k Ω (1%)158k Ω (1%)Inductor SelectionA 1µH to 10µH inductor with DC current rating at least 25% higher than the maximum load current is recommended for most applications. For best efficiency, the inductor DC resistance shall be <200m Ω. See Table 2 for recommended inductors and manufacturers. For most designs, the inductance value can be derived from the following equation:()OSCL IN OUT IN OUT f I V V V V L ×∆×−×=where ∆I L is Inductor Ripple Current. Choose inductor ripple current approximately 30% of the maximum load current, 800mA.The maximum inductor peak current is:2I I I LLOAD )MAX (L ∆+= Under light load conditions below 100mA, larger inductance is recommended for improved efficiency. Table 3 lists inductors recommended for this purpose.MP2105 – 1MHz 800mA SYNCHRONOUS STEP-DOWN CONVERTERTMTable 2—Suggested Surface Mount InductorsManufacturerPart NumberInductance (µH)Max DCR (Ω)Saturation Current (A)Dimensions LxWxH (mm 3)Coilcraft D01605T-472 4.70.150 1.20 5.4x4.2x1.8 Toko D52LC 4.7 0.087 1.14 5x5x2 Sumida CR43-4R7 4.7 0.109 1.15 4.3x4.8x3.5Table 3—Inductors for Improved Efficiency at 25mA, 50mA, under 100mA Load.ManufacturerPart NumberInductance (µH)Max DCR (Ω)Saturation Current (A)I RMS (A)Coilcraft DO1605T-103MX 100.3 1.0 0.9 Murata LQH4C100K04 10 0.2 1.2 0.8 Sumida CR32-100 10 0.2 1.0 0.7 Sumida CR54-100 100.1 1.21.4Input Capacitor SelectionThe input capacitor reduces the surge current drawn from the input and switching noise from the device. The input capacitor impedance at the switching frequency shall be less than input source impedance to prevent high frequency switching current passing to the input. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. For most applications, a 4.7µF capacitor is sufficient. Output Capacitor SelectionThe output capacitor keeps output voltage ripple small and ensures regulation loop stable. The output capacitor impedance shall be low at the switching frequency. Ceramic capacitors with X5R or X7R dielectrics are recommended. The output ripple ∆VOUT is approximately:()⎟⎟⎠⎞⎜⎜⎝⎛××+×××−×≤∆3C f 81ESR L f V V V V V OSC OSC IN OUT IN OUT OUTPC Board LayoutThe high current paths (GND, IN and SW)should be placed very close to the device with short, direct and wide traces. Input capacitor C1 needs to be as close as possible to the IN and GND pins. The external feedback resistors shall be placed next to the FB pin. Keep the switching node SW short and away from the feedback network. Figure 2 illustrates an example of PCB layout and signal routing.Figure 2—MP2105 Suggested LayoutMP2105 – 1MHz 800mA SYNCHRONOUS STEP-DOWN CONVERTERNOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications.TMPACKAGE INFORMATIONTSOT23-5Gauge Plane0.25 BSC.±0.10-+0.4000°0°4°(2 plcs)10°TYP.2.90 BSC(5PLCS)0.300(Min)LC TYP .0.950LC TYP .0.9502.80 B S C1.60 B S C330.500(Max)SEATING PLANE0.87±0.030.00-0.101.00M a x .(2 plcs)。
FCK-801C技术及使用说明书
FCK-801C微机测控装置技术及使用说明书（Version 1.00）许继电气股份有限公司XJ ELECTRIC CO.，LTD.目录1概述 (1)1.1应用范围 (1)1.2功能配置 (1)1.3产品特点 (1)2技术指标 (2)2.1交直流测量 (2)2.2状态输入 (2)2.3控制输出 (2)2.4工作电源 (3)2.5绝缘性能 (3)2.6机械性能 (3)2.7抗电气干扰性能 (3)2.8环境条件 (3)2.9通信接口 (4)3装置功能 (5)3.1遥测功能 (5)3.2遥信功能 (5)3.3遥控功能 (5)3.4遥调功能 (6)3.5同期功能 (6)3.6逻辑闭锁 (7)3.7报告记录 (8)3.8通信功能 (8)3.9自检功能 (8)3.10对时功能 (9)4定值整定 (10)4.1直流定值 (10)4.2遥调定值 (10)4.3同期定值 (10)4.4软压板 (11)5参数设置 (12)5.1系统参数 (12)6装置硬件介绍 (13)6.1机箱结构 (13)6.2插件布置图 (13)6.3装置端子图 (14)7使用说明 (15)7.1指示灯说明 (15)7.2调试接口和键盘说明 (15)7.3命令菜单 (16)7.4液晶显示说明 (18)7.5装置操作说明 (18)8调试说明 (21)8.1调试注意事项 (21)8.2开关量输入检查 (21)8.3开出回路检查 (21)8.4模拟量输入检查 (21)8.5装置异常信息说明及处理意见 (21)8.6事故分析注意事项 (21)9订货须知 (22)10附录 (23)1概述1.1应用范围FCK-801C系列测控装置（以下简称装置）是适用于500kV及以下电压等级的间隔层测控单元，具有全范围高精度测量、高可靠性控制、完备的间隔层监视、间隔层逻辑闭锁等功能特点，支持IEC 61850和TCP 103通讯协议。
1.2功能配置装置具体功能配置详见表1-1。
SOCAY电子有限公司 ESD05V14T-LC 四线保护芯片说明书
SOT-143 Circuit Diagram
Protection Solution to Meet
IEC61000-4-2 (ESD) ±15kV (air), ±8kV (contact) IEC61000-4-4 (EFT) 40A (5/50ns) IEC61000-4-5 (Lightning) 6.5A (8/20μs)
Junction Capacitance
Symbol VR VBR IR VC
CJ
Conditions
IT = 1mA VR = 5V pin4 to pin1 IPP =1A, tp =8/20μs IPP =4A, tp =8/20μs VR = 0V, f = 1MHz Any I/O pin to Ground VR = 0V, f = 1MHz Between I/O pins
Main Applications Fire Wire & USB Sensitive Analog Inputs Notebook Computers Portable Electronics LAN/WAN equipment Video Line Protection Microcontroller Input Protection
Symbol TSTG TJ TL PPP
VESD
Value -55 to +150 -55 to +125 260 (10 sec.)
100 ±15 ±8
Байду номын сангаас
Electrical Characteristics (TA=25℃)
Parameter Reverse Working Voltage Reverse Breakdown Voltage Reverse Leakage Current Clamping Voltage （I/O pin to Ground）
明德扬 MP801 开发板说明书
明德扬MP801开发板说明书修订日期：20200409 版本：v5.0目录明德扬MP801开发板说明书 (1)一、明德扬MP801开发板介绍 (3)二、开发板硬件介绍 (4)1、FPGA芯片 (4)2、数码管和LED灯 (4)3、拨码开关 (5)4、普通按键和复位按键 (5)5、温度传感器 (6)6、EEPROM存储器 (6)7、VGA接口 (7)8、锋鸣器 (7)9、SDRAM存储器 (8)10、千兆网口 (8)11、USB串口 (9)12、AD9709与AD9280 (9)13、基它扩展口 (10)三、配套学习资料 (10)四、配套案例列举 (11)五、技术支持 (12)六、更多帮助 (12)一、明德扬MP801开发板介绍MP801开发板是基于altera Cyclone IV 系列FPGA自主研发的高校级教学开发板，6层板制作工艺，尺寸为130mm*100mm。
该板非常适合初学者以及项目进阶训练，明德扬为此提供大量的配套练习，以及提供完善的售后服务。
从简单的led 到复杂的SDRAM等一应俱全，其中板载EP4CE15F23C8，拥有15K逻辑资源，504K bit ram资源，且板载3片128M bit SDRAM，适合存储大容量的数据；并且拥有125Mhz 双通道转换速率的高速并行DA芯片AD9709和32Mhz 转换速率的高速并行AD芯片AD9280，编程简单，适用做算法验证；并且采用64M spi flash存储器存储程序，满足开发需求。
在此，明德扬希望您早日掌握FPGA编程技术，学有所成。
二、开发板硬件介绍1、FPGA芯片Altera Cyclone IV系列芯片，采用型号为：EP4CE15F23C8，逻辑单元：15408,用户可用IO：6272，内部存储器：516096，PLL：4，M9K:112,可通过低功耗和成本实现较高的功能性。
2、数码管和LED灯开发板板载红色8个数码管，采用动态显示的方式和FPGA连接，其中数码管采用共阳极数码管，开发板led电路采用上拉接法，板载8个绿色的led。
FLW-801C 产品使用说明书
文档类别：维护文档密级：保密FLW-801C版权与许可深圳市畅锐科技有限公司版权所有，翻印必究。
除非版权法允许，否则，在事先未经书面许可的情况下，严禁复制、改编或翻译本手册。
与此手册相关用户具有以下权力：A:打印本手册以获得其硬盘拷贝，用于个人、内部或公司用途，而不得用于销售、转售或分发目的；B:将本手册仅作为深圳市畅锐科技有限公司自助产品的维护使用。
文档声明本文所含信息如有更改，恕不另行通知。
本公司不对本书作任何担保。
本公司对于由本书所含错误及其供应、性能或使用所造成的意外性或随发性损失概不负责。
目录第一章功能环境指标 (4)第二章功能 (4)第三章拼接单元框图 (6)第四章系统构成原理 (7)第五章屏幕墙拼接组成框图(2X2) (8)第六章常见故障处理 (8)第七章功能指标 (9)第八章实物图及其端口定义 (10)第九章尺寸定义 (13)第十章软件烧录 (13)第十一章PC软件使用说明 (16)第十二章主界面 (18)第十三章遥控说明 (50)第十四章安全注意事项 (58)第一章功能环境指标输入1路CVBS 接口为BNC 座子, 支持PAL/NTSC 全制式1路VGA 支持VGA 信号1920×1080 60Hz 以下的大部分60Hz 分辨率 1路DVI支持DVI 信号3840×2160P30Hz 信号以下的分辨率 2路HDMI 支持HDMI 3840×2160p30Hz 信号以下的分辨率 1路DP 支持HDMI 3840×2160p30Hz 信号以下的分辨率 1路USB 程序升级1路RJ45RS232控制信号环入端口、红外接入转换接口（接口类型为RJ45） 输出背光 背光控制信号输出LVDS 支持单双路LVDS ，最高可支持WUXGA （1920×1080)屏幕。
2路RJ45RS232控制信号环出端口第二章功能• 全硬件构架，无CPU 和操作系统； • 多总线并行处理，处理功能强大； • 无病毒感染风险，安全性好；• 集成多路视频信号源种类：DVI 、HDMI 、DP 、复合视频、VGA ； • 内嵌3D 视频亮色分离电路单元；• 内嵌3D 逐行处理及帧频归一转化电路单元； • 内嵌3D 数字信号降噪单元；• 单元可支持驱动到4K@30HZ(3840X2160)的液晶屏幕； • 可全天24小时持续工作；工程系统软件 拼接控制系统，RS232接口控制（1路环入，2路环出）工作温度 -15℃-65℃ 工作湿度 5～95％RH 电源电压 220V 交流供电功率消耗≤248W• 操作方便，配合FTM_CONTROL软件可以灵活的对系统进行操作；• 可开放底层通讯协议，便于用户灵活采用第三方中控系统；•RS232 串口远程控制；每单元支持RS232一路环入，两路环出；USB上电升级功能利用板卡自带的USB接口，以实现FLW-801C模块升级，只要在U盘内存入需升级软体，利用U盘连接到对应FLW-801C，然后重新上电后，FLW-801C检测到升级软体后便自动进入升级模块，对应电源指示灯闪烁提示升级，待指示灯停止闪烁后便升级完成。
XJY801光扩散剂使用中英说明书
有机硅树脂光扩散剂XJY-801 Series【产品概述】光扩散粉801系列是结合有机硅的润滑性，耐冲击性，光扩散性，耐热性等优异性能的高性能粉末。
该粉末可提供平衡的透光率、雾度以及光散射效果等多种光学性能，广泛应用于高端透明PC 灯/灯罩/灯箱、平板液晶光扩散板等领域。
XJY-801系列可提供粒径从0.5－30μm，粒径均一。
【技术规格】电子显微镜照片粒径分布图材质：有机硅树脂外观：白色流动性粉末折射率： 1.42-1.45 低于丙烯酸系列及PS/PMMA/PC等透明树脂形状：球状含水率：≦1%耐热性: >400℃非常出色、不黄变、不产生黑点密度: 1.3【XJY-801系列型号】牌号XJY-80106 XJY-8011 XJY-80113 XJY-80116 XJY-8012 XJY-8015 XJY-801105 XJY-801300 粒径/µm 0.6±0.05 1.0±0.1 1.3±0.1 1.6±0.1 2.0±0.2 5.0±0.5 15±2.0 30±5 【应用范围】◆光扩散板、光扩散膜：通过与PC，聚苯乙烯，PMMA等树脂的结合赋予其优异的光扩散性，也可通过添加到喷涂中赋予膜的光扩散性；◆用于油漆、涂料及油墨，可显著改进色料的分散性及润滑性，赋予涂料滑润质感及艺术的亚光效果；优点如下：1）亮度高、添加量更少；2）光扩散性优异；3）光透过率高； 4）在树脂中分散性好，可直接添加;5）耐高温至470℃、不变色、不泛黄、不发灰；挤出灯管灯罩过程中不易生成黑点，成品率高。
【使用方法】根据所需要的不同的透光及雾度要求，选择不同的XJY-801光扩散剂系列产品，一般添加量为0.4-0.8%。
最终结果需要根据不同材料形态、厚度以及透光雾度要求，通过小试测试得出结论。
【储存和包装】在低于25°C (77°F)下未开封保存于原容器中，该产品自生产之日起保质期为12个月。
zl38010中文资料_数据手册_IC数据表
1Features•Full duplex transcoder with four encode channels and four decode channels•32kbps, 24kbps and 16kbps ADPCM coding complying with ITU-T (previously CCITT) G.726 (without 40kbps), and ANSI T1.303-1989•Low power operation, 6.5mW typical•Asynchronous 4.096MHz master clock operation •SSI and ST-BUS interface options •Transparent PCM bypass •Transparent ADPCM bypass •Linear PCM code•No microprocessor control required •Simple interface to Codec devices •Pin selectable µ−Law or A-Law operation •Pin selectable ITU-T or signed magnitude PCM coding•Single 3.3Volts power supplyApplications•Pair gain•Voice mail systems•Wireless telephony systemsDescriptionThe Quad ADPCM Transcoder is a low power, CMOS device capable of four encode and four decode functions per frame. Four 64kbps PCM octets are compressed into four 32, 24 or 16kbps ADPCM words,and four 32, 24 or 16 kbps ADPCM words are expanded into four 64kbps PCM octets. The 32, 24and 16kbps ADPCM transcoding algorithms utilized conform to ITU-T Recommendation G.726 (excluding 40kbps), and ANSI T1.303 - 1989.January 2007Ordering InformationZL38010DCE 28 Pin SOIC TubesZL38010DCF 28 Pin SOIC Tape & Reel ZL38010DCE128 Pin SOIC**TubesZL38010DCF128 Pin SOIC**Tape & Reel**Pb Free Matte Tin-40°C to +85°CZL38010Low Power Quad ADPCM TranscoderData SheetFigure 1 - Functional Block DiagramADPCM I/OPCM I/OControl DecodeVDD VSS PWRDN IC MS1MS2A/µFORMAT MS5MS4MS3MS6LINEAR SELTimingADPCMi ADPCMoENB1ENB2/F0odBCLK F0i MCLK C2o EN1EN2PCMo1PCMi1PCMo2PCMi2Full Duplex Quad TranscoderZL38010Data SheetSwitching, on-the-fly, between 32kbps and 24kbps ADPCM, is possible by controlling the appropriate mode select (MS1 - MS6) control pins. All optional functions of the device are pin selectable allowing a simple interface to industry standard codecs, digital phone devices and Layer 1 transceivers. Linear coded PCM is provided to facilitate external DSP functions.Change SummaryChanges from October 2005 Issue to January 2007 Issue.Figure 2 - Pin ConnectionsPin Description Page ItemChange1Ordering Information BoxAdded Pb Free part numbers.Pin #Name Description1EN1Enable Strobe 1 (Output). This 8 bit wide, active high strobe is active during the B1 PCM channel in ST-BUS mode. Becomes a single bit, high true pulse when LINEAR=1. In SSI mode this output is high impedance.2MCLKMaster Clock (input). This is a 4.096MHz (minimum) input clock utilized by thetranscoder function; it must be supplied in both ST-BUS and SSI modes of operation. In ST-BUS mode the C4 ST-BUS clock is applied to this pin. This synchronous clock is also used to control the data I/O flow on the PCM and ADPCM input/output pins according to ST-BUS requirements.In SSI mode this master clock input is derived from an external source and may beasynchronous with respect to the 8kHz frame. MCLK rates greater than 4.096MHz are acceptable in this mode since the data I/O rate is governed by BCLK.3F0i Frame Pulse (Input). Frame synchronization pulse input for ST-BUS operation. SSI operation is enabled by connecting this pin to V SS .4C2o2.048MHz Clock (Output). This ST-BUS mode bit clock output is the MCLK (C4) input divided by two, inverted, and synchronized to F0i. This output is high-impedance during SSI operation.12345678910111213141516171819202827262524232221MS1VDD MS3ICMS4FORMAT MS2PWRDN ADPCMi ADPCMo MS5MS6EN2PCMo1BCLK PCMi1LINEAR ENB2/F0odVSS C2o MCLK F0i PCMi2ENB1PCMo2EN1SEL A/µZL38010Data SheetPin #Name Description5BCLK Bit Clock (Input). 128kHz to 4096kHz bit clock input for both PCM and ADPCM ports;used in SSI mode only. The falling edge of this clock latches data into ADPCMi, PCMi1and PCMi2. The rising edge clocks data out on ADPCMo, PCMo1 and PCMo2. This inputmust be tied to V SS for ST-BUS operation.6PCMo1Serial PCM Stream 1 (Output). 128kbps to 4096kbps serial companded/linear PCM out-put stream. Data are clocked out by rising edge of BCLK in SSI mode. Clocked out byMCLK divided by two in ST-BUS mode. See Figure 14.7PCMi1Serial PCM Stream 1 (Input). 128kbps to 4096kbps serial companded/linear PCM input stream. Data are clocked in on falling edge of BCLK in SSI mode. Clocked in at the3/4 bit position of MCLK in ST-BUS mode. See Figure 14.8V SS Digital Ground. Nominally 0 volts9LINEAR Linear PCM Select (Input). When tied to V DD the PCM I/O ports (PCM1,PCM2) are 16-bit linear PCM. Linear PCM operates only at a bit rate of 2048kbps. Companded PCM isselected when this pin is tied to V SS. See Figure 5 & Figure 8.10ENB2/F0od PCM B-Channel Enable Strobe 2 (Input) / Delayed Frame Pulse (Output).SSI operation: ENB2 (Input). An 8-bit wide enable strobe input defining B2 channel(AD)PCM data. A valid 8-bit strobe must be present at this input for SSI operation. SeeFigure 4 & Figure 6.ST-BUS operation: F0od(Output). This pin is a delayed frame strobe output. When LIN-EAR=0, this becomes a delayed frame pulse output occurring 64 C4 clock cycles afterF0i and when LINEAR = 1 at 128 C4 clock cycles after F0i. See Figures 7, 8, 9 & 14.11ENB1PCM B-Channel Enable Strobe 1 (Input).SSI operation: An 8-bit wide enable strobe input defining B1 channel (AD)PCM data. Avalid 8-bit strobe must be present at this input for SSI operation.ST-BUS operation: When tied to V SS transparent bypass of the ST-BUS D- and C- chan-nels is enabled. When tied to V DD the ST-BUS D-channel and C-channel output timeslotsare forced to a high-impedance state.12PCMo2Serial PCM Stream 2 (Output). 128kbps to 4096kbps serial companded/linear PCM out-put stream. Clocked out by rising edge of BCLK in SSI mode. Clocked out by MCLK divid-ed by two in ST-BUS mode. See Figure 14.13PCMi2Serial PCM Stream 2 (Input). 128kbps to 4096kbps serial companded/linear PCM input stream. Data bits are clocked in on falling edge of BCLK in SSI mode. Clocked in at the3/4 bit position of MCLK in ST-BUS mode. See Figure 14.14SEL SELECT (Input).PCM bypass mode: When SEL=0 the PCM1 port is selected for PCM bypass operationand when SEL=1 the PCM2 port is selected for PCM bypass operation.See Figure 6 & Figure 9.16kbps transcoding mode:SSI Operation - in 16kbps transcoding mode, the ADPCM words are assigned to the I/Otimeslot defined by ENB2 when SEL=1 and by ENB1 when SEL=0. See Figure 4.ST-BUS operation- in 16kbps transcoding mode, the ADPCM words are assigned to theB2 timeslot when SEL=1 and to the B1 timeslot when SEL=0. See Figure 9.ZL38010Data SheetAll unused inputs should be connected to logic low or high unless otherwise stated. All outputs should be left open circuit when not used.All inputs have TTL compatible logic levels except for MCLK which has CMOS compatible logic levels and PWRDN which has Schmitt trigger compatible logic levels.All outputs are CMOS with CMOS logic levels (See DC Electrical Characteristics).15A/µA-Law/µ−Law Select (Input). This input pin selects µ−Law companding when set to logic 0, and A-Law companding when set to logic 1. This control is for all channels.This input is ignored in Linear mode during which it may be tied to V SS or V DD .16FORMATFORMAT Select (Input). Selects ITU-T PCM coding when high and Sign-Magnitude PCM coding when low. This control is for all channels.This input is ignored in Linear mode during which it may be tied to V SS or V DD .17PWRDN Power-down (Input). An active low reset forcing the device into a low power mode where all outputs are high-impedance and device operation is halted. 18IC Internal Connection (Input). Tie to V SS for normal operation.192021MS1MS2MS3Mode Selects 1, 2 and 3 (Inputs). Mode selects for all four encoders.MS3MS2MS1MODE 00032kbps ADPCM 00124kbps ADPCM 01016kbps ADPCM in EN1/ENB1 when SEL=0in EN2/ENB2 when SEL=1011ADPCM Bypass for 32kbps and 24kbps 100ADPCM Bypass for 16kbps 101PCM Bypass (64kbps) to PCM1 if SEL=0, PCM2 if SEL=1110Algorithm reset (ITU-T optional reset)111ADPCMo disable 22V DD Positive Power Supply. Nominally 3.3Volts +/-10%23ADPCMiSerial ADPCM Stream (Input). 128kbps to 4096kbps serial ADPCM word input stream. Data bits are clocked in on falling edge of BCLK in SSI mode and clocked in on the 3/4 bit edge of MCLK in ST-BUS mode.24ADPCMoSerial ADPCM Stream (Output). 128kbps to 4096kbps serial ADPCM word output stream. Data bits are clocked out by rising edge of BCLK in SSI mode and clocked out by MCLK divided by two in ST-BUS mode.252627MS4MS5MS6Mode Selects 4, 5 and 6 (Inputs). Mode selects for all four decoders.MS6MS5MS4MODE 00032kbps ADPCM 00124kbps ADPCM 01016kbps ADPCM in EN1/ENB1 when SEL=0in EN2/ENB2 when SEL=1011ADPCM Bypass for 32kbps and 24kbps 100ADPCM Bypass for 16kbps 101PCM Bypass (64kbps) to PCM1 if SEL=0, PCM2 if SEL=1110Algorithm reset (ITU-T optional reset)111PCMo1/2 disable 28EN2Enable Strobe 2 (Output). This 8 bit wide, active high strobe is active during the B2 PCM channel in ST-BUS mode. Forced to high impedance when LINEAR=1.Pin #Name DescriptionZL38010Data Sheet Functional DescriptionThe Quad-channel ADPCM Transcoder is a low power, CMOS device capable of four encode and four decode operations per frame. Four 64kbps channels (PCM octets) are compressed into four 32, 24 or 16kbps ADPCM channels (ADPCM words), and four 32, 24 or 16kbps ADPCM channels (ADPCM words) are expanded into four 64kbps PCM channels (PCM octets). The ADPCM transcoding algorithm utilized conforms to ITU-T recommendation G.726 (excluding 40kbps), and ANSI T1.303 - 1989. Switching on-the-fly between 32 and 24kbps transcoding is possible by toggling the appropriate mode select pins (supports T1 robbed-bit signalling). All functions supported by the device are pin selectable. The four encode functions comprise a common group controlled via Mode Select pins MS1, MS2 and MS3. Similarly, the four decode functions form a second group commonly controlled via Mode Select pins MS4, MS5 and MS6. All other pin controls are common to the entire transcoder.The device requires 6.5mWatts (MCLK= 4.096MHz) typically for four channel transcode operation. A minimum master clock frequency of 4.096MHz is required for the circuit to complete four encode channels and four decode channels per frame. For SSI operation a master clock frequency greater than 4.096MHz and asynchronous, relative to the 8kHz frame, is allowed.The PCM and ADPCM serial busses support both ST-BUS and Synchronous Serial Interface (SSI) operation. This allows serial data clock rates from 128kHz to 4096kHz, as well as compatibility with Zarlink’s standard Serial Telecom BUS (ST-BUS). For ST-BUS operation, on chip channel counters provide channel enable outputs as well as a 2048kHz bit clock output which may be used by down-stream devices utilizing the SSI bus interface.Linear coded PCM is also supported. In this mode the encoders compress, four 14-bit, two’s complement (S,S,S,12,...,1,0), uniform PCM channels into four 4, 3 or 2 bit ADPCM channels. Similarly, the decoder expands four 4, 3 or 2 bit ADPCM channels into four 16-bit, two’s complement (S,14,...,1,0), uniform PCM channels. The data rate for both ST-BUS and SSI operation in this mode is 2048 kbps.ZL38010Data Sheet Serial (AD)PCM Data I/OSerial data transfer to/from the Quad ADPCM transcoder is provided through one ADPCM and two PCM ports (ADPCMi, ADPCMo, PCMi1, PCMo1, PCMi2, PCMo2). Data is transferred through these ports according to either ST-BUS or SSI requirements. The device determines the mode of operation by monitoring the signal applied to the F0i pin. When a valid ST-BUS frame pulse (244nSec low going pulse) is applied to the F0i pin the transcoder will assume ST-BUS operation. If F0i is tied continuously to V SS the transcoder will assume SSI operation. Pin functionality in each of these modes is described in the following sub-sections.ST-BUS ModeDuring ST-BUS operation the C2o, EN1, EN2 and F0od outputs become active and all serial timing is derived from the MCLK (C4) and F0i inputs while the BCLK input is tied to V SS. (See Figures 7, 8 & 9.)Basic Rate “D” and “C” ChannelsIn ST-BUS mode, when ENB1 is brought low, transparent transport of the ST-BUS "Basic Rate D- and C-channels" is supported through the PCMi1 and PCMo1 pins. This allows a microprocessor controlled device, connected to the PCMi/o1 pins, to access the "D" and "C" channels of a transmission device connected to the ADPCMi/o pins. When ENB1 is brought high, the “D” and “C” channel outputs are tristated. Basic Rate “D” and “C” channels are not supported in LINEAR mode.(See Figure 7.)SSI ModeDuring SSI operation the BCLK, ENB1 and ENB2/F0od inputs become active. The C2o, EN1, and EN2 outputs are forced to a high-impedance state except during LINEAR operation during which the EN1 output remains active. (See Figures 4, 5 & 6.)The SSI port is a serial data interface, including data input and data output pins, a variable rate bit clock input and two input strobes providing enables for data transfers. There are three SSI I/O ports on the Quad ADPCM; the PCMi/o1 PCM port, the PCMi/o2 PCM port, and the ADPCMi/o port. The two PCM ports may transport 8-bit companded PCM or 16-bit linear PCM. The alignment of the channels is determined by the two input strobe signals ENB1 and ENB2/F0od. The bit clock (BCLK) and input strobes (ENB1 and ENB2/F0od) are common for all three of the serial I/O ports. BCLK can be any frequency between 128kHz and 4096kHz synchronized to the input strobes. BCLK may be discontinuous outside of the strobe boundaries except when LINEAR=1. In LINEAR mode, BCLK must be 2048kHz and continuous for 64 cycles after the ENB1 rising edge and for the duration of ENB2/F0od. Mode Select Operation (MS1, MS2, MS3, MS4, MS5, MS6)Mode Select pins MS1, MS2 and MS3 program different bit rate ADPCM coding, bypass, algorithmic reset and disable modes for all four encoder functions simultaneously. When 24kbps ADPCM mode is selected bit 4 is unused while in 16kbps ADPCM mode all ADPCM channels are packed contiguously into one 8-bit octet. Mode Select pins MS4, MS5 and MS6 operate in the same manner for the four decode functions. The mode selects must be set up according to the timing constraints illustrated in Figures 16 and 17.32 kbps ADPCM ModeIn 32kbps ADPCM mode, the 8-bit PCM octets of the B1, B2, B3 and B4 channels (PCMi1 and PCMi2) are compressed into four 4-bit ADPCM words on ADPCMo. Conversely, the 4-bit ADPCM words of the B1, B2, B3 and B4 channels from ADPCMi are expanded into four 8-bit PCM octets on PCMo1 and PCMo2. The 8-bit PCM octets (A-Law or µ-Law) are transferred most significant bit first starting with b7 and ending with b0. ADPCM words are transferred most significant bit first starting with I1 and ending with I4 (See Figures 4 & 7). Reference ITU-T G.726 for I-bit definitions.ZL38010Data Sheet24 kbps ADPCM ModeIn 24kbps mode PCM octets are transcoded into 3-bit words rather than the 4-bit words utilized in 32kbps ADPCM. This is useful in situations where lower bandwidth transmission is required. Dynamic operation of the mode select control pins will allow switching from 32kbps mode to 24kbps mode on a frame by frame basis. The 8 bit PCM octets (A-Law or µ-Law) are transferred most significant bit first starting with b7 and ending with b0. ADPCM words are transferred most significant bit first starting with I1 and ending with I3 (I4 becomes don’t care). (See Figures 4 & 7.)16 kbps ADPCM ModeWhen SEL is set to 0, the 8-bit PCM octets of the B1, B2, B3 and B4 channels (PCMi1 and PCMi2) are compressed into four 2-bit ADPCM words on ADPCMo during the ENB1 timeslot in SSI mode and during the B1 timeslot in ST-BUS mode. Similarly, the four 2-bit ADPCM words on ADPCMi are expanded into four 8-bit PCM octets (on PCMo1 and PCMo2) during the ENB1/B1 timeslot. (See Figures 4 & 7.)When SEL is set to 1, The same conversion takes place as described when SEL = 0 except that the ENB2/B2 timeslots are utilized.A-Law or µ-Law 8-bit PCM are received and transmitted most significant bit first starting with b7 and ending with b0. ADPCM data are most significant bit first starting with I1 and ending with I2.ADPCM BYPASS (32 and 24 kbps)In ADPCM bypass mode the B1 and B2 channel ADPCM words are bypassed (with a two-frame delay) to/from the ADPCM port and placed into the most significant nibbles of the PCM1/2 port octets. Note that the SEL pin performs no function for these two modes (See Figures 6 & 9). LINEAR, FORMAT and A/µ pins are ignored in bypass mode. In 32kbps ADPCM bypass mode, Bits 1 to 4 of the B1, B2, B3 and B4 channels from PCMi1 and PCMi2 are transparently passed, with a two frame delay, to the same channels on ADPCMo. In the same manner, the B1, B2, B3 and B4 channels from ADPCMi are transparently passed, with a two frame delay, to the same channels on PCMo1 and PCMo2 pins. Bits 5 to 8 are don’t care. This feature allows two voice terminals, which utilize ADPCM transcoding, to communicate through a system without incurring unnecessary transcode conversions. This arrangement allows byte-wide or nibble-wide transport through a switching matrix.24kbps ADPCM bypass mode is the same as 32 kbps mode bypass excepting that only bits 1 to 3 are bypassed and bits 4 to 8 are don’t care.ADPCM BYPASS (16 kbps)When SEL is set to 0, only bits 1 and 2 of the B1, B2, B3 and B4 PCM octets (on PCMi1 and PCMi2) are bypassed, with a two frame delay, to the same channels on ADPCMo during the ENB1 timeslot in SSI mode and during the B1 timeslot in ST-BUS mode. Similarly, the four 2-bit ADPCM words on ADPCMi are transparently bypassed, with a two frame delay, to PCMo1 and PCMo2 during the ENB1 or B1 timeslot. Bits 3-8 are don’t care. (See Figures 6 & 9.)When SEL is set to 1, the same bypass occurs as described when SEL = 0 except that the ENB2 or B2 timeslots are utilized.LINEAR, FORMAT and A/µ pins are ignored in bypass mode.ZL38010Data SheetPCM BYPASSWhen SEL is set to 0, the B1 and B2 PCM channels on PCMi1 are transparently passed, with a two-frame delay, to the same channels on the ADPCMo. Summarily, the two 8-bit words which are on ADPCMi are transparently passed, with a two-frame delay, to channels B1 and B2 of PCMo1 while PCMo2 is set to a high-impedance state.(See Figures 6 & 9.)When SEL is set to 1, the B3 and B4 channels on PCMi2 are transparently passed, with a two frame delay, to the same channels on ADPCMo. Similarly, the two 8-bit words which are on ADPCMi are transparently passed, with a two-frame delay, to channels B3 and B4 of PCMo2. In this case PCMo1 is always high-impedance if ENB1 = 0. If ENB1 = 1 during ST-BUS operation then the D and C channels are active on PCMo1.LINEAR, FORMAT and A/µ pins are ignored in bypass mode.Algorithm Reset ModeWhile an algorithmic reset is asserted the device will incrementally converge its internal variables to the 'Optional reset values' stated in G.726. Algorithmic reset requires that the master clock (MCLK) and frame pulse (ENB1/2 or F0i) remain active and that the reset condition be valid for at least four frames. Note that this is not a power down mode; see PWRDN for this function.ADPCMo & PCMo1/2 DisableWhen the encoders are programmed for ADPCMo disable (MS1 to MS3 set to 1) the ADPCMo output is set to a high impedance state and the internal encode function remains active. Therefore convergence is maintained. The decode processing function and data I/O remain active.When the decoders are programmed for PCMo1/2 disable (MS4 to MS6 set to 1) the PCMo1/2 outputs are high impedance during the B Channel timeslots and also, during ST-BUS operation, the D and C channel timeslots according to the state of ENB1. Therefore convergence is maintained. The encode processing function and data I/O remain active.Whenever any combination of the encoders or decoders are set to the disable mode the following outputs remain active. A) ST-BUS mode: ENB2/F0od, EN1, EN2 and C2o. Also the “D” and “C” channels from PCMo1 and ADPCMo remain active if ENB1 is set to 0. If ENB1 is brought high then PCMo1 and ADPCMo are fully tri-stated. B) SSI mode: When used in the 16-bit linear mode, only the EN1 output remains active. For complete chip power down see PWRDN.ZL38010Data Sheet Other Pin Controls16 Bit Linear PCMSetting the LINEAR pin to logic one causes the device to change to 16-bit linear (uniform) PCM transmission on the PCMi/o1 and PCMi/o2 ports. The data rate for both ST-BUS and SSI operation in this mode is 2048 kbps and all decode and encode functions are affected by this pin. In SSI mode, the input channel strobes ENB1 and ENB2/F0od remain active for 8 cycles of BCLK for an ADPCM transfer. The EN1 output is high for one BCLK period at the end of the frame (i.e., during the 256th BCLK period). In ST-BUS mode, the output strobes EN1 and ENB2/F0od are adjusted to accommodate the required PCM I/O streams. The EN1 output becomes a single bit high true pulse during the last clock period of the frame (i.e., the 256th bit period) while ENB2/F0od becomes a delayed, low true frame-pulse (F0od) output occurring during the 64th bit period after the EN1 rising edge.Linear PCM on PCMi1 and PCMi2, are received as 14-bit, two’s complement data with three bits of sign extension in the most significant positions (i.e., S,S,S,12,...1,0) for a total of 16 bits. The linear PCM data transmitted from PCMo1 and PCmo2 are 16-bit, two’s complement data with one sign bit in the most significant position (i.e., S,14,13,...1,0)32 and 24 kbps ADPCM modeIn 32kbps and 24kbps linear mode, the 16-bit uniform PCM dual-octets of the B1, B2, B3 and B4 channels (from PCMi1 and PCMi2) are compressed into four 4-bit words on ADPCMo. The four 4-bit ADPCM words of the B1, B2, B3 and B4 channels from ADPCMi are expanded into four 16-bit uniform PCM dual-octets on PCMo1 and PCMo2. 16-bit uniform PCM are received and transmitted most significant bit first starting with b15 and ending with b0. ADPCM data are transferred most significant bit first starting with I1 and ending with I4 for 32kbps and ending with I3 for 24kbps operation (i.e., I4 is don’t care).(See Figures 5 & 8.)16 kbps ADPCM modeWhen SEL is set to 0, the four, 2-bit ADPCM words are transmitted/received on ADPCMo/i during the ENB1 time-slot in SSI mode and during the B1 timeslot in ST-BUS mode. When SEL is set to 1, the four, 2-bit ADPCM words are transmitted/received on ADPCMo/i during the ENB2 timeslot in SSI mode and during the B2 timeslot in ST-BUS mode. (See Figures 5 & 8.)PCM Law Control (A/µ, FORMAT)The PCM companding/coding law invoked by the transcoder is controlled via the A/µ and FORMAT pins. ITU-T G.711 companding curves, µ-Law and A-Law, are selected by the A/µ pin (0=µ-Law; 1=A-Law). Per sample, digital code assignment can conform to ITU-T G.711 (when FORMAT=1) or to Sign-Magnitude coding (when FORMAT=0). Table 1 illustrates these choices.ZL38010Data SheetTable 1 - Companded PCMPower DownSetting the PWRDN pin low will asynchronously cause all internal operation to halt and the device to go to a power down condition where no internal clocks are running. Output pins C2o, EN1, EN2, PCMo1, PCMo2 and ADPCMo and I/O pin F0od/ENB2 are forced to a high-impedance state. Following the reset (i.e., PWRDN pin brought high)and assuming that clocks are applied to the MCLK and BCLK pins, the internal clocks will still not begin to operate until the first frame alignment is detected on the ENB1 pin for SSI mode or on the F0i pin for ST-BUS mode. The C2o clock and EN1, EN2 pins will not start operation until a valid frame pulse is applied to the F0i pin. If the F0i pin remains low for longer than 2 cycles of MCLK then the C2o pin will top toggling and will stay low. If the F0i pin is held high then the C2o pin will continue to operate. In ST-BUS mode the EN1 and EN2 pins will stop toggling if the frame pulse (F0i) is not applied every frame.Master Clock (MCLK)A minimum 4096kHz master clock is required for execution of the transcoding algorithm. The algorithm requires 512 cycles of MCLK during one frame for proper operation. For SSI operation this input, at the MCLK pin, may be asynchronous with the 8kHz frame provided that the lowest frequency and deviation due to clock jitter still meets the strobe period requirement of a minimum of 512 t C4P - 25%t C4P (see Figure 3). For example, a system producing large jitter values can be accommodated by running an over-speed MCLK that will ensure a minimum 512 MCLK cycles per frame is obtained. The minimum MCLK period is 61nSec, which translates to a maximum frequency of 16.384MHz. Extra MCLK cycles (>512/frame) are acceptable since the transcoder is aligned by the appropriate strobe signals each frame.Figure 3 - MCLK Minimum RequirementFORMAT01PCM CodeSign-Magnitude A/µ = 0 or 1ITU-T (G.711)(A/µ = 0)(A/µ = 1)+ Full Scale 1111 11111000 00001010 1010+ Zero 1000 00001111 11111101 0101- Zero 0000 00000111 11110101 0101- Full Scale0111 11110000 00000010 1010ENB1MCLK512 t C4P - 25%t C4P MinimumZL38010Data Sheet Bit Clock (BCLK)For SSI operation the bit rate, for both ADPCM and PCM ports, is determined by the clock input at BCLK. BCLK must be eight periods in duration and synchronous with the 8kHz frame inputs at ENB1 and ENB2. Data is sampled at PCMi1/2 and at ADPCMi concurrent with the falling edge of BCLK. Data is available at PCMo1/2 and ADPCMo concurrent with the rising edge of BCLK. BCLK may be any rate between 128kHz and 4096kHz. For ST-BUS operation BCLK is ignored (tie to V SS) and the bit rate is internally set to 2048kbps.Figure 4 - SSI 8-Bit Companded PCM Relative TimingZL38010Data SheetFigure 5 - SSI 16-Bit Linear PCM Relative TimingZL38010Data SheetFigure 6 - SSI PCM and ADPCM Bypass Relative TimingZL38010Data SheetFigure 7 - ST-BUS 8-Bit Companded PCM Relative TimingZL38010Data SheetFigure 8 - ST-BUS 16-Bit Linear PCM Relative TimingZL38010Data SheetFigure 9 - ST-BUS PCM and ADPCM Bypass Relative TimingZL38010Data Sheet Processing Delay Through the DeviceIn order to accommodate variable rate PCM and ADPCM interfaces, the serial input and output streams require a complete frame to load internal shift registers. Internal frame alignment of the encoding/decoding functions are taken from either of the F0i or ENB1 & ENB2 input strobes depending upon the device operating mode (i.e., ST-BUS or SSI). The encoding/decoding of all channels then takes one frame to complete before the output buffers are loaded. This results in a two frame transcoding delay. The two frame delay also applies to the D and C channels and to the PCM and ADPCM bypass functions.(See Figure 10.)Note: When changing the relative positions of the ENB1 and ENB2 strobes, precaution must be taken to ensure that two conditions are met. They are:1.There must be at least 512 master clock cycles between consecutive rising edges of ENB1. This condition alsoholds true for ENB2.2.The ENB1 strobe must alternate with the ENB2 strobe.Violation of these requirements may cause noise on the output channels.Figure 10 - Data ThroughputApplicationsFigure 11 depicts an ISDN line card utilizing a ’U’ interface transceiver and ZL38010 ADPCM transcoder. This central office application implements the network end of a Pair-Gain system. Figure 12 shows Zarlink devices used to construct the remote Pair-Gain loop terminator.。
43860-0016中文资料
FEATURES AND SPECIFICATIONSModular Jack43860Right Angle, Low Profile Inverted Shielded and Unshielded Versions with Low or High Temperature LightpipesFeatures and Benefits s Plug latch on tops Lightpipes molded in low- or high-temperature materials s Lower electrical noise than LED offerings s 34% fewer leads than LED offerings s Enhanced grounding tabs on shields Surface Mount Compatible for high temperature lightpipe versions Shortened leads with bottom contacts Reference InformationProduct Specification: PS-43860-003ElectricalElectrical Voltage: 125V Current: 1.5A max.Contact Resistance: 10m Ω max.Dielectric Withstanding Voltage: 1000V AC Insulation Resistance: 500 M Ω min.MechanicalDurability: 500 cyclesPhysicalHousing: Black glass-filled, high-temperature nylon, UL 94V-0Plating: Contact area—1.27µm (50µ") min. GoldORDERING INFORMATION AND DIMENSIONSLow TemperatureHigh TemperatureCircuits Loaded ContactsOrder No.DimensionUnshielded ShieldedA B C D With All Panel Grounding Tabs With Offset Panel Grounding Tabs6443860-000915.17 (.670)3.07 (.120)9.88 (.389)13.21 (.520)6443860-001216.18 (.637) 3.07 (.120)9.88 (.389)13.53 (.533)6443860-001816.18 (.637) 3.07 (.120)9.88 (.389)13.53 (.533)6643860-000815.17 (.670) 5.09 (.200)9.88 (.389)13.21 (.520)6643860-001116.18 (.637) 5.09 (.200)9.88 (.389)13.53 (.533)6643860-001716.18 (.637) 5.09 (.200)9.88 (.389)13.53 (.533)8843860-000715.17 (.670)7.11 (.280)11.91 (.469)13.21 (.520)8843860-001016.18 (.637)7.11 (.280)11.91 (.469)13.53 (.533)8843860-001616.18 (.637)7.11 (.280)11.91 (.469)13.53 (.533)Circuits Loaded ContactsOrder No.DimensionWith All Panel Grounding Tabs With Offset Panel Grounding TabsA B C D 6443860-101216.18 (.637) 3.07 (.120)9.88 (.389)13.53 (.533)6443860-101816.18 (.637) 3.07 (.120)9.88 (.389)13.53 (.533)6643860-101116.18 (.637) 5.09 (.200)9.88 (.389)13.53 (.533)6643860-101716.18 (.637) 5.09 (.200)9.88 (.389)13.53 (.533)8843860-101016.18 (.637)7.11 (.280)11.91 (.469)13.53 (.533)8843860-101616.18 (.637)7.11 (.280)11.91 (.469)13.53 (.533)网Molex's New Modular Jacks With Lightpipes Reduce EMI/RFI Over 50%Molex Incorporated introduces a new inverted right angle modular jack with lightpipes that significantly reduces the noise created by the "antenna" effect of LED leads incorporated into the modular jack. The lightpipes direct the light emitted from the LEDs mounted on the PC board rather than using conventional LEDs mounted in the modular jacks. This design maintains signal integrity since there is no interference from LED leads. Because the LEDs are located on the PC board, you can select the colors used for the LEDs. Unlike typical LED modular jacks, you are not restricted to the standard green, yellow or orange LEDs. The combination of PC board mounted LEDs and lightpipes results in less noise being radiated though transmission lines.The inverted modular jacks with lightpipes are available in through hole styles for wave soldering or a high temperature version for reflow soldering. The high-temperature version maintains performance at a +260°C reflow solderingtemperature for 1 minute without deforming the modular jack or lightpipe. Shielded and unshielded offerings are available for both RJ11 and RJ45 configurations for the standard through hole version and a shielded modular jack is offered with the high temperature lightpipes.Features and Benefitss Signal integrity remains high due to no interference from LED leadss Lightpipes reduce the electronic noise from LEDs by as much as 50%s The inverted RJ45 Lightpipe modular jack provides Cate-gory 5 performance for fast Ethernet applicationss Meets FCC 68.5 specification when plating selection is 50µ" of gold (30 and 15µ" of gold plating are also available) s Each Molex modular jack is 100% electronically tested to detect possible shorting conditions before the product is shippeds Plug latch on top of jack provides easy thumb depression for mating and unmatings Inventory can be reduced by not stocking modjacks with different colored LEDsTypical Applicationss Networking Products (Hubs, Routers, Switches, and Bridges)s Security Systemss Multimedia Set-Top Boxes (Interactive) s Mini-PCIs Home Office Routers and Hubs sModemsAmericas Headquarters Lisle, Illinois 60532 U.S.A.Tel: 1-800-78MOLEX Fax: 630-969-1352 Far East North Headquarters Yamato, Kanagawa, Japan Tel: 81-462-65-2324Fax: 81-462-65-2366 Far East South Headquarters Jurong, Singapore Tel: 65-268-6868Fax: 65-265-6044 European Headquarters Munich, Germany Tel: 49-89-413092-0Fax: 49-89-401527Corporate Headquarters 2222 Wellington Ct.Lisle, IL 60532 U.S.A.Tel: 630-969-4550 Fax: 630-969-1352Visit our Web site at http: //Order No. USA-062Printed in USA/5K/JI/JI/99.08©1999, Molex网。
板料
111-000000057-0A 板料 五金 板料 SECC(电解板) 1.2 1250 2030 本色 SECC-O 外购件 无需首件 PCS 原材料 五金原料仓
111-000000068-0A 板料 五金 板料 SECC(电解板) 1 628 202 本色 外购件 无需首件 PCS 原材料 五金原料仓
111-000000071-0A 板料 五金 板料 SECC(电解板) 1 222 145 -000000033-0A 板料 五金 板料 SECC(电解板) 1 1219 560 本色 外购件 无需首件 PCS 原材料 五金原料仓
111-000000034-0A 板料 五金 板料 SECC(电解板) 1 1250 550 本色 外购件 无需首件 PCS 原材料 五金原料仓
111-000000043-0A 板料 五金 板料 SECC(电解板) 1 391.5 550 本色 外购件 无需首件 PCS 原材料 五金原料仓
111-000000044-0A 板料 五金 板料 SECC(电解板) 1 628 50.5 本色 外购件 无需首件 PCS 原材料 五金原料仓
111-000000031-0A 板料 五金 板料 SECC(电解板) 1 827 537 本色 外购件 无需首件 PCS 原材料 五金原料仓
111-000000032-0A 板料 五金 板料 SECC(电解板) 1 1219 550 本色 外购件 无需首件 PCS 原材料 五金原料仓
111-000000050-0A 板料 五金 板料 SECC(电解板) 1 419.5 550 本色 外购件 无需首件 PCS 原材料 五金原料仓
SMA-C04产品规格书说明书
SMA-C04 产品规格书版本V1.0版权© 2018关于本手册本手册介绍了SMA-C04模块产品特性、电气特性、管脚布局及定义、功能描述、射频指标、尺寸图，包含以下章节。
章标题内容第1章产品简介概述SMA-C04模块的特点和应用第2章产品展示展示实际产品图片及特性说明第3章电气特性列出产品的基本参数第4章管脚定义提供管脚布局、定义及管脚功能说明第5章功能描述模块功能描述及具体说明第6章射频指标提供模块射频特性表第7章尺寸图提供了模块的尺寸图发布说明日期标题发布说明编制审核2018.3.24 V1.0 首次发布张少茹武鹏飞1. 产品简介SMA-C04是一款基于ESP8285的超低功耗的Wi-Fi四通道开关模块，拥有业内极富竞争力的封装尺寸和超低能耗技术，专为移动设备和物联网应用设计，可将用户的物理设备连接到Wi-Fi无线网络上，进行互联网或局域网通信，实现联网功能。
该模块可以作为4个家用电器的开关控制。
既可以通过本地的按键控制，也可以通过连接APP （易微联）远程控制。
SMA-C04可广泛应用于智能电网、智能交通、智能家具、手持设备、工业控制等领域。
2. 产品展示图 1 SMA-C04正面展示图 2 SMA-C04反面展示产品特性● 3.3VDC供电，最大工作电流210mA；●内置32位MCU，可兼作应用处理器；●支持无线802.11 b/g/n 标准；●************，支持WPA/WPA2 安全模式；●802.11b 模式下+20.5dBm的输出功率；●四通道控制；●支持本地硬件开关控制；●支持Wi-Fi远程控制；●APP支持安卓、iOS系统；●主要应用领域：智能电网、智能交通、智能家居、手持设备及工控领域。
3. 电气特性3.1 额定参数条件：VDD=3.3V±10%，GND=0V；室温25°C下测试。
表 1 额定参数说明类型参数模块型号SMA-C04主芯片ESP8285硬件参数硬件接口UART，GPIO工作电压 2.7V~3.6VGPIO驱动能力Max：12mA工作电流平均电流：≈80mA最大工作电流：210mA待机：<200uA工作温度-40℃~125℃存储环境温度：<40℃，相对湿度：<90%RH 尺寸大小15mm×15mm×1.0mm软件参数无线网络类型STA/AP/STA+AP安全机制WEP/WPA-PSK/WPA2-PSK 加密类型WEP64/WEP128/TKIP/AES 固件升级OTA远程升级3.2 Wi-Fi参数条件：VDD=3.3V±10%，GND=0V；室温25°C下测试。
DGT801系列技术说明书1
DGT801系列数字式发电机变压器组保护装置技术说明书V1.2.1国电南京自动化股份有限公司国电南自凌伊电力自动化有限公司2005年7月本说明书可能被修改，请注意最新版本资料更多产品信息，请访问互联网：技术支持：TEL：025－－601，FAX：025－国电南自技术部监制目录1 概述 (1)1.1 DGT801系列装置简介 (1)1.2应用范围 (1)1.3保护功能 (2)2 装置性能特点 (6)2.1 双电源双CPU系统硬件结构 (6)2.2 高性能的硬件平台 (6)2.3 独创的双CPU并行处理技术 (6)2.4 独创的双回路直流电源供电 (7)2.5 完善的自检及互检功能 (8)2.6 信号出口指示直观明确 (8)2.7 保护压板和出口压板独立设置，状态明确指示 (9)2.8 友好的人机界面，装置全透明化 (9)2.9 强大的通讯功能 (9)2.10 强抗干扰能力 (9)2.11 保护功能齐全 (9)2.12 保护配置灵活可靠 (9)2.13 保护采用新原理、新技术 (10)2.14 先进的软件设计技术 (10)2.15 发电机差动保护和变压器差动的特性 (10)2.16 专用定子匝间保护特性 (10)2.17 定子接地保护特性 (11)2.18 转子接地保护特性 (11)2.19 失磁保护特性 (11)2.20 失步保护特性 (12)2.21 后备保护类型可灵活配置 (12)2.22后备保护类型可灵活配置 (12)3 配置方案 (13)3.1 600MW（300MW）—500kV发变组单元接线保护配置（双重化的双套配置） (13)3.2 300MW—220kV发变组保护配置方案1（双重化的双套配置） (15)3.3 300MW—220kV发变组保护配置方案2（单套化） (17)3.4 125MW机组（三卷变压器）保护配置方案1（双重化的双套配置） (19)3.5 125MW机组（三卷变）保护配置方案2（单套化） (20)3.6 双套化配置方案中高厂变高压侧TA配置说明 (24)4 技术参数 (27)4.1 机械及工作环境参数 (27)4.2 储存、运输极限环境温度和工作使用地点要求 (27)4.3 额定电气参数 (27)4.4 功率消耗 (27)4.5 过载能力 (27)4.6 绝缘性能 (28)4.7 抗干扰性能 (28)4.8 直流电源影响 (28)4.9 连续通电 (28)5 保护的主要技术指标 (29)5.1 发电机纵差动（循环闭锁出口方式） (29)5.2 发电机纵差动（单相出口方式）、发电机不完全差动、发电机裂相横差、励磁机差动、电缆差 (29)5.3 发变组差动、变压器差动（包括主变、厂变、励磁变、备变） (29)5.4 发电机高灵敏横差保护 (30)5.5 发电机纵向零序电压匝间保护 (30)5.6 发电机故障分量负序方向匝间保护 (30)5.7 发电机3U0定子接地保护 (30)5.8发电机三次谐波式定子接地保护 (30)5.9 发电机3I0定子接地保护 (31)5.10 发电机转子一点接地保护 (31)5.11 发电机转子二点接地保护 (31)5.12 发电机对称过负荷保护（定、反时限） (31)5.13 发电机负序过负荷保护（定、反时限） (31)5.14 发电机失磁保护（阻抗原理） (31)5.15 发电机失磁保护（逆无功原理） (32)35.16 发电机失步保护 (32)5.17 发电机过电压低电压保护 (32)5.18 发电机过激磁保护（定、反时限） (33)5.19 发电机逆功率、低功率保护 (33)5.20 发电机频率异常保护 (33)5.21 发电机励磁回路过负荷（交流）保护（定、反时限） (33)5.22 发电机励磁回路过负荷（直流）保护（定、反时限） (33)5.23 发电机误上电保护 (34)5.24 发电机启停机保护 (34)5.25 发电机轴电流保护 (34)5.26 发电机次同步过流保护 (34)5.27 电压闭锁过电流保护（包括发电机、主变、厂变、备变） (34)5.28阻抗保护（包括发电机、变压器） (34)5.29 变压器零序电流保护 (35)5.30 变压器间隙零序保护 (35)5.31 变压器通风启动 (35)5.32 断路器失灵启动保护 (35)5.33 断路器非全相保护 (35)5.34 变压器电压闭锁方向过流保护 (35)5.35 变压器零序方向过流保护 (36)5.36 变压器负序方向过流保护 (36)5.37 非电量保护 (36)6 保护原理及逻辑说明 (37)6.1 发电机纵差动保护 (37)6.2 变压器纵差动保护（包括发变组、主变、厂变、励磁变、启备变） (42)6.3 变压器零序差动保护 (49)6.4 发电机横差保护 (51)6.5 励磁机差动保护 (56)6.6 发电机纵向零序电压式匝间保护 (57)6.7 发电机基波零序电压式定子接地保护 (60)6.8 发电机三次谐波电压式定子接地保护 (63)6.9 发电机零序电流式定子接地保护 (65)6.10 发电机注入式转子一点接地保护 (66)6.11 发电机转子两点接地保护 (67)6.12 发电机失磁保护（阻抗原理） (68)6.13 发电机失磁保护（逆无功原理） (72)6.14 发电机失步保护 (74)6.15 发电机逆功率保护和程跳逆功率保护 (78)6.16 发电机频率异常保护 (79)6.17 过激磁保护（包括发电机、变压器） (81)6.18 发电机过电压保护 (84)6.19 发电机过负荷及过电流保护（定时限） (85)6.20 发电机负序过负荷及负序过流保护（定时限） (86)6.21 发电机反时限对称过负荷保护 (87)6.22 发电机反时限不对称过负荷保护 (89)6.23 发电机转子绕组过负荷及过流保护 (92)6.24电压闭锁过流保护（包括发电机、主变、厂变、启备变） (95)6.25 发电机轴电压和轴电流保护 (98)6.26 低电流保护 (100)6.27 阻抗保护（包括发电机、变压器） (100)6.28 变压器间隙零序保护 (103)6.29 变压器零序电流保护（包括主变、厂变、备变） (104)6.30 变压器零序方向过流保护 (106)6.31 负序方向过流保护 (107)6.32 变压器方向过流保护 (109)6.33 变压器电压闭锁方向过流保护 (111)6.34 发电机误上电保护及断路器闪络保护 (113)6.35双分支电压闭锁过流保护（包括高厂变、启备变） (116)6.36高压侧断路器失灵启动保护 (118)6.37 非全相保护 (120)6.38 电压平衡式TV断线判别 (121)6.39 非电量保护 (122)5·概述·1 概述本说明书为DGT801A、DGT801B、DGT801C、DGT801F数字式发电机变压器组保护装置的技术说明部分。
EP4CE6E22C8中文资料（Altera）中文数据手册「EasyDatasheet-矽..
1.Cyclone IV器件手册December 2013CYIV-53001-1.8CYIV-53001-1.8本章介绍了电气和开关特性旋风IV设备.电气特性包括操作条件和功耗.开关特性包括收发信机的规格,核心,和外围性能.本章还介绍了I / O定时,包括可编程I / O单元（IOE）延迟和可编程输出缓冲延迟.本章包括以下几个部分：■■■■■1-1页上的“工作条件”“功耗”第1-14页“开关特性”第1-14页“I / O时序”1-37页1-37页上的“词汇表”运行条件当Cyclone IV器件在一个系统中实现,它们是根据一组定义的参数的分级.为了保持CycloneIV器件中最高的性能和可靠性,您必须考虑本章所述的操作要求.Cyclone IV器件在商业,工业,延伸产业和汽车级版本. Cyclone IV E器件提供-6（最快）,-7,-8,-8L和-9L速度等级的商用设备,-8L速度等级为工业设备,以及用于扩展工业和汽车设备-7速度等级. Cyclone IV GX器件提供-6（最快）,-7和-8速度等级的商用设备和-7为工业设备的速度等级.f有关支持的速度牌号为各自的Cyclone IV更多信息设备,指的是Cyclone IV FPGA器件系列简介一章.1Cyclone IV E器件均提供了 1.0和1.2与1.0伏的核心电压V. Cyclone IV E器件的核心电压已经连接到速度等级为“L”字头.在这一章中,与工作温度范围相关联的前缀所连接到速度等级;商业用“C”字头,工业用“I”前缀,汽车有一个“A”字头.因此,商用设备被表示为C6,C7,C8,C8L,或C9L每各自的速率等级.工业设备被表示为I7,I8,或I8L.汽车设备被表示为A7.芯片中文手册,看全文,戳1–２第1章：Cyclone IV器件手册运行条件1Cyclone IV E工业设备I7提供具有扩展的工作温度范围.绝对最大额定值绝对最大额定值规定的最大工作条件Cyclone IV器件.该值是基于与所述设备和击穿和损伤机理理论模型进行的实验.该装置的功能操作不在这些条件暗示.表1-1列出的绝对对于Cyclone IV器件最大额定值.c超出所列条件表1-1对器件造成永久性损坏.此外,在延长的时间周期的绝对最大额定值设备操作具有设备上的不良影响.表1-1.对Cyclone IV器件绝对最大额定值(1)符V CCINTV CCAV CCD_PLL V CCIOV CC_CLKIN V CCH_GX BV CCA_GX BV CCL_GX B V II OUTT ST GT J参数内核电压,PCI Express的(PCIe）硬IP块,和收发器物理编码子层（PCS）电源Phase-锁相环（PLL）模拟电源PLL数字供电I / O组电源差分时钟输入引脚供电收发器输出缓冲器电源收发器物理介质附加（PMA）和辅助电源收发器PMA和辅助电源直流输入电压直流输出电流,每个引脚储存温度工作结温Min–0.5–0.5–0.5–0.5–0.5–0.5–0.5–0.5–0.5–25–65–40Max1.83.754.53.754.53.753.751.84.240150125UnitVVVVVVVVVmA°Ｃ°Ｃ注意表1-1：（1）电源电压规格适用于电压器件引脚采取相对于地面,而不是在读电源.最大允许过冲或冲电压在转换过程中,输入信号可以过冲到中所示的电压表1-2and冲至-2.0 V的电流小于100mA的幅度和周期小于20纳秒短.表1-2列出所允许的最大输入电压的过冲和过冲电压作为在装置的寿命的百分比的持续时间.允许的最大过冲的持续时间被指定为高的时间比设备的寿命百分比.芯片中文手册,看全文,戳第1章：Cyclone IV器件手册运行条件1–３1DC信号是相当于100％占空比.例如,过冲,以4.3V的信号只能是在 4.3V的用于在装置的寿命为65％;为10年的设备使用寿命,这相当于一年65 /十分之.表1-2.最大允许过冲在转换过程中,在10-期限完成Cyclone IV器件符参数条件（V）V I= 4.20V I= 4.25V I= 4.30V i 交流输入电压V I= 4.35V I= 4.40V I= 4.45V I= 4.50V I= 4.55V I= 4.60过冲持续时间为％高时间10098654329201396Unit%%%%%%%%%图1-1示出的方法来确定过冲持续时间.该过冲电压示于红色和存在于的气旋IV输入引脚设备超过4.3V,但低于4.4 V.从表1-2,为4.3伏,所述过冲高时间过冲比例可高达65％,超过10年的时间.高时间百分比的计算公式为（δT] / T）×100.这10年的时间就认定该设备始终是打开的,100％I / O触发率和50％占空比信号.对于较低的I / O触发率和情况,其中设备处于空闲状态,寿命增加.图1-1. Cyclone IV器件超调时间4.4 V4.3 V3.3 VDTT芯片中文手册,看全文,戳1–４第1章：Cyclone IV 器件手册运行条件推荐工作条件本节列出了AC 和DC 参数功能操作界限Cyclone IV 器件.表1-3and 表1-4列出的稳态电压和电流从的Cyclone IV E 和Cyclone IV GX 器件的预期值.所有物资必须是没有高原严格单调.表1-3.推荐工作条件Cyclone IV E 器件(1),符参数电源电压为内部逻辑,1.2-V操作电源电压为内部逻辑,1.0-V 操作电源电压为输出缓冲器,3.3-V 操作电源电压为输出缓冲器,3.0-V 操作电源电压为输出缓冲器,2.5-V操作电源电压为输出缓冲器,1.8-V 操作电源电压为输出缓冲器,1.5-V 操作电源电压为输出缓冲器,1.2-V 操作V CCA (3)(2)（第2部1）Min 1.150.973.1352.852.3751.711.4251.142.3751.150.97–0.500–40–40–4050 μｓ50 μｓTyp 1.21.03.332.51.81.51.22.51.21.0————————Max 1.251.033.4653.152.6251.891.5751.262.6251.251.033.6V CCIO 8510012512550毫秒3毫秒UnitVV V V VV V VV VVV V°Ｃ°Ｃ°Ｃ°Ｃ——条件—————————————对于商业用途工业用对于扩展温度(5)对于汽车使用标准的上电复位(POR)(6)快速POR (7)V CCINT (3)V CCIO (3), (4)供应（模拟）电压PLL调节器供应（数字）电压PLL,1.2-V 操作供应（数字）电压PLL,1.0-V 操作输入电压输出电压V CCD_PLL (3)V I V O T J 工作结温t RAM P 电源斜坡时间第1章：Cyclone IV器件手册运行条件1–５表1-3.推荐工作条件Cyclone IV E器件(1),符I Diode参数直流电流的幅度的PCI-钳位二极管时启用条件—(2)（2/2）Min—Typ—Max10UnitmA须知表1-3：（1）Cyclone IV E 1.0V的核心电压设备仅支持C8L,C9L和I8L速度等级.Cyclone IV E 1.2 V内核电压设备只支持C6,C7,C8,I7和A7速度等级.(2) V CCIO所有I / O块设备的操作过程中都必须启动.都VCCA管脚必须供电到 2.5 V（即使不使用锁相环）并且必须加电并断电的同时.(3) V CC必须上升单调.(4) V CCIO权力全部输入缓冲器.（5）设备支持扩展的工作结温的I7高达125°Ｃ（正常范围为-40°Ｃ至100°Ｃ）.当在使用I7设备更宽的结温范围为-40°Ｃ至125°C,在Quartus设计时选择C8作为目标设备II的软件.该I7设备满足所有C8时序规格,当I7设备使用超过100°Ｃ和高达125°C.（6）上电复位时间标准POR介于50和200毫秒.每个单独的电源必须达到推荐的工作范围在50毫秒内.（7）上电复位时间,快速POR范围9之间3毫秒.每个单独的电源必须达到在推荐的工作范围3毫秒.表1-4.推荐工作条件Cyclone IV GX器件（第2第1部分）符V CCINT V CCA (3)参数核心电压,PCIe硬核IP模块,和收发器PCS电源PLL模拟电源PLL数字供电3.3 I / O插槽电源-V手术3.0 I / O插槽电源-V手术2.5 I / O插槽电源-V手术1.8 I / O插槽电源-V手术1.5 I / O插槽电源-V手术1.2 I / O插槽电源-V手术差分时钟输入引脚电源供应3.3-V工作电压差分时钟输入引脚电源供应3.0-V工作电压条件———————————————Min1.162.3751.163.1352.852.3751.711.4251.143.1352.852.3751.711.4251.14Typ1.22.51.23.332.51.81.51.23.332.51.81.51.2Max1.242.6251.243.4653.152.6251.891.5751.263.4653.152.6251.891.5751.26UnitVVVVVVVVVVVVVVV(1), (3)(2) V CCD_PLL V CCIO(3), (4)V CC_CLKIN (3), (5), (6)差分时钟输入引脚电源供应2.5-V工作电压差分时钟输入引脚电源供应1.8-V工作电压差分时钟输入引脚电源供应1.5-V工作电压差分时钟输入引脚电源供应1.2-V工作电压。
中文四版-SMC样本
2.5, 4
CAT.C06-02A
6, 10, 15
CAT.C06-02A
6, 10, 16
CAT.C04-01A
错误内容 产品规格变更
改正日期 06年8月
型号表示错误，易造成选型错误 06年8月
螺纹表示错误，易造成选型错误 06年8月
注解错误，易造成选型错误
07年11月
产品尺寸错误，易造成选型错误 07年8月
内容更新
07年11月
内容更新
07年11月
产品尺寸错误，易造成选型错误 磁性开关变更 词汇更正、录入错误
CAT.ES20-152B CAT.ES20-177A CAT.E256A CAT.ES20-179B CAT.E216B CAT.ES20-95B CAT.ES20-157B P-1991-6 CAT.ES20-160A CAT.E204A CAT.ES20-159A CAT.ES20-159A CAT.ES20-159A CAT.ES20-147A
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FCK-801C技术及使用说明书
FCK-801C微机测控装置 技术及使用说明书（Version 1.00）许继电气股份有限公司XJ ELECTRIC CO.，LTD.目 录1概述 (1)1.1应用范围 (1)1.2功能配置 (1)1.3产品特点 (1)2技术指标 (3)2.1交直流测量 (3)2.2状态输入 (3)2.3控制输出 (3)2.4工作电源 (4)2.5绝缘性能 (4)2.6机械性能 (4)2.7抗电气干扰性能 (4)2.8环境条件 (5)2.9通信接口 (5)3装置功能 (6)3.1遥测功能 (6)3.2遥信功能 (6)3.3遥控功能 (6)3.4遥调功能 (7)3.5同期功能 (7)3.6逻辑闭锁 (8)3.7报告记录 (9)3.8通信功能 (9)3.9自检功能 (9)3.10对时功能 (10)4定值整定 (11)4.1直流定值 (11)4.2遥调定值 (11)4.3同期定值 (11)4.4软压板 (12)5参数设置 (14)5.1系统参数 (14)5.2遥控定值............................................................................................................... 错误!未定义书签。
5.3遥信定值............................................................................................................... 错误!未定义书签。
6装置硬件介绍 (15)6.1机箱结构 (15)6.2插件布置图 (15)6.3装置端子图 (16)7使用说明 (17)7.1指示灯说明 (17)7.2调试接口和键盘说明 (17)7.3命令菜单 (18)7.4液晶显示说明 (20)7.5装置操作说明 (21)8调试说明 (24)8.1调试注意事项 (24)8.2开关量输入检查 (24)8.3开出回路检查 (24)8.4模拟量输入检查 (24)8.5装置异常信息说明及处理意见 (24)8.6事故分析注意事项 (24)9订货须知 (25)10附录 (26)1概述1.1应用范围FCK-801C系列测控装置（以下简称装置）是适用于500kV及以下电压等级的间隔层测控单元，具有全范围高精度测量、高可靠性控制、完备的间隔层监视、间隔层逻辑闭锁等功能特点，支持IEC 61850和TCP 103通讯协议。