MIC3289-16YML中文资料

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R928中文资料

PHOTOMULTlPLlER TUBESR928, R955Subject to local technical requirements and regulations, availability of products included in this promotional material may vary. Please consult with our sales office. lnformation furnished by HAMAMATSU is believed to be reliabIe. However, no responsibility is assumed for possibIe inaccuracies or ommissions. Specifications are subject to change without notice. No patent right are granted to any of the circuits described herein. © 1997 Hamamatsu Photonics K.K.PHOTOMULTlPLlER TUBES R928, R955 MAXIMUM RATINGS (Absolute Maximum Values)CHARACTERISTlCS (at 25SuppIy Voltage : 1000VdcK : Cathode, Dy : Dynode, P : AnodeJ:K:L:The electron transit time is the interval between the arrival of delta function light pulse at the entrance window of the tube and the time when the anode output reaches the peak amplitude. In measurement, the whole photo-cathode is illuminated.Also called transit time jitter. This is the fluctuation in electron transit time between individual pulses in the signal photoelectron mode, and may be defined as the FWHM of the frequency distribution of electron transit times.Hysteresis is temporary instability in anode current after light and voltage are applied.(1)Current HysteresisThe tube is operated at 750 volts with an anode current of 1 micro-ampere for 5 minutes. The light is then removed from the tube for a minute. The tube is then re-illuminated by the previous light level for a minute to measure the variation.(2)Voltage HysteresisThe tube is operated at 300 volts with an anode current of 0.1 micro-ampere for 5 minutes. The light is then removed from the tube and the supply voltage is quickly increased to 800 volts. After a minute, the supply voltage is then reduced to the previous value and the tube is re-illuminated for a minute to measure the variation.Hysteresis =100(%)l max.l il min.Figure 2: Anode Luminous Sensitivity and Gain CharacteristicsFigure 3: Typical Time ResponseFigure 4: Typical Temperature Coefficient of Anode SensitivityFigure 5: Typical Temperature Characteristic of Dark Current (at 1000V, after 30minute storage)TPMSB0002EATPMSB0003EBTIMEA N O D E 200300500700100010–2A N O D E L U M I N O U S S E N S I T I V I T Y (A /l m )1500G A I N10–1100101102103104102103104105106107108SUPPLY VOLTAGE (V)SUPPLY VOLTAGE (V)T I M E (n s )124681020406080100TPMSB0005EA–40–200+20TEMPERATURE (°C)1608020A N O D E S E N S I T I V I T Y (%)140100+401206040TPMSB0006EA–40–200+20TEMPERATURE (°C)10010.01A N O D E D A R K C U R R E N T (n A )+40100.1PHOTOMULTlPLlER TUBES R928, R955TPMS1001E06MAY. 1997Figure 6: Dimensional Outline and Basing Diagram (Unit : mm)Figure 7: Optional Accessories (Unit : mm)TPMSA0008EADIRECTION OF LIGHTBOTTOM VIEW (BASING DIAGRAM)TACCA0064EASocketD Type Socket Assembly E717-21Warning–Personal Safety HazardsElectrical Shock–Operating voltages applied to thisdevice present a shock hazard.Hamamatsu also provides C4900 series compact high voltage power sup-plies and C6270 series DP type socket assemblies which incorporate a DC to DC converter type high voltage power supply.(E678 – 11A)TACCA0002ED: 330k: 0.01 F SOCKET HAMAMATSU PHOTONICS K.K., Electoron Tube Center314-5, Shimokanzo, Toyooka-village, Iwata-gun, Shizuoka-ken, 438-0193, Japan, Telephone: (81)539/62-5248, Fax: (81)539/62-2205U.S.A.: Hamamatsu Corporation: 360 Foothill Road, Bridgewater. N.J. 08807-0910, U.S.A., Telephone: (1)908-231-0960, Fax: (1)908-231-1218Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49)8152-375-0, Fax: (49)8152-2658France: Hamamatsu Photonics France S.A.R.L.: 8, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: (33)1 69 53 71 00, Fax: (33)1 69 53 71 10United Kingdom: Hamamatsu Photonics UK Limted: Lough Point, 2 Gladbeck Way, Windmill Hill, Enfield, Middlesex EN2 7JA, United Kingdom, Telephone: (44)181-367-3560, Fax: (44)181-367-6384North Europe: Hamamatsu Photonics Norden AB: Färögatan 7, S-164-40 Kista Sweden, Telephone: (46)8-703-29-50, Fax: (46)8-750-58-95Italy: Hamamatsu Photonics Italia: S.R.L.: Via Della Moia, 1/E, 20020 Arese, (Milano), Italy, Telephone: (39)2-935 81 733, Fax: (39)2-935 81 741Hybrid Assembly of R928H957-08The H957-08 integrates on R928, a voltage-divider circuit, and a high voltage power supply into a compact magnetic shield case. It can be readily operated by input of 15Vdc.。

MX28F160C3T资料

MX28F160C3T/B16M-BIT [1M x16] CMOS SINGLE VOLTAGE3V ONLY FLASH MEMORY- Word write suspend to read- Sector erase suspend to word write- Sector erase suspend to read register report•Automatic sector erase, word write and sector lock/unlock configuration •Status Reply- Detection of program and erase operation comple-tion.- Command User Interface (CUI)- Status Register (SR)•Data Protection Performance- Include boot sectors and parameter and main sectors to be locked/unlocked•100,000 minimum erase/program cycles •Common Flash Interface (CFI)•128-bit Protection Register- 64-bit Unique Device Identifier - 64-bit User-Programmable•Latch-up protected to 100mA from -1V to VCC+1V •Package type:- 48-pin TSOP (12mm x 20mm)- 48-ball CSP (8mm x 6mm)FEATURES•Bit Organization: 1,048,576 x 16•Single power supply operation- VCC=VCCQ=2.7~3.6V for read, erase and program operation- VPP=12V for fast production programming - Operating temperature:-40°C~85°C •Fast access time : 70/90/110ns •Low power consumption- 9mA typical active read current, f=5MHz- 18mA typical program current (VPP=1.65~3.6V)- 21mA typical erase current (VPP=1.65~3.6V)- 7uA typical standby current under power saving mode•Sector architecture- Sector structure : 4Kword x 2 (boot sectors), 4Kword x 6 (parameter sectors), 32Kword x 31 (main sectors)- Top/Bottom Boot•Auto Erase and Auto Program- Automatically program and verify data at specified address- Auto sector erase at specified sector •Automatic Suspend EnhanceGENERAL DESCRIPTIONThe MX28F160C3T/B is a 16-mega bit Flash memory organized as 1M words of 16 bits. The 1M word of data is arranged in eight 4Kword boot and parameter sectors,and thirty-one 32K word main sectors which are indi-vidually erasable. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX28F160C3T/B is packaged in 48-pin TSOP and 48-ball CSP . It is designed to be re-programmed and erased in system or in standard EPROM programmers.fast as 70ns, allowing operation of high-speed micropro-cessors without wait states.MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX28F160C3T/B uses a command register to manage this functionality. The command register allows for 100%TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maxi-mum EPROM compatibility.MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXICMX28F160C3T/Bmechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cy-cling. The MX28F160C3T/B uses a 2.7V~3.6V VCC sup-ply to perform the High Reliability Erase and auto Pro-gram/Erase algorithms.The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up pro-tection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.The dedicated VPP pin gives complete data protection when VPP< VPPLK.A Command User Interface (CUI) serves as the inter-face between the system processor and internal opera-tion of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algo-rithms and timings necessary for erase, word write and sector lock/unlock configuration operations.A sector erase operation erases one of the device's 32K-word sectors typically within 1.0s, 4K-word sectors typi-cally within 0.5s independent of other sectors. Each sec-tor can be independently erased minimum 100,000 times. Sector erase suspend mode allows system software to suspend sector erase to read or write data from any other sector.Writing memory data is performed in word increments of the device's 32K-word sectors typically within 0.8s and 4K-word sectors typically within 0.1s. Word program sus-pend mode enables the system to read data or execute code from any other memory array location.MX28F160C3T/B features with individual sectors lock-ing by using a combination of bits thirty-nine sector lock-bits and WP, to lock and unlock sectors.The status register indicates when the WSM's sector erase, word program or lock configuration operation is done.The access time is 70/90/110ns (tELQV) over the oper-ating temperature range (-40°C to +85°C) and VCC sup-ply voltage range of 2.7V~3.6V.MX28F160C3T/B's power saving mode feature substan-tially reduces active current when the device is in static mode (addresses not switching). In this mode, the typi-cal ICCS current is 7uA (CMOS) at 3.0V VCC.As CE and RP are at VCC, ICC CMOS standby mode is enabled. When RP is at GND, the reset mode is enabled which minimize power consumption and provide data write protection.A reset time (tPHQV) is required from RP switching high until outputs are valid. Similarly, the device has a wake time (tPHEL) from RP-high until writes to the CUI are recognized. With RP at GND, the WSM is reset and the status register is cleared.MX28F160C3T/BMX28F160C3T/BMX28F160C3T/BTable 1. Pin DescriptionSymbol Type Description and FunctionA0-A19input Address inputs for memory address. Data pin float to high-impedance when the chip isdeselected or outputs are disable. Addresses are internally latched during a write orerase cycle.DQ0-DQ15input/output Data inputs/outputs: Inputs array data on the second CE and WE cycle during a pro-gram command. Data is internally latched. Outputs array and configuration data. Thedata pin float to tri-state when the chip is de-selected.CE input Chip Enable : Activates the device's control logic, input buffers, and sense amplifiers.CE high de-selects the memory device and reduce power consumption to standbylevel. CE is active low.RP input Reset/Deep Power Down: when RP=VIL, the device is in reset/deep power down mode,which drives the outputs to High Z, resets the WSM and minimizes current level.When RP=VIH, the device is normal operation. When RP transitions from VIL to VIH,the device defaults to the read array mode.WE input Write Enable: to control write to CUI and array sector. WE=VIL becomes active. Thedata and addresses are latched on the rising edge of the second WE pulse.VPP input/supply Program/Erase Power Supply:(1.65V~3.6V or 11.4V~12.6V)Lower VPP<VPPLK, to protect any contents against Program and Erase Command.Set VPP=VCC for in-system Read, Program and Erase Operation.Raise VPP to 12V±5% for faster program and erase in a production environment.OE input Output enable: gates the device's outputs during a real cycle.WP input Write Protect: When WP is VIL, the sectors marked Lock Down can't be unlockedthrough software. When WP is VIH, the lock down mechanism is disable and sectorspreviously locked down are now locked and can be unlocked and locked through soft-ware. After WP goes low, any sectors previously marked lock down revert to that state. VCC supply Device power supply: (2.7V~3.6V).VCCQ input I/O Power Supply: supplies for input/output buffers. (VCCQ must be tied to VCC) GND supply Ground voltage: all the GND pin shall not be connected.MX28F160C3T/BSECTOR STRUCTURE (TOP)Sector Sector Size Address Range (h)Boot Sector 04K Word FF000 ~ FFFFFBoot Sector 14K Word FE000 ~ FEFFFParameter Sector 04K Word FD000 ~ FDFFFParameter Sector 14K Word FC000 ~ FCFFFParameter Sector 24K Word FB000 ~ FBFFFParameter Sector 34K Word FA000 ~ FAFFFParameter Sector 44K Word F9000 ~ F9FFFParameter Sector 54K Word F8000 ~ F8FFFMain Sector 032K Word F0000 ~ F7FFFMain Sector 132K Word E8000 ~ EFFFFMain Sector 232K Word E0000 ~ E7FFFMain Sector 332K Word D8000 ~ DFFFFMain Sector 432K Word D0000 ~ D7FFFMain Sector 532K Word C8000 ~ CFFFFMain Sector 632K Word C0000 ~ C7FFFMain Sector 732K Word B8000 ~ BFFFFMain Sector 832K Word B0000 ~ B7FFFMain Sector 932K Word A8000 ~ AFFFFMain Sector 1032K Word A0000 ~ A7FFFMain Sector 1132K Word98000 ~ 9FFFFMain Sector 1232K Word90000 ~ 97FFFMain Sector 1332K Word88000 ~ 8FFFFMain Sector 1432K Word80000 ~ 87FFFMain Sector 1532K Word78000 ~ 7FFFFMain Sector 1632K Word70000 ~ 77FFFMain Sector 1732K Word68000 ~ 6FFFFMain Sector 1832K Word60000 ~ 67FFFMain Sector 1932K Word58000 ~ 5FFFFMain Sector 2032K Word50000 ~ 57FFFMain Sector 2132K Word48000 ~ 4FFFFMain Sector 2232K Word40000 ~ 47FFFMain Sector 2332K Word38000 ~ 3FFFFMain Sector 2432K Word30000 ~ 37FFFMain Sector 2532K Word28000 ~ 2FFFFMain Sector 2632K Word20000 ~ 27FFFMain Sector 2732K Word18000 ~ 1FFFFMain Sector 2832K Word10000 ~ 17FFFMain Sector 2932K Word08000 ~ 0FFFFMX28F160C3T/BSECTOR STRUCTURE (BOTTOM)Sector Sector Size Address Range (h)Boot Sector 04K Word00000 ~ 00FFFBoot Sector 14K Word01000 ~ 01FFFParameter Sector 04K Word02000 ~ 02FFFParameter Sector 14K Word03000 ~ 03FFFParameter Sector 24K Word04000 ~ 04FFFParameter Sector 34K Word05000 ~ 05FFFParameter Sector 44K Word06000 ~ 06FFFParameter Sector 54K Word07000 ~ 07FFFMain Sector 032K Word08000 ~ 0FFFFMain Sector 132K Word10000 ~ 17FFFMain Sector 232K Word18000 ~ 1FFFFMain Sector 332K Word20000 ~ 27FFFMain Sector 432K Word28000 ~ 2FFFFMain Sector 532K Word30000 ~ 37FFFMain Sector 632K Word38000 ~ 3FFFFMain Sector 732K Word40000 ~ 47FFFMain Sector 832K Word48000 ~ 4FFFFMain Sector 932K Word50000 ~ 57FFFMain Sector 1032K Word58000 ~ 5FFFFMain Sector 1132K Word60000 ~ 67FFFMain Sector 1232K Word68000 ~ 6FFFFMain Sector 1332K Word70000 ~ 77FFFMain Sector 1432K Word78000 ~ 7FFFFMain Sector 1532K Word80000 ~ 87FFFMain Sector 1632K Word88000 ~ 8FFFFMain Sector 1732K Word90000 ~ 97FFFMain Sector 1832K Word98000 ~ 9FFFFMain Sector 1932K Word A0000 ~ A7FFFMain Sector 2032K Word A8000 ~ AFFFFMain Sector 2132K Word B0000 ~ B7FFFMain Sector 2232K Word B8000 ~ BFFFFMain Sector 2332K Word C0000 ~ C7FFFMain Sector 2432K Word C8000 ~ CFFFFMain Sector 2532K Word D0000 ~ D7FFFMain Sector 2632K Word D8000 ~ DFFFFMain Sector 2732K Word E0000 ~ E7FFFMain Sector 2832K Word E8000 ~ EFFFFMain Sector 2932K Word F0000 ~ F7FFFMX28F160C3T/B2 PRINCIPLES OF OPERATIONThe product includes an on-chip WSM to manage sec-tor erase, word write and lock-bit configuration functions.After initial device power-up or return from reset mode (see section on Bus Operations), the device defaults to read array mode. Manipulation of external memory con-trol pins allow array read, standby and output disable operations.Status register and identifier codes can be accessed through the CUI independent of the VPP voltage. All functions associated with altering memory contents -sector erase, word write, sector lock/unlock, status and identifier codes - are accessed via the CUI and verified through the status register.Commands are written using standard microprocessor write timings. The CUI contents serve as input to the WSM, which controls the sector erase, word write and sector lock/unlock. The internal algorithms are regulated by the WSM, including pulse repetition, internal verifica-tion and margining of data. Addresses and data are in-ternally latched during write cycles. Address is latched at falling edge of CE and data latched at rising edge of WE. Writing the appropriate command outputs array data, accesses the identifier codes or outputs status register data.Interface software that initiates and polls progress of sector erase, word write and sector lock/unlock can be stored in any sector. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Sector erase suspend allows system software to suspend a sector erase to read/write data from/to sectors other than that which is suspend. Word write suspend allows system software to suspend a word write to read data from any other flash memory array location.With the mechanism of sector lock, memory contents cannot be altered due to noise or unwanted operation. When RP=VIH and VCC<VLKO (lockout voltage), any data write alteration can be failure. During read opera-tion, if write VPP voltage is below VPPLK, then hard-ware level data protection is achieved. With CUI's two-step command sequence sector erase, word write or sector lock/unlock, software level data protection is 3 BUS OPERATIONThe local CPU reads and writes flash memory in-sys-tem. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.3.1 ReadInformation can be read from any sector, configuration codes or status register independent of the VPP volt-age. RP can be at VIH.The first task is to write the appropriate read mode com-mand (Read Array, Read Configuration, Read Query or Read Status Register) to the CUI. Upon initial device power-up or after exit from reset, the device automati-cally resets to read array mode. In order to read data, control pins set for CE, OE, WE, RP and WP must be driven to active. CE and OE must be active to obtain data at the outputs. CE is the device selection control. OE is the data output (DQ0-DQ15) control and active drives the selected memory data onto the I/O bus, WE must be VIH, RP must be VIH, WP must be at VIL or VIH.3.2 Output DisableWith OE at a logic-high level (VIH), the device outputs are disabled. Output pins (DQ0-DQ15) are placed in a high-impedance state.3.3 StandbyCE at a logic-high level (VIH) places the device in standby mode which substantially reduces device power consumption. DQ0~DQ15 outputs are placed in a high-impedance state independent of OE. If deselected dur-ing sector erase, word write or sector lock/unlock, the device continues functioning, and consuming active power until the operation completes.3.4 ResetAs RP=VIL, it initiates the reset mode. The device en-ters reset/deep power down mode. However, the data stored in the memory has to be sustained at least 100nsMX28F160C3T/Band output high impedance state.In read modes, RP-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. RP must be held low for a minimum of 100ns. Time tPHQV is required after return from reset mode until initial memory access outputs are valid. Af-ter this wake-up interval tPHEL or tPHWL, normal op-eration is restored. The CUI is reset to read array mode and status register is set to 80H. Sector lock bit is set at lock status.During sector erase, word write or sector lock/unlock modes, RP-low will abort the operation. Memory con-tents being altered are no longer valid; the data may be partially erased or written.In addition, CUI will go into either array read mode or erase/write interrupted mode. When power is up and the device reset subsequently, it is necessary to read sta-tus register in order to assure the status of the device. Recognizing status register (SR.7~0) will assure if the device goes back to normal reset and enters array read mode.3.5 Read Configuration CodesThe read configuration codes operation outputs the manu-facturer code, device code, sector lock configuration codes, and the protection register. Using the manufac-turer and device codes, the system CPU can automati-cally match the device with its proper algorithms. The sector lock codes identify locked and unlocked sectors.3.6 WriteWriting commands to the CUI enable reading of device data and identifier codes. They also control inspection and clearing of the status register. When VCC=2.7V-3.6V and VPP within VPP1 or VPP2 range, the CUI addition-ally controls sector erase, word write and sector lock/ unlock.The Sector Erase command requires appropriate com-mand data and an address within the sector to be erased. The Full Chip Erase command requires appropriate com-mand data and an address within the device. The Word Write command requires the command and address of mands require the command and address within the de-vice or sector within the device (Sector Lock) to be locked. The Clear Sector Lock-Bits command requires the command and address within the device.The CUI does not occupy an addressable memory loca-tion. It is written when WE and CE are active (whichever goes high first). The address and data needed to ex-ecute a command are latched on the rising edge of WE or CE. Standard microprocessor write timings are used.MX28F160C3T/B4 COMMAND DEFINITIONSThe flash memory has four read modes: read array, readconfiguration, read status, read query, and two writemodes: program, erase. These read modes are acces-sible independent of the VPP voltage. But write modesare disable during VPP<VPPLK. Placing VPP on VPP1/2 enables successful sector erase, word write and sec-tor lock/unlock.Device operations are selected by writing specific com-mands into the CUI. T able 3 defines these commands.Table 2. Bus OperationMode Notes RP CE OE WE DQ0~DQ15Read1,2VIH VIL VIL VIH DOUTOutput Disable2VIH VIL VIH VIH High ZStandby2VIH VIH X X High ZReset2VIL X X X High ZWrite2,3,4,5VIH VIL VIH VIL DINNotes:1.Refer to DC Characteristics for VPPLK, VPP1, VPP2 voltage.2.X can be VIL or VIH for pin and addresses.3.RP at GND±0.2 to ensure the lowest power consumption.4.Refer to Table 3 for valid DIN during a write operation.5.To program or erase the lockable sectors holds WP at VIH.MX28F160C3T/BTable 3. Command Definition (1)Command Bus Notes First Bus Cycle Second Bus CycleCycles Operation Address Data Operation Address DataRequired(1)(2)(3)(1)(2)(3) Read Array1Write X FFHRead Configuration> 22,4Write X90H Read IA ID Read Query22,7Write X98H Read QA QD Read Status Register23Write X70H Read X SRD Clear Status Register13Write X50HSector Erase/Confirm2Write X20H Write SA D0H Word Write22,5Write X40H/10H Write WA WD Program/Erase Suspend1Write X B0HProgram/Erase Resume1Write X D0HSector Lock2Write X60H Write SA01H Sector Unlock26Write X60H Write SA D0H Lock-Down Sector2Write X60H Write SA2FH Protection Program2Write X C0H Write P A PDNotes:1.Bus operation are defined in Table 2 and referred to AC Timing Waveform.2.X=Any address within device.IA=ID-Code Address (refer to Table 4).ID=Data read from identifier code.SA=Sector Address within the sector being erased.WA=Address of memory location to be written.WD=Data to be written at location WA.PA=Program Address, PD=Program DataQA=Query Address, QD=Query Data.3.Data is latched from the rising edge of WE or CE (whichever goes high first)SRD=Data read from status register, see T able 6 for description of the status register bits.4.Following the Read Configuration codes command, read operation access manufacturer, device codes, sectorlock/unlock codes, see chapter 4.2.5.Either 40H or 10H command is recognized by the WSM as word write setup.6.The sector unlock operation simultaneously clear all sector lock.7.Read Query Command is read for CFI query information.MX28F160C3T/B4.1 Read Array CommandUpon initial device power-up and after exit from reset mode, the device defaults to read array mode. This op-eration is also initiated by writing the Read Array com-mand. The device remains enabled for reads until an-other command is written. Once the internal WSM has started a sector erase, word write or sector lock con-figuration the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via a Sector Erase Suspend or Word Write Suspend command. If RP=VIL device is in read Read Array command mode, this read operation no longer requires VPP . The Read Array command func-tions independently of the VPP voltage and RP can be VIH.4.2 Read Configuration Codes CommandThe configuration code operation is initiated by writing the Read Configuration Codes command (90H). To re-turn to read array mode, write the Read Array Command (FFH). Following the command write, read cycles from addresses shown in T able 4 retrieve the manufacturer,device, sector lock configuration codes and the protec-tion register(see Table 4 for configuration code values).T o terminate the operation, write another valid command.Like the Read Array command, the Read Configuration Codes command functions independently of the VPP voltage and RP can be VIH. Following the Read Configu-ration Codes command, the information is shown:CodeAddress Data (A19-A0)(DQ15-DQ0)Manufacturer Code00000H00C2H Device Code(Top/Bottom)00001H 88C2/88C3H Sector Lock Configuration XX002H LocK - Sector is unlocked DQ0=0- Sector is locked DQ0=1- Sector is locked-down DQ1=1Protection Register Lock 80PR-LK Protection Register81-88PRTable 4: ID Code4.3 Read Status Register CommandCUI writes read status command (70H). The status reg-ister may be read to determine when a sector erase,word write or lock-bit configuration is complete and whether the operation completed successfully. (refer to table 6) It may be read at any time by writing the Read Status Register command. After writing this command,all subsequent read operations output data from the sta-tus register until another valid command is written. The status register contents are latched on the falling edge of CE or OE, whichever occurs last. CE or OE must toggle to VIH before further reads to update the status register latch. The Read Status Register command func-tions independently of the VPP voltage. RP can be VIH.4.4 Clear Status Register CommandStatus register bits SR.5, SR.4, SR.3 or SR.1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command (50H). These bits indicate various failure conditions (see Table 6). By allowing sys-tem software to reset these bits, several operations (such as cumulatively erasing multiple sectors or writing sev-eral words in sequence) may be performed. The status register may be polled to determine if an error occurred during the sequence.T o clear the status register, the Clear Status Register command (50H) is written on CUI. It functions indepen-dently of the applied VPP Voltage. RP can be VIH. This command is not functional during sector erase or word write suspend modes.MX28F160C3T/B4.5 Sector Erase CommandErase is executed one sector at a time and initiated by a two-cycle command. A sector erase setup is first writ-ten (20H), followed by a sector erase confirm (D0H). This command sequence requires appropriate sequencing and an address within the sector to be erased. Sector pre-conditioning, erase, and verify are handled internally by the WSM. After the two-cycle sector erase sequence is written, the device automatically outputs status register data when read (see Figure 8). The CPU can detect sec-tor erase completion by analyzing the output data of the status register bit SR.7.When the sector erase is complete, status register bit SR.5 should be checked. If a sector erase error is de-tected, the status register should be cleared before sys-tem software attempts corrective actions. The CUI re-mains in read status register mode until a new com-mand is issued.This two-step command sequence of set-up followed by execution ensures that sector contents are not acciden-tally erased. An invalid sector Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable sector erasure can only occur when 2.7V~3.6V and VPP=VPP1/2. In the absence of this high voltage, sector contents are protected against erasure. If sector erase is attempted while VPP<VPPLK SR.3 and SR.5 will be set to "1". T o successfully erase the boot sector, the corresponding sector lock-bit must be clear first. In parameter and sectors case, it must be cleared the corresponding sector lock-bit. If sector erase is attempted when the excepting above sector being locked conditions, SR.1 and SR.5 will be set to "1". Sec-tor erase is not functional.4.6 Word Write CommandWord write is executed by a two-cycle command se-quence. Word write setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data. The WSM then takes over, controlling the word write and write verify algorithms internally. Af-ter the word write sequence is written, the device auto-matically outputs status register data when read (see Figure 6). The CPU can detect the completion of the word write event by analyzing the status register bit SR.7. When word write is complete, status register bit SR.4should be checked. If word write error is detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully write to "0"s. The CUI remains in read status register mode until it receives another command.Reliable word writes can only occur when VCC=2.7V~3.6V and VPP=VPP1/2. If VPP is not within acceptable limits, the WSM doesn't execut the program command. If word write is attempted while VPP<VPPLK, status register bits SR.3 and SR.4 will be set to "1". Successful word write requires for boot sector that WP is VIH the corresponding sector lock-bit be cleared. In parameter and main sectors case, it must be cleared the corresponding sector lock-bit. If word write is at-tempted when the excepting above sector being clocked conditions, SR.1 and SR.4 will be set to "1". Word write is not functional.4.7 Sector Erase Suspend CommandThe Sector Erase Suspend command (50H) allows sec-tor-erase interruption to read or word write data in an-other sector of memory. Once the sector erase process starts, writing the Sector Erase Suspend command re-quests that the WSM suspend the sector erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Sector Erase Suspend command is written. Polling status reg-ister bits SR.7 and SR.6 can determine when the sector erase operation has been suspended (both will be set to "1"). Specification tWHRH2/tEHRH2 defines the sector erase suspend latency.When Sector Erase Suspend command is written to the CUI, if sector erase was finished, the device would be placed read array mode. Therefore, after Sector Erase Suspend command is written to the CUI, Read Status Register command (70H) has to be written to CUI, then status register bit SR.6 should be checked if/when the device is in suspend mode.At this point, a Read Array command can be written to read data from sectors other than that which is sus-pended. A Word Write commands sequence can also be issued during erase suspend to program data in other sectors. Using the Word Write Suspend command (see Section 4.9), a word write operation can also be sus-pended. During a word write operation with sector erase suspended, status register bit SR.7 will return to "0".MX28F160C3T/BHowever, SR.6 will remain "1" to indicate sector erase suspend status.The only other valid commands while sector erase is suspended are Read Status Register, Read Configura-tion, Read Query, Program Setup, Program Resume, Sector Lock, Sector Unlock, Sector Lock-Down and sec-tor erase Resume. After a Sector Erase Resume com-mand is written to the flash memory, the WSM will con-tinue the sector erase process. Status register bits SR.6 and SR.7 will automatically be cleared. After the Erase Resume command is written, the device automatically outputs status register data when read (see Figure 9). VPP must remain at VPP1/2 while sector erase is sus-pended. RP must also remain at VIH (the same RP level used for sector erase). Sector cannot resume until word write operations initiated during sector erase suspend has completed.If the time between writing the Sector Erase Resume command and writing the Sector Erase Suspend com-mand is shorter than 15ms and both commands are writ-ten repeatedly, a longer time is required than standard sector erase until the completion of the operation.4.8 Word Write Suspend CommandThe Word Write Suspend command allows word write interruption to read data in other flash memory locations. Once the word write process starts, writing the Word Write Suspend command requests that the WSM sus-pend the Word write sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the Word Write Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the word write operation has been suspended (both will be set to "1"). Specification tWHRH1/tEHRH1 defines the word write suspend latency. When Word Write Suspend command write to the CUI, if word write was finished, the device places read array mode. Therefore, after Word Write Suspend command write to the CUI, Read Status Register command (70H) has to be written to CUI, then status register bit SR.2 should be checked for if/when the device is in suspend mode.At this point, a Read Array command can be written to read data from locations other than that which is sus-pended. The only other valid commands while word write is suspended are Read Status Register Read Configura-tion, Read Query and Word Write Resume. After Word Write Resume command is written to the flash memory, the WSM will continue the Word write process. Status register bits SR.2 and SR.7 will automatically be cleared. After the Word Write Resume command is written, the device automatically outputs status register data when read (see Figure 7). VPP must remain at VPP1/2 while in word write suspend mode. RP must also remain at VIH (the same RP level used for word write).If the time between writing the Word Write Resume com-mand and writing the Word Write Suspend command is short and both commands are written repeatedly, a longer time is required than standard word write until the comple-tion of the operation.。

ATMEGA16A中文资料

ATMEGA16A中文资料高性能,低功耗AVR 8-bit微控制器•高级RISC建筑– 131条指令–绝大多数为单时钟周期执行– 32 x 8通用工作寄存器–全静态工作–高达16吞吐量在MIPS 16 MHz–片2—cycle乘数高耐久性非易失性内存段– 16K字节的程序存储器，在系统内可编程Flash– 512字节的EEPROM– 1K字节内部SRAM–写/擦除周期：10，000闪光/ 100，000的EEPROM–数据保存：在20年85°C/100年在25°C（1)–可选引导具有独立锁定Bits代码段•在系统编程的片上引导程序•真Read-While-Write操作–锁编程软件安全JTAG (IEEE std。

1149.1兼容）接口–边界扫描功能根据JTAG标准–广泛的片上调试支持–编程闪存，EEPROM，熔丝位和锁定Bits通过JTAG接口外设特点–两个8—bit定时器/计数器具有独立预分频器和比较模式–一个16-bit定时器/计数器具有独立预分频器,比较功能和捕捉模式–实时计数器具有独立振荡器–四PWM频道– 8-channel, 10-bit ADC• 8单端通道• 7在TQFP 包装差分通道只有• 2在1x, 10x,差分通道具有可编程增益或200x–面向字节的两线串行接口可编程串行USART的––主/从串行接口SPI–可编程看门狗定时器具有独立片内振荡器–片内模拟比较器单片机的特殊功能–上电复位和可编程的掉电检测–内部振荡器校准RC–外部和内部中断源– 6种睡眠模式：空闲，ADC降噪，省电，省电，待机和扩展待机I / O和封装– 32可编程I / O线– 40—pin PDIP, 44—lead TQFP，和44—pad QFN/MLF 工作电压– 2。

7为- 5。

5V ATmega16A速度等级– 0 —为16 MHz ATmega16A功耗＠ 1 MHz, 3V，和25°C为ATmega16A–活动:0。

cici-手机外围电路详细介绍

T-FLASH电路
•
•
TF CLK频率为24MHZ，26，25平台均使用的12MHZ的频率。上电后先有CLK信号，通过TFCMD信号发送指令查看时何种类型的T卡，是单线的还是多线的。如果是单线的就用TF-CMD 通讯，如果支持多线就用TF-DAT-0，1，2，3，进行传输。 HSP301-HSP307为主板上的尖端放电点，和TVS管一起使用用来加快放电，消除ESD的干扰
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MIC电路
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MICBIASP和MICBIASN为MIC电路的正负两路偏置电压，一般为2.4V-2.7V左右的电压。 C204，C205主要为滤除射频信号的干扰。如果有GSM900MHZ的干扰则使用33PF的电容，如果有DCS1800MHZ的干扰可以使用12PF的电容，如果有WIFI 2.4GHZ的干扰则使用8.2PF的电容。 C206主要是抑制共模信号。 C201,C202为100NF电容，主要作用为隔直通交，防止直流电使PA饱和，产生信号偏移，主要滤除100HZ一下的电流。 B201，B202为磁珠，主要滤除高频部分的干扰。 MIC偏置电流流向为从MICBIASP----MICBIASN，而不用公共的GND，主要是因为GND干扰太大。磁珠有很高的电阻率和磁导率，他等效于电阻和电感串联，但电阻值和电感值都随频率变化。他比普通的电感有更好的高频滤波特性，在高频时呈现阻性，所以能在相当宽的频率范围内保持较高的阻抗，从而提高调频滤波效果
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开机关机过程

多家LED驱动IC规格参数资料更新

HV9921/22/23 85 to 264VAC or DC input voltage of 20 to 400V. 20/30/50mA
HV9925 Output Current to 50mA；Universal 85-264VAC Operation；Fixed OFF-Time Buck Converter；Internal 500V Power MOSFET
DM621 4×3装饰照明专用PWM输出驱动恒流IC
DM631 12比特内置PWM+实时检测恒流驱动IC
DM632 16比特内置PWM+实时检测恒流驱动IC
DM163 8×3通道4096级PWM输出恒流驱动IC
DM164 8×3通道4096级PWM输出恒流驱动IC
DD211 二倍升压驱动IC 2-3.3V 最大升压100mA固定式恒流IC
500种 LED驱动IC规格参数资料
台湾地区部分：
明阳半导体股份有限公司
MY9268 适用于动态扫描驱动之16位高精度恒流LED驱动器内建16位多路扫描脉冲密度调变控制
MY9262 16位高精度恒流LED驱动器内建16位自适应脉冲密度调变控制及节能功能
MY9221 12通道(支援 R/G/B *4)恆流LED驱动芯片内建灰阶自适应脉冲密度调制
MY9231 3通道(支援 R/G/B *1)恆流LED驱动芯片内建灰阶自适应脉冲密度调制
MY9291 4通道(支援 R/G/B/W *1)恆流LED驱动芯片内建灰阶自适应脉冲密度调制
MY9163 内建错误侦测及可编程电流增益及节能功能的16位高精度恆流LED驱动器
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DD231 3信道驱动IC 5-30mA 可设置小体上电即亮型IC

Micrel KSZ8851-16MLL 48-pin单端口以太网控制器与非PCI接口评估板用户指南

KSZ8851-16MLL48-pin Single-Port Ethernet ControllerWith 8-bit or 16-bit Non-PCI InterfaceEvaluation Board User’s GuideRevision 1.1August 2010© Micrel, Inc. 2007All rights reservedMicrel is a registered trademark of Micrel and its subsidiaries in theUnited States and certain other countries. All other trademarks are theproperty of their respective owners.The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user.Micrel, Inc. August 6, 2010A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.Revision HistoryRevisionDateSummary of Changes1.0 2/20/2008 Initial Release1.1 8/6/2010Add JP8 for connection between VDD_IO and 1.8V (if VDD_IO is 1.8V). Changed the LED pulled up to 3.3V.Table of Contents1.0Introduction (5)2.0Board Features (5)3.0Evaluation Kit Contents (5)4.0Hardware Description (6)4.1Host Interface (7)4.2Jumper Setting & Definition (8)4.3Power Supply and Test Point Definition (9)4.4RJ-45 Connector and Transformer (9)4.5EEPROM and LED Indicators (9)4.6Board Reset (10)5.0Bill of Materials (11)Micrel, Inc. August 6, 2010List of FiguresFigure 1. KSZ8851-16MLL Evaluation Board (6)Figure 2. KSZ8851-16MLL-Eval Host Interface Connection with Spirent SmartBits (7)List of TablesTable 1. Header JP1 – Host Interface Connection for SD[15:0] (7)Table 2. Header JP1 – Host Interface Connection for Control and Power (8)Table 3. KSZ8851-16MLL-Eval Jumper Definition (8)Table 4. KSZ8851-16MLL-Eval Test Point Definition (9)Table 5. KSZ8851-16MLL EEPROM Format (9)Table 6. KSZ8851-16MLL-Eval Port Status LED Definition (10)Table 7. KSZ8851-16MLL-Eval LED Definition (10)Micrel, Inc. August 6, 20101.0 IntroductionThe KSZ8851-16MLL-Eval Evaluation Board is intended to provide a convenient and fast way to evaluate or demonstrate the functionality and performance of this new Single-Port Ethernet Controller KSZ8851-16MLL device from Micrel.The KSZ8851-16MLL comes with a 48-pin, lead-free LQFP (7mm x 7mm) package and provides an ideal solution for applications requiring high-performance from single-port Ethernet Controller with 8-bit or 16-bit generic processor interface. The KSZ8851-16MLL offers the most cost-effective solution for adding high-throughput Ethernet connectivity to traditional embedded systems.This evaluation board is designed as a stand alone without microcontroller or M16C on board. By default the KSZ8851-16MLL-Eval board comes with an operation of 16-bit bus mode, Little Endian mode and disabled EEPROM for KSZ8851-16MLL device. Customer may wire the board for his desired interface. The purpose is to provide a simple tool that can be used to evaluate the KSZ8851-16MLL device by connecting via headers to customer provided Microcontroller or Non-PCI hardware platform.Micrel provides a basic software driver based on the 8 or 16-bit bus solution and different operating system platforms to evaluate the KSZ8851-16MLL functionality and performance. The software includes a configuration utility to allow quick and easy device setup, initialization and transmit/receive packet. All KSZ8851-16MLL configuration pins and host interface signals are accessible either by jumpers, test points or headers.2.0 Board Features•One KSZ8851-16MLL 48-pin Single-Port Ethernet Controller with shared data bus for host interface•Single +5V/GND power input from headers•RJ-45 Jack for Fast Ethernet cable interface•HP Auto-MDIX for automatic detection and correction for straight-through and crossover cables•Two on board LDO voltage regulators, one for VDD_IO and the other for VDD_A3.3•One AT93C46 for external EEPROM interface•Two LED indicators for port status and activity•One LED indicator for 3.3V output ready•One LED indicator for Power Management Event (PME) output status•Jumpers to configure strapping pins and VDD_IO voltage option•Headers to wire the host interface from external hardware platform•Manual reset button for quick reboot after re-configuration of strapping pins3.0 Evaluation Kit ContentsThe KSZ8851-16MLL Evaluation Kit includes the following hardware:•KSZ8851-16MLL Evaluation BoardThe KSZ8851-16MLL Data Sheet and Hardware Design Package with the following collaterals that can be downloaded from Micrel’s website at •KSZ8851-16MLL Eval Board Schematic (PDF and OrCAD DSN file)•KSZ8851-16MLL Eval Board Gerber File (PDF version included)•KSZ8851-16MLL Eval Board User’s Guide (this document and included BOM)•KSZ8851-16MLL IBIS ModelMicrel, Inc. August 6, 20104.0 Hardware DescriptionThe KSZ8851-16MLL-Eval (shown in Figure 1) comes in a compact form factor and plugs directly into industry standard test equipment such as Spirent SmartBits, the other side of board is wired to external host interface through headers. Configuration of the KSZ8851-16MLL is accomplished through on-board jumper selections and/or by register access via the host shared data/control bus Interface.Figure 1. KSZ8851-16MLL Evaluation Board (Rev 1.1)Other features include a RJ-45 Jack for Fast Ethernet cable connection, transformer (Pulse H1102) to block DC level and provide a true AC coupling, EEPROM (Atmel AT93C46) to load MAC address when it is enabled, jumper to select LDO output for VDD_IO voltage, programmable LED indicators for reporting port link status and activity, and a manual reset button for quick reboot after re-configuration of strapping pins.The KSZ8851-16MLL-Eval receives +5V DC input power supply from its Headers JP1.Micrel, Inc. August 6, 2010Micrel, Inc. August 6, 20104.1 Host InterfaceThe KSZ8851-16MLL-Eval board receives +5V power from the header JP1 (pin 1/3). Figure 2 shows the Host interface connection with Spirent SmartBits for system set-up and performance test.Figure 2. KSZ8851-16MLL-Eval Host Interface Connection with Spirent SmartBitsThe KSZ8851-16MLL-Eval has a 40-pin header (JP1) for Host interface to external any Non-PCI hardware platform. Table 1 lists Shared Data SD[15:0] pin outs for the Host interface on header JP1. Table 2 lists the rest of control signals and power/ground pin outs for the Host interface on header JP1.16-Bit Bus Mode (pin 1 pull-up) 8-Bit Bus Mode (pin 1 pull down) Pin # (JP1) Shared Data Bus Signal CMD = 0 (low) CMD = 1 (high) CMD = 0 (low) CMD = 1 (high) 20 SD0 D0 x (don’t care) D0 A0 19SD1D1 x (don’t care) D1 A1 18 SD2 D2 A2 D2 A2 17 SD3 D3 A3 D3 A3 16 SD4 D4 A4 D4 A4 15 SD5 D5 A5 D5 A5 14 SD6 D6 A6 D6 A6 13 SD7 D7 A7 D7 A7 12 SD8 D8 x (don’t care) GND GND 11 SD9 D9 x (don’t care) GND GND 10 SD10 D10 x (don’t care) GND GND 9SD11D11 x (don’t care) GND GND 8 SD12 D12 BE0 GND GND 7 SD13 D13 BE1 GND GND 6 SD14 D14 BE2 GND GND 5 SD15D15BE3GNDGNDTable 1. Header JP1 – Host Interface Connection for SD[15:0]Pin # (JP1) Power & ControlSignal NamesDescription1, 3 5.0V_IN +5V power supply inputs for this board 2, 4, 21, 22, 25,26, 29, 33, 34, 37, 38, 39, 40 GND Groundinputs/pins23 CPU_CSN Chip Select input from host CPU24 CPU_RSTN Reset input from host CPU27 CPU_PME Power Management Event output to host CPU28 CPU_CMD Command type input from host CPU31 CPU_INTRN Interrupt output to host CPU35 CPU_WRN Write input from host CPU36 CPU_RDN Read input from host CPU30, 32 Spares For customer to useTable 2. Header JP1 – Host Interface Connection for Control and Power4.2 Jumper Setting & DefinitionThe KSZ8851-16MLL-Eval does not require any jumper for normal operation except the VDD_IO option. During power-up, the KSZ8851-16MLL is configured using the chip’s internal pull-up and pull-down resistors with its default strapping pin values which will set this device in operation of 16-bit bus mode, little endian and without EEPROM. Jumpers are provided to override the default settings, allowing for quick configuration and re-configuration of the board. To override the default settings, simply select and close the desired jumper setting(s) and toggle the on-board manual reset button (S1) for the new setting(s) to take effect.The KSZ8851-16MLL-Eval jumper settings are defined in Table 3 below.Jumper Definition Setting DescriptionJP2 EED_IO OFF (Default) OFF: EEPROM is not presentON: EEPROM is presentJP3 3.3V ON (Default) ON: to select 3.3V for VDD_IO (JP5 and JP6 must be OFF)OFF: De-select 3.3VJP4 EESK OFF (Default) OFF: Little EndianON: Big EndianJP5 2.5V OFF (Default) ON: to select 2.5V for VDD_IO (JP3 and JP6 must be OFF)OFF: De-select 2.5VJP6 1.8V OFF (Default) ON: to select 1.8V for VDD_IO (JP3 and JP5 must be OFF)OFF: De-select 1.8VJP7 P1LED1 OFF (Default) OFF: 16-Bit bus modeON: 8-Bit bus modeJP8 VDD_IO OFF (Default) OFF: VDD_IO = 2.5V or 3.3VON: VDD_IO = 1.8VTable 3. KSZ8851-16MLL-Eval Jumper DefinitionMicrel, Inc. August 6, 2010Power Supply and Test Point DefinitionThe KSZ8851-16MLL-Eval is supplied from external +5.0V DC power through a jumper (pin 1 and 3 at JP1), this +5.0V DC input is converted to both +3.3V with a Micrel LDO voltage regulator (U3, MIC5209BM) for VDD_A3.3 analog power and VDD (option for 3.3V, 2.5V or 1.8V) with a Micrel LDO voltage regulator (U5, MIC5209BM) for VDD_IO digital power. The KSZ8851-16MLL contains an internal +1.8V LDO, to provide its core, analog and PLL voltages.The KSZ8851-16MLL-Eval has four test points. They are defined in the following Table 4.Test Point DefinitionTP1 Power supply measurement for VDD_IOTP2 Power supply measurement for VDD_A3.3TP3 1.8V digital core voltage output measurement fromKSZ8851-16MLL internal LDOTP4 External power supply 5.0V_IN measurementTable 4. KSZ8851-16MLL-Eval Test Point Definition4.3 RJ-45 Connector and TransformerThe RJ-45 Jack (J1) connects to standard CAT-5 Ethernet cable to interface with 10Base-T/100Base-TX Ethernet devices. The LAN interface on the KSZ8851-16MLL is connected to a transformer (T1) with 50 ohm termination resistors for both TX+/- and RX+/- differential pairs. The line side of the transformer is connected to the RJ-45 connectors (J1).J1 also supports Auto-MDIX and Auto-Negotiation / Forced Modes.4.4 EEPROM and LED IndicatorsIt is optional in the KSZ8851-16MLL to use an external EEPROM. The EED_IO (JP2) must be pulled high (ON) to use external EEPROM.An external serial EEPROM with a standard microwire bus interface is used for non-volatile storage of information such as the host MAC address. The KSZ8851-16MLL can detect if the EEPROM is either a 1KB (93C46) or 4KB (93C66) EEPROM device. The EEPROM must be organized as 16-bit mode.The KSZ8851-16MLL EEPROM format is given in Table 5.WORD 15 8 7 00H Reserved1H Host MAC Address Byte 2 Host MAC Address Byte 12H Host MAC Address Byte 4 Host MAC Address Byte 33H Host MAC Address Byte 6 Host MAC Address Byte 54H – 6H Reserved7H-3FH Not used for KSZ8851-16MLL (available for user to use)Table 5. KSZ8851-16MLL EEPROM FormatMicrel, Inc. August 6, 2010A dual LED indicator (LED1) is located adjacent to the RJ-45 Connector (J1). The top LED is connected to P1LED1 (pin 1) and bottom LED is connected to P1LED0 (pin 2) of the KSZ8851-16MLL.The two LEDs are programmable to LED mode ‘0’ or ‘1’ via register 0xC6 bits [9], and are defined in the following Table 6.LED Mode0 (Default) 1LED1 (Top) 100BT ACTLED1 (Bottom) LINK/ACT LINKTable 6. KSZ8851-16MLL-Eval Port Status LED DefinitionTable 7 shows the rest of LEDs definition.LED Color DescriptionLED2 Green Power Management Event (PME) StatusLED3 Red 3.3V Power available indicatorTable 7. KSZ8851-16MLL-Eval LED Definition4.5 Board ResetThe KSZ8851-16MLL-Eval generates a reset signal from the reset circuitry during power up. It also provides a push button S1 reset circuit to reset the KSZ8851-16MLL device. During power up, the board is automatically reset. User can also press reset button S1 on the board for a manual reset.Micrel, Inc. August 6, 2010KSZ8851-16MLL-Eval Evaluation Board User’s Guide Rev. 1.1 Micrel, Inc.August 6, 201011/11 5.0 Bill of MaterialsKSZ8851-16MLL Eval Board (Revision 1.1)。

MSM8939核心板项目规格书

I2S NFC 指纹模块接口摄像头闪光灯控制接口环境光传感器接口电池接口 USB MIC EAR Output SPEAKER 耳机
为外挂回声抑制预留 NFC 接口
SPI 总线指纹模块接口
支持
1 1 2 路，开关切换双路 1 路差分输出 1 路，0.8W max 1路 12+（不用的引脚复用可增加
27 28 30
PRI_MIC_GND PRI_MIC_P MIC_BIAS1
AUDIO AUDIO AUDIO
主 MIC 参考地主 MIC 输入信号 MIC 偏压 1.8v
主 MIC 地
不要接外围主地，直接 31 32 33 34 SEC_MIC_GND SEC_MIC_P SPKR_OUT_M SPKR_OUT_P AUDIO AUDIO AUDIO AUDIO 副 MIC 参考地副 MIC 输入引脚扬声器输出 M 扬声器输出 P 不要接外围主地，直接 35 36 37 38 39 40 42 43 44 GND_HEADSET EAR_OUT_M EAR_OUT_P CDC_HPH_L CDC_HPH_R MIC_P_HSET BLSP3_CS1_N PS_HOLD_PMIC_TP LED_R_DRV AUDIO GND AUDIO AUDIO AUDIO AUDIO AUDIO SPI DEBUG PIN LED_DRV 耳机参考地 earpice 输出 M earpice 输出 P 耳机左声道输出耳机右声道输出耳机 mic 输入指纹/SPI 片选信号 1，SPI sdcard 时使用 PS_HOLD 调试引脚 5mA 1.8v logic 接耳机地副 MIC 地
深圳元麦科技有限公司
WCDMA Band Standard CDMA Band Standard GSM BAND Standard WLAN/BT/ FM 802.11a/b/g/n/ac WLAN WIFI 热点 Bluetooth 4.0 FM 支持支持 RX 2.4G & 5.8G supported 支持 GSM 850/900/1800/1900; follow 3GPP spec CDMA 1x&EVDO 800; follow 3GPP spec WCDMA 850/900/1900/2100; follow 3GPP spec

MIC4120YME;MIC4129YML TR;MIC4129YME;MIC4120YME TR;MIC4129YME TR;中文规格书,Datasheet资料

MIC4120/41296A-Peak Low-Side MoSfet Driver Bipolar/CMoS/DMoS ProcessGeneral DescriptionMIC4120 and MIC4129 MOSFET drivers are resilient, efficient, and easy to use. The MIC4129 is an inverting driver, while the MIC4120 is a non-inverting driver. The MIC4120 and MIC4129 are improved versions of the MIC4420 and MIC4429.The drivers are capable of 6A (peak) output and can drive the largest MOSFETs with an improved safe operating margin. The MIC4120/4129 accept any logic input from 2.4V to V S without external speed-up capacitors or resis -tor networks. Proprietary circuits allow the input to swing negative by as much as 5V without damaging the part. Ad -ditional circuits protect against damage from electrostatic discharge.MIC4120/4129 drivers can replace three or more discrete components, reducing PCB area requirements, simplifying product design, and reducing assembly cost.Modern BiCMOS/DMOS construction guarantees freedom from latch-up. The rail-to-rail swing capability insures ad -equate gate voltage to the MOSFET during power up/down sequencing.features• CMOS Construction• Latch-Up Protected: Will Withstand >200mA Reverse Output Current• Logic Input Withstands Negative Swing of Up to 5V • Matched Rise and Fall Times ................................25ns • High Peak Output Current ...............................6A Peak • Wide Operating Range ...............................4.5V to 20V • High Capacitive Load Drive ............................10,000pF • Low Delay Time ..............................................55ns Typ • Logic High Input for Any Voltage From 2.4V to V S• Low Equivalent Input Capacitance (typ) ..................6pF • Low Supply Current ...............450µA With Logic 1 Input • Low Output Impedance .........................................2.5Ω• Output Voltage Swing Within 25mV of Ground or V S • Exposed backside pad packaging reduces heat- ePAD SOIC-8L (θJA = 58°C/W )- 3mm x 3mm MLF™-8L (θJA = 60°C/W )Applications• Switch Mode Power Supplies • Motor Controls• Pulse Transformer Driver •Class-D Switching Amplifiersfunctional DiagramV Micrel, Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 474-1000 • MLF is a registered trademark of Amkor Technology, Inc.Pin ConfigurationsV S OUT OUT GNDV S IN NC GND EPAD SOIC-8 (ME)MLF-8 (ML)Ordering InformationPart Number Package Configuration Lead Finish MIC4120YME EPAD 8-Pin SOICNon-Inverting Pb-Free MIC4120YML 8-Pin MLF Non-Inverting Pb-Free MIC4129YME EPAD 8-Pin SOICInverting Pb-Free MIC4129YML8-Pin MLFInvertingPb-FreePin DescriptionPin NumberPin NamePin Function 2IN Control Input4, 5GND Ground: Duplicate pins must be externally connected together 1, 8VS Supply Input: Duplicate pins must be externally connected together 6, 7OUT Output: Duplicate pins must be externally connected together 3NC Not connected EPGNDGround: BacksideElectrical Characteristics: (T A = 25°C with 4.5V ≤ V S ≤ 20V unless otherwise specified. Note 3.) Input Voltage slew rate>1V/µs Symbol ParameterConditionsMinTypMaxUnitsINPUT V IH Logic 1 Input Voltage 2.4 1.9 V V IL Logic 0 Input Voltage 1.5 0.8 V V IN Input Voltage Range–5 V S + 0.3 V I IN Input Current0 V ≤ V IN ≤ V S–1010µAOUTPUT V OH High Output Voltage See Figure 1 V S –0.025V V OL Low Output Voltage See Figure 10.025 V R O Output Resistance, I OUT = 10 mA, V S = 20 V 1.4 5 Ω Output Low R O Output Resistance, I OUT = 10 mA, V S = 20 V 1.5 5 Ω Output High I PK Peak Output Current V S = 20 V (See Figure 6) 6 A I R Latch-Up Protection200mAWithstand Reverse CurrentSwItChInG tIMet R Rise Time Test Figure 1, C L = 2200 pF 12 30 ns35 ns t F Fall Time Test Figure 1, C L = 2200 pF 13 30 ns35 ns t D1 Delay Time Test Figure 1 45 75 ns100 ns t D2 Delay Time Test Figure 1 50 75 ns100 ns POWER SUPPLYI S Power Supply Current V IN = 3 V 0.45 3 mAV IN = 0 V 60 400 µA V SOperating Input Voltage4.520V1. Functional operation above the absolute maximum stress ratings is not implied.2. Static-sensitive device. Store only in conductive containers. Handling personnel and equipment should be grounded to prevent damage from static discharge.3. Specification for packaged product only.4. Devices are ESD sensitive. Handling precautions recommended. Human body model: 1.5kΩ in series with 100pF.Absolute Maximum Ratings (Notes 1, 2 and 3)Supply Voltage ...........................................................24V Input Voltage ...............................V S + 0.3V to GND – 5V Input Current (V IN > V S ) ..........................................50mA Storage Temperature .............................–65°C to +150°C Lead Temperature (10 sec.) ...................................300°C ESD Rating, note 4operating RatingsSupply Voltage ..............................................4.5V to 20V Junction Temperature ............................–40°C to +125°C Package Thermal Resistance3x3 MLF™ (q JA ) ...............................................60°C/W EPAD SOIC-8 (q JA ) ..........................................58°C/WFigure 1. Inverting Driver Switching Time90%10%10%0V 5V V S OUTPUTINPUT90%0V90%10%10%0V 5V V S OUTPUTINPUT90%0VFigure 2. Non-inverting Driver Switching Timetest CircuitsTypical CharacteristicsApplications InformationSupply BypassingCharging and discharging large capacitive loads quickly requires large currents. For example, charging a 2500pF load to 18V in 25ns requires a 1.8 A current from the device power supply.The MIC4120/4129 has double bonding on the supply pins, the ground pins and output pins This reduces parasitic lead inductance. Low inductance enables large currents to be switched rapidly. It also reduces internal ringing that can cause voltage breakdown when the driver is operated at or near the maximum rated voltage.Internal ringing can also cause output oscillation due to feedback. This feedback is added to the input signal since it is referenced to the same ground.To guarantee low supply impedance over a wide frequency range, a parallel capacitor combination is recommended for supply bypassing. Low inductance ceramic capacitors should be used. A 1µF low ESR film capacitor in parallel with two 0.1 µF low ESR ceramic capacitors provide adequate bypassing. Connect one ceramic capacitor directly between pins 1 and 4. Connect the second ceramic capacitor directly between pins 8 and 5.GroundingThe high current capability of the MIC4120/4129 demands careful PC board layout for best performance. Since the MIC4129 is an inverting driver, any ground lead impedance will appear as negative feedback which can degrade switch-ing speed. Feedback is especially noticeable with slow-rise time inputs.Figure 3 shows the feedback effect in detail. As the MIC4129 input begins to go positive, the output goes negative and several amperes of current flow in the ground lead. As little as 0.05Ω of PC trace resistance can produce hundreds of millivolts at the MIC4129 ground pins. If the driving logic is referenced to power ground, the effective logic input level is reduced and oscillation may result.To insure optimum performance, separate ground traces should be provided for the logic and power connections. Con-necting the logic ground directly to the MIC4129 GND pins will ensure full logic drive to the input and ensure fast output switching. Both of the MIC4129 GND pins should, however, still be connected to power ground.The E-Pad and MLF packages have an exposed pad under the package. It's important for good thermal performance that this pad is connected to a ground plane.Table 1: MIC4129 Maximum operating frequencyV S Max Frequency20V 1Mhz 15V 1.5MHz 10V 3.5MHzConditions:T A = 25°C, 3. C L = 2500pFInput StageThe input voltage level of the 4129 changes the quiescent supply current. The N channel MOSFET input stage transistor drives a 450µA current source load. With a logic “1” input, the maximum quiescent supply current is 450µA. Logic “0” input level signals reduce quiescent current to 55µA maximum.The MIC4120/4129 input is designed to provide hysteresis. This provides clean transitions, reduces noise sensitivity, and minimizes output stage current spiking when changing states. Input voltage threshold level is approximately 1.5V, making the device TTL compatible over the 4.5V to 20V operating supply voltage range. Input current is less than 10µA over this range.The MIC4129 can be directly driven by the MIC9130, MIC3808, MIC38HC42 and similar switch mode power supply. By offload -ing the power-driving duties to the MIC4120/4129, the power supply controller can operate at lower dissipation. This can improve performance and reliability.The input can be greaterthan the +V S supply, however, current will flow into the input lead. The propagation delay for T D2 will increase to as much as 400ns at room temperature. The input currents can be as high as 30mA p-p (6.4mA RMS ) with the input, 6 V greater than the supply voltage. No damage will occur to MIC4120/4129 however, and it will not latch.The input appears as a 7pF capacitance, and does not change even if the input is driven from an AC source. Care should be taken so that the input does not go more than 5 volts below the negative rail.Power DissipationCMOS circuits usually permit the user to ignore power dis -sipation. Logic families such as 4000 and 74C have outputs which can only supply a few milliamperes of current, and even shorting outputs-to-ground will not force enough current to destroy the device. The MIC4120/4129, on the other hand, can source or sink several amperes and drive large capacitive loads at high frequency. The package power dissipation limitcan easily be exceeded. Therefore, some attention should be given to power dissipation when driving low impedance loads and/or operating at high frequency.The supply current vs frequency and supply current vs capaci -tive load characteristic curves aid in determining power dissi -pation calculations. Table 1 lists the maximum safe operating frequency for several power supply voltages when driving a 2500pF load. More accurate power dissipation figures can be obtained by summing the three dissipation sources.Given the power dissipation in the device, and the thermal resistance of the package, junction operating temperature for any ambient is easy to calculate. For example, the ther -mal resistance of the 8-pin EPAD MSOP package, from the data sheet, is 60°C/W. In a 25°C ambient, then, using a maximum junction temperature of 150°C, this package will dissipate 2W.Accurate power dissipation numbers can be obtained by total -ing the three sources of power dissipation in the device:• Load Power Dissipation (P L )• Quiescent power dissipation (P Q )• Transition power dissipation (P T )Calculation of load power dissipation differs depending upon whether the load is capacitive, resistive or inductive.Resistive Load Power DissipationDissipation caused by a resistive load can be calculated as:P L = I 2 R O D where:I = the current drawn by the loadR O = the output resistance of the driver when the output is high, at the power supply voltage used. (See data sheet)D = fraction of time the load is conducting (duty cycle)Figure 3. Switching Time Degradation Due tonegative feedbacktransition Power DissipationTransition power is dissipated in the driver each time its out -put changes state, because during the transition, for a very brief interval, both the N- and P-channel MOSFETs in the output totem-pole are ON simultaneously, and a current is conducted through them from V +S to ground. The transition power dissipation is approximately:P T = 2 f V S (A•s)where (A•s) is a time-current factor derived from the typical characteristic curves.Total power (P D ) then, as previously described is: P D = P L + P Q +P TDefinitionsC L = Load Capacitance in Farads.D = Duty Cycle expressed as the fraction of time theinput to the driver is high. f = Operating Frequency of the driver in Hertz. I H = Power supply current drawn by a driver when bothinputs are high and neither output is loaded. I L = Power supply current drawn by a driver when bothinputs are low and neither output is loaded. I D = Output current from a driver in Amps. P D = Total power dissipated in a driver in Watts. P L = Power dissipated in the driver due to the driver’sload in Watts. P Q = Power dissipated in a quiescent driver in Watts.P T = Power dissipated in a driver when the outputchanges states (“shoot-through current”) in Watts. NOTE: The “shoot-through” current from a dual transition (once up, once down) for both drivers is shown by the "Typical Characteristic Curve": Crossover Area vs. Supply Voltage and is in am -pere-seconds. This figure must be multiplied by the number of repetitions per second (frequency) to find Watts. R O = Output resistance of a driver in Ohms.V S = Power supply voltage to the IC in Volts.Capacitive Load Power DissipationDissipation caused by a capacitive load is simply the energy placed in, or removed from, the load capacitance by the driver. The energy stored in a capacitor is described by the equation:E = 1/2 C V 2As this energy is lost in the driver each time the load is charged or discharged, for power dissipation calculations the 1/2 is removed. This equation also shows that it is good practice not to place more voltage on the capacitor than is necessary, as dissipation increases as the square of the voltage applied to the capacitor. For a driver with a capacitive load: P L = f C (V S )2where:f = O perating Frequency C = L oad Capacitance V S = D river Supply VoltageInductive Load Power DissipationFor inductive loads the situation is more complicated. For the part of the cycle in which the driver is actively forcing current into the inductor, the situation is the same as it is in the resistive case:P L1 = I 2 R O DHowever, in this instance the R O required may be either the on resistance of the driver when its output is in the high state, or its on resistance when the driver is in the low state, depending on how the inductor is connected, and this is still only half the story. For the part of the cycle when the induc -tor is forcing current through the driver, dissipation is best described asP L2 = I V D (1-D)where V D is the forward drop of the clamp diode in the driver (generally around 0.7V). The two parts of the load dissipation must be summed in to produce P LP L = P L1 + P L2Quiescent Power DissipationQuiescent power dissipation (P Q , as described in the input section) depends on whether the input is high or low. A low input will result in a maximum current drain (per driver) of ≤0.2mA; a logic high will result in a current drain of ≤2.0mA. Quiescent power can therefore be found from: P Q = V S [D I H + (1-D) I L ]where: I H = quiescent current with input high I L = quiescent current with input lowD = fraction of time input is high (duty cycle)V S =power supply voltage5.0V 0V18V0Vfigure 4. Peak output Current test CircuitPackage Information8-Pin 3x3 MLF (ML)8-Pin Exposed Pad SOIC (ME)MICREL INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USAtel + 1 (408) 944-0800 fax + 1 (408) 474-1000 web This information furnished by Micrel in this data sheet is believed to be accurate and reliable. However no responsibility is assumed by Micrel for its use.Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnifyMicrel for any damages resulting from such use or sale.© 2004 Micrel Incorporated分销商库存信息:MICRELMIC4120YME MIC4129YML TR MIC4129YME MIC4120YME TR MIC4129YME TR MIC4120YML TR。

收音芯片汇总

KT0922
（立体声）
SOP16
2.2V-3.6V
AM：500KHz-1710KHz
FM：32.0MHz-110.0MHz
32768Hz
1．无需MCU控制（单芯片AM/FM收音机）。
2．通过调整单联电位器来选台（PVR）。
3．通过调整单联电位器来调节音量（立体声）。
4．频率起点和终点可自由设定。
5.新增一路LINEIN功能、立体声指示灯和调谐指示灯。
KT0921
（立体声）
SSOP16
2.2V-3.6V
AM：500KHz-1710KHz
FM：32.0MHz-110.0MHz
32768Hz
1．无需MCU控制（单芯片AM/FM收音机）。
2．通过三种方式选台：按键（CH+、CH-）；编码器；单联电位器（PVR）。
3．支持3610频率显示。
4．频率起点和终点可自由设定。
KT0922M
（单声道）
SSOP16
2.2V-3.6V
AM：500KHz-1710KHz
FM：32.0MHz-110.0MHz
32768Hz
1．无需MCU控制（单芯片AM/FM收音机）。
2．通过调整单联电位器来选台（PVR）。
3．通过调整单联电位器来调节音量。
4．频率起点和终点可自由设定。
5.新增一路调谐指示灯。
收音芯片汇总
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4．CH+、CH-、VOL+、VOL-按键。
KT0830EG
（立体声）
SOP16
2.0V-3.6V
FM：64.0MHz-109.0MHz
32768Hz
(可软件设定其他参考频率，最高26.0MHz)

常用开关电源芯片大全之欧阳育创编

常用开关电源芯片大全第1章DC-DC电源转换器/基准电压源1.1 DC-DC电源转换器1.低噪声电荷泵DC-DC电源转换器AAT3113/AAT31142.低功耗开关型DC-DC电源转换器ADP30003.高效3A开关稳压器AP15014.高效率无电感DC-DC电源转换器FAN56605.小功率极性反转电源转换器ICL76606.高效率DC-DC电源转换控制器IRU30377.高性能降压式DC-DC电源转换器ISL64208.单片降压式开关稳压器L49609.大功率开关稳压器L4970A10.1.5A降压式开关稳压器L497111.2A高效率单片开关稳压器L497812.1A高效率升压/降压式DC-DC电源转换器L597013.1.5A降压式DC-DC电源转换器LM157214.高效率1A降压单片开关稳压器LM1575/LM2575/LM2575HV15.3A降压单片开关稳压器LM2576/LM2576HV16.可调升压开关稳压器LM257717.3A降压开关稳压器LM259618.高效率5A开关稳压器LM267819.升压式DC-DC电源转换器LM2703/LM270420.电流模式升压式电源转换器LM273321.低噪声升压式电源转换器LM275022.小型75V降压式稳压器LM500723.低功耗升/降压式DC-DC电源转换器LT107324.升压式DC-DC电源转换器LT161525.隔离式开关稳压器LT172526.低功耗升压电荷泵LT175127.大电流高频降压式DC-DC电源转换器LT176528.大电流升压转换器LT193529.高效升压式电荷泵LT193730.高压输入降压式电源转换器LT195631.1.5A升压式电源转换器LT196132.高压升/降压式电源转换器LT343333.单片3A升压式DC-DC电源转换器LT343634.通用升压式DC-DC电源转换器LT346035.高效率低功耗升压式电源转换器LT346436.1.1A升压式DC-DC电源转换器LT346737.大电流高效率升压式DC-DC电源转换器LT378238.微型低功耗电源转换器LTC175439.1.5A单片同步降压式稳压器LTC187540.低噪声高效率降压式电荷泵LTC191141.低噪声电荷泵LTC3200/LTC3200-542.无电感的降压式DC-DC电源转换器LTC325143.双输出/低噪声/降压式电荷泵LTC325244.同步整流/升压式DC-DC电源转换器LTC340145.低功耗同步整流升压式DC-DC电源转换器LTC340246.同步整流降压式DC-DC电源转换器LTC340547.双路同步降压式DC-DC电源转换器LTC340748.高效率同步降压式DC-DC电源转换器LTC341649.微型2A升压式DC-DC电源转换器LTC342650.2A两相电流升压式DC-DC电源转换器LTC342851.单电感升/降压式DC-DC电源转换器LTC344052.大电流升/降压式DC-DC电源转换器LTC344253.1.4A同步升压式DC-DC电源转换器LTC345854.直流同步降压式DC-DC电源转换器LTC370355.双输出降压式同步DC-DC电源转换控制器LTC373656.降压式同步DC-DC电源转换控制器LTC377057.双2相DC-DC电源同步控制器LTC380258.高性能升压式DC-DC电源转换器MAX1513/MAX151459.精简型升压式DC-DC电源转换器MAX1522/MAX1523/MAX152460.高效率40V升压式DC-DC电源转换器MAX1553/MAX155461.高效率升压式LED电压调节器MAX1561/MAX159962.高效率5路输出DC-DC电源转换器MAX156563.双输出升压式DC-DC电源转换器MAX1582/MAX1582Y64.驱动白光LED的升压式DC-DC电源转换器MAX158365.高效率升压式DC-DC电源转换器MAX1642/MAX164366.2A降压式开关稳压器MAX164467.高效率升压式DC-DC电源转换器MAX1674/MAX1675/MAX167668.高效率双输出DC-DC电源转换器MAX167769.低噪声1A降压式DC-DC电源转换器MAX1684/MAX168570.高效率升压式DC-DC电源转换器MAX169871.高效率双输出降压式DC-DC电源转换器MAX171572.小体积升压式DC-DC电源转换器MAX1722/MAX1723/MAX172473.输出电流为50mA的降压式电荷泵MAX173074.升/降压式电荷泵MAX175975.高效率多路输出DC-DC电源转换器MAX180076.3A同步整流降压式稳压型MAX1830/MAX183177.双输出开关式LCD电源控制器MAX187878.电流模式升压式DC-DC电源转换器MAX189679.具有复位功能的升压式DC-DC电源转换器MAX194780.高效率PWM降压式稳压器MAX1992/MAX199381.大电流输出升压式DC-DC电源转换器MAX61882.低功耗升压或降压式DC-DC电源转换器MAX62983.PWM升压式DC-DC电源转换器MAX668/MAX66984.大电流PWM降压式开关稳压器MAX724/MAX72685.高效率升压式DC-DC电源转换器MAX756/MAX75786.高效率大电流DC-DC电源转换器MAX761/MAX76287.隔离式DC-DC电源转换器MAX8515/MAX8515A88.高性能24V升压式DC-DC电源转换器MAX872789.升/降压式DC-DC电源转换器MC33063A/MC34063A90.5A升压/降压/反向DC-DC电源转换器MC33167/MC3416791.低噪声无电感电荷泵MCP1252/MCP125392.高频脉宽调制降压稳压器MIC220393.大功率DC-DC升压电源转换器MIC229594.单片微型高压开关稳压器NCP1030/NCP103195.低功耗升压式DC-DC电源转换器NCP1400A96.高压DC-DC电源转换器NCP140397.单片微功率高频升压式DC-DC电源转换器NCP141098.同步整流PFM步进式DC-DC电源转换器NCP142199.高效率大电流开关电压调整器NCP1442/NCP1443/NCP1444/NCP1445100.新型双模式开关稳压器NCP1501101.高效率大电流输出DC-DC电源转换器NCP1550102.同步降压式DC-DC电源转换器NCP1570103.高效率升压式DC-DC电源转换器NCP5008/NCP5009 104.大电流高速稳压器RT9173/RT9173A105.高效率升压式DC-DC电源转换器RT9262/RT9262A106.升压式DC-DC电源转换器SP6644/SP6645107.低功耗升压式DC-DC电源转换器SP6691108.新型高效率DC-DC电源转换器TPS54350109.无电感降压式电荷泵TPS6050x110.高效率升压式电源转换器TPS6101x111.28V恒流白色LED驱动器TPS61042112.具有LDO输出的升压式DC-DC电源转换器TPS6112x 113.低噪声同步降压式DC-DC电源转换器TPS6200x114.三路高效率大功率DC-DC电源转换器TPS75003115.高效率DC-DC电源转换器UCC39421/UCC39422116.PWM控制升压式DC-DC电源转换器XC6371117.白光LED驱动专用DC-DC电源转换器XC9116118.500mA同步整流降压式DC-DC电源转换器XC9215/XC9216/XC9217119.稳压输出电荷泵XC9801/XC9802120.高效率升压式电源转换器ZXLB16001.2 线性/低压差稳压器121.具有可关断功能的多端稳压器BAXXX122.高压线性稳压器HIP5600123.多路输出稳压器KA7630/KA7631124.三端低压差稳压器LM2937125.可调输出低压差稳压器LM2991126.三端可调稳压器LM117/LM317127.低压降CMOS500mA线性稳压器LP38691/LP38693128.输入电压从12V到450V的可调线性稳压器LR8129.300mA非常低压降稳压器（VLDO）LTC3025130.大电流低压差线性稳压器LX8610131.200mA负输出低压差线性稳压器MAX1735132.150mA低压差线性稳压器MAX8875133.带开关控制的低压差稳压器MC33375134.带有线性调节器的稳压器MC33998135.1.0A低压差固定及可调正稳压器NCP1117136.低静态电流低压差稳压器NCP562/NCP563137.具有使能控制功能的多端稳压器PQxx138.五端可调稳压器SI-3025B/SI-3157B139.400mA低压差线性稳压器SPX2975140.五端线性稳压器STR20xx141.五端线性稳压器STR90xx142.具有复位信号输出的双路输出稳压器TDA8133143.具有复位信号输出的双路输出稳压器TDA8138/TDA8138A144.带线性稳压器的升压式电源转换器TPS6110x145.低功耗50mA低压降线性稳压器TPS760xx146.高输入电压低压差线性稳压器XC6202147.高速低压差线性稳压器XC6204148.高速低压差线性稳压器XC6209F149.双路高速低压差线性稳压器XC64011.3 基准电压源150.新型XFET基准电压源ADR290/ADR291/ADR292/ADR293151.低功耗低压差大输出电流基准电压源MAX610x152.低功耗1.2V基准电压源MAX6120153.2.5V精密基准电压源MC1403154.2.5V/4.096V基准电压源MCP1525/MCP1541155.低功耗精密低压降基准电压源REF30xx/REF31xx156.精密基准电压源TL431/KA431/TLV431A第2章AC-DC转换器及控制器1.厚膜开关电源控制器DP104C2.厚膜开关电源控制器DP308P3.DPA-Switch系列高电压功率转换控制器DPA423/DPA424/DPA425/DPA4264.电流型开关电源控制器FA13842/FA13843/FA13844/FA138455.开关电源控制器FA5310/FA53116.PWM开关电源控制器FAN75567.绿色环保的PWM开关电源控制器FAN76018.FPS型开关电源控制器FS6M07652R9.开关电源功率转换器FS6Sxx10.降压型单片AC-DC转换器HV-2405E11.新型反激准谐振变换控制器ICE1QS0112.PWM电源功率转换器KA1M088013.开关电源功率转换器KA2S0680/KA2S088014.电流型开关电源控制器KA38xx15.FPS型开关电源功率转换器KA5H0165R16.FPS型开关电源功率转换器KA5Qxx17.FPS型开关电源功率转换器KA5Sxx18.电流型高速PWM控制器L499019.具有待机功能的PWM初级控制器L599120.低功耗离线式开关电源控制器L659021.LINK SWITCH TN系列电源功率转换器LNK304/LNK305/LNK30622.LINK SWITCH系列电源功率转换器LNK500/LNK501/LNK52023.离线式开关电源控制器M51995A24.PWM电源控制器M62281P/M62281FP25.高频率电流模式PWM控制器MAX5021/MAX502226.新型PWM开关电源控制器MC4460427.电流模式开关电源控制器MC4460528.低功耗开关电源控制器MC4460829.具有PFC功能的PWM电源控制器ML482430.液晶显示器背光灯电源控制器ML487631.离线式电流模式控制器NCP120032.电流模式脉宽调制控制器NCP120533.准谐振式PWM控制器NCP120734.低成本离线式开关电源控制电路NCP121535.低待机能耗开关电源PWM控制器NCP123036.STR系列自动电压切换控制开关STR8xxxx37.大功率厚膜开关电源功率转换器STR-F665438.大功率厚膜开关电源功率转换器STR-G865639.开关电源功率转换器STR-M6511/STR-M652940.离线式开关电源功率转换器STR-S5703/STR-S5707/STR-S570841.离线式开关电源功率转换器STR-S6401/STR-S6401F/STR-S6411/STR-S6411F 442.开关电源功率转换器STR-S651343.离线式开关电源功率转换器TC33369～TC3337444.高性能PFC与PWM组合控制集成电路TDA16846/TDA1684745.新型开关电源控制器TDA1685046.“绿色”电源控制器TEA150447.第二代“绿色”电源控制器TEA150748.新型低功耗“绿色”电源控制器TEA153349.开关电源控制器TL494/KA7500/MB375950.Tiny SwitchⅠ系列功率转换器TNY253、TNY254、TNY25551.Tiny SwitchⅡ系列功率转换器TNY264P～TNY268G52.TOP Switch（Ⅱ）系列离线式功率转换器TOP209～TOP22753.TOP Switch-FX系列功率转换器TOP232/TOP233/TOP23454.TOP Switch-GX系列功率转换器TOP242～TOP25055.开关电源控制器UCX84X56.离线式开关电源功率转换器VIPer12AS/VIPer12ADIP57.新一代高度集成离线式开关电源功率转换器VIPer53第3章功率因数校正控制/节能灯电源控制器1.电子镇流器专用驱动电路BL83012.零电压开关功率因数控制器FAN48223.功率因数校正控制器FAN75274.高电压型EL背光驱动器HV8265.EL场致发光背光驱动器IMP525/IMP5606.高电压型EL背光驱动器/反相器IMP8037.电子镇流器自振荡半桥驱动器IR21568.单片荧光灯镇流器IR21579.调光电子镇流器自振荡半桥驱动器IR215910.卤素灯电子变压器智能控制电路IR216111.具有功率因数校正电路的镇流器电路IR216612.单片荧光灯镇流器IR216713.自适应电子镇流器控制器IR252014.电子镇流器专用控制器KA754115.功率因数校正控制器L656116.过渡模式功率因数校正控制器L656217.集成背景光控制器MAX8709/MAX8709A18.功率因数校正控制器MC33262/MC3426219.固定频率电流模式功率因数校正控制器NCP165320.EL场致发光灯高压驱动器SP440321.功率因数校正控制器TDA4862/TDA486322.有源功率因数校正控制器UC385423.高频自振荡节能灯驱动器电路VK05CFL24.大功率高频自振荡节能灯驱动器电路VK06TL第4章充电控制器1.多功能锂电池线性充电控制器AAT36802.可编程快速电池充电控制器BQ20003.可进行充电速率补偿的锂电池充电管理器BQ20574.锂电池充电管理电路BQ2400x5.单片锂电池线性充电控制器BQ2401xB接口单节锂电池充电控制器BQ2402x7.2A同步开关模式锂电池充电控制器BQ241008.集成PWM开关控制器的快速充电管理器BQ29549.具有电池电量计量功能的充电控制器DS277010.锂电池充电控制器FAN7563/FAN756411.2A线性锂/锂聚合物电池充电控制器ISL629212.锂电池充电控制器LA5621M/LA5621V13.1.5A通用充电控制器LT157114.2A恒流/恒压电池充电控制器LT176915.线性锂电池充电控制器LTC173216.带热调节功能的1A线性锂电池充电控制器LTC173317.线性锂电池充电控制器LTC173418.新型开关电源充电控制器LTC198019.开关模式锂电池充电控制器LTC400220.4A锂电池充电器LTC400621.多用途恒压/恒流充电控制器LTC400822.4.2V锂离子/锂聚合物电池充电控制器LTC405223.可由USB端口供电的锂电池充电控制器LTC405324.小型150mA锂电池充电控制器LTC405425.线性锂电池充电控制器LTC405826.单节锂电池线性充电控制器LTC405927.独立线性锂电池充电控制器LTC406128.镍镉/镍氢电池充电控制器M62256FP29.大电流锂/镍镉/镍氢电池充电控制器MAX150130.锂电池线性充电控制器MAX150731.双输入单节锂电池充电控制器MAX1551/MAX155532.单节锂电池充电控制器MAX167933.小体积锂电池充电控制器MAX1736B接口单节锂电池充电控制器MAX181135.多节锂电池充电控制器MAX187336.双路输入锂电池充电控制器MAX187437.单节锂电池线性充电控制器MAX189838.低成本/多种电池充电控制器MAX190839.开关模式单节锂电池充电控制器MAX1925/MAX192640.快速镍镉/镍氢充电控制器MAX2003A/MAX200341.可编程快速充电控制器MAX712/MAX71342.开关式锂电池充电控制器MAX74543.多功能低成本充电控制器MAX846A44.具有温度调节功能的单节锂电池充电控制器MAX8600/MAX860145.锂电池充电控制器MCP73826/MCP73827/MCP7382846.高精度恒压/恒流充电器控制器MCP73841/MCP73842/MCP73843/MCP73844 647.锂电池充电控制器MCP73861/MCP7386248.单节锂电池充电控制器MIC7905049.单节锂电池充电控制器NCP180050.高精度线性锂电池充电控制器VM7205。

迈来芯芯片datasheet

FeaturesMicrocontroller: MLX16-FX RISC CPUo16 bit RISC CPU with 20DMIPS and Power-Saving-Modeso Co-processor for fast multiplication and divisiono Flash and EEPROM memory with EECprotocol TruSense Motor Control Technologyand slope control for optimal EMC and thermal performance during power N-FET switching o Monitoring of Drain-Source voltages of the N-FETsPeripheryo 4 independent 16 bit timer modules with capture and compare, and additional software timero 3 programmable 12 bit PWM units with programmable frequencieso10 bit ADC converter (2µs conversion time) and DMA accesso On-chip temperature sensor with ±10K accuracyo System-clock-independent fully integrated watchdogo32 MHz ±5% internal RC oscillator with PLLo Optional crystal oscillatoro Load dump and brown out interrupt functiono Integrated shunt current amplifier with programmable gainApplicationsThe MLX81205/07/10/15 controls BLDC motors via external FET transistors for:Contents1.FUNCTIONAL DIAGRAM (5)2.PIN DESCRIPTION (6)3.777 4.8810111213 5.1414141415 6.1616167.178.181. Functional DiagramHS2T......f mainFigure 1 - Block Diagram Black: common for all versions,Blue: additional pins / functionality for MLX81207,Blue + red: additional pins / functionality for MLX81210 / MLX81215Table 3 - Pin Description MLX81205 / MLX81207 / MLX81210 / MLX81215 3.Electrical CharacteristicsTable 5 - Absolute Maximum Ratings[1] Target temperature specification after qualification. With temperature applications at TA>125°C a reduction of chip internal power dissipation with external supply transistor is mandatory. The extended temperature range is only allowed for a limited period of time, customer’s mission profile has to be agreed by Melexis as a mandatory part of the Part Submission Warrant.4.Application ExamplesThe following sections show typical application examples[1].externalThecan beof the [1]4.2 Sensor-less BLDC Motor Control on the LIN-Bus or via PWM-Interface withreverse polarity protection in the high side pathIn the sample application of Figure 3, the MLX81207 has been selected in order to benefit from the external high side reverse polarity protection possibility compared to the application shown in section 4.1.All other remarks from the previous application example remain valid.Figure 3 – Typical Sensor-less BLDC Motor Control Application Example with MLX812074.3 Sensor based BLDC Motor ControlIn the sample application of, Figure 4, the MLX81207 can realize the driving of a BLDC motor with three Hall sensors. An external P-FET is used to derive the 3.3V supply with a higher current capability in order to bring power consumption outside the MLX81207.4.4 Sensor-less BLDC Motor Control with absolute position sensingIn the sample application of Figure 5, the MLX81210 is working with an absolute position sensor in order to measure the position of the gear shaft in throttle valve application systems or any other similar applications, where absolute precise position sensing is requested.4.5 Sensor-less BLDC Motor Control via a CAN-Bus-InterfaceIn this sample application the MLX81215 can realize the sensor-less driving of a BLDC motor via a CAN-Bus Interface. System wake-up on CAN-bus traffic is possible. The 5V and a 3.3V voltage supply needed for the CAN-Bus, is generated via external N-FET control in order to limit the power dissipation in the package.The motor current can be monitored via shunt resistors in the ground and battery path in case the application requests a double side monitoring for security reasons.Figure 6 – Typical BLDC Motor Control Application Example on the CAN-Bus with MLX812155. Mechanical Specification5.1 QFN5.1.1. QFN32 5x5 (32 leads)Symbol [1][2]Table 6 – QFN32 5x5 Package Dimensions5.1.2. QFN48 7x7 (48 leads)Symbol [1][2]AA1 A3bDD2EE2eLN [3] ND [4] NE [4] 0.80 00.18 5.00 5.00 0.45 0.85 0.02 0.25 5.10 5.10 0.50Min QFN48 Nom Max0.90 0.05 0.20 0.30 7.00 5.20 7.00 5.20 0.50 0.55481212Table 7 - QFN48 7x7 Package Dimensions[1]Dimensions and tolerances conform to ASME Y14.5M-1994 [2] All dimensions are in Millimeters. All angels are in degrees [3] N is the total number of terminals[4]ND and NE refer to the number of terminals on each D and E side respectively5.2 TQFP EP 48 7x7 (48 leads)Table 8 – TQFP EP 7x7 Package DimensionsNotes:1. All Dimensioning and Tolerances conform to ASME Y14.5M-1994,∆2. Datum Plane [-|-|-] located at Mould Parting Line and coincident with Lead, where Lead exists, plastic body at bottom of parting line. ∆3. Datum [A-B] and [-D-] to be determined at centerline between leads where leads exist, plastic body at datum plane [-|-|-]∆4. To be determined at seating plane [-C-]∆5. Dimensions D1 and E1 do not include Mould protrusion. Dimensions D1 and E1 do not include mould protrusion. Allowable mould protrusion is 0.254 mm on D1 and E1 dimensions.6. 'N' is the total number of terminals∆7. These dimensions to be determined at datum plane [-|-|-]8. Package top dimensions are smaller than bottom dimensions and top of package will not overhang bottom of package.∆9. Dimension b does not include dam bar protrusion, allowable dam bar protrusion shall be 0.08mm total in excess of the "b"dimension at maximum material condition, dam bar can not be located on the lower radius of the foot.10. Controlling dimension millimeter.11. Maximum allowable die thickness to be assembled in this package family is 0.38mm12. This outline conforms to JEDEC publication 95 Registration MS-026, Variation ABA, ABC & ABD.∆13. A1 is defined as the distance from the seating plane to the lowest point of the package body.∆14. Dimension D2 and E2 represent the size of the exposed pad. The actual dimensions are specified ion the bonding diagram, and are independent from die size.15. Exposed pad shall be coplanar with bottom of package within 0.05.6.Marking/Order Code 6.1 Marking MLX81205/07/10/157.Assembly InformationThis Melexis device is classified and qualified regarding soldering technology, solder ability and moisture sensitivity level, as defined in this specification, according to following test methods: •IPC/JEDEC J-STD-0208.DisclaimerThe product abstract just provides an overview of the described devices. Please consult the complete product specification/datasheet in its latest revision for any detailed information.Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding theextendedmilitary, For the latest version of this document, go to our website atOr for additional information contact Melexis Direct:Europe, Africa, Asia: America:Phone: +32 1367 0495 Phone: +1 248 306 5400E-mail: sales_europe@ E-mail: sales_usa@ISO/TS16949 and ISO14001 Certified。

MEMORY存储芯片MT29F4G16ABCWC中文规格书

Address MultiplexingThe multiplexed address option is available by setting mode register bit M5 to 1. Oncethis bit is set, the READ, WRITE, and MRS commands follow the format described in theCommand Description in Multiplexed Address Mode figure. Further information on op-eration with multiplexed addresses can be seen in the Multiplexed Address Mode sec-tion.Although the device has the ability to operate with an SRAM interface by accepting theentire address in one clock, an option in the mode register can be set so that it functionswith multiplexed addresses, similar to a traditional DRAM.In multiplexed address mode, the address can be provided to the device in two partsthat are latched into the memory with two consecutive rising clock edges. This providesthe advantage of only needing a maximum of 11 address balls to control the device, re-ducing the number of signals on the controller side. The data bus efficiency in continu-ous burst mode is only affected when using the BL = 2 setting because the device re-quires two clocks to read and write the data.The bank addresses are delivered to the device at the same time as the WRITE andREAD command and the first address part, A x. The Address Mapping in MultiplexedAddress Mode table shows the addresses needed for both the first and second risingclock edges (A x and A y, respectively).The AREF command does not require an address on the second rising clock edge, as on-ly the bank address is needed during this command. Because of this, AREF commandsmay be issued on consecutive clocks.DLL RESETDLL reset is selected with bit M7 of the mode register. The default setting for this optionis LOW, whereby the DLL is disabled.Once M7 is set HIGH, 1024 cycles (5µs at 200 MHz) are needed before a READ com-mand can be issued. This time enables the internal clock to be synchronized with theexternal clock.Failing to wait for synchronization to occur may result in a violation of the t CKQK pa-rameter.A reset of the DLL is necessary if t CK or V DD is changed after the DLL has already beenenabled. To reset the DLL, an MRS command must be issued where M7 is set LOW. Afterwaiting t MRSC, a subsequent MRS command should be issued whereby M7 goes HIGH.1024 clock cycles are then needed before a READ command is issued.Drive Impedance MatchingThe device is equipped with programmable impedance output buffers. This option isselected by setting bit M8 HIGH during the MRS command. The purpose of the pro-grammable impedance output buffers is to enable the user to match the driver impe-dance to the system. To adjust the impedance, an external precision resistor (RQ) isconnected between the ZQ ball and V SS. The value of the resistor must be five times thedesired impedance. For example, a 300Ω resistor is required for an output impedance of60Ω. The range of RQ is 125–300Ω, which guarantees output impedance in the range of25–60Ω (within 15%).Output impedance updates may be required because over time variations may occur insupply voltage and temperature. When the external drive impedance is enabled in theMRS, the device will periodically sample the value of RQ. An impedance update is trans-parent to the system and does not affect device operation. All data sheet timing andcurrent specifications are met during an update.When bit M8 is set LOW during the MRS command, the device provides an internal im-pedance at the output buffer of 50Ω (±30% with temperature variation). This impe-dance is also periodically sampled and adjusted to compensate for variation in supplyvoltage and temperature.On-Die Termination (ODT)ODT is enabled by setting M9 to a value of 1 during an MRS command. With ODT on,the DQ and DM are terminated to V TT with a resistance R TT. The command, address,QVLD, and clock signals are not terminated.The ODT function is dynamically switched off when DQ begins to drive after a READcommand is issued. Similarly, ODT is designed to switch on at DQ after the device hasissued the last piece of data. The DM pin will always be terminated.Table 23: On-Die Termination DC ParametersNotes: 1.All voltages referenced to V SS (GND).2.V TT is expected to be set equal to V REF and must track variations in the DC level of V REF.3.The R TT value is measured at 95°C T C.Figure 16: On-Die Termination-Equivalent CircuitV TTREAD CommandRead accesses are initiated with a READ command, as shown in the figure below. Ad-dresses are provided with the READ command.During READ bursts, the memory device drives the read data so it is edge-aligned with the QK x signals. After a programmable READ latency, data is available at the outputs.One half clock cycle prior to valid data on the read bus, the data valid signal, QVLD,transitions from LOW to HIGH. QVLD is also edge-aligned with the QK x signals.The skew between QK and the crossing point of CK is specified as t CKQK. t QKQ0 is the skew between QK0 and the last valid data edge generated at the DQ signals associated with QK0 (t QKQ0 is referenced to DQ0–DQ17 for the x36 configuration and DQ0–DQ8for the x18 configuration). t QKQ1 is the skew between QK1 and the last valid data edge generated at the DQ signals associated with QK1 (t QKQ1 is referenced to DQ18–DQ35for the x36 and DQ9–DQ17 for the x18 configuration). t QKQ x is derived at each QK x clock edge and is not cumulative over time. t QKQ is defined as the skew between either QK differential pair and any output data edge.After completion of a burst, assuming no other commands have been initiated, output data (DQ) will go High-Z. The QVLD signal transitions LOW on the last bit of the READ burst. Note that if CK/CK# violates the V id(DC) specification while a READ burst is occur-ring, QVLD will remain HIGH until a dummy READ command is issued. The QK clocks are free-running and will continue to cycle after the READ burst is complete. Back-to-back READ commands are possible, producing a continuous flow of output data.The data valid window is derived from each QK transition and is defined as:t QHP - (t QKQ [MAX] + |t QKQ [MIN]|). See the Read Data Valid Window for x9 Device fig-ure, the Read Data Valid Window for x18 Device figure, and the Read Data Valid Window for x36 Device figure for illustration.Any READ burst may be followed by a subsequent WRITE command. The READ-to-WRITE figure illustrates the timing requirements for a READ followed by a WRITE. Some systems having long line lengths or severe skews may need additional idle cycles inser-ted between READ and WRITE commands to prevent data bus contention.Figure 17: READ CommandDON’T CARECKCK#CS#WE#REF#ADDRESSBANK ADDRESS 288Mb: x9, x18, x36 CIO RLDRAM 2READ Command。

MIC22200YML评估板：Micrel MIC22200YML评估板是一种集成2A同步降压调节器

MIC22200YML Evaluation BoardIntegrated 2A Synchronous BuckRegulatorRamp Control is a trademark of Micrel, Inc.Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 •General DescriptionThis board enables the evaluation of the MIC22200; a highpower density, frequency-adjustable synchronous buckregulator. The MIC22200 features integrated 2AMOSFETs, integrated frequency compensation, flexible sequencing and tracking abilities. The board is optimized for ease of testing, with all major components are on a single side. The voltage mode feedback loop is designed to allow high bandwidth with just 2 external compensation components. The high side MOSFET is a P-Channel one,allowing duty cycle control up to 100%.The Micrel MIC22200 is a high efficiency 2A Integratedsynchronous buck (step-down) regulator. The MIC22200 isoptimized for highest power density and achieves over85% efficiency whilst switching at 4MHz with only 1µHinductor and down to 22µF output capacitor. The ultra highspeed control loop keeps the output voltage withinregulation even under extreme transient load swingscommonly found in FPGAs and low voltage ASICs. Theoutput voltage can be adjusted down to 0.7V to address alllow voltage power needs. The MIC22200 offers a full-range of sequencing and tracking options. The enable/delay pin combined with the power good/POR pin allows multiple outputs to be sequenced in any way on turn-on and turn-off. The RC (Ramp Control™) pin allows the device to be connected to another MIC22200 device to keep the output voltages within a certain delta V on start up. RequirementsThis board needs a single bench power source adjustable over the input voltage of interest that can provide at least 2A of current. The loads can either be active (electronic load) or passive (resistor) with the ability to dissipate the maximum load power while keeping accessible surfaces ideally < 70°C. It is ideal to have an oscilloscope to view the circuit waveforms, but not essential. For the simplest tests, two Voltage meters are required to measure input and output voltages. For efficiency measurements, two voltage and two current meters are required to prevent errors due to measurement inaccuracies.PrecautionsThere is no reverse input protection on this board. Whenconnecting the input sources, ensure that the correctpolarity is observed.Under extreme load conditions such as short circuit testing, input transients can be quite large if long test leads are used. In such cases, place a 22µF or 47µF, 6.3V Tantalum capacitor at the V IN terminals to prevent over voltage damage to the IC. Getting Started 1. Connect V IN supply to the input terminals +V IN and GND . With the output of this supply disabled, set its voltage to the desired input test voltage. This supply voltage should be monitored at the test boards input terminals to allow voltage drops in the test cables (and ammeter if used) to be accounted for. An ammeter can be added inline with the +V IN input terminal to accurately measure input current as some power sources current andvoltage displays can be misleading. 2. Connect the loads to the output terminalsbetween +V O and GND . Again, this output voltage should be monitored by connecting the voltmeter at the +V O and GND terminals. An ammeter can be added inline with the +V O terminal of the evaluation board to accurately measure the output current. Initially, set the output load to 0A to check that the output is regulating properly prior to loaded tests. 3. Enable the input supply . By default, the outputvoltage is enabled when an input supply of > 2.5V is applied. When this threshold is crossed, the enable pin capacitor (1nF) begins to charge at 1V/µs until it reaches 1.25V, where switching begins. To test the Enable functions of the MIC22200, a test point is provided.Ordering InformationPart Number DescriptionMIC22200YML EVEvaluation board with the Integrated 2A MIC22200 deviceOther FeaturesEnable DelayC7 creates a delay set by an internal 1µA source charging to a 1.25V threshold. Using a switch-to-ground (Q1) using ‘Shdn’ to enable the part will exhibit approximately 1.3µs enable delay from ‘Shdn’ going low to the start of switching. Using a pulse generator with a low impedance output connected to the EN terminal will remove this delay as it defeats the internal 1µA source.RC (Ramp Control™) CapacitorThe MIC22200 has a nominal 1µA current source/sink to the RC pin. The startup output voltage waveform tracks the voltage on RC. 100% output voltage is represented by 0.7V on RC. The default capacitor on RC (C3) of 1nF therefore sets the ramp up time to approximately 700µs. Feedback resistorsThe output is set nominally at 1.8V. This can be changed by adjusting the upper or lower resistor in the FB potential dividers. It is recommended that R1 or R2 value should be kept <10k to reduce noise susceptibility and offset currents from creating voltage errors. Therefore, choosing R1<10k: R2 = R1 V REF/(V O – V REF)Where V REF = 0.7VDelayAdding an external capacitor to this pin allows the Power Good delay to be adjusted to perform as a Power-On Reset (POR). As with the RC pin, this pin has an internal 1µA current source and sink. When V FB reaches 90% of its nominal voltage (~ 630mV) the internal 1µA current source charges the capacitor on this pin (C4) to the rising threshold of 1.25V, at this point, PG is asserted high. When the enable pin is set low, POR is asserted low immediately. However, the internal ‘Delay’ current sink discharges the capacitor (C4) to 1.25V lower than its starting point, at which point, it enables the RC pin 1µA current sink to begin discharging C3. Power On Reset (POR)This is an open drain connection with an on board pull-up resistor (R3) to SV IN. This is only asserted high when the FB pin reaches >90% of its nominal set voltage. This can be used as part of the Tracking and sequencing function described in the data sheet.Typical Characteristics606570758085909510000.51 1.52OUTPUT CURRENT (A)V IN = 3.3VV IN = 5.0V 606570758085909510000.51 1.52OUTPUT CURRENT (A)V IN = 3.3VV IN = 5.0VFunctional CharacteristicsEvaluation Board SchematicBill of MaterialsItem Part Number ManufacturerDescription Qty. C2012X5R0J106K TDK (1)GRM2196R60J106K Murata (2) C108056D106KAT2A AVX (3) Capacitor, 10µF, 6.3V, X5R, Size 08051C1608X5R0J105K TDK (1)GRM188R60J105KA01D Murata (2) C206036D105KAT2A AVX (3)Capacitor, 1µF, 6.3V, X5R, Size 0603 1C1608C0G1H102J TDK (1)GRM1885C1H102JA01D Murata (2)C3, C7, C8 06035A102KAT2A AVX (3)Capacitor, 1nF, 50V, NPO, Size 0603 3C1608X7R1H332K TDK (1)GRM188R71H332KA01D Murata (2) C406035C332KAT2A AVX (3)Capacitor, 3.3nF, 50V, X7R, Size 0603 1C1608C0G1H470J TDK (1)GQM1885C1H470JB01D Murata (2) C506035A470JAT2A AVX (3)Capacitor, 47pF, 50V, NPO, Size 0603 1C1608C0G1H221J TDK (1)GRM1885C1H221JA01D Murata (2)C606035A221JAT2A AVX (3)Capacitor, 220pF, 50V, NPO, Size 06031Notes:1. TDK: 2. Murata: 3. Vishay: 4.Micrel, Inc.: PCB Layout RecommendationsTop LayerTop SilkPCB Layout Recommendations (Continued)Bottom Layer。

AT90PWM316-16ME中文资料

Features•High Performance, Low Power AVR ® 8-bit Microcontroller •Advanced RISC Architecture–129 Powerful Instructions - Most Single Clock Cycle Execution –32 x 8 General Purpose Working Registers–Fully Static Operation–Up to 1 MIPS throughput per MHz–On-chip 2-cycle Multiplier•Data and Non-Volatile Program Memory–16K Bytes Flash of In-System Programmable Program Memory•Endurance: 10,000 Write/Erase Cycles–Optional Boot Code Section with Independent Lock Bits•In-System Programming by On-chip Boot Program•True Read-While-Write Operation–512 Bytes of In-System Programmable EEPROM•Endurance: 100,000 Write/Erase Cycles–1024 Bytes Internal SRAM–Programming Lock for Flash Program and EEPROM Data Security•On Chip Debug Interface (debugWIRE)•Peripheral Features–Two or three 12-bit High Speed PSC (Power Stage Controllers) with 4-bitResolution Enhancement•Non Overlapping Inverted PWM Output Pins With Flexible Dead-Time•Variable PWM duty Cycle and Frequency•Synchronous Update of all PWM Registers•Auto Stop Function for Event Driven PFC Implementation•Less than 25 Hz Step Width at 150 kHz Output Frequency•PSC2 with four Output Pins and Output Matrix–One 8-bit General purpose Timer/Counter with Separate Prescaler and Capture Mode–One 16-bit General purpose Timer/Counter with Separate Prescaler, Compare Mode and Capture Mode–Programmable Serial USART•Standard UART mode•16/17 bit Biphase Mode for DALI Communications–Master/Slave SPI Serial Interface–10-bit ADC•Up To 11 Single Ended Channels and 2 Fully Differential ADC Channel Pairs •Programmable Gain (5x, 10x, 20x, 40x on Differential Channels)•Internal Reference Voltage–10-bit DAC–Two or three Analog Comparator with Resistor-Array to Adjust ComparisonVoltage–4 External Interrupts–Programmable Watchdog Timer with Separate On-Chip Oscillator•Special Microcontroller Features–Low Power Idle, Noise Reduction, and Power Down Modes–Power On Reset and Programmable Brown Out Detection–Flag Array in Bit-programmable I/O Space (4 bytes)Microcontroller with 16K Bytes In-System Programmable AT90PWM216 AT90PWM316Summary27710CS–AVR–01/08AT90PWM216/316–In-System Programmable via SPI Port –Internal Calibrated RC Oscillator ( 8 MHz)–On-chip PLL for fast PWM ( 32 MHz, 64 MHz) and CPU (16 MHz)•Operating Voltage: 2.7V - 5.5V •Extended Operating Temperature:–-40°C to +105°1.History2.DisclaimerTypical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max val-ues will be available after the device is characterized.Product Package 12 bit PWM with deadtime ADC Input ADC Diff Analog Compar ApplicationAT90PWM216SO24 2 x 2812One fluorescent ballast AT90PWM316SO32,QFN323 x 21123HID ballast, fluorescent ballast, Motor controlProduct RevisionAT90PWM216AT90PWM316First revision of parts37710CS–AVR–01/08AT90PWM216/3163.Pin ConfigurationsFigure 3-1.SOIC 24-pin PackageFigure 3-2.SOIC 32-pin Package47710CS–AVR–01/08AT90PWM216/3163.1Pin Descriptions:Table 3-1.Pin out descriptionS024 PinNumberSO32 Pin NumberQFN32 Pin NumberMnemonic Type Name, Function & Alternate Function795GND Power Ground: 0V reference182420AGNDPowerAnalog Ground: 0V reference for analog part57710CS–AVR–01/08AT90PWM216/316684VCCpowerPower Supply:172319AVCC PowerAnalog Power Supply: This is the power supply voltage for analog partFor a normal use this pin must be connected.192521AREF PowerAnalog Reference : reference for analog converter . This is the reference voltage of the A/D converter. As output, can be used by external analog8128PBO I/OMISO (SPI Master In Slave Out)PSCOUT20 output9139PB1I/OMOSI (SPI Master Out Slave In)PSCOUT21 output162016PB2I/O ADC5 (Analog Input Channel5 )INT1202723PB3I/O AMP0- (Analog Differential Amplifier 0 Input Channel )212824PB4I/O AMP0+ (Analog Differential Amplifier 0 Input Channel )223026PB5I/OADC6 (Analog Input Channel 6)INT 2233127PB6I/O ADC7 (Analog Input Channel 7)ICP1B (Timer 1 input capture alternate input)PSCOUT11 output (see note 1)243228PB7I/O PSCOUT01 outputADC4 (Analog Input Channel 4)SCK (SPI Clock)NA230PC0I/OPSCOUT10 output (see note 1) INT373PC1I/OPSCIN1 (PSC 1 Digital Input) OC1B (Timer 1 Output Compare B)106PC2I/OT0 (Timer 0 clock input)PSCOUT22 output 117PC3I/O T1 (Timer 1 clock input)PSCOUT23 output2117PC4I/OADC8 (Analog Input Channel 8)AMP1- (Analog Differential Amplifier 1 Input Channel )2218PC5I/OADC9 (Analog Input Channel 9)AMP1+ (Analog Differential Amplifier 1 Input Channel )2622PC6I/O ADC10 (Analog Input Channel 10)ACMP1 (Analog Comparator 1 Positive Input )2925PC7I/OD2A : DAC outputTable 3-1.Pin out description (Continued)S024 Pin NumberSO32 Pin NumberQFN32 Pin NumberMnemonic Type Name, Function & Alternate Function67710CS–AVR–01/08AT90PWM216/3161.PSCOUT10 & PSCOUT11 are not present on 24 pins package4.OverviewThe AT90PWM216/316 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90PWM216/316 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.1129PD0I/O PSCOUT00 outputXCK (UART Transfer Clock)SS_A (Alternate SPI Slave Select)3432PD1I/OPSCIN0 (PSC 0 Digital Input )CLKO (System Clock Output)451PD2I/O PSCIN2 (PSC 2 Digital Input)OC1A (Timer 1 Output Compare A)MISO_A (Programming & alternate SPI Master In Slave Out)562PD3I/OTXD (Dali/UART Tx data)OC0A (Timer 0 Output Compare A)SS (SPI Slave Select)MOSI_A (Programming & alternate Master Out SPI Slave In)121612PD4I/OADC1 (Analog Input Channel 1)RXD (Dali/UART Rx data)ICP1A (Timer 1 input capture)SCK_A (Programming & alternate SPI Clock)131713PD5I/OADC2 (Analog Input Channel 2)ACMP2 (Analog Comparator 2 Positive Input )141814PD6I/O ADC3 (Analog Input Channel 3 )ACMPM reference for analog comparators INT0151915PD7I/O ACMP0 (Analog Comparator 0 Positive Input )2331PE0I/O or IRESET (Reset Input)OCD (On Chip Debug I/O)101410PE1I/OXTAL1: XTAL InputOC0B (Timer 0 Output Compare B)111511PE2I/OXTAL2: XTAL OuTputADC0 (Analog Input Channel 0)Table 3-1.Pin out description (Continued)S024 Pin NumberSO32 Pin NumberQFN32 Pin NumberMnemonicTypeName, Function & Alternate Function77710CS–AVR–01/08AT90PWM216/3164.1Block DiagramFigure 4-1.Block DiagramThe AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con-ventional CISC microcontrollers.The AT90PWM216/316 provides the following features: 16K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 1024 bytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers,three Power Stage Controllers, two flex-ible Timer/Counters with compare modes and PWM, one USART with DALI mode, an 11-channel 10-bit ADC with two differential input stage with programmable gain, a 10-bit DAC, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, an On-chip Debug system and four software selectable power saving modes.87710CS–AVR–01/08AT90PWM216/316The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switch-ing noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption.The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,the Atmel AT90PWM216/316 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.The AT90PWM216/316 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emula-tors, and evaluation kits.4.2Pin Descriptions4.2.1VCCDigital supply voltage.4.2.2GNDGround.4.2.3Port B (PB7..PB0)Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,even if the clock is not running.Port B also serves the functions of various special features of the AT90PWM216/316 as listed on page 67.4.2.4Port C (PC7..PC0)Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,even if the clock is not running.Port C is not available on 24 pins package.Port C also serves the functions of special features of the AT90PWM216/316 as listed on page 70.97710CS–AVR–01/08AT90PWM216/3164.2.5Port D (PD7..PD0)Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,even if the clock is not running.Port D also serves the functions of various special features of the AT90PWM216/316 as listed on page 73.4.2.6Port E (PE2..0) RESET/ XTAL1/XTAL2Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,even if the clock is not running.If the RSTDISBL Fuse is programmed, PE0 is used as an I/O pin. Note that the electrical char-acteristics of PE0 differ from those of the other pins of Port C.If the RSTDISBL Fuse is unprogrammed, PE0 is used as a Reset input. A low level on this pin for longer than the minimum pulse length will generate a Reset, even if the clock is not running.The minimum pulse length is given in Table 9-1 on page 45. Shorter pulses are not guaranteed to generate a Reset.Depending on the clock selection fuse settings, PE1 can be used as input to the inverting Oscil-lator amplifier and input to the internal clock operating circuit.Depending on the clock selection fuse settings, PE2 can be used as output from the inverting Oscillator amplifier.The various special features of Port E are elaborated in “Alternate Functions of Port E” on page 76 and “Clock Systems and their Distribution” on page 28.4.2.7AVCCAVCC is the supply voltage pin for the A/D Converter. It should be externally connected to V CC ,even if the ADC is not used. If the ADC is used, it should be connected to V CC through a low-pass filter.4.2.8AREFThis is the analog reference pin for the A/D Converter.4.3About Code ExamplesThis documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-tation for more details.107710CS–AVR–01/08AT90PWM216/3165.Register SummaryAddressNameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Page(0xFF)PICR2H page 171(0xFE)PICR2L page 171(0xFD)PFRC2B PCAE2B PISEL2B PELEV2B PFLTE2B PRFM2B3PRFM2B2PRFM2B1PRFM2B0page 169(0xFC)PFRC2A PCAE2A PISEL2A PELEV2A PFLTE2A PRFM2A3PRFM2A2PRFM2A1PRFM2A0page 169(0xFB)PCTL2PPRE21PPRE20PBFM2PAOC2B PAOC2A PARUN2PCCYC2PRUN2page 168(0xFA)PCNF2PFIFTY2PALOCK2PLOCK2PMODE21PMODE20POP2PCLKSEL2POME2page 165(0xF9)OCR2RBH page 164(0xF8)OCR2RBL page 164(0xF7)OCR2SBH page 164(0xF6)OCR2SBL page 164(0xF5)OCR2RAH page 164(0xF4)OCR2RAL page 164(0xF3)OCR2SAH page 164(0xF2)OCR2SAL page 164(0xF1)POM2POMV2B3POMV2B2POMV2B1POMV2B0POMV2A3POMV2A2POMV2A1POMV2A0page 171(0xF0)PSOC2POS23POS22PSYNC21PSYNC20POEN2DPOEN2BPOEN2CPOEN2Apage 163(0xEF)PICR1H page 171(0xEE)PICR1L page 171(0xED)PFRC1B PCAE1B PISEL1B PELEV1B PFLTE1B PRFM1B3PRFM1B2PRFM1B1PRFM1B0page 169(0xEC)PFRC1A PCAE1A PISEL1A PELEV1A PFLTE1A PRFM1A3PRFM1A2PRFM1A1PRFM1A0page 169(0xEB)PCTL1PPRE11PPRE10PBFM1PAOC1B PAOC1A PARUN1PCCYC1PRUN1page 167(0xEA)PCNF1PFIFTY1PALOCK1PLOCK1PMODE11PMODE10POP1PCLKSEL1-page 165(0xE9)OCR1RBH page 164(0xE8)OCR1RBL page 164(0xE7)OCR1SBH page 164(0xE6)OCR1SBL page 164(0xE5)OCR1RAH page 164(0xE4)OCR1RAL page 164(0xE3)OCR1SAH page 164(0xE2)OCR1SAL page 164(0xE1)Reserved ––––––––(0xE0)PSOC1––PSYNC11PSYNC10–POEN1B–POEN1Apage 163(0xDF)PICR0H page 170(0xDE)PICR0L page 170(0xDD)PFRC0B PCAE0B PISEL0B PELEV0B PFLTE0B PRFM0B3PRFM0B2PRFM0B1PRFM0B0page 169(0xDC)PFRC0A PCAE0A PISEL0A PELEV0A PFLTE0A PRFM0A3PRFM0A2PRFM0A1PRFM0A0page 169(0xDB)PCTL0PPRE01PPRE00PBFM0PAOC0B PAOC0A PARUN0PCCYC0PRUN0page 166(0xDA)PCNF0PFIFTY0PALOCK0PLOCK0PMODE01PMODE00POP0PCLKSEL0-page 165(0xD9)OCR0RBH page 164(0xD8)OCR0RBL page 164(0xD7)OCR0SBH page 164(0xD6)OCR0SBL page 164(0xD5)OCR0RAH page 164(0xD4)OCR0RAL page 164(0xD3)OCR0SAH page 164(0xD2)OCR0SAL page 164(0xD1)Reserved ––––––––(0xD0)PSOC0––PSYNC01PSYNC00–POEN0B–POEN0Apage 163(0xCF)Reserved ––––––––(0xCE)EUDR EUDR7EUDR6EUDR5EUDR4EUDR3EUDR2EUDR1EUDR0page 222(0xCD)MUBRRH MUBRR15MUBRR014MUBRR13MUBRR12MUBRR011MUBRR010MUBRR9MUBRR8page 227(0xCC)MUBRRL MUBRR7MUBRR6MUBRR5MUBRR4MUBRR3MUBRR2MUBRR1MUBRR0page 227(0xCB)Reserved ––––––––(0xCA)EUCSRC ––––FEM F1617STP1STP0page 226(0xC9)EUCSRB –––EUSART EUSBS –EMCH BODR page 225(0xC8)EUCSRA UTxS3UTxS2UTxS1UTxS0URxS3URxS2URxS1URxS0page 224(0xC7)Reserved ––––––––(0xC6)UDR UDR07UDR06UDR05UDR04UDR03UDR02UDR01UDR00page 222 & page 203(0xC5)UBRRH ––––UBRR011UBRR010UBRR09UBRR08page 208(0xC4)UBRRL UBRR07UBRR06UBRR05UBRR04UBRR03UBRR02UBRR01UBRR00page 208(0xC3)Reserved ––––––––(0xC2)UCSRC –UMSEL0UPM01UPM00USBS0UCSZ01UCSZ00UCPOL0page 206(0xC1)UCSRB RXCIE0TXCIE0UDRIE0RXEN0TXEN0UCSZ02RXB80TXB80page 205(0xC0)UCSRA RXC0TXC0UDRE0FE0DOR0UPE0U2X0MPCM0page 204(0xBF)Reserved––––––––AT90PWM216/316Address Name Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Page(0xBE)Reserved––––––––(0xBD)Reserved––––––––(0xBC)Reserved––––––––(0xBB)Reserved––––––––(0xBA)Reserved––––––––(0xB9)Reserved––––––––(0xB8)Reserved––––––––(0xB7)Reserved––––––––(0xB6)Reserved––––––––(0xB5)Reserved––––––––(0xB4)Reserved––––––––(0xB3)Reserved––––––––(0xB2)Reserved––––––––(0xB1)Reserved––––––––(0xB0)Reserved––––––––(0xAF)AC2CON AC2EN AC2IE AC2IS1AC2IS0AC2SADE-AC2M2AC2M1AC2M0page 232(0xAE)AC1CON AC1EN AC1IE AC1IS1AC1IS0AC1ICE AC1M2AC1M1AC1M0page 231(0xAD)AC0CON AC0EN AC0IE AC0IS1AC0IS0-AC0M2AC0M1AC0M0page 230(0xAC)DACH- / DAC9- / DAC8- / DAC7- / DAC6- / DAC5- / DAC4DAC9 / DAC3DAC8 / DAC2page 263(0xAB)DACL DAC7 / DAC1DAC6 /DAC0DAC5 / -DAC4 / -DAC3 / -DAC2 / -DAC1 / -DAC0 / page 263(0xAA)DACON DAATE DATS2DATS1DATS0-DALA DAOE DAEN page 262(0xA9)Reserved––––––––(0xA8)Reserved––––––––(0xA7)Reserved––––––––(0xA6)Reserved––––––––(0xA5)PIM2--PSEIE2PEVE2B PEVE2A--PEOPE2page 172(0xA4)PIFR2--PSEI2PEV2B PEV2A PRN21PRN20PEOP2page 173(0xA3)PIM1--PSEIE1PEVE1B PEVE1A--PEOPE1page 172(0xA2)PIFR1--PSEI1PEV1B PEV1A PRN11PRN10PEOP1page 173(0xA1)PIM0--PSEIE0PEVE0B PEVE0A--PEOPE0page 172(0xA0)PIFR0--PSEI0PEV0B PEV0A PRN01PRN00PEOP0page 172(0x9F)Reserved––––––––(0x9E)Reserved––––––––(0x9D)Reserved––––––––(0x9C)Reserved––––––––(0x9B)Reserved––––––––(0x9A)Reserved––––––––(0x99)Reserved––––––––(0x98)Reserved––––––––(0x97)Reserved––––––––(0x96)Reserved––––––––(0x95)Reserved––––––––(0x94)Reserved––––––––(0x93)Reserved––––––––(0x92)Reserved––––––––(0x91)Reserved––––––––(0x90)Reserved––––––––(0x8F)Reserved––––––––(0x8E)Reserved––––––––(0x8D)Reserved––––––––(0x8C)Reserved––––––––(0x8B)OCR1BH OCR1B15OCR1B14OCR1B13OCR1B12OCR1B11OCR1B10OCR1B9OCR1B8page 128(0x8A)OCR1BL OCR1B7OCR1B6OCR1B5OCR1B4OCR1B3OCR1B2OCR1B1OCR1B0page 128(0x89)OCR1AH OCR1A15OCR1A14OCR1A13OCR1A12OCR1A11OCR1A10OCR1A9OCR1A8page 128(0x88)OCR1AL OCR1A7OCR1A6OCR1A5OCR1A4OCR1A3OCR1A2OCR1A1OCR1A0page 128(0x87)ICR1H ICR115ICR114ICR113ICR112ICR111ICR110ICR19ICR18page 128(0x86)ICR1L ICR17ICR16ICR15ICR14ICR13ICR12ICR11ICR10page 128(0x85)TCNT1H TCNT115TCNT114TCNT113TCNT112TCNT111TCNT110TCNT19TCNT18page 128(0x84)TCNT1L TCNT17TCNT16TCNT15TCNT14TCNT13TCNT12TCNT11TCNT10page 128(0x83)Reserved––––––––(0x82)TCCR1C FOC1A FOC1B––––––page 127(0x81)TCCR1B ICNC1ICES1–WGM13WGM12CS12CS11CS10page 126(0x80)TCCR1A COM1A1COM1A0COM1B1COM1B0––WGM11WGM10page 124(0x7F)DIDR1––ACMP0D AMP0PD AMP0ND ADC10D/ACMP1D ADC9D/AMP1PD ADC8D/AMP1ND page 254(0x7E)DIDR0ADC7D ADC6D ADC5D ADC4D ADC3D/ACMPMD ADC2D/ACMP2D ADC1D ADC0D page 254(0x7D)Reserved––––––––Address Name Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Page (0x7C)ADMUX REFS1REFS0ADLAR–MUX3MUX2MUX1MUX0page 249 (0x7B)ADCSRB ADHSM–––ADTS3ADTS2ADTS1ADTS0page 252 (0x7A)ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2ADPS1ADPS0page 251 (0x79)ADCH- / ADC9- / ADC8- / ADC7- / ADC6- / ADC5- / ADC4ADC9 / ADC3ADC8 / ADC2page 253 (0x78)ADCL ADC7 / ADC1ADC6 / ADC0ADC5 / -ADC4 / -ADC3 / -ADC2 / -ADC1 / -ADC0 / page 253 (0x77)AMP1CSR AMP1EN-AMP1G1AMP1G0-AMP1TS2AMP1TS1AMP1TS0page 258 (0x76)AMP0CSR AMP0EN-AMP0G1AMP0G0-AMP0TS2AMP0TS1AMP0TS0page 257 (0x75)Reserved––––––––(0x74)Reserved––––––––(0x73)Reserved––––––––(0x72)Reserved––––––––(0x71)Reserved––––––––(0x70)Reserved––––––––(0x6F)TIMSK1––ICIE1––OCIE1B OCIE1A TOIE1page 129 (0x6E)TIMSK0–––––OCIE0B OCIE0A TOIE0page 101 (0x6D)Reserved––––––––(0x6C)Reserved––––––––(0x6B)Reserved––––––––(0x6A)Reserved––––––––(0x69)EICRA ISC31ISC30ISC21ISC20ISC11ISC10ISC01ISC00page 80 (0x68)Reserved––––––––(0x67)Reserved––––––––(0x66)OSCCAL–CAL6CAL5CAL4CAL3CAL2CAL1CAL0page 33 (0x65)Reserved––––––––(0x64)PRR PRPSC2PRPSC1PRPSC0PRTIM1PRTIM0PRSPI PRUSART PRADC page 41 (0x63)Reserved––––––––(0x62)Reserved––––––––(0x61)CLKPR CLKPCE–––CLKPS3CLKPS2CLKPS1CLKPS0page 37 (0x60)WDTCSR WDIF WDIE WDP3WDCE WDE WDP2WDP1WDP0page 520x3F (0x5F)SREG I T H S V N Z C page 120x3E (0x5E)SPH SP15SP14SP13SP12SP11SP10SP9SP8page 140x3D (0x5D)SPL SP7SP6SP5SP4SP3SP2SP1SP0page 140x3C (0x5C)Reserved––––––––0x3B (0x5B)Reserved––––––––0x3A (0x5A)Reserved––––––––0x39 (0x59)Reserved––––––––0x38 (0x58)Reserved––––––––0x37 (0x57)SPMCSR SPMIE RWWSB–RWWSRE BLBSET PGWRT PGERS SPMEN page 2720x36 (0x56)Reserved––––––––0x35 (0x55)MCUCR SPIPS––PUD––IVSEL IVCE page 58 & page 67 0x34 (0x54)MCUSR––––WDRF BORF EXTRF PORF page 480x33 (0x53)SMCR––––SM2SM1SM0SE page 390x32 (0x52)MSMCR Monitor Stop Mode Control Register reserved0x31 (0x51)MONDR Monitor Data Register reserved0x30 (0x50)ACSR ACCKDIV AC2IF AC1IF AC0IF–AC2O AC1O AC0O page 2330x2F (0x4F)Reserved––––––––0x2E (0x4E)SPDR SPD7SPD6SPD5SPD4SPD3SPD2SPD1SPD0page 1830x2D (0x4D)SPSR SPIF WCOL–––––SPI2X page 1820x2C (0x4C)SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1SPR0page 1810x2B (0x4B)Reserved––––––––0x2A (0x4A)Reserved––––––––0x29 (0x49)PLLCSR-----PLLF PLLE PLOCK page 350x28 (0x48)OCR0B OCR0B7OCR0B6OCR0B5OCR0B4OCR0B3OCR0B2OCR0B1OCR0B0page 1010x27 (0x47)OCR0A OCR0A7OCR0A6OCR0A5OCR0A4OCR0A3OCR0A2OCR0A1OCR0A0page 1010x26 (0x46)TCNT0TCNT07TCNT06TCNT05TCNT04TCNT03TCNT02TCNT01TCNT00page 1010x25 (0x45)TCCR0B FOC0A FOC0B––WGM02CS02CS01CS00page 1000x24 (0x44)TCCR0A COM0A1COM0A0COM0B1COM0B0––WGM01WGM00page 970x23 (0x43)GTCCR TSM ICPSEL1–––––PSRSYNC page 830x22 (0x42)EEARH––––EEAR11EEAR10EEAR9EEAR8page 200x21 (0x41)EEARL EEAR7EEAR6EEAR5EEAR4EEAR3EEAR2EEAR1EEAR0page 200x20 (0x40)EEDR EEDR7EEDR6EEDR5EEDR4EEDR3EEDR2EEDR1EEDR0page 210x1F (0x3F)EECR––––EERIE EEMWE EEWE EERE page 210x1E (0x3E)GPIOR0GPIOR07GPIOR06GPIOR05GPIOR04GPIOR03GPIOR02GPIOR01GPIOR00page 260x1D (0x3D)EIMSK––––INT3INT2INT1INT0page 810x1C (0x3C)EIFR––––INTF3INTF2INTF1INTF0page 810x1B (0x3B)GPIOR3GPIOR37GPIOR36GPIOR35GPIOR34GPIOR33GPIOR32GPIOR31GPIOR30page 27AT90PWM216/316Address Name Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Page 0x1A (0x3A)GPIOR2GPIOR27GPIOR26GPIOR25GPIOR24GPIOR23GPIOR22GPIOR21GPIOR20page 26 0x19 (0x39)GPIOR1GPIOR17GPIOR16GPIOR15GPIOR14GPIOR13GPIOR12GPIOR11GPIOR10page 26 0x18 (0x38)Reserved––––––––0x17 (0x37)Reserved––––––––0x16 (0x36)TIFR1––ICF1––OCF1B OCF1A TOV1page 130 0x15 (0x35)TIFR0–––––OCF0B OCF0A TOV0page 102 0x14 (0x34)Reserved––––––––0x13 (0x33)Reserved––––––––0x12 (0x32)Reserved––––––––0x11 (0x31)Reserved––––––––0x10 (0x30)Reserved––––––––0x0F (0x2F)Reserved––––––––0x0E (0x2E)PORTE–––––PORTE2PORTE1PORTE0page 79 0x0D (0x2D)DDRE–––––DDE2DDE1DDE0page 79 0x0C (0x2C)PINE–––––PINE2PINE1PINE0page 79 0x0B (0x2B)PORTD PORTD7PORTD6PORTD5PORTD4PORTD3PORTD2PORTD1PORTD0page 78 0x0A (0x2A)DDRD DDD7DDD6DDD5DDD4DDD3DDD2DDD1DDD0page 78 0x09 (0x29)PIND PIND7PIND6PIND5PIND4PIND3PIND2PIND1PIND0page 79 0x08 (0x28)PORTC PORTC7PORTC6PORTC5PORTC4PORTC3PORTC2PORTC1PORTC0page 78 0x07 (0x27)DDRC DDC7DDC6DDC5DDC4DDC3DDC2DDC1DDC0page 78 0x06 (0x26)PINC PINC7PINC6PINC5PINC4PINC3PINC2PINC1PINC0page 78 0x05 (0x25)PORTB PORTB7PORTB6PORTB5PORTB4PORTB3PORTB2PORTB1PORTB0page 78 0x04 (0x24)DDRB DDB7DDB6DDB5DDB4DDB3DDB2DDB1DDB0page 78 0x03 (0x23)PINB PINB7PINB6PINB5PINB4PINB3PINB2PINB1PINB0page 78 0x02 (0x22)Reserved––––––––0x01 (0x21)Reserved––––––––0x00 (0x20)Reserved––––––––Note: 1.For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.2.I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In theseregisters, the value of single bits can be checked by using the SBIS and SBIC instructions.3.Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBIinstructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. TheCBI and SBI instructions work with registers 0x00 to 0x1F only.4.When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/ORegisters as data space using LD and ST instructions, 0x20 must be added to these addresses. The AT90PWM216/316 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDDinstructions can be used.6.Instruction Set SummaryMnemonics Operands Description Operation Flags#Clocks ARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H1 ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H1 SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H1 SBCI Rd, K Subtract with Carry Constant from Reg.Rd ← Rd - K - C Z,C,N,V,H1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S2 AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V1 ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V1 OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V1 ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V1 EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V1 COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V1 NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H1 SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V1 CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K)Z,N,V1 INC Rd Increment Rd ← Rd + 1Z,N,V1 DEC Rd Decrement Rd ← Rd − 1 Z,N,V1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V1 SER Rd Set Register Rd ← 0xFF None1 MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C2 MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C2 MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C2 FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1Z,C2 FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd x Rr) << 1Z,C2 FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr) << 1Z,C2 BRANCH INSTRUCTIONSRJMP k Relative Jump PC ← PC + k + 1None2 IJMP Indirect Jump to (Z)PC ← Z None2 JMP k Direct Jump PC ← k None3 RCALL k Relative Subroutine Call PC ← PC + k + 1None3 ICALL Indirect Call to (Z)PC ← Z None3 CALL k Direct Call PC ← k None4 RET Subroutine Return PC ← STACK None4 RETI Interrupt Return PC ← STACK I4 CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3None1/2/3 CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H1 CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3None1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3None1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1None1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1None1/2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1None1/2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1None1/2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1None1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1None1/2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1None1/2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1None1/2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1None1/2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1None1/2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1None1/2 BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1None1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1None1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1None1/2 BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1None1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1None1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1None1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1None1/2。

MIC3289-24YML中文资料

元器件交易网MIC32891.2MHz PWM White LED Driver with Internal Schottky Diode and True 1-Wire Digital Control PRELIMINARY INFORMATIONGeneral DescriptionThe MIC3289 is a PWM boost-switching regulator that is optimized for constant-current white LED driver applications. The MIC3289 features an internal Schottky diode, allowing an efficient DC/DC solution that requires only 4 external components. The MIC3289 allows for a single wire simple digital interface to control the dimming over 16 steps with a log scale to give better resolution at the lower currents to better match the sensitivity of the human eye The feedback voltage of the MIC3289 is only 250mV, allowing high efficiency while retaining excellent accuracy for the white LED current. The MIC3289 implements a constant frequency 1.2MHz PWM control scheme. The high frequency PWM operation saves board space by reducing external component sizes. The 1.2MHz PWM scheme also reduces switching noise and ripple to the input power source. The 2.5V to 6.5V input voltage range of MIC3289 allows direct operation from single cell Li Ion as well as 3- to 4cell NiCad/ NiMH/Alkaline batteries. Battery life is preserved with a low 1µA shutdown current. The MIC3289 is available in a low profile Thin SOT23 6® lead package and a 2mm × 2mm MLF -8L package and has a junction temperature range of –40°C to +125°C. Data sheets and support documentation can be found on Micrel’s web site at .Features• • • • • • • • • • • • • • • 2.5V to 6.5V input voltage Output voltage up to 24V 16V & 24V OVP options Single wire combines 16 level logarithmic brightness & shutdown control Internal Schottky diode 1.2 MHz PWM operation Over 500mA switch current Programmable ±5% current control <1% line and load regulation <1µA shutdown current Over temperature protection UVLO Thin SOT23-6L package option ® 2mm × 2mm leadless MLF -8L package option o o –40 C to +125 C junction temperature rangeApplications• White/Blue LED driver for backlighting - Cell phones - PDAs - GPS systems - Digital cameras - Multimedia / MP3 players • LED flashlights • Constant current power supplies ___________________________________________________________________________________________________________MicroLead Frame and MLF are registered trademarks of Amkor Technologies. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • March 2007M9999-030407 (408) 944-0800元器件交易网Micrel, Inc.MIC3289Typical ApplicationMIC3289 2mm×2mm MLFDigital Control0.27µF2mm×2mm 8-lead MLF White LED Driver with OVP and Digital Control®Ordering InformationPart Number MIC3289-16YD6 MIC3289-24YD6 MIC3289-16YML MIC3289-24YML Marking Code WF16 WF24 WFA WFB Output Voltage Adjustable Adjustable Adjustable Adjustable Over Voltage Protection 16V 24V 16V 24V Junction Temp. Range -40°C to 125°C -40°C to 125°C -40°C to 125°C -40°C to 125°C Package TSOT23-6 TSOT23-6 2x2 MLF -8L 2x2 MLF -8L® ®Pin ConfigurationOUT 1 2 3 4 8 7 6 5®GND SW FB NCSW 1 GND 2 FB 36 OUT 5 VIN 4 DCVIN DC GNDTSOT23-6 (D)2mm × 2mm 8-pin MLF (ML)March 20072M9999-030407 (408) 944-0800元器件交易网Micrel, Inc.MIC3289Pin DescriptionPin Number SOT23-6 Pin Number 8-pin MLF®Pin NamePin Name6 5 4 3 1 21 2 3 5 6 7 4,8 PadOUT VIN DC N/C FB SW GND GNDOutput and Over Voltage Protection (output) Supply (Input): 2.5V to 6.5V for internal circuitry. See diagrams No connect (no internal connection to die) Feedback (Input): Output voltage sense node. Connect the cathode of the LED to this pin. Switch Node (Input): Internal power BIPOLAR collector. Ground (Return): Ground. Ground (Return): Backside pad.March 20073M9999-030407 (408) 944-0800元器件交易网Micrel, Inc.MIC3289Absolute Maximum Ratings(1)Supply voltage (VIN) .....................................................7.5V Switch voltage (VSW ) ..................................... –0.3V to 27V Digital Control Voltage (VDC).............................. –0.3 to VIN FB Voltage (VFB) .............................................................6V Switch Current (ISW ) ........................................................2A Ambient Storage Temperature (TS) .........–65°C to +150°C ESD Rating, Note 3 ..................................................... 2KVOperating Ratings(2)Supply Voltage (VIN) …………………..…… ..... 2.5V to 6.5V Output Voltage (VOUT) …………….…...VIN to (VSW(MAX) - 4V) or VIN to VOVP (for options with over voltage protection) Junction Temperature Range (TJ) ……......-40°C to +125°C Package Thermal Impedance ® θJA 2mm × 2mm MLF -8L ..................................93°C/W θJA TSOT23-6 ..................................................235°C/WElectrical Characteristics(4)TA=25 C, VIN = 3.6V, VOUT = 10V, IOUT = 20mA, unless otherwise noted. Bold values indicate -40°C ≤ TJ ≤ 125°C.Symbol Parameter Condition Min Typ Max UnitsoVIN VUVLO IVIN ISD VFB IFBSupply Voltage Range Under-voltage Lockout Quiescent Current Shutdown Current (DC pin low ) Feedback Voltage Feedback Input Current Line Regulation Load Regulation VFB >500mV VDC = 0V for > 2ms. (+/-5%) VFB = 250mV 2.5V ≤ VIN ≤ 4.5V 5mA ≤ IOUT ≤ 20mA2.5 1.8 2.1 1.4 0.01 237 250 450 0.5 0.5 85 VIN = 3.6V High Low VDC = 3.6V VIN = 2.8V to 5.5V VDC = Low VIN = 2.8V to 5.5V VDC = Low VIN = 2.8V to 5.5V VDC = Low VIN = 2.8V to 5.5V VIN = 2.8V to 5.5V VIN = 2.8V to 5.5V VIN = 2.8V to 5.5V VDC = High VIN = 2.8V to 5.5V 1260 100 420 140 1 1 140 35 1 1.2 500 1.1 90 7506.5 2.4 5 1 263V V mA µA mV nA % % %DMAX ISW VDCMaximum Duty Cycle Switch Current Limit DC pin thresholds DC Pin Hysteresis1200 0.4mA V mV20 5 10IDC tshutdown tMODE_UP tMODE_DOWNDC Pin Current Shutdown Pulse Width Count UP mode pulse width Count Down mode pulse width Turn-on Delay Time Programming pulse width low Programming pulse width high Minimum Delay for mode change First Pulse Window for Preprogramming Oscillator FrequencyµA µs µs µs µs160 500tstart_up tprog_low tprog_high tdelay Tprog_setup fSW32 32µs µs µs50 1.35µs MHzMarch 20074M9999-030407 (408) 944-0800元器件交易网Micrel, Inc.Symbol Parameter Condition Min Typ MaxMIC3289UnitsVD IRD VOVPSchottky Forward Drop Schottky Leakage Current Over Voltage Protection Over-Temperature Threshold ShutdownID = 150mA VR = 30V 3289- 16 only (nominal voltage) 3289- 24 only (nominal voltage) 13 210.8 14 22.5 1501 4 16 24V µA V V °CTjNotes: 1.Absolute maximum ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply when operating the device outside of its operating ratings. The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(Max), the junction-to-ambient thermal resistance, θ JA, and the ambient temperature, TA. The maximum allowable power dissipation will result in excessive die temperature, and the regulator will go into thermal shutdown. This device is not guaranteed to operate beyond its specified operating rating. IC devices are inherently ESD sensitive. Handling precautions required. Specification for packaged product only.2. 3. 4.March 20075M9999-030407 (408) 944-0800元器件交易网Micrel, Inc.MIC3289Typical CharacteristicsMarch 20076M9999-030407 (408) 944-0800元器件交易网Micrel, Inc.MIC3289Functional CharacteristicsMarch 20077M9999-030407 (408) 944-0800元器件交易网Micrel, Inc.MIC3289Functional DiagramVIN FB OUTOVP SW gm PWM GeneratorDCDigital I/F1.2MHz OscillatorRamp GeneratorGNDMIC3289 Block DiagramFunctional DescriptionThe MIC3289 is a constant frequency, PWM current mode boost regulator. The MIC3289 is composed of an oscillator, slope compensation ramp generator, current amplifier, gm error amplifier, PWM generator, bipolar output transistor, digital interface with D/A converter and Schottky rectifier diode. It features true one-wire digital control that may be used to vary the brightness of the output LEDs and place the device into shutdown mode. The oscillator generates a 1.2MHz clock which triggers the PWM generator that turns on the output transistor and resets the slope compensation ramp generator. The current amplifier is used to measure the switch current by amplifying the voltage signal from the internal sense resistor. The output of the current amplifier is summed with the output of the slope compensation ramp generator. This summed current-loop signal is fed to one of the inputs of the PWM generator. MIC3289 Block Diagram The gm error amplifier measures the LED current through the external sense resistor and amplifies the error between the detected signal and the reference voltage indicated by the digital interface. The output of the gm error amplifier provides the voltage-loop signal that is fed to the other input of the PWM generator.When the current-loop signal exceeds the voltage-loop signal, the PWM generator turns off the bipolar output transistor. The next clock period initiates the next switching cycle, maintaining the constant frequency current-mode PWM control. The LED current level at maximum brightness is set by the feedback resistor:ILED =250mV RLEDMIC3289 Digital InterfaceThe MIC3289 incorporates an easy to use single-wire, serial programming interface allowing users to set LED brightness to one of 16 levels spaced in a logarithmic manner. In contrast to other solutions requiring a PWM drive signal to maintain LED brightness, the MIC3289 is “set and forget”, relieving the controlling processor of the constant burden of supplying a drive signal. Additionally, brightness levels can be preset so that LEDs can be turned on at a particular brightness level.State Diagram The MIC3289 logic state flow is depicted in Figure 1 below. State changes are asynchronous and are edge triggered, with the exception of Start Up and Shutdown, which are level triggered.March 20078M9999-030407 (408) 944-0800元器件交易网Micrel, Inc.MIC3289Figure 1. MIC3289 Logic State DiagramWith an input supply voltage between 2.5V and 6.5V and a logic-level LOW applied to the DC pin, the MIC3289 will enter State 0, Shutdown, and remain there consuming less than 1µA until a logic level high is applied to the DC pin.Start Up Applying a logic-level HIGH to the DC pin initiates the start-up sequence. After the tSTART_UP period the MIC3289 will transition to State 1, the boost drive will turn on and begin regulating LED drive current at maximum brightness level 15, and DC pin programming pulses will cause the brightness level to decrease.shutdown mode.Figure 3. Shutdown TimingOnce the device is shutdown, the boost supply is disabled, and the LEDs are turned off. Brightness level information stored in the MIC3289 prior to shutdown will be lost.Programming Pulse Counter Modes Referring once again to the state diagram in Figure 1, notice that there are two programming pulse counting modes. At power up the MIC3289 defaults to State 1, the count-down mode. The counting mode can be changed to State 2, the count-up mode, by pulling the DC pin low for a period equal to tMODE_UP. Subsequent programming pulses will then increase the LED brightness one level for each pair of programming pulses. Figure 4 shows the timing for the mode change.Figure 2. Start-Up TimingShutdown Whenever a logic-level LOW is applied to the DC input pin for a period greater than or equal to tSHUTDOWN, the MIC3289 will return to State 0 entering its power savingMarch 20079M9999-030407 (408) 944-0800元器件交易网Micrel, Inc.MIC3289 as tPROG_LOW and tPROG_HIGH are not exceeded. To maintain operation at the current brightness level simply maintain a logic level high signal at the DC pin.Figure 4. Mode Change to Count UpTo return the programming pulse counter to the CountDown Mode, apply a negative going pulse to the DC pin with a period equal to tMODE_DOWN. Now each pair of programming pulses will cause the LED brightness to decrease one level.Figure 7. Decreasing Brightness Several LevelstMODE_DOWN DCMODECOUNT DOWNFigure 5. Mode Change to Count DownAs mentioned, the MIC3289 can be programmed to set LED drive current to produce one of 16 distinct brightness levels. The MIC3289s internal logic keeps track of the brightness level with an Up/Down counter circuit. The following section explains how the MIC3289s brightness counter functions with continued programming pulses.Counter Roll-Over The MIC3289 internal up/down counter counts from 0 to 15. When counting DOWN, and brightness level 0 is reached, the counter will roll-over to level 15. This is illustrated in Figure 8 below.Programming the Brightness Level When it is powered up and the DC pin is at a logic level high for greater than tSTART_UP, the MIC3289 will begin regulating LED drive current at the maximum brightness level (Level 15). The internal control logic is set to decrease the LED brightness upon receiving programming pulses (falling edges of the DC input pin). Applying a pair of clock signals as shown in Figure 6 below, decreases the brightness one level. Notice that the first clock pulse is ignored. This is done so that Mode Change pulses do not produce brightness changes. The user may also elect to send a Mode Change as shown in Figure 4 to set the MIC3289 to increment the brightness level with subsequent programming pulses.tPROG_LOWtPROG_HIGHFigure 8. Down Counter Roll-overDCLEVEL n + 1 LEVEL n LEVEL n - 1When the counter Mode is set to count Up and brightness level 15 is reached, the counter will roll-over to level 0. Figure 9 shows that continuing to send programming pulses will cause the brightness level to start over at level zero.BRIGHTNESS LEVELPULSE IGNOREDFigure 6. Brightness Programming PulsesBrightness programming pulses are not restricted to just one pair at a time. Multiple level changes can be set as shown in Figure 7 below. Just remember that the first falling edge of the DC input clock will be ignored so long March 2007 10M9999-030407 (408) 944-0800元器件交易网Micrel, Inc.MIC3289Figure 11. One-Step Brightness Increase Figure 9. Up Counter Roll-overOne-Step Brightness Changes For applications where a keypad button press is to be translated into a brightness level change, the following method of decreasing the brightness level may be useful. This “One-Step” brightness change procedure relieves the user from keeping track of the MIC3289’s up/down counter state. It combines a counter mode change with a programming pulse, therefore a one-step decrease in brightness is assured no matter what the previous up/down counter mode was.Presetting Brightness The brightness level can be preset by sending a series of programming pulses via the DC pin within the tPROG_SETUP period. This pre-programming window starts at 35µs after the DC pin is driven high and ends 15µs later. Although the MIC3289s does not drive current into the load until DC pin is kept high for tstart_up, preprogramming must begin somewhere with the 15µs window or the MIC3289 may continue to start at the full (default) brightness level.Figure 10. One-Step Brightness DecreaseFigure 12. Pre-programming TimingThis method is quite simple and the only requirement is that the first DC down clock period be equal to the tMODE_DOWN period. Similarly a one-step increase can be assured by generating a first DC down pulse whose period is equal to the tMODE_UP period followed by one DC falling edge.Figure 12 shows the correct pre-programming sequence to set the MIC3289 brightness to level 6 prior to start up. The sequence is initiated by driving the DC pin low for a period exceeding tSHUTDOWN, to insure that the part has enter the power saving shutdown state, then the DC pin is driven high and a number of programming pulses are sent. Notice that when using the pre-programming feature the first programming pulse is not ignored. This is because the counter’s default mode is count down. The MIC3289 does not drive current into the load until the DC pin has remained high for time period tstart_up from the last programming activity. Note that the same limits on programming timing in normal operation also apply in pre-programming.March 200711M9999-030407 (408) 944-0800元器件交易网Micrel, Inc.MIC3289Package Information6-Pin TSOT23 (D)March 200712M9999-030407 (408) 944-0800元器件交易网Micrel, Inc.MIC32898-Pin MLF™ (ML)MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USATEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2007 Micrel, Incorporated.March 200713M9999-030407 (408) 944-0800。

MEMORY存储芯片MT48LC16M16A2B4-6A中文规格书

Figure 183: WRITE (BC4) OTF to WRITE (BL8) with 1t CK Preamble in Different Bank GroupCommand DQ CK_t CK_cDQS_t,DQS_cBank GroupAddress Address Notes: 1.BL = 8/BC = 4, AL = 0, CL = 9, Preamble = 1t CK.2.DI n (or b ) = data-in from column n (or column b ).3.DES commands are shown for ease of illustration; other commands may be valid atthese times.4.BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0.BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during WRITE command at T4.5.CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Disable.6.The write recovery time (t WR) and write timing parameter (t WTR) are referenced fromthe first rising clock edge after the last write data shown at T17.WRITE Operation Followed by READ OperationFigure 184: WRITE (BL8) to READ (BL8) with 1t CK Preamble in Different Bank GroupCommand DQ CK_t CK_cDQS_t,DQS_cBank GroupAddress Address Notes: 1.BL = 8, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1t CK, WRITE preamble =1t CK.2.DI b = data-in from column b .3.DES commands are shown for ease of illustration; other commands may be valid atthese times.4.BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 duringWRITE command at T0 and READ command at T15.5.CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,Write CRC = Disable.6.The write timing parameter (t WTR_S) is referenced from the first rising clock edge afterthe last write data shown at T13.Figure 185: WRITE (BL8) to READ (BL8) with 1t CK Preamble in Same Bank GroupCommand DQ CK_t CK_c DQS_t,DQS_cBank GroupAddress Address Notes: 1.BL = 8, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1t CK, WRITE preamble =1t CK.2.DI b = data-in from column b .3.DES commands are shown for ease of illustration; other commands may be valid atthese times.4.BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 duringWRITE command at T0 and READ command at T17.5.CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,Write CRC = Disable.6.The write timing parameter (t WTR_L) is referenced from the first rising clock edge afterthe last write data shown at T13.Figure 186: WRITE (BC4) OTF to READ (BC4) OTF with 1t CK Preamble in Different Bank GroupCommand DQ CK_t CK_cDQS_t,DQS_cBank GroupAddress Address Notes: 1.BC = 4, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1t CK, WRITE preamble =1t CK.2.DI b = data-in from column b .3.DES commands are shown for ease of illustration; other commands may be valid atthese times.4.BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0 andREAD command at T15.5.CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,Write CRC = Disable.6.The write timing parameter (t WTR_S) is referenced from the first rising clock edge afterthe last write data shown at T13.Figure 187: WRITE (BC4) OTF to READ (BC4) OTF with 1tCK Preamble in Same Bank GroupCommand DQ CK_t CK_cDQS_t,DQS_cBank GroupAddress Address Notes: 1.BC = 4, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1t CK, WRITE preamble =1t CK.2.DI b = data-in from column b .3.DES commands are shown for ease of illustration; other commands may be valid atthese times.4.BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0 andREAD command at T17.8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation。

MIC2207资料

MIC22073mmx3mm 2MHz 3A PWM BuckRegulatorGeneral DescriptionThe Micrel MIC2207 is a high efficiency PWM buck(step-down) regulators that provides up to 3A ofoutput current. The MIC2207 operates at 2MHz andhas proprietary internal compensation that allows aclosed loop bandwidth of over 200KHz.The low on-resistance internal p-channel MOSFETof the MIC2207 allows efficiencies over 94%,reduces external components count and eliminatesthe need for an expensive current sense resistor.The MIC2207 operates from 2.7V to 5.5V input andthe output can be adjusted down to 1V. The devicescan operate with a maximum duty cycle of 100% foruse in low-dropout conditions.The MIC2207 is available in the exposed pad 3mm x3mm MLF-12L package with a junction operatingrange from –40°C to +125°C.Features• 2.7 to 5.5V supply voltage• 2MHz PWM mode•Output current to 3A• >94% efficiency•100% maximum duty cycle•Adjustable output voltage option down to 1V•Ultra-fast transient response• Ultra-small external componentsStable with a 1µH inductor and a 4.7µFoutput capacitor•Fully integrated 3A MOSFET switch• Micropower shutdown•Thermal shutdown and current limitprotection•Pb-free 3mm x 3mm MLF-12L package• –40°C to +125°C junction temperature rangeApplications•5V or 3.3V Point of Load Conversion•Telecom/Networking Equipment•Set Top Boxes• Storage Equipment• Video Cards____________________________________________________________________________________________________ Typical ApplicationMIC22073A 2MHz Buck RegulatorOrdering InformationPart Number Output Voltage (1)Junction Temp. Range Package Lead Finish MIC2207YMLAdj.–40° to +125°C3x3 MLF-12LPb-freeNote:1. Other Voltage options available. Contact Micrel for details.Pin ConfigurationBIAS EN SW VIN PGND SGND SW VIN PGND PGOOD FB NC3mm x 3mm MLF-12 (ML)Pin DescriptionPin NumberPin Name Pin Function1,12SWSwitch (Output): Internal power P-Channel MOSFET output switch2,11 VINSupply Voltage (Input): Supply voltage for the source of the internal P-channel MOSFET and driver.Requires bypass capacitor to GND.3,10PGNDPower Ground. Provides the ground return path for the high-side drive current.4 SGND Signal (Analog) Ground. Provides return path for control circuitry and internal reference. 5BIASInternal circuit bias supply. Must be bypassed with a 0.1uF ceramic capacitor to SGND.6 FBFeedback. Input to the error amplifier, connect to the external resistor divider network to set the output voltage.7 NC No Connect. Not internally connected to die. This pin can be tied to any other pinif desired. 8 ENEnable (Input). Logic level low will shutdown the device, reducing the current draw to less than 5uA. 9 PGOODPower Good. Open drain output that is pulled to ground when the output voltage is outside +/- 7.5% of the set regulation voltage EPGNDConnect to ground.Absolute Maximum Ratings(1)Supply Voltage (V IN) (6)Output Switch Voltage (V SW) (6)Output Switch Current (I SW).................................11A Logic Input Voltage (V EN).........................-0.3V to V IN Storage Temperature (T s)................-60°C to +150°C ESD Rating(3)........................................................2kV Operating Ratings(2)Supply Voltage (V IN)............................+2.7V to +5.5V Logic Input Voltage (V EN).............................0V to V IN Junction Temperature (T J)..............–40°C to +125°C Junction Thermal Resistance3x3 MLF-12L (θJA)...................................60°C/WElectrical Characteristics (4)V IN = V EN = 3.6V; L = 1µH; C OUT = 4.7µF; T A = 25°C, unless noted. Bold values indicate –40°C< T J < +125°CParameter Condition MinTypMaxUnits Supply Voltage Range 2.7 5.5 VUnder-Voltage LockoutThreshold(turn-on) 2.45 2.55 2.65 VUVLO Hysteresis 100 mVQuiescent Current V FB = 0.9 * V NOM (not switching) 570 900 µAShutdown Current V EN = 0V 2 10 µA[Adjustable] Feedback Voltage ± 1% I LOAD = 100mA± 2% (over temperature) I LOAD = 100mA0.990.981 1.011.02 VFB pin input current 1 nA Current Limit in PWM Mode V FB = 0.9 * V NOM 3.5 5 7 AOutput Voltage Line Regulation V OUT > 2V; V IN = V OUT+500mV to 5.5V; I LOAD= 100mAV OUT < 2V; V IN = 2.7V to 5.5V; I LOAD= 100mA0.07 %Output Voltage LoadRegulation20mA < I LOAD < 3A 0.2 0.5 % Maximum Duty Cycle V FB≤ 0.4V 100 %PWM Switch ON-Resistance I SW = 50mA V FB = 0.7V FB_NOM (High Side Switch) 95 200300mΩOscillator Frequency 1.8 2 2.2 MHz Enable Threshold 0.5 0.85 1.3 V Enable Hysteresis 50 mV Enable Input Current 0.1 2 µA Power Good Range ±7 ±10 % Power Good Resistance I PGOOD = 500µA 145 200 ΩOver-Temperature Shutdown 160°COver-TemperatureHysteresis20 °CNotes:1. Exceeding the absolute maximum rating may damage the device.2. The device is not guaranteed to function outside its operating rating.3. Devices are ESD sensitive. Handling precautions recommended. Human body model: 1.5kΩ in series with 100pF.4. Specification for packaged product only.5. Dropout voltage is defined as the input-to-output differential at which the output voltage drops 2% below its nominal value that is initiallymeasured at a 1V differential. For outputs below 2.7V, the dropout voltage is the input-to-output voltage differential with a minimum input voltage of 2.7V.Typical CharacteristicsTypical Characteristics cont.Typical Characteristics cont.Functional DiagramMIC2207 Block DiagramFunctional CharacteristicsContinuious Current TIME (200ns/di v.)S W I T C H V O L T A G E (2V /d i v .)I N D U C T O R C U R R E N T00m A /d i v .)Discontinuous CurrentTIME (200ns/di v.)S W I T C H V O L T A G E(2V /d i v .)I N D U C T O R C U R R E N T(200m A /d i v .)V IN = 3.3VV OUT = 1V L = 1µHC OUT = 4.7µF I OUT = 30mA0ALoad Transient Respons eTIME (400µs/di v.)O U T P U T V O L T A G E (20m V /d i v .)O U T P U T C U R R E N T(2A /d i v .)V IN = 3.3V V OUT = 1.8V0AOutput RippleTIME (400ns/di v.)S W I T C H V O L T A G E(2V /d i v .)O U T P U T V O L T AG E (10m V /d i v .)A C C O U P L E DI OUT = 3.0AStart-Up Waveform sTIME (40µs/di v.)E N A B L E V O L T A G E(2i v .)N D U C T O R C U R R E N T (2A /i v .)I N P U T C U R R E N T (1i v .)F E E D B A C K V O L T A G E (1V /d i v .)Pin DescriptionsVINTwo pins for VIN provide power to the source of the internal P-channel MOSFET along with the current limiting sensing. The VIN operating voltage range is from 2.7V to 5.5V. Due to the high switching speeds, a 10µF capacitor is recommended close to VIN and the power ground (PGND) for each pin for bypassing. Please refer to layout recommendations. BIASThe bias (BIAS) provides power to the internal reference and control sections of the MIC2207. A 10 Ohm resistor from VIN to BIAS and a 0.1uF from BIAS to SGND is required for clean operation. ENThe enable pin provides a logic level control of the output. In the off state, supply current of the device is greatly reduced (typically <1µA). Do not drive the enable pin above the supply voltage.FBThe feedback pin (FB) provides the control path to control the output. For adjustable versions, a resistor divider connecting the feedback to the output is used to adjust the desired output voltage. The output voltage is calculated as follows:⎟⎠⎞⎜⎝⎛+×=1R2R1V V REF OUT where V REF is equal to 1.0V.A feedforward capacitor is recommended for most designs using the adjustable output voltage option. To reduce current draw, a 10K feedback resistor is recommended from the output to the FB pin (R1). Also, a feedforward capacitor should be connected between the output and feedback (across R1). The large resistor value and the parasitic capacitance of the FB pin can cause a high frequency pole that can reduce the overall system phase margin. By placing a feedforward capacitor, these effects can be significantly reduced. Feedforward capacitance (C FF ) can be calculated as follows:200kHzR121C FF ××=πSWThe switch (SW) pin connects directly to the inductor and provides the switching current nessasary to operate in PWM mode. Due to the high speed switching on this pin, the switch node should be routed away from sensitive nodes. This pin also connects to the cathode of the free-wheeling diode. PGOODPower good is an open drain pull down that indicates when the output voltage has reached regulation. For a power good low, the output voltage is within +/- 10% of the set regulation voltage. For output voltages greater or less than 10%, the PGOOD pin is high. This should be connected to the input supply through a pull up resistor. A delay can be added by placing a capacitor from PGOOD to ground.PGNDPower ground (PGND) is the ground path for the MOSFET drive current. The current loop for the power ground should be as small as possible and separate from the Signal ground (SGND) loop. Refer to the layout considerations fro more details.SGNDSignal ground (SGND) is the ground path for the biasing and control circuitry. The current loop for the signal ground should be separate from the power ground (PGND) loop. Refer to the layout considerations for more detailsApplications InformationThe MIC2207 is a 3A PWM non-synchronous buck regulator. By switching an input voltage supply, and filtering the switched voltage through an Inductor and capacitor, a regulated DC voltage is obtained. Figure 1 shows a simplified example of anon-synchronous buck converter.Figure 1.For a non-synchronous buck converter, there are two modes of operation; continuous and discontinuous. Continuous or discontinuous refer to the inductor current. If current is continuously flowing through the inductor throughout the switching cycle, it is in continuous operation. If the inductor current drops to zero during the off time, it is in discontinuous operation. Critically continuous is the point where any decrease in output current will cause it to enter discontinuous operation. The critically continuous load current can be calculated as follows;L22MHz V V V IN 2OUT OUT OUT ××⎥⎥⎦⎤⎢⎢⎣⎡−=IContinuous or discontinuous operation determines how we calculate peak inductor current.Continuous OperationFigure 2 illustrates the switch voltage and inductor current during continuous operation.Figure 2. Continuous OperationThe output voltage is regulated by pulse width modulating (PWM) the switch voltage to the average required output voltage. The switching can be broken up into two cycles; On and Off.During the on-time, the high side switch is turned on, current flows from the input supply through theinductor and to the output. The inductor current isFigure 3. On-Timecharged at the rate;()LV V OUT IN −To determine the total on-time, or time at which the inductor charges, the duty cycle needs to be calculated. The duty cycle can be calculated as;INOUTV V D =and the On time is;2MHzDT ON =Therefore, peak to peak ripple current is;()L2MHz V V V V I INOUTOUT IN pk pk ××−=−Since the average peak to peak current is equal to the load current. The actual peak (or highest current the inductor will see in a steady state condition) is equal to the output current plus ½ the peak to peak current.()L2MHz 2V V V V I I INOUTOUT IN OUT pk ×××−+=Figure 4 demonstrates the off-time. During the off-time, the high-side internal P-channel MOSFET turns off. Since the current in the inductor has to discharge, the current flows through the free-wheeling Schottky diode to the output. In this case, the inductor discharge rate is (where V D is the diode forward voltage); ()LV V D OUT +−The total off time can be calculated as;2MHzD1T OFF −=Figure 4. Off-TimeDiscontinuous OperationDiscontinuous operation is when the inductor current discharges to zero during the off cycle. Figure 5. demonstrates the switch voltage and inductorcurrents during discontinuous operation.Figure 5. Discontinuous OperationWhen the inductor current (I L ) has completely discharged, the voltage on the switch node rings at the frequency determined by the parasitic capacitance and the inductor value. In figure 5, it is drawn as a DC voltage, but to see actual operation (with ringing) refer to the functional characteristics. Discontinuous mode of operation has the advantage over full PWM in that at light loads, the MIC2207 will skip pulses as nessasary, reducing gate drive losses, drastically improving light load efficiency.Efficiency ConsiderationsCalculating the efficiency is as simple as measuring power out and dividing it by the power in;100P PEfficiency IN OUT ×=Where input power (P IN ) is;IN IN IN I V P ×=and output power (P OUT ) is calculated as;OUT OUT OUT I V P ×=The Efficiency of the MIC2207 is determined by several factors.•Rdson (Internal P-channel Resistance) • Diode conduction losses •Inductor Conduction losses• Switching lossesRdson losses are caused by the current flowing through the high side P-channel MOSFET. The amount of power loss can be approximated by;D I R P 2OUT DSON SW ××=Where D is the duty cycle.Since the MIC2207 uses an internal P-channel MOSFET, Rdson losses are inversely proportional to supply voltage. Higher supply voltage yields a higher gate to source voltage, reducing the Rdson, reducing the MOSFET conduction losses. A graph showing typical Rdson vs input supply voltage can be found in the typical characteristics section of this datasheet.Diode conduction losses occur due to the forward voltage drop (V F ) and the output current. Diode power losses can be approximated as follows;()D 1I V P OUT F D −××=For this reason, the Schottky diode is the rectifier of choice. Using the lowest forward voltage drop will help reduce diode conduction losses, and improve efficiency.Duty cycle, or the ratio of output voltage to input voltage, determines whether the dominant factor in conduction losses will be the internal MOSFET or the Schottky diode. Higher duty cycles place the power losses on the high side switch, and lower duty cycles place the power losses on the schottky diode. Inductor conduction losses (P L ) can be calculated by multiplying the DC resistance (DCR) times the square of the output current;2OUT L I DCR P ×=Also, be aware that there are additional core losses associated with switching current in an inductor. Since most inductor manufacturers do not give data on the type of material used, approximating core losses becomes very difficult, so verify inductor temperature rise.Switching losses occur twice each cycle , when the switch turns on and when the switch turns off. This is caused by a non-ideal world where switching transitions are not instantaneous, and neither are currents. Figure 6 demonstrates (Or exaggerates…) how switching losses due to the transitions dissipatepower in the switch.Figure 6. Switching Transition LossesNormally, when the switch is on, the voltage across the switch is low (virtually zero) and the current through the switch is high. This equates to low power dissipation. When the switch is off, voltage across the switch is high and the current is zero, again with power dissipation being low. During the transitions, the voltage across the switch (V S-D ) and the current through the switch (I S-D ) are at middle, causing the transition to be the highest instantaneous power point. During continuous mode, these losses are the highest. Also, with higher load currents, these losses are higher. For discontinuous operation, the transition losses only occur during the “off” transition since the “on” transitions there is no current flow through the inductor.Component SelectionInput CapacitorA 10µF ceramic is recommended on each VIN pin for bypassing. X5R or X7R dielectrics are recommended for the input capacitor. Y5V dielectrics lose most of their capacitance over temperature and are therefore not recommended. Also, tantalum and electrolytic capacitors alone are not recommended due their reduced RMS current handling, reliability, and ESR increases.An additional 0.1µF is recommended close to the VIN and PGND pins for high frequency filtering. Smaller case size capacitors are recommended due to their lower ESR and ESL. Please refer to layout recommendations for proper layout of the input capacitor.Output CapacitorThe MIC2207 is designed for a 4.7µF output capacitor. X5R or X7R dielectrics are recommended for the output capacitor. Y5V dielectrics lose most of their capacitance over temperature and are therefore not recommended.In addition to a 4.7µF, a small 0.1uF is recommended close to the load for high frequency filtering. Smaller case size capacitors arerecommended due to there lower equivalent series ESR and ESL.The MIC2207 utilizes type III voltage mode internal compensation and utilizes an internal zero to compensate for the double pole roll off of the LC filter. For this reason, larger output capacitors can create instabilities. In cases where a 4.7uF output capacitor is not sufficient, the MIC2208 offers the ability to externally control the compensation, allowing for a wide range of output capacitor types and values.Inductor SelectionThe MIC2207 is designed for use with a 1µH inductor. Proper selection should ensure the inductor can handle the maximum average and peak currents required by the load. Maximum current ratings of the inductor are generally given in two methods; permissible DC current and saturation current. Permissible DC current can be rated either for a 40°C temperature rise or a 10% to 20% loss in inductance. Ensure the inductor selected can handle the maximum operating current. When saturation current is specified, make sure that there is enough margin that the peak current will not saturate the inductor.Diode SelectionSince the MIC2207 is non-synchronous, a free-wheeling diode is required for proper operation. A schottky diode is recommended due to the low forward voltage drop and their fast reverse recovery time. The diode should be rated to be able to handle the average output current. Also, the reverse voltage rating of the diode should exceed the maximum input voltage. The lower the forward voltage drop of the diode the better the efficiency. Please refer to the layout recommendations to minimize switching noise.Feedback ResistorsThe feedback resistor set the output voltage by dividing down the output and sending it to the feedback pin. The feedback voltage is 1.0V. Calculating the set output voltage is as follows;⎟⎠⎞⎜⎝⎛+=1R2R1V V FB OUT Where R1 is the resistor from VOUT to FB and R2 isthe resistor from FB to GND. The recommended feedback resistor values for common output voltages is available in the bill of materials on page 19. Although the range of resistance for the FB resistors is very wide, R1 is recommended to be 10K. This minimizes the effect the parasitic capacitance of the FB node.Feedforward Capacitor (C FF )A capacitor across the resistor from the output to the feedback pin (R1) is recommended for most designs. This capacitor can give a boost to phase margin and increase the bandwidth for transient response. Also, large values of feedforward capacitance can slow down the turn-on characteristics, reducing inrush current. For maximum phase boost, C FF can be calculated as follows;R1200kHz 21C FF ××=πBias filterA small 10 Ohm resistor is recommended from the input supply to the bias pin along with a small 0.1uF ceramic capacitor from bias to ground. This will bypass the high frequency noise generated by the violent switching of high currents from reaching the internal reference and control circuitry. Tantalum and electrolytic capacitors are not recommended for the bias, these types of capacitors lose their ability to filter at high frequencies.Loop Stability and Bode AnalysisBode analysis is an excellent way to measure small signal stability and loop response in power supply designs. Bode analysis monitors gain and phase of a control loop. This is done by breaking the feedback loop and injecting a signal into the feedback node and comparing the injected signal to the output signal of the control loop. This will require a network analyzer to sweep the frequency and compare the injected signal to the output signal. The most common method of injection is the use of transformer. Figure 7 demonstrates how a transformer is used to inject a signal into thefeedback network.Figure 7. Transformer InjectionA 50 ohm resistor allows impedance matching from the network analyzer source. This method allows the DC loop to maintain regulation and allow thenetwork analyzer to insert an AC signal on top of the DC voltage. The network analyzer will then sweep the source while monitoring A and R for an A/R measurement. While this is the most common method for measuring the gain and phase of a power supply, it does have significant limitations. First, to measure low frequency gain and phase, the transformer needs to be high in inductance. This makes frequencies <100Hz require an extremely large and expensive transformer. Conversely, it must be able to inject high frequencies. Transformers with these wide frequency ranges generally need to be custom made and are extremely expensive (usually in the tune of several hundred dollars!). By using an op-amp, cost and frequency limitations used by an injection transformer are completely eliminated. Figure 8 demonstrates using an op-amp in a summing amplifier configuration for signal injection.Network Analyzer Source+8VR11kR31kR41k 50FeedbackOutputNetwork Analyzer “A” Input Network Analyzer “R” Input MIC922BC5Figure 8. Op Amp InjectionR1 and R2 reduce the DC voltage from the output tothe non-inverting input by half. The network analyzer is generally a 50 Ohm source. R1 and R2 also divide the AC signal sourced by the network analyzer by half. These two signals are “summed” together at half of their original input. The output is then gained up by 2 by R3 and R4 (the 50 Ohm is to balance the network analyzer’s source impedance) and sent to the feedback signal. This essentially breaks the loop and injects the AC signal on top of the DC output voltage and sends it to the feedback. By monitoring the feedback “R” and output “A”, gain and phase are measured. This method has no minimum frequency. Ensure that the bandwidth of the op-amp being used is much greater than the expected bandwidth of the power supplies control loop. An op-amp with >100MHz bandwidth is more than sufficient for most power supplies (which includes both linear and switching) and are more common and significantly cheaper than the injection transformers previously mentioned. The one disadvantage to using the op-amp injection method, is the supply voltages need to below the maximum operating voltage of the op-amp. Also, the maximum output voltage for driving 50 Ohm inputs using the MIC922 is 3V. For measuring higher output voltages, a 1MOhm input impedance is required for the A and R channels. Remember to always measure the output voltage with an oscilloscope to ensure the measurement is working properly. You should see a single sweeping sinusoidal waveform without distortion on the output. If there is distortion of the sinusoid, reduce the amplitude of the source signal. You could be overdriving the feedback causing a large signal response.The following Bode analysis show the small signal loop stability of the MIC2207. The MIC2207 utilizes a type III compensation. This is a dominant low frequency pole, followed by 2 zero’s and finally the double pole of the inductor capacitor filter, creating a final 20dB/decade roll off. Bode analysis gives us a few important data points; speed of response (Gain Bandwidth or GBW) and loop stability. Loop speed or GBW determines the response time to a load transient. Faster response times yield smaller voltage deviations to load steps.Instability in a control loop occurs when there is gain and positive feedback. Phase margin is the measure of how stable the given system is. It is measured by determining how far the phase is from crossing zerowhen the gain is equal to 1 (0dB).Typically for 3.3Vin and 1.8Vout at 3A;• Phase Margin=47 Degrees •GBW=156KHzGain will also increase with input voltage. The following graph shows the increase in GBW for an increase in supply voltage.5Vin, 1.8Vout at 3A load;• Phase Margin=43.1 Degrees •GBW= 218KHzBeing that the MIC2207 is non-synchronous; the regulator only has the ability to source current. This means that the regulator has to rely on the load to be able to sink current. This causes a non-linear response at light loads. The following plot shows the effects of the pole created by the nonlinearity of the output drive during light load (discontinuous) conditions.3.3Vin, 1.8Vout Iout=50mA;• Phase Margin=90.5 Degrees •GBW= 64.4KHzFeed Forward CapacitorThe feedback resistors are a gain reduction block in the overall system response of the regulator. By placing a capacitor from the output to the feedback pin, high frequency signal can bypass the resistordivider, causing a gain increase up to unity gain.The graph above shows the effects on the gain and phase of the system caused by feedback resistors and a feedforward capacitor. The maximum amount of phase boost achievable with a feedforward capacitor is graphed below.By looking at the graph, phase margin can be affected to a greater degree with higher output voltages.The next bode plot shows the phase margin of a 1.8V output at 3A without a feedforward capacitor.As you can see the typical phase margin, using the same resistor values as before without a feedforward capacitor results in 33.6 degrees of phase margin. Our prior measurement with a feedforward capacitor yielded a phase margin of 47 degrees. The feedforward capacitor has given us aphase boost of 13.4 degrees (47 degrees- 33.6 Degrees = 13.4 Degrees).Output Impedance and Transient responseOutput impedance, simply stated, is the amount of output voltage deviation vs. the load current deviation. The lower the output impedance, the better.OUTOUTOUT I V Z ∆∆=Output impedance for a buck regulator is the parallel impedance of the output capacitor and the MOSFET and inductor divided by the gain;COUT LDSON TOTAL X GAINX DCR R Z ++=To measure output impedance vs. frequency, the load current must be load current must be swept across the frequencies measured, while the output voltage is monitored. Fig 9 shows a test set-up to measure output impedance from 10Hz to 1MHz using the MIC5190 high speed controller.By setting up a network analyzer to sweep the feedback current, while monitoring the output of the voltage regulator and the voltage across the load resistance, output impedance is easily obtainable. To keep the current from being too high, a DC offset needs to be applied to the network analyzer’s source signal. This can be done with an external supply and 50 Ohm resistor. Make sure that the currents are verified with an oscilloscope first, to ensure the integrity of the signal measurement. It is always a good idea to monitor the A and R measurements with a scope while you are sweeping it. To convert the network analyzer data from dBm to something more useful (such as peak to peak voltage and current in our case);707.0250Ω1mW 10V 10dBm ×××=∆and peak to peak current;LOAD10dBm R 707.0250Ω1mW 10I ××××=∆The following graph shows output impedance vs frequency at 2A load current sweeping the AC current from 10Hz to 10MHz, at 1A peak to peak amplitude.From this graph, you can see the effects of bandwidth and output capacitance. For frequencies <200KHz, the output impedance is dominated by the gain and inductance. For frequencies >200KHz, the output impedance is dominated by the capacitance. A good approximation for transient response can be calculated from determining the frequency of the load step in amps per second;π2A/sec=f。

328169资料

328169 Product DetailsHome | Customer Support | Suppliers | Site Map | Privacy Policy | Browser Support© 2008 Tyco Electronics Corporation All Rights Reserved SearchProducts Documentation Resources My Account Customer Support Home > Products > By Type > Product Feature Selector > Product Details328169Active AMPOWER TerminalsAlways EU RoHS/ELV Compliant (Statement of Compliance)Product Highlights:?Power Generation and DistributionApplication?Wire Size (AWG/CM) = 1/0 AWG [50-60²]?Wire Range = 83700 -119500 CMA?Terminal Type = Standard?Stud Size = 5/16 [M8]View all Features | Find SimilarProductsCheck Pricing &AvailabilitySearch for ToolingProduct FeatureSelectorContact Us AboutThis ProductQuick LinksDocumentation & Additional InformationProduct Drawings:?TERMINAL, AMPOWER, WIRE SIZE: 1/0 AWG(PDF, English)Catalog Pages/Data Sheets:?None AvailableProduct Specifications:?None AvailableApplication Specifications:?None AvailableInstruction Sheets:?None AvailableCAD Files:?None AvailableList all Documents Additional Information:?Product Line InformationRelated Products:?ToolingProduct Features (Please use the Product Drawing for all design activity)Product Type Features:?Terminal Type = Standard?Stud Size = 5/16 [M8]?Stud Diameter (mm [in]) = 7.92 [0.312]?Material = Copper (Annealed) per ASTM B-75?Body Style = Straight?Tongue Material Thickness (mm [in]) = 2.54[0.100]?Finish = Tin?Comment = Electrodeposited Tin Plate per MIL-T-10727.Body Related Features:?Wire Size (AWG/CM) = 1/0 AWG [50-60²]?Wire Range (CMA) = 83,700 –119,500?Stud Hole Diameter (mm [in]) = 8.33 [0.328]?Number of Holes = 2?Barrel I.D. Min. (mm [in]) = 11.63 [0.458]?Barrel Length = Standard?Inspection Slot = With Industry Standards:?RoHS/ELV Compliance = RoHS compliant, ELVcompliant?Lead Free Solder Processes = Not relevant forlead free process?RoHS/ELV Compliance History = Always wasRoHS compliantOperation/Application:?Application = Power Generation andDistributionPackaging Related Features:?Packaging Quantity = 50Other:?Brand = AMPProvide Website Feedback | Contact Customer Support。

MEMORY存储芯片MT48LC16M16A2P-75 IT中文规格书

Burst TypeAccesses within a given burst may be programmed to be either sequential or inter-leaved. The burst type is selected via bit M3, as shown in Figure 36. The ordering of ac-cesses within a burst is determined by the burst length, the burst type, and the startingcolumn address, as shown in Table 41. DDR2 SDRAM supports 4-bit burst mode and 8-bit burst mode only. For 8-bit burst mode, full interleaved address ordering is suppor-ted; however, sequential address ordering is nibble-based.Table 41: Burst DefinitionOperating ModeThe normal operating mode is selected by issuing a command with bit M7 set to “0,”and all other bits set to the desired values, as shown in Figure 36 (page 79). When bit M7is “1,” no other bits of the mode register are programmed. Programming bit M7 to “1”places the DDR2 SDRAM into a test mode that is only used by the manufacturer andshould not be used. No operation or functionality is guaranteed if M7 bit is “1.”DLL RESETDLL RESET is defined by bit M8, as shown in Figure 36. Programming bit M8 to “1” willactivate the DLL RESET function. Bit M8 is self-clearing, meaning it returns back to avalue of “0” after the DLL RESET function has been issued.Anytime the DLL RESET function is used, 200 clock cycles must occur before a READcommand can be issued to allow time for the internal clock to be synchronized with theexternal clock. Failing to wait for synchronization to occur may result in a violation ofthe t AC or t DQSCK parameters.2Gb: x4, x8, x16 DDR2 SDRAM Mode Register (MR)Table 9: I DD7 Timing Patterns (8-Bank Interleave READ Operation)Notes: 1. A = active; RA = read auto precharge; D = deselect.2.All banks are being interleaved at minimum t RC (I DD ) without violating t RRD (I DD ) usinga BL = 4.3.Control and address bus inputs are STABLE during DESELECTs.2Gb: x4, x8, x16 DDR2 SDRAM Electrical Specifications – I DD Parameters。

RT9819A-49PYR资料

Function Block Diagram
VDD
VSET
CMP
Timer
Threshold Voltage Setting
POR
Power On Reset
VDD
P MOS N MOS
RESET/ RESET
2
DS9819-05 August 2007
元器件交易网
Applications
z Computers z Controllers z Intelligent Instruments z Critical μP and μC Power Monitoring z Portable/Battery-Powered Equipment
Marking Information
Ordering Information
RT9819 -
Package Type
U3 : SC-70-3
V : SOT-23-3
VL : SOT-23-3 Fra bibliotekL-Type)
Y : SC-82
YR : SC-82 (R-Type)
Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commer-
DS9819-05 August 2007
Features
z Internally Fixed Threshold 1.2V to 5V in 0.1V Step z High Accuracy ±1.5% z Low Supply Current 3μA z No External Components Required z Quick Reset within 20μs z Built-in Recovery Delay Include 0ms, 55ms, 220ms,

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