10B 25 MS_S PIPELINED SAR ADC WITH DUAL- PHASE ZERO-CROSSING

SYSTEM ARCHITECTURE
The schematic of the designed pipelined SAR ADC is shown in Figure 1. It consists of two SAR-based sub-ADCs, ZCB circuits, digital controller and output D flip-flop (DFF) array. A 5b SAR ADC is used as the first stage sub-ADC and a 6b SAR ADC constructs the second stage. Two sub-ADCs are both asynchronous SAR ADCs using common mode-based switching method, which means 50% capacitors are saved and gains more power efficiency. The ZCB circuits are introduced instead of an OTA-based MDAC, performing the charge transfer. Low power zero-crossing detector (ZCD) with power efficient current sources is designed. The last unit capacitor of the first stage acts as a feedback capacitor. The whole circuits are controlled by a digital controller. The results are output applications low-power register demand high­ by a OFF array. The operation sequence of the ADC is shown in Figure 2.
v;.es.MDAC
=
=
v'deal + v"rr
_l'pGm
CL
(1)
< 1 I 2LSE
sources begin to charge. After the coarse detector detects the 'zero-crossing',
C!Jze turns low and shut down most of
L...--+----lrL--
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CIRCUIT IMPLEMENTATION
ZCD is the key block in this design. Then comparator and digital controller are presented.
ZCB Circuits
In order to illustrate why ZCB circuit is utilized to substitute the conventional OTA-based MDAC, OTA-based MDAC is analyzed firstly. Assuming a
CLK
INTRODUCTION
Portable resolution Successive
(>1Ob)
electronic and
analog-to-digital ADCs are
converters (ADC) with a signal bandwidth of tens of MHz. approximation (SAR) popular for achieving high energy efficiency. However, they suffer from limitations of resolution and speed. Pipeline ADCs can achieve high resolution and high speed but have lower energy-efficiency and are more complex. To combine the two architectures, a two-stage pipeline ADC with a SAR-based sub-ADC was presented in [1]. As the result, SAR-based sub-ADC enables a high stage resolution and eliminates the need for
fJ is the
C!J z
turns low and shut down the last unit of
feedback factor, Gm is the transconductance and CL is the closed-loop SAR-based bandwidth decision
L------'-_L---'--4+--
fJ is quite small (1/32). Thus, Gm should be quite large.
ZCB circuits do not suffer from loop stability issues and gain-bandwidth tradeoffs, which are less affected by technology scaling since they operate as threshold detectors. Eq. (3) shows how the voltage on the load capacitance VresZCBC is determined if ZCB circuits are used.
an
---1
Digital Controller
�>
"'"d-!
DFF Array '--___ ------'
h:::
CLK lOb
active front-end
pt Stage SAR ADC
2nd Stage SAR ADC
SIR, which means lower power consumption. However, the power-hungry OTA-based high resolution MDAC in it is still a challenge. Zero-crossing-based (ZCB) circuits [2] [3] have recently emerged as low-power alternatives to traditional OTA-based MDACs, which replaces the power-hungry OTA with power-efficient and current sources and a continuous time comparator. Due to the absence of loop stability issues gain-bandwidth tradeoffs, ZCB circuits offer potential to achieve very low power ADCs with the scaling of technology. In this paper, high-gain and high-bandwidth op-amps in the pipelined SAR ADC are substituted by ZCB circuits. The corresponding design and analysis of a zero-crossing based lOb 25 MS/s two-stage pipelined SAR ADC is presented. The system architecture is introduced in Section II. The circuit design and the simulation results are presented in Section III and Section IV, respectively. Finally, the conclusion is given.
lOB 25 MS/S PIPELINED SAR ADC WITH DUAL- PHASE ZERO-CROSSING DETECTOR Pengcheng Yan, Yan Song, Peipei Ran, Li Geng *
Department of Microelectronics, Xi'an Jiaotong University, Shaanxi, China, 710049
current sources. The charge transfer finishes and ZCD is shut down to save power. The timing diagram of the ZCD is shown in Figure 5.
dJ
r----------------- -----1
*Email: gengli@
ABSTRACT
A successive approximation register (SAR)-assisted two-stage pipeline ADC is presented, achieving low power consumption, high resolution and high speed. A dual-phase zero-crossing detector is used to replace the power-hungry OTA-based MDAC. Since the SAR architecture and zero-crossing circuit are proved to be voltage scalable, this ADC will be benefited from the technology scaling. Simulation results show that the ADC consumes 1.66mW at 25MS/s with 1.5V supply voltage. And it achieves a FoM of 91.7 fJ!conv.-step at the ENOB of 9.50b. The SNDR and SFDR are 58.94dB and 70.62dB, respectively.