MSP430F2013IPWR

MSP430F20x3MSP430F20x2MSP430F20x1 SLAS491H–AUGUST2005–REVISED AUGUST2011MIXED SIGNAL MICROCONTROLLERFEATURES•Low Supply Voltage Range1.8V to3.6V•Serial Onboard Programming,No ExternalProgramming Voltage Needed,Programmable •Ultra-Low Power ConsumptionCode Protection by Security Fuse –Active Mode:220µA at1MHz,2.2V•On-Chip Emulation Logic With Spy-Bi-Wire –Standby Mode:0.5µAInterface–Off Mode(RAM Retention):0.1µA•Family Members:•Five Power-Saving Modes–MSP430F2001•Ultra-Fast Wake-Up From Standby Mode in–1KB+256B Flash Memory Less Than1µs–128B RAM•16-Bit RISC Architecture,62.5-ns Instruction–MSP430F2011Cycle Time–2KB+256B Flash Memory•Basic Clock Module Configurations:–128B RAM–Internal Frequencies up to16MHz WithFour Calibrated Frequencies to±1%–MSP430F2002–Internal Very Low-Power Low-Frequency–1KB+256B Flash Memory Oscillator–128B RAM–32-kHz Crystal–MSP430F2012–External Digital Clock Source–2KB+256B Flash Memory•16-Bit Timer_A With Two Capture/Compare–128B RAMRegisters–MSP430F2003•On-Chip Comparator for Analog Signal–1KB+256B Flash Memory Compare Function or Slope A/D–128B RAM(MSP430F20x1)–MSP430F2013•10-Bit200-ksps A/D Converter With Internal–2KB+256B Flash Memory Reference,Sample-and-Hold,and Autoscan(MSP430F20x2)–128B RAM•16-Bit Sigma-Delta A/D Converter With•Available in14-Pin Plastic Small-Outline Thin Differential PGA Inputs and Internal Reference Package(TSSOP),14-Pin Plastic Dual Inline (MSP430F20x3)Package(PDIP),and16-Pin QFN•Universal Serial Interface(USI)Supporting SPI•For Complete Module Descriptions,See the and I2C(MSP430F20x2and MSP430F20x3)MSP430x2xx Family User's Guide(SLAU144)•Brownout DetectorDESCRIPTIONThe Texas Instruments MSP430family of ultra-low-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications.The architecture,combined with five low-power modes is optimized to achieve extended battery life in portable measurement applications.The device features a powerful16-bit RISC CPU,16-bit registers,and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator(DCO)allows wake-up from low-power modes to active mode in less than1µs. The MSP430F20xx series is an ultra-low-power mixed signal microcontroller with a built-in16-bit timer and ten I/O pins.In addition,the MSP430F20x1has a versatile analog comparator.The MSP430F20x2and MSP430F20x3have built-in communication capability using synchronous protocols(SPI or I2C)and a10-bit A/D converter(MSP430F20x2)or a16-bit sigma-delta A/D converter(MSP430F20x3).Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.MSP430F20x3MSP430F20x2MSP430F20x1SLAS491H–AUGUST2005–REVISED Typical applications include sensor systems that capture analog signals,convert them to digital values,and then process the data for display or for transmission to a host system.Stand alone RF sensor front end is another area of application.Table1.Available Options(1)PACKAGED DEVICES(2)T APLASTIC14-PIN TSSOP(PW)PLASTIC14-PIN DIP(N)PLASTIC16-PIN QFN(RSA)MSP430F2001IPW MSP430F2001IN MSP430F2001IRSAMSP430F2011IPW MSP430F2011IN MSP430F2011IRSAMSP430F2002IPW MSP430F2002IN MSP430F2002IRSA -40°C to85°CMSP430F2012IPW MSP430F2012IN MSP430F2012IRSAMSP430F2003IPW MSP430F2003IN MSP430F2003IRSAMSP430F2013IPW MSP430F2013IN MSP430F2013IRSAMSP430F2001TPW MSP430F2001TN MSP430F2001TRSAMSP430F2011TPW MSP430F2011TN MSP430F2011TRSAMSP430F2002TPW MSP430F2002TN MSP430F2002TRSA -40°C to105°CMSP430F2012TPW MSP430F2012TN MSP430F2012TRSAMSP430F2003TPW MSP430F2003TN MSP430F2003TRSAMSP430F2013TPW MSP430F2013TN MSP430F2013TRSA(1)For the most current package and ordering information,see the Package Option Addendum at the end of this document,or see the TIweb site at .(2)Package drawings,thermal data,and symbolization are available at /packaging.V A1A1/CA6/TDI/TCLKP1.5/T P1.2/T P1.1/T P1.0/T PW or N PACKAGERSA PACKAGE (TOP VIEW)C CS S CC P1.2/T P1.1/T P1.0/T A1P 1.7/C A O U T /C A 7/TD O /T D P 1.6/T A 1/C A 6/T D I /T C L P 1.4/S M C L K /C A 4/T C P 1.5/T A 0/C A 5/T M MSP430F20x3MSP430F20x2MSP430F20x1SLAS491H –AUGUST 2005–REVISED AUGUST 2011Device Pinout,MSP430F20x1See port schematics section for detailed I/O information.V A1A1/A6/SDO/SCL/TDI/TCLKP1.5/T P1.3/ADC10CLK/A3/VREF−/V P1.0/T P1.4/SMCLK/A4/VREF+/V PW or N PACKAGERSA PACKAGE (TOP VIEW)V C CV S S V C CV S S P1.3/ADC10CLK/A3/VREF−/V P1.0/T A1P 1.7/A 7/S D I /S D A /T D O /T D P 1.6/T A 1/A 6/S D O /S C L /T D I /T C L KP 1.4/S M C L K /A 4/V R E F +/V e R E F +/T C KP 1.5/T A 0/A 5/S C L K /T M MSP430F20x3MSP430F20x2MSP430F20x1SLAS491H –AUGUST 2005–REVISED AUGUST 2011Device Pinout,MSP430F20x2See port schematics section for detailed I/O information.V A1A1/A3+/SDO/SCL/TDI/TCLKPW or N PACKAGERSA PACKAGE (TOP VIEW)V C CV S S C CS S P1.0/T A1P 1.7/A 3−/S D I /S D A /T D O /T D P 1.6/T A 1/A 3+/S D O /S C L /T D I /T C L KP 1.4/S M C L K /A 2+/T C KP 1.5/T A 0/A 2−/S C L K /T M MSP430F20x3MSP430F20x2MSP430F20x1SLAS491H –AUGUST 2005–REVISED AUGUST 2011Device Pinout,MSP430F20x3See port schematics section for detailed I/O information.RST/NMIVCCVSSP1.x &JTAGP2.x &RST/NMIVCCVSSP1.x &JTAGP2.x &MSP430F20x3MSP430F20x2MSP430F20x1SLAS491H –AUGUST 2005–REVISED AUGUST 2011Functional Block Diagram,MSP430F20x1NOTE:See port schematics section for detailed I/O information.Functional Block Diagram,MSP430F20x2NOTE:See port schematics section for detailed I/O information.RST/NMIVCCVSSP1.x &JTAGP2.x &MSP430F20x3MSP430F20x2MSP430F20x1SLAS491H –AUGUST 2005–REVISED AUGUST 2011Functional Block Diagram,MSP430F20x3NOTE:See port schematics section for detailed I/O information.MSP430F20x3MSP430F20x2MSP430F20x1SLAS491H–AUGUST2005–REVISED Table2.Terminal Functions,MSP430F20x1TERMINALNO.DESCRIPTIONNAME I/OPW,N RSAGeneral-purpose digital I/O pinTimer_A,clock signal TACLK inputP1.0/TACLK/ACLK/CA021I/OACLK signal outputComparator_A+,CA0inputGeneral-purpose digital I/O pinP1.1/TA0/CA132I/O Timer_A,capture:CCI0A input,compare:Out0outputComparator_A+,CA1inputGeneral-purpose digital I/O pinP1.2/TA1/CA243I/O Timer_A,capture:CCI1A input,compare:Out1outputComparator_A+,CA2inputGeneral-purpose digital I/O pinP1.3/CAOUT/CA354I/OComparator_A+,output/CA3inputGeneral-purpose digital I/O pinSMCLK signal outputP1.4/SMCLK/C4/TCK65I/OComparator_A+,CA4inputJTAG test clock,input terminal for device programming and testGeneral-purpose digital I/O pinTimer_A,compare:Out0outputP1.5/TA0/CA5/TMS76I/OComparator_A+,CA5inputJTAG test mode select,input terminal for device programming and testGeneral-purpose digital I/O pinTimer_A,compare:Out1outputP1.6/TA1/CA6/TDI/TCLK87I/OComparator_A+,CA6inputJTAG test data input or test clock input during programming and testGeneral-purpose digital I/O pinP1.7/CAOUT/CA7/TDO/TDI(1)98I/O Comparator_A+,output/CA7inputJTAG test data output terminal or test data input during programming and testInput terminal of crystal oscillatorXIN/P2.6/TA11312I/O General-purpose digital I/O pinTimer_A,compare:Out1outputOutput terminal of crystal oscillatorXOUT/P2.71211I/OGeneral-purpose digital I/O pin(2)Reset or nonmaskable interrupt inputRST/NMI/SBWTDIO109ISpy-Bi-Wire test data input/output during programming and testSelects test mode for JTAG pins on Port1.The device protection fuse is TEST/SBWTCK1110I connected to TEST.Spy-Bi-Wire test clock input during programming and testV CC116Supply voltageV SS1414Ground referenceNC NA13,15Not connectedQFN Pad NA Pad NA QFN package pad.Connection to VSS is recommended.(1)TDO or TDI is selected via JTAG instruction.(2)If XOUT/P2.7is used as an input,excess current flows until P2SEL.7is cleared.This is due to the oscillator output driver connection tothis pad after reset.MSP430F20x3MSP430F20x2MSP430F20x1 SLAS491H–AUGUST2005–REVISED AUGUST2011Table3.Terminal Functions,MSP430F20x2TERMINALNO.DESCRIPTIONNAME I/OPW,N RSAGeneral-purpose digital I/O pinTimer_A,clock signal TACLK inputP1.0/TACLK/ACLK/A021I/OACLK signal outputADC10analog input A0General-purpose digital I/O pinP1.1/TA0/A132I/O Timer_A,capture:CCI0A input,compare:Out0outputADC10analog input A1General-purpose digital I/O pinP1.2/TA1/A243I/O Timer_A,capture:CCI1A input,compare:Out1outputADC10analog input A2General-purpose digital I/O pinADC10conversion clock outputP1.3/ADC10CLK/A3/54I/O ADC10analog input A3VREF-/VeREF-Input for negative external reference voltage/negative internal reference voltageoutputGeneral-purpose digital I/O pinSMCLK signal outputP1.4/SMCLK/A4/VREF+/ADC10analog input A465I/OVeREF+/TCK Input for positive external reference voltage/positive internal reference voltageoutputJTAG test clock,input terminal for device programming and testGeneral-purpose digital I/O pinTimer_A,compare:Out0outputP1.5/TA0/A5/SCLK/TMS76I/O ADC10analog input A5USI:external clock input in SPI or I2C mode;clock output in SPI modeJTAG test mode select,input terminal for device programming and testGeneral-purpose digital I/O pinTimer_A,capture:CCI1B input,compare:Out1outputP1.6/TA1/A6/SDO/SCL/87I/O ADC10analog input A6TDI/TCLKUSI:Data output in SPI mode;I2C clock in I2C modeJTAG test data input or test clock input during programming and testGeneral-purpose digital I/O pinP1.7/A7/SDI/SDA/ADC10analog input A798I/OTDO/TDI(1)USI:Data input in SPI mode;I2C data in I2C modeJTAG test data output terminal or test data input during programming and testInput terminal of crystal oscillatorXIN/P2.6/TA11312I/O General-purpose digital I/O pinTimer_A,compare:Out1outputOutput terminal of crystal oscillatorXOUT/P2.71211I/OGeneral-purpose digital I/O pin(2)Reset or nonmaskable interrupt inputRST/NMI/SBWTDIO109ISpy-Bi-Wire test data input/output during programming and testSelects test mode for JTAG pins on Port1.The device protection fuse isTEST/SBWTCK1110I connected to TEST.Spy-Bi-Wire test clock input during programming and testV CC1NA Supply voltageV SS14NA Ground referenceDV CC NA16Digital supply voltageAV CC NA15Analog supply voltageDV SS NA14Digital ground referenceAV SS NA13Analog ground referenceQFN Pad NA Pad NA QFN package pad.Connection to VSS is recommended.(1)TDO or TDI is selected via JTAG instruction.(2)If XOUT/P2.7is used as an input,excess current flows until P2SEL.7is cleared.This is due to the oscillator output driver connection tothis pad after reset.MSP430F20x3MSP430F20x2MSP430F20x1SLAS491H–AUGUST2005–REVISED Table4.Terminal Functions,MSP430F20x3TERMINALNO.DESCRIPTIONNAME I/OPW,N RSAGeneral-purpose digital I/O pinTimer_A,clock signal TACLK inputP1.0/TACLK/ACLK/A0+21I/OACLK signal outputSD16_A positive analog input A0General-purpose digital I/O pinTimer_A,capture:CCI0A input,compare:Out0outputP1.1/TA0/A0-/A4+32I/OSD16_A negative analog input A0SD16_A positive analog input A4General-purpose digital I/O pinTimer_A,capture:CCI1A input,compare:Out1outputP1.2/TA1/A1+/A4-43I/OSD16_A positive analog input A1SD16_A negative analog input A4General-purpose digital I/O pinInput for an external reference voltage/internal reference voltage output(can beP1.3/VREF/A1-54I/Oused as mid-voltage)SD16_A negative analog input A1General-purpose digital I/O pinSMCLK signal outputP1.4/SMCLK/A2+/TCK65I/OSD16_A positive analog input A2JTAG test clock,input terminal for device programming and testGeneral-purpose digital I/O pinTimer_A,compare:Out0outputP1.5/TA0/A2-/SCLK/TMS76I/O SD16_A negative analog input A2USI:external clock input in SPI or I2C mode;clock output in SPI modeJTAG test mode select,input terminal for device programming and testGeneral-purpose digital I/O pinTimer_A,capture:CCI1B input,compare:Out1outputP1.6/TA1/A3+/SDO/SCL/87I/O SD16_A positive analog input A3TDI/TCLKUSI:Data output in SPI mode;I2C clock in I2C modeJTAG test data input or test clock input during programming and testGeneral-purpose digital I/O pinP1.7/A3-/SDI/SDA/SD16_A negative analog input A398I/OTDO/TDI(1)USI:Data input in SPI mode;I2C data in I2C modeJTAG test data output terminal or test data input during programming and testInput terminal of crystal oscillatorXIN/P2.6/TA11312I/O General-purpose digital I/O pinTimer_A,compare:Out1outputOutput terminal of crystal oscillatorXOUT/P2.71211I/OGeneral-purpose digital I/O pin(2)Reset or nonmaskable interrupt inputRST/NMI/SBWTDIO109ISpy-Bi-Wire test data input/output during programming and testSelects test mode for JTAG pins on Port1.The device protection fuse isTEST/SBWTCK1110I connected to TEST.Spy-Bi-Wire test clock input during programming and testV CC1NA Supply voltageV SS14NA Ground referenceDV CC NA16Digital supply voltageAV CC NA15Analog supply voltageDV SS NA14Digital ground referenceAV SS NA13Analog ground referenceQFN Pad NA Pad NA QFN package pad.Connection to VSS is recommended.(1)TDO or TDI is selected via JTAG instruction.(2)If XOUT/P2.7is used as an input,excess current flows until P2SEL.7is cleared.This is due to the oscillator output driver connection tothis pad after reset.General-Purpose Register Program Counter Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register General-Purpose Register PC/R0SP/R1SR/CG1/R2CG2/R3R4R5R12R13General-Purpose Register General-Purpose Register R6R7General-Purpose Register General-Purpose Register R8R9General-Purpose Register General-Purpose Register R10R11General-Purpose Register General-Purpose RegisterR14R15SHORT-FORM DESCRIPTIONCPUThe MSP430CPU has a 16-bit RISC architecture that is highly transparent to the application.All operations,other than program-flow instructions,are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.The CPU is integrated with 16registers that provide reduced instruction execution time.The register-to-register operation execution time is one cycle of the CPU clock.Four of the registers,R0to R3,are dedicated as program counter,stack pointer,status register,and constant generator respectively.The remaining registers are general-purpose registers.Peripherals are connected to the CPU using data,address,and control buses,and can be handled with all instructions.Instruction SetThe instruction set consists of 51instructions with three formats and seven address modes.Each instruction can operate on word and byte data.Table 5shows examples of the three types of instruction formats;Table 6shows the address modes.Table 5.Instruction Word FormatsINSTRUCTION FORMAT EXAMPLE OPERATION Dual operands,source-destination ADD R4,R5R4+R5--->R5Single operands,destination only CALL R8PC -->(TOS),R8-->PC Relative jump,un/conditionalJNEJump-on-equal bit =0Table 6.Address Mode DescriptionsADDRESS MODES (1)D (1)SYNTAX EXAMPLE OPERATION Register ✓✓MOV Rs,Rd MOV R10,R11R10-->R11Indexed✓✓MOV X(Rn),Y(Rm)MOV 2(R5),6(R6)M(2+R5)-->M(6+R6)Symbolic (PC relative)✓✓MOV EDE,TONI M(EDE)-->M(TONI)Absolute ✓✓MOV &MEM,&TCDAT M(MEM)-->M(TCDAT)Indirect✓MOV @Rn,Y(Rm)MOV @R10,Tab(R6)M(R10)-->M(Tab+R6)M(R10)-->R11Indirect autoincrement✓MOV @Rn+,Rm MOV @R10+,R11R10+2-->R10Immediate✓MOV #X,TONIMOV #45,TONI #45-->M(TONI)(1)S =source,D =destinationOperating ModesThe MSP430has one active mode and five software-selectable low-power modes of operation.An interrupt event can wake the device from any of the five low-power modes,service the request,and restore back to the low-power mode on return from the interrupt program.The following six operating modes can be configured by software:•Active mode(AM)–All clocks are active•Low-power mode0(LPM0)–CPU is disabled–ACLK and SMCLK remain active–MCLK is disabled•Low-power mode1(LPM1)–CPU is disabled–ACLK and SMCLK remain active.MCLK is disabled–DCO's dc-generator is disabled if DCO not used in active mode•Low-power mode2(LPM2)–CPU is disabled–MCLK and SMCLK are disabled–DCO's dc-generator remains enabled–ACLK remains active•Low-power mode3(LPM3)–CPU is disabled–MCLK and SMCLK are disabled–DCO's dc-generator is disabled–ACLK remains active•Low-power mode4(LPM4)–CPU is disabled–ACLK is disabled–MCLK and SMCLK are disabled–DCO's dc-generator is disabled–Crystal oscillator is stoppedInterrupt Vector AddressesThe interrupt vectors and the power-up starting address are located in the address range of0FFFFh to0FFC0h. The vector contains the16-bit address of the appropriate interrupt handler instruction sequence.If the reset vector(located at address0FFFEh)contains0FFFFh(for example,flash is not programmed)the CPU goes into LPM4immediately after power-up.Table7.Interrupt SourcesSYSTEMINTERRUPT SOURCE INTERRUPT FLAG WORD ADDRESS PRIORITYINTERRUPTPower-up PORIFGExternal reset RSTIFGWatchdog Timer+WDTIFG Reset0FFFEh31,highestFlash key violation KEYVPC out-of-range(1)See(2)NMI NMIIFG(non)-maskable,Oscillator fault OFIFG(non)-maskable,0FFFCh30Flash memory access violation ACCVIFG(2)(3)(non)-maskable0FFFAh290FFF8h28 Comparator_A+(MSP430F20x1)CAIFG(4)maskable0FFF6h27 Watchdog Timer+WDTIFG maskable0FFF4h26 Timer_A2TACCR0CCIFG(4)maskable0FFF2h25Timer_A2TACCR1CCIFG.TAIFG(2)(4)maskable0FFF0h240FFEEh230FFECh22 ADC10(MSP430F20x2)ADC10IFG(4)maskable0FFEAh21SD16CCTL0SD16OVIFG,SD16_A(MSP430F20x3)maskableSD16CCTL0SD16IFG(2)(4)USIUSIIFG,USISTTIFG(2)(4)maskable0FFE8h20(MSP430F20x2,MSP430F20x3)I/O Port P2(two flags)P2IFG.6to P2IFG.7(2)(4)maskable0FFE6h19I/O Port P1(eight flags)P1IFG.0to P1IFG.7(2)(4)maskable0FFE4h180FFE2h170FFE0h16 See(5)0FFDEh to0FFC0h15to0,lowest (1)A reset is generated if the CPU tries to fetch instructions from within the module register memory address range(0h to01FFh)or fromwithin unused address ranges.(2)Multiple source flags(3)(non)-maskable:the individual interrupt-enable bit can disable an interrupt event,but the general interrupt enable cannot.(4)Interrupt flags are located in the module.(5)The interrupt vectors at addresses0FFDEh to0FFC0h are not used in this device and can be used for regular program code ifnecessary.Special Function RegistersMost interrupt and module enable bits are collected into the lowest address space.Special function register bits not allocated to a functional purpose are not physically present in the device.Simple software access is provided with this arrangement.Legend rw:Bit can be read and written.rw-0,1:Bit can be read and written.It is reset or set by PUC.rw-(0,1):Bit can be read and written.It is reset or set by POR.SFR bit is not present in device.Table8.Interrupt Enable Register1and2Address76543210 00h ACCVIE NMIIE OFIE WDTIErw-0rw-0rw-0rw-0 WDTIE Watchdog Timer interrupt enable.Inactive if watchdog mode is selected.Active if Watchdog Timer is configured in interval timer mode.OFIE Oscillator fault interrupt enableNMIIE(Non)maskable interrupt enableACCVIE Flash access violation interrupt enableAddress76543210 01hTable9.Interrupt Flag Register1and2Address76543210 02h NMIIFG RSTIFG PORIFG OFIFG WDTIFGrw-0rw-(0)rw-(1)rw-1rw-(0) WDTIFG Set on watchdog timer overflow(in watchdog mode)or security key violation.Reset on V CC power-on or a reset condition at the pin in reset mode.OFIFG Flag set on oscillator fault.PORIFG Power-On Reset interrupt flag.Set on V CC power-up.RSTIFG External reset interrupt flag.Set on a reset condition at pin in reset mode.Reset on V CC power-up.NMIIFG Set via pinAddress76543210 03hMemory OrganizationTable10.Memory OrganizationMSP430F200x MSP430F201xMemory Size1KB Flash2KB FlashMain:interrupt vector Flash0FFFFh-0FFC0h0FFFFh-0FFC0hMain:code memory Flash0FFFFh-0FC00h0FFFFh-0F800hSize256Byte256ByteInformation memoryFlash010FFh-01000h010FFh-01000h128Byte128ByteRAM Size027Fh-0200h027Fh-0200h16-bit01FFh-0100h01FFh-0100hPeripherals8-bit0FFh-010h0FFh-010h8-bit SFR0Fh-00h0Fh-00hFlash MemoryThe flash memory can be programmed via the Spy-Bi-Wire/JTAG port,or in-system by the CPU.The CPU can perform single-byte and single-word writes to the flash memory.Features of the flash memory include:•Flash memory has n segments of main memory and four segments of information memory(A to D)of 64bytes each.Each segment in main memory is512bytes in size.•Segments0to n may be erased in one step,or each segment may be individually erased.•Segments A to D can be erased individually,or as a group with segments0to n.Segments A to D are also called information memory.•Segment A contains calibration data.After reset segment A is protected against programming and erasing.It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is required.Peripherals are connected to the CPU through data,address,and control busses and can be handled using all instructions.For complete module descriptions,refer to the MSP430F2xx Family User's Guide.Oscillator and System ClockThe clock system is supported by the basic clock module that includes support for a32768-Hz watch crystal oscillator,an internal very-low-power low-frequency oscillator and an internal digitally-controlled oscillator(DCO). The basic clock module is designed to meet the requirements of both low system cost and low power consumption.The internal DCO provides a fast turn-on clock source and stabilizes in less than1µs.The basic clock module provides the following clock signals:•Auxiliary clock(ACLK),sourced either from a32768-Hz watch crystal or the internal LF oscillator.•Main clock(MCLK),the system clock used by the CPU.•Sub-Main clock(SMCLK),the sub-system clock used by the peripheral modules.Table11.DCO Calibration Data(Provided From Factory in Flash InformationMemory Segment A)DCO FREQUENCY CALIBRATION REGISTER SIZE ADDRESSCALBC1_1MHZ byte010FFh1MHzCALDCO_1MHZ byte010FEhCALBC1_8MHZ byte010FDh8MHzCALDCO_8MHZ byte010FChCALBC1_12MHZ byte010FBh12MHzCALDCO_12MHZ byte010FAhCALBC1_16MHZ byte010F9h16MHzCALDCO_16MHZ byte010F8hBrownoutThe brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off.Digital I/OThere is one8-bit I/O port implemented—port P1—and two bits of I/O port P2:•All individual I/O bits are independently programmable.•Any combination of input,output,and interrupt condition is possible.•Edge-selectable interrupt input capability for all the eight bits of port P1and the two bits of port P2.•Read/write access to port-control registers is supported by all instructions.•Each I/O has an individually programmable pullup/pulldown resistor.Watchdog Timer(WDT+)The primary function of the watchdog timer(WDT+)module is to perform a controlled system restart after a software problem occurs.If the selected time interval expires,a system reset is generated.If the watchdog function is not needed in an application,the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals.Timer_A2is a16-bit timer/counter with two capture/compare registers.Timer_A2can support multiple capture/compares,PWM outputs,and interval timing.Timer_A2also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.Table12.Timer_A2Signal Connections(MSP430F20x1)INPUT PIN NUMBER MODULE OUTPUT PIN NUMBERDEVICE INPUT MODULE MODULEOUTPUTSIGNAL INPUT NAME BLOCKPW,N RSA PW,N RSASIGNAL2-P1.01-P1.0TACLK TACLKACLK ACLKTimer NASMCLK SMCLK2-P1.01-P1.0TACLK INCLK3-P1.12-P1.1TA0CCI0A3-P1.12-P1.1ACLK(internal)CCI0B7-P1.56-P1.5CCR0TA0V SS GNDV CC V CC4-P1.23-P1.2TA1CCI1A4-P1.23-P1.2CAOUTCCI1B8-P1.67-P1.6(internal)CCR1TA1V SS GND13-P2.612-P2.6V CC V CCTable13.Timer_A2Signal Connections(MSP430F20x2,MSP430F20x3)INPUT PIN NUMBER MODULE OUTPUT PIN NUMBERDEVICE INPUT MODULE MODULEOUTPUTSIGNAL INPUT NAME BLOCKPW,N RSA PW,N RSASIGNAL2-P1.01-P1.0TACLK TACLK Timer NAACLK ACLKSMCLK SMCLK2-P1.01-P1.0TACLK INCLK3-P1.12-P1.1TA0CCI0A CCR0TA03-P1.12-P1.1 7-P1.56-P1.5ACLK(internal)CCI0B7-P1.56-P1.5V SS GNDV CC V CC4-P1.23-P1.2TA1CCI1A CCR1TA14-P1.23-P1.2 8-P1.67-P1.6TA1CCI1B8-P1.67-P1.6V SS GND13-P2.612-P2.6V CC V CCComparator_A+(MSP430F20x1)The primary function of the comparator_A+module is to support precision slope analog-to-digital conversions, battery-voltage supervision,and monitoring of external analog signals.USI(MSP430F20x2and MSP430F20x3)The universal serial interface(USI)module is used for serial data communication and provides the basic hardware for synchronous communication protocols like SPI and I2C.ADC10(MSP430F20x2)The ADC10module supports fast,10-bit analog-to-digital conversions.The module implements a10-bit SAR core,sample select control,reference generator and data transfer controller,or DTC,for automatic conversion result handling,allowing ADC samples to be converted and stored without any CPU intervention.SD16_A(MSP430F20x3)The SD16_A module supports16-bit analog-to-digital conversions.The module implements a16-bit sigma-delta core and reference generator.In addition to external analog inputs,internal V CC sense and temperature sensors are also available.Peripheral File MapTable14.Peripherals With Word AccessADC10ADC control0ADC10CTL001B0h (MSP430F20x2)ADC control1ADC10CTL101B2hADC memory ADC10MEM01B4hADC data transfer start address ADC10SA01BCh SD16_A General Control SD16CTL0100h (MSP430F20x3)Channel0Control SD16CCTL00102hInterrupt vector word register SD16IV0110hChannel0conversion memory SD16MEM00112h Timer_A Capture/compare register TACCR10174hCapture/compare register TACCR00172hTimer_A register TAR0170hCapture/compare control TACCTL10164hCapture/compare control TACCTL00162hTimer_A control TACTL0160hTimer_A interrupt vector TAIV012Eh Flash Memory Flash control3FCTL3012ChFlash control2FCTL2012AhFlash control1FCTL10128h Watchdog Timer+Watchdog/timer control WDTCTL0120hTable15.Peripherals With Byte AccessADC10Analog enable ADC10AE04Ah (MSP430F20x2)ADC data transfer control register1ADC10DTC1049hADC data transfer control register0ADC10DTC0048h SD16_A Channel0Input Control SD16INCTL00B0h (MSP430F20x3)Analog Enable SD16AE0B7h USI USI control0USICTL0078h (MSP430F20x2and MSP430F20x3)USI control1USICTL1079hUSI clock control USICKCTL07AhUSI bit counter USICNT07BhUSI shift register USISR07Ch Comparator_A+Comparator_A+port disable CAPD05Bh (MSP430F20x1)Comparator_A+control2CACTL205AhComparator_A+control1CACTL1059h Basic Clock System+Basic clock system control3BCSCTL3053hBasic clock system control2BCSCTL2058hBasic clock system control1BCSCTL1057hDCO clock frequency control DCOCTL056h Port P2Port P2resistor enable P2REN02FhPort P2selection P2SEL02EhPort P2interrupt enable P2IE02DhPort P2interrupt edge select P2IES02ChPort P2interrupt flag P2IFG02BhPort P2direction P2DIR02AhPort P2output P2OUT029hPort P2input P2IN028h Port P1Port P1resistor enable P1REN027hPort P1selection P1SEL026hPort P1interrupt enable P1IE025hPort P1interrupt edge select P1IES024hPort P1interrupt flag P1IFG023hPort P1direction P1DIR022hPort P1output P1OUT021hPort P1input P1IN020h Special Function SFR interrupt flag2IFG2003hSFR interrupt flag1IFG1002hSFR interrupt enable2IE2001hSFR interrupt enable1IE1000h。