A low power 10 Gbs AGC optical postamplifier in SiGe
Converge SR 1212A数字矩阵混音器与四通道电源放大器数据资料说明书
Converge TM|SR 1212ADigital Matrix Mixer with Four Channel Power AmplifierConverge Pro DATA SHeeT <THE ULTIMATE IN AUDIO PROCESSING AND DIGITAL MATRIX MIXING APPLICATIonSBoardroomsTraining CentersMunicipal RoomsCourtroomsHouses of WorshipTelemedicinePresentation SystemsZoned PagingMasking SystemsADvAnTAgeSAdvanced Feature SetManagement Improvements+Integrated Ethernet and USB connections>SNMP and HTML remote management agents>Event scheduler>Diagnostic console>Simplified Configuration Software+Drag & drop A/V and channel objects>Selectable views -- unit, matrix, channel>Expanded serial command set+Superior Audio PerformanceDARE™ (Dynamic Automatic Resonance Elimination) for control of feedback+Unique automatic mixing process delivers optimum intelligibility+20 Hz-22 kHz bandwidth for full-range audio response+ALC & AGC keep participants’ audio balanced and consistent+Advanced Digital Processing on each amplifier channel+Configuration FlexibilityFour built-in 35 Watt amplifiers, 8Ω or 70V/100V+Up to 96 microphones+Link multiple Converge/Converge Pro units (Converge Pro 880, 880T, 880TA, 840T, 8i, TH20,+Converge SR 1212 and SR 1212A) for extensive microphone coverage and up to 16 phonelinesEnhanced expansion bus, featuring 18 mix-minus audio buses for routing between units+Ten mic gating groups (four internal & six global) allow separation of mics into individual+mixer gating groups for greater configuration flexibility32 presets can be executed on-the-fly without disturbing other ongoing preset operations+255 Macros for customized audio control/configuration with single command execution+No space required between rack mounted units+NEw!Audio PerformanceConditions: Unless otherwise specified,all measurements are performedfrom 20 Hz to 22 kHz Bw limit (no weighting)Frequency Response: 20 Hz to 22 kHz+/- 1 dBNoise (EIN): -126 dBu, 20 kHz Bw,max gainRs= 150ΩTHD+ Noise: <0.02%Dynamic Range: >105 dB (non A weighted)Crosstalk: <-91 dB re 20 dBu full band. Mic/Line Inputs 1-8Push-on mini-terminal block, balanced, bridgingImpedance: > 5 KΩNominal Level: adjustable -56 dBu to 0 dBu (7dB step coarse gain adjustment) Maximum Level: -65 to +20 dBu Phantom Power: 24V, selectableLine Inputs 9-12Push-on mini-terminal block, balanced, bridgingImpedance: > 5 KΩNominal Level: 0 dBuMaximum Level: 20 dBuoutput 1-8Push-on mini-terminal block, balanced, bridgingImpedance: < 50ΩNominal Level: 0 dBuMaximum Level: 20 dBuAuto Mixer ParametersNumber of Open Microphones (NOM)PA Adaptive ModeFirst Mic Priority ModeMaximum # of MicsAmbient LevelGate Threshold AdjustOff Attenuation AdjustHold TimeDecay RateChairman Override96 T otal Microphones per site6- Global Gating Groups4- Internal Gating Groups Matrix Mixing Parameters8- Microphone Analog Inputs4- Analog Line Inputs8- Analog Line Outputs4- Power Amplifier Outputs18- Expansion Bus in/out8- Assignable Processing Blocks in/outAssignable Processing BlocksFiltersAll PassLow PassHigh PassLow shelvingHigh shelvingPEQNotchCrossoversCD HornCompressorDelay: adjustable up to 250 msPower Amplifier output ProcessingFeedBack Elimination w/ring cancellation10-band EQ filter4-node filter bank for CrossoverDelay BlockCompressor/LimiterNoise Gate for Hiss ControlSound Masking Generator per channelAdaptive Volume ControlMulti Channel ControlMicrophone Processing4-node filter bankAGC/ALCPower AmplifiersChannels: 4Amplifier Output: 4x35 Watts into 8ΩImpedance: Selectable 8Ω, 70V, 100VTHD + Noise: <0.2% (1/3 Power)Crosstalk: <-68 dBexpansion BusConnection: CAT 5, RJ45Mix Minus Structure18 Audio Buses6 Gating Buses8 Reference Busesnetwork10/100 Auto Switching (PC andNetwork Port)HTTP ServerT elnet ClientSNMP AgentSMTP ClientDNSDHCPrS-232DB-99.6k – 115k baud8/1/0Hardware Flow ControlUSBVersion 2.0 compatibleT ype: B-connectorgPIoDB 25 female (A/B)Inputs: Active LowOutputs: Open Collector, 40Vdc, 40 mAPower100-240VAC; 50/60 Hz,300 watts (maximum)Idle: 139 BTU/hrFull Load: 779 BTU/hrEfficiency: >80%Humidity15 to 80%MechanicalDimensions: 2RU3.5” H x 17.25” w x 15.92” Dweight: < 30 lbs.environmentalOperating temperature:32-122 degrees FComplianceFCCIndustry CanadaCERoHSClass 2 wiring RequiredPart number910-151-901 Converge SR 1212ACONVERGE PRO SR 1212A DATA SHeeT <> Converge Pro Sr 1212A BACK PAneL > SPeCIFICATIonS> CLeArone LoCATIonSHeadquarters:Salt Lake City, UT USA 5225 wiley Post way Suite 500Salt Lake City, UT 84116 Tel: 801-975-7200T oll Free: 800-945-7730 Fax: 801-977-0087******************Latin AmericaTel: 801-974-3621*******************EMEATel: 44 (0) 1189 036 053*******************APACTel: 801-303-3388*******************Other product names may be registered trademarks of their respective owners who do not necessarily endorse ClearOne or ClearOne’s products. All rights reserved. Information in this document subject to change without notice.© ClearOne. 802-151-901-DS Revision 1.9。
电子术语缩写大全
专业术语常用名词缩写中英文对照请选择您所要查询的字母:A-B-C-D-E-F-G-H-I-L-M-O-P-R-S-T-U-VA:Actuator 执行器A:Amplifier 放大器A:Attendance员工考勤A:Attenuation衰减AA:Antenna amplifier 开线放大器AA:Architectural Acoustics建筑声学AC:Analogue Controller 模拟控制器ACD:Automatic Call Distribution 自动分配话务ACS:Access Control System出入控制系统AD:Addressable Detector地址探测器ADM:Add/Drop Multiplexer分插复用器ADPCM:Adaptive Differential ulse Code Modulation 自适应差分脉冲编码调制AF:Acoustic Feedback 声反馈AFR:Amplitude /Frequency Response 幅频响应AGC:Automati Gain Control自动增益控制AHU:Air Handling Unit 空气处理机组A-I:Auto-iris自动光圈AIS:Alarm Indication Signal 告警指示信号AITS:Acknowledged Information Transfer Service确认操作ALC:Automati Level Control 自动平衡控制ALS:Alarm Seconds 告警秒ALU:Analogue Lines Unit 模拟用户线单元AM:Administration Module管理模块AN:Access Network 接入网ANSI:American National Standards Institute美国国家标准学会APS:Automatic Protection Switching 自动保护倒换ASC:Automati Slope Control 自动斜率控制ATH:Analogue Trunk Unit 模拟中继单元ATM:Asynchrous Transfer Mode 异步传送方式AU- PPJE:AU Pointer Positive Justification 管理单元正指针调整AU:Administration Unit 管理单元AU-AIS:Administrative Unit Alarm Indication SignalAU告警指示信号AUG:Administration Unit Group 管理单元组AU-LOP:Loss of Administrative Unit Pointer AU指针丢失AU-NPJE:AU Pointer Negative Justification管理单元负指针调整AUP:Administration Unit Pointer管理单元指针AVCD:Auchio &Video Control Device 音像控制装置AWG:American Wire Gauge美国线缆规格BA:Bridge Amplifier桥接放大器TOPBAC:Building Automation & Control net建筑物自动化和控制网络BAM:Background Administration Module后管理模块BBER:Background Block Error Ratio背景块误码比BCC:B-channel Connect ControlB通路连接控制BD:Building DistributorBEF:Buiding Entrance Facilities 建筑物入口设施BFOC:Bayonet Fibre Optic Connector大口式光纤连接器BGN:Background Noise背景噪声BGS: Background Sound 背景音响BIP-N:Bit Interleaved Parity N code 比特间插奇偶校验N位码B-ISDN:Brand band ISDN 宽带综合业务数字网B-ISDN:Broad band -Integrated Services Digital Network 宽带综合业务数字网BMC:Burst Mode Controller 突发模式控制器BMS:Building Management System 智能建筑管理系统BRI:Basic Rate ISDN 基本速率的综合业务数字网BS:Base Station基站BSC:Base Station Controller基站控制器BUL:Back up lighting备用照明C/S: Client/Server客户机/服务器TOPC:Combines 混合器C:Container 容器CA:Call Accounting电话自动计费系统CATV:Cable Television 有线电视CC:Call Control 呼叫控制CC:Coax cable 同轴电缆CCD:Charge coupled devices 电荷耦合器件CCF:Cluster Contril Function 簇控制功能CD:Campus Distributor 建筑群配线架CD:Combination detector 感温,感烟复合探测器CDCA:Continuous Dynamic Channel Assign 连续的动态信道分配CDDI:Copper Distributed Data 合同缆分布式数据接口CDES:Carbon dioxide extinguisbing system 二氧化碳系统CDMA:Code Division Multiplex Access 码分多址CF:Core Function 核心功能CFM:Compounded Frequency Modulation 压扩调频繁CIS:Call Information System 呼叫信息系统CISPR:Internation Special Conmittee On Radio Interference 国际无线电干扰专门委员会CLNP:Connectionless Network Protocol 无连接模式网络层协议CLP:Cell Loss Priority信元丢失优先权CM:Communication Module 通信模块CM:Configuration Management 配置管理CM:Cross-connect Matrix交叉连接矩阵CMI:Coded Mark Inversion传号反转码CMISE:Common Management Information Service公用管理信息协议服务单元CPE:Convergence protocol entity 会聚协议实体CR/E:card reader /Encoder (Ticket reader )卡读写器/编码器CRC:Cyclic Redundancy Check 循环冗佘校验CRT:Cathode Ray Tabe 显示器,监视器,阴极射线管CS: Convergence service 会聚服务CS:Cableron Spectrum 旧纳档块化技术CS:Ceiling Screen 挡烟垂壁CS:Convergence Sublayer合聚子层CSC:Combined Speaker Cabinet 组合音响CSCW:Computer supported collaborative work 计算机支持的协同工作CSES:Continuius Severely Errored Second 连续严重误码秒CSF:Cell Site Function 单基站功能控制CTB:Composite Triple Beat 复合三价差拍CTD:Cable Thermal Detector 缆式线型感温探测器CTNR:carrier to noise ratio 载波比CW:Control Word 控制字D:Directional 指向性TOPD:Distortion 失真度D:Distributive 分布式DA:Distribution Amplifier 分配的大器DBA:Database Administrator数据库管理者DBCSN:Database Control System Nucleus数据库控制系统核心DBOS:Database Organizing System 数据库组织系统DBSS:Database Security System 数据库安全系统DC:Door Contacts大门传感器DCC:Digital Communication Channel数字通信通路DCN:Data Communication Network 数据通信网DCP-I:Distributed Control Panel -Intelligent智能型分散控制器DCS:Distributed Control System集散型控制系统DDN:Digital Data Network 数字数据网DDS:Direct Dignital Controller直接数字控制器DDW:Data Describing Word 数据描述字DECT:Digital Enhanced Cordless Telecommunication增强数字无绳通讯DFB:Distributed Feedback 分布反馈DID:Direct Inward Dialing 直接中继方式,呼入直拨到分机用户DLC:Data Link Control Layer 数据链路层DLI:DECT Line InterfaceDODI:Direct Outward Dialing One 一次拨号音DPH:DECT PhoneDRC:Directional Response Cahracteristics 指向性响应DS:Direct Sound 直正声DSP:Digital signal Processing 数字信号处理DSS:Deiision Support System 决策支持系统DTMF:Dual Tone Multi-Frequency 双音多频DTS:Dual -Technology Sensor 双鉴传感器DWDM:Dense Wave-length Division Multiplexing 密集波分复用DXC:Digital Cross-Connect 数字交叉连接E:Emergency lighting照明设备TOPE:Equalizer 均衡器E:Expander 扩展器EA-DFB:Electricity Absorb-Distributed Feedback 电吸收分布反馈ECC:Embedded Control Channel 嵌入或控制通道EDFA:Erbium-Doped Fiber Amplifier掺饵光纤放大器EDI:Electronic Data Interexchange 电子数据交换EIC:Electrical Impedance Characteristics 电阻抗特性EMC:Electro Magnetic Compatibiloty 电磁兼容性EMI:Electro Magnetic Interference 电磁干扰EMS:Electromagnetic Sensitibility 电磁敏感性EN:Equivalent Noise 等效噪声EP:Emergency Power 应急电源ES:Emergency Sooket 应急插座ES:Evacuation Sigvial疏散照明ESA:Error SecondA 误码秒类型AESB:ErrorSecondB 误码秒类型BESD:Electrostatic Discharge静电放电ESR:Errored Second Ratio 误码秒比率ETDM:Electrical Time Division Multiplexing电时分复用ETSI:European Telecommunication Standards Institute欧洲电信标准协会F:Filter 滤波器TOPFAB:Fire Alarm Bell 火警警铃FACU:Fire Alarm Contrlol Unit 火灾自动报警控制装置FC:Failure Count 失效次数FC:Frequency Converter 频率变换器FCC:Fire Alarm System 火灾报警系统FCS:Field Control System 现场总线FCU:Favn Coil Unit风机盘管FD:Fire Door 防火门FD:Flame Detector 火焰探测器FD:Floor DistributorFD:Frequency Dirsder 分频器FDD:Frequency Division Dual 频分双工FDDI:Fiberdistributed Data Interface光纤缆分布式数据接口。
常用的弱电术语缩写
专业术语常用名词缩写中英文对照A:Actuator执行器A:Amplifier放大器A:Attendance员工考勤A:Attenuation衰减AA:Antenna amplifier开线放大器AA:Architectural Acoustics建筑声学AC:Analogue Controller模拟控制器ACD:Automatic Call Distribution自动分配话务ACS:Access Control System出入控制系统AD:Addressable Detector地址探测器ADM:Add/Drop Multiplexer分插复用器ADPCM:Adaptive Differential ulse Code Modulation自适应差分脉冲编码调制AF:Acoustic Feedback声反馈AFR:Amplitude /Frequency Response幅频响应AGC:Automati Gain Control自动增益控制AHU:Air Handling Unit空气处理机组A-I:Auto-iris自动光圈AIS:Alarm Indication Signal告警指示信号AITS:Acknowledged Information Transfer Service确认操作ALC:Automati Level Control自动平衡控制ALS:Alarm Seconds告警秒ALU:Analogue Lines Unit模拟用户线单元AM:Administration Module管理模块AN:Access Network接入网ANSI:American National Standards Institute美国国家标准学会APS:Automatic Protection Switching自动保护倒换ASC:Automati Slope Control自动斜率控制ATH:Analogue Trunk Unit模拟中继单元ATM:Asynchrous Transfer Mode异步传送方式AU- PPJE:AU Pointer Positive Justification管理单元正指针调整AU:Administration Unit管理单元AU-AIS:Administrative Unit Alarm Indication SignalAU告警指示信号AUG:Administration Unit Group管理单元组AU-LOP:Loss of Administrative Unit Pointer AU指针丢失AU-NPJE:AU Pointer Negative Justification管理单元负指针调整AUP:Administration Unit Pointer管理单元指针AVCD:Auchio &Video Control Device音像控制装置AWG:American Wire Gauge美国线缆规格BA:Bridge Amplifier桥接放大器BAC:Building Automation & Control net建筑物自动化和控制网络BAM:Background Administration Module后管理模块BBER:Background Block Error Ratio背景块误码比BCC:B-channel Connect ControlB通路连接控制BD:Building DistributorBEF:Buiding Entrance Facilities建筑物入口设施BFOC:Bayonet Fibre Optic Connector大口式光纤连接器BGN:Background Noise背景噪声BGS: Background Sound背景音响BIP-N:Bit Interleaved Parity N code比特间插奇偶校验N位码B-ISDN:Brand band ISDN宽带综合业务数字网B-ISDN:Broad band -Integrated Services Digital Network宽带综合业务数字网BMC:Burst Mode Controller突发模式控制器BMS:Building Management System智能建筑管理系统BRI:Basic Rate ISDN基本速率的综合业务数字网BS:Base Station基站BSC:Base Station Controller基站控制器BUL:Back up lighting备用照明C/S: Client/Server客户机/服务器C:Combines混合器C:Container容器CA:Call Accounting电话自动计费系统CATV:Cable Television有线电视CC:Call Control呼叫控制CC:Coax cable同轴电缆CCD:Charge coupled devices电荷耦合器件CCF:Cluster Contril Function簇控制功能CD:Campus Distributor建筑群配线架CD:Combination detector感温,感烟复合探测器CDCA:Continuous Dynamic Channel Assign连续的动态信道分配CDDI:Copper Distributed Data合同缆分布式数据接口CDES:Carbon dioxide extinguisbing system二氧化碳系统CDMA:Code Division Multiplex Access码分多址CF:Core Function核心功能CFM:Compounded Frequency Modulation压扩调频繁CIS:Call Information System呼叫信息系统CISPR:Internation Special Conmittee On Radio Interference国际无线电干扰专门委员会CLNP:Connectionless Network Protocol无连接模式网络层协议CLP:Cell Loss Priority信元丢失优先权CM:Communication Module通信模块CM:Configuration Management配置管理CM:Cross-connect Matrix交叉连接矩阵CMI:Coded Mark Inversion传号反转码CMISE:Common Management Information Service公用管理信息协议服务单元CR/E:card reader /Encoder (Ticket reader )卡读写器/编码器CRC:Cyclic Redundancy Check循环冗佘校验CRT:Cathode Ray T abe显示器,监视器,阴极射线管CS: Convergence service会聚服务CS:Cableron Spectrum旧纳档块化技术CS:Ceiling Screen挡烟垂壁CS:Convergence Sublayer合聚子层CSC:Combined Speaker Cabinet组合音响CSCW:Computer supported collaborative work计算机支持的协同工作CSES:Continuius Severely Errored Second连续严重误码秒CSF:Cell Site Function单基站功能控制CTB:Composite Triple Beat复合三价差拍CTD:Cable Thermal Detector缆式线型感温探测器CTNR:carrier to noise ratio载波比CW:Control Word控制字D irectional指向性D istortion失真度D istributive分布式DA istribution Amplifier分配的大器DBA atabase Administrator数据库管理者DBCSN atabase Control System Nucleus数据库控制系统核心DBOS atabase Organizing System数据库组织系统DBSS atabase Security System数据库安全系统DC oor Contacts大门传感器DCC igital Communication Channel数字通信通路DCN:Data Communication Network数据通信网DCP-I:Distributed Control Panel -Intelligent智能型分散控制器DCS:Distributed Control System集散型控制系统DDN:Digital Data Network数字数据网DDS:Direct Dignital Controller直接数字控制器DDW:Data Describing Word数据描述字DECT:Digital Enhanced Cordless Telecommunication增强数字无绳通讯DFB:Distributed Feedback分布反馈DID:Direct Inward Dialing直接中继方式,呼入直拨到分机用户DLC:Data Link Control Layer数据链路层DLI:DECT Line InterfaceDODI:Direct Outward Dialing One一次拨号音DPH:DECT PhoneDRC:Directional Response Cahracteristics指向性响应DS:Direct Sound直正声DSP:Digital signal Processing数字信号处理DSS:Deiision Support System决策支持系统CR/E:card reader /Encoder (Ticket reader )卡读写器/编码器CRC:Cyclic Redundancy Check循环冗佘校验CRT:Cathode Ray T abe显示器,监视器,阴极射线管CS: Convergence service会聚服务CS:Cableron Spectrum旧纳档块化技术CS:Ceiling Screen挡烟垂壁CS:Convergence Sublayer合聚子层CSC:Combined Speaker Cabinet组合音响CSCW:Computer supported collaborative work计算机支持的协同工作CSES:Continuius Severely Errored Second连续严重误码秒CSF:Cell Site Function单基站功能控制CTB:Composite Triple Beat复合三价差拍CTD:Cable Thermal Detector缆式线型感温探测器CTNR:carrier to noise ratio载波比CW:Control Word控制字D irectional指向性D istortion失真度D istributive分布式DA istribution Amplifier分配的大器DBA atabase Administrator数据库管理者DBCSN atabase Control System Nucleus数据库控制系统核心DBOS atabase Organizing System数据库组织系统DBSS atabase Security System数据库安全系统DC oor Contacts大门传感器DCC igital Communication Channel数字通信通路DCN:Data Communication Network数据通信网DCP-I:Distributed Control Panel -Intelligent智能型分散控制器DCS:Distributed Control System集散型控制系统DDN:Digital Data Network数字数据网DDS:Direct Dignital Controller直接数字控制器DDW:Data Describing Word数据描述字DECT:Digital Enhanced Cordless Telecommunication增强数字无绳通讯DFB:Distributed Feedback分布反馈DID:Direct Inward Dialing直接中继方式,呼入直拨到分机用户DLC:Data Link Control Layer数据链路层DLI:DECT Line InterfaceDODI:Direct Outward Dialing One一次拨号音DPH:DECT PhoneDRC:Directional Response Cahracteristics指向性响应DS:Direct Sound直正声DSP:Digital signal Processing数字信号处理DSS:Deiision Support System决策支持系统DTMF:Dual Tone Multi-Frequency双音多频DTS:Dual -Technology Sensor双鉴传感器DWDM:Dense Wave-length Division Multiplexing密集波分复用DXC:Digital Cross-Connect数字交叉连接E:Emergency lighting照明设备E:Equalizer均衡器E:Expander扩展器EA-DFB:Electricity Absorb-Distributed Feedback电吸收分布反馈ECC:Embedded Control Channel嵌入或控制通道EDFA:Erbium-Doped Fiber Amplifier掺饵光纤放大器EDI:Electronic Data Interexchange电子数据交换EIC:Electrical Impedance Characteristics电阻抗特性EMC:Electro Magnetic Compatibiloty电磁兼容性EMI:Electro Magnetic Interference电磁干扰EMS:Electromagnetic Sensitibility电磁敏感性EN:Equivalent Noise等效噪声EP:Emergency Power应急电源ES:Emergency Sooket应急插座ES:Evacuation Sigvial疏散照明ESA:Error SecondA误码秒类型AESB:ErrorSecondB误码秒类型BESD:Electrostatic Discharge静电放电ESR:Errored Second Ratio误码秒比率ETDM:Electrical Time Division Multiplexing电时分复用ETSI:European Telecommunication Standards Institute欧洲电信标准协会F:Filter滤波器FAB:Fire Alarm Bell火警警铃FACU:Fire Alarm Contrlol Unit火灾自动报警控制装置FC:Failure Count失效次数FC:Frequency Converter频率变换器FCC:Fire Alarm System火灾报警系统FCS:Field Control System现场总线FCU:Favn Coil Unit风机盘管FD:Fire Door防火门FD:Flame Detector火焰探测器FD:Floor DistributorFD:Frequency Dirsder分频器FDD:Frequency Division Dual频分双工FDDI:Fiberdistributed Data Interface光纤缆分布式数据接口。
计算机英语缩写大全
计算机语言缩写大全3C(China Compulsory Certification,中国强制性产品认证制度)3D(Three Dimensional,三维)3DCG(3D computer graphics,三维计算机图形)3DNow!(3D no waiting,无须等待的3D处理)3DPA(3D Positional Audio,3D定位音频)3DS(3D SubSystem,三维子系统)3GIO(Third Generation Input/Output,第三代输入输出技术)AA(Accuview Antialiasing,高精度抗锯齿)AAC(Advanced Audio Compression,高级音频压缩)AAM(AMD Analyst Meeting,AMD分析家会议)AAM(Automatic Acoustic Management,自动机械声学管理)AAS(Automatic Area Segments)AAT(Average access time,平均存取时间)ABB(Advanced Boot Block,高级启动块)ABP(Address Bit Permuting,地址位序列改变)ABP(Advanced Branch Prediction,高级分支预测)ABS(Auto Balance System,自动平衡系统)A-Buffer(Accumulation Buffer,积聚缓冲)AC(Acoustic Edge,声学边缘)AC(Audio Codec,音频多媒体数字信号编解码器)AC-3(Audio Coding 3,第三代音响编码)AC97(Audio Codec 97,多媒体数字信号解编码器1997年标准)ACCP(Applied Computing Platform Providers,应用计算平台提供商)ACG(Aggressive Clock Gating,主动时钟选择)ACIRC(Advanced Cross Interleave Reed - Solomon Code,高级交叉插入里德所罗门代码)ACOPS(Automatic CPU OverHeat Prevention System(CPU过热预防系统)ACPI(Advanced Configuration and Power Interface,先进设置和电源管理)ACR(Advanced Communications Riser,高级通讯升级卡)ACS(Access Control Software,存取控制软件)ACT(Action,动作类游戏)AD(Analog to Digitalg,模拟到数字转换)ADC(Analog to Digital Converter,模数传换器)ADC(Apple Display Connector,苹果专用显示器接口)ADI(Adaptive De-Interlacing,自适应交错化技术)ADIMM(advanced Dual In-line Memory Modules,高级双重内嵌式内存模块)ADIP(Address In Pre-Groove,预凹槽寻址)ADSL(Asymmetric Digital Subscriber Line,不对称数字订阅线路)ADT(Advanced DRAM Technology,高级内存技术)AE(Atmospheric Effects,大气雾化效果)AE(Auto Focus,自动测光)AES-OCB(Advanced Encryption Standard-Operation Cipher Block,高级加密标准-操作密码块)AF(Auto Focus,自动对焦)AFC media(antiferromagnetically coupled media,反铁磁性耦合介质)AFC(Advanced Frame Capture、高级画面捕获)AFC(Amplitude-frequency characteristic,振幅频率特征)AFE(Analog Front End,模拟前置)AFM(Atomic Force Microscope,原子力显微镜)AFR(Alternate Frame Rendering,交替渲染技术)AG(Aperture Grills,栅条式金属板)AGBS(Advance GameBoy development System,高级GameBoy发展系统)AGC(Anti Glare Coatings,防眩光涂层)AGP(Accelerated Graphics Port,图形加速接口)AGPS(Assisted Global Positioning System,援助全球定位系统)AGTL+(Assisted Gunning Transceiver Logic,援助发射接收逻辑电路)AGU(Address Generation Units,地址产成单元)AH(Authentication Header,鉴定文件头)AHA(Accelerated Hub Architecture,加速中心架构)AI(Artificial Intelligence,人工智能)AIMM(AGP Inline Memory Module,AGP板上内存升级模块)AIS(Alternate Instruction Set,交替指令集)AL(Additive Latency,附加反应时间)AL(Artificial Life,人工生命)ALAT(advanced load table,高级载入表)ALDC(Adaptive Lossless Data Compression,适应无损数据压缩)ALU(Arithmetic Logic Unit,算术逻辑单元)Aluminum(铝)AM(Acoustic Management,声音管理)AMC(audio/modem codec,音频/调制解调器多媒体数字信号编解码器)AMR(Audio/Modem Riser,音效/调制解调器主板附加直立插卡)An isotropic Filtering(各向异性过滤)ANSI(American National Standards Institute,美国国立标准协会)AOI(Automatic Optical Inspection,自动光学检验)AOL(Alert On LAN,局域网警告)APC(Advanced Power Control,高级能源控制)API(Application Programming Interfaces,应用程序接口)APIC(Advanced Programmable Interrupt Controller,高级可编程中断控制器)APM(Advanced Power Management,高级能源管理)APPE(Advanced Packet Parsing Engine,增强形帧解析引擎)APS(Alternate Phase Shifting,交替相位跳转)APS(Audio Production Studio,音频生产工作室)APU(Audio Processing Unit,音频处理单元)APX(All Position eXpansion,全方位扩展)AR(Auto-Resume,自动恢复)ARC(Anti Reflect Coating,防反射涂层)ARF(Asynchronous Receive FIFO,异步接收先入先出)ARP(Address Resolution Protocol,地址解析协议)ARPG(Action Role Play Games,动作角色扮演游戏)ARR(Annual Return Rate,年返修率)ASB(Advanced System Buffering,高级系统缓冲)ASC(Advanced Size Check,高级尺寸检查)ASC(Anti Static Coatings,防静电涂层)ASC(Auto-Sizing and Centering,自动调效屏幕尺寸和中心位置)ASCI(The 10-year Accelerated Strategic Computing Initiative,领先10年战略加速计算机)ASCII(American Standard Code for Information Interchange,美国国家标准信息交换代码)ASD(Auto Stereoscopic Display,自动立体显示)ASF(Advanced Streaming Format,高级数据流格式)ASF(Alert Standards Forum,警告标准讨论)ASIC(Application Specific Integrated Circuit,特殊应用积体电路)ASIO(Audio Streaming Input and Output interface,音频流输入输出接口)ASK IR(Amplitude Shift Keyed Infra-Red,长波形可移动输入红外线)ASMO(Advanced Storage Magneto-Optical,增强形光学存储器)ASP(Active Server Pages,活动服务页)ASP(Application Service Provider,应用服务提供商)ASPI(Advanced SCSI Programming Interface,高级SCSI可编程接口)AST(amorphous-silicon TFT,非晶硅薄膜晶体管)AST(Average Seek time,平均寻道时间)AT(Advanced Technology,先进技术)ATA(Advanced Technology Attachment,高级技术附加装置)ATAPI(AT Attachment Packet Interface,AT扩展包接口)ATC(Access Time from Clock,时钟存取时间)ATC(Advanced Transfer Cache,高级转移缓存)ATD(Assembly Technology Development,装配技术发展)ATL(ActiveX Template Library,ActiveX模板库)ATM(Asynchronous Transfer Mode,异步传输模式)ATM(Automatic Teller Machine,自动提款机)ATOMM(Advanced super Thin-layer and high-Output Metal Media,增强形超薄高速金属媒体)ATP(Active to Precharge,激活到预充电)ATRAC(Adaptive TRansform Acoustic Coding,可适应转换声学译码)ATSC(Advanced Television Systems Committee,高级电视系统委员会)ATX(AT Extend,扩展型AT)AUD_EXT(Audio Extension,音频扩展)AUX(Auxiliary Input,辅助输入接口)AV(Analog Video,模拟视频)AV(Audio & Video,音频和视频)AVG(Adventure Genre,冒险类游戏)AVI(Audio Video Interleave,音频视频插入)B Splines(B样条)B.O.D.E(Body Object Design Envioment,人体/物体/设计/环境渲染自动识别)BAC(Bad Angle Case,边角损坏采样)Back Buffer(后置缓冲)Backface culling(隐面消除)BAD(Best Amiga Dominators)BASIC(Beginners All-purpose Symbolic Instruction Codec,初学者通用指令代码)Battle for Eyeballs(眼球大战)BBS(BIOS Boot Specification,基本输入/输出系统启动规范)BBUL(Bumpless Build-Up Layer,内建非凹凸层)BCF(Boot Catalog File,启动目录文件)BEDO(Burst Enhanced Data-Out RAM,突发型数据增强输出内存)Benchmarks(基准测试程序数值BGA(Ball Grid Array,球状网阵排列)BHT(branch prediction table,分支预测表)BIF(Boot Image File,启动映像文件)Bilinear Filtering(双线性过滤)BIOS(Basic Input/Output System,基本输入/输出系统)BLA(Bearn Landing Area,电子束落区)BLP(Bottom Leaded Package,底部导向封装)BMC(Black Matrix Screen,超黑矩阵屏幕)BMS(Blue Magic Slot,蓝色魔法槽)BOD(Bandwidth On Demand,弹性带宽运用)BOPS(Billion Operations Per Second,十亿次运算/秒)BP(Brach Prediction,分支预测)BPA(Bit Packing Architecture,位封包架构)BPI(Bit Per Inch,位/英寸)bps(bit per second,位/秒)bps(byte per second,字节/秒)BPU(Branch Processing Unit,分支处理单元)BRC(Beta Release Candidate,测试发布候选版)BSD(Berkeley Software Distribution,伯克利软件分配代号)BSP(Binary Space Partitioning,二进制空间分区)BSP(Boot Strap Processor,启动捆绑处理器)BSRAM(Burst pipelined synchronous static RAM,突发式管道同步静态存储器)BTAC(Branch Target Address Calculator,分支目标寻址计算器)BTO(Build-To-Order,按序构建)BURN-Proof(Buffer UnderRuN-Proof,防止缓冲区溢出)C.O.P(CPU overheating protection,处理器过热保护)C2C(card-to-card interleaving,卡到卡交错存取CAD(computer-aided design,计算机辅助设计)CAM(Common Access Model,公共存取模型)CAM(Computer-aided manufacturing,计算机辅助制造)CAS(Column Address Strobe,列地址控制器)CAV(Constant Angular Velocity,恒定角速度)CBDS(Continuous Background Defect Scanning,连续后台错误扫描)CBF(Cable Broadband Forum,电缆宽带论坛)CBGA(Ceramic Ball Grid Array,陶瓷球状网阵排列)CBMC(Crossbar based memory controller,内存控制交叉装置)CBR(Committed Burst Rate,约定突发速率)CBR(Constant Bit Rate,固定比特率)CBU(color blending unit,色彩混和单位)CCD(Charge Coupled Device,电荷连接设备)CCIRN(Coordinating Committee for Intercontinental Research Networking,洲际研究网络协调委员会)CCM(Call Control Manager,拨号控制管理)cc-NUMA(cache-coherent non uniform memory access,连贯缓冲非统一内存寻址)CCS(Cross Capacitance Sensing,交叉电容感应)CCS(Cut Change System)CCT(Clock Cycle Time,时钟周期)CD(Compact Disc)cd/m^2(candela/平方米,亮度的单位)CDIP(Ceramic Dual-In-Line,陶瓷双重直线)CDPD(Cellular digital Packet data,细胞数字信息包数据)CDR(CD Recordable,可记录光盘)CDRAM(Cache DRAM,附加缓存型DRAM)CD-ROM/XA(CD-ROM eXtended Architecture,唯读光盘增强形架构)CDRS(Curved Directional Reflection Screen,曲线方向反射屏幕)CDRW(CD-Rewritable,可重复刻录光盘)CDSL(Consumer Digital Subscriber Line(消费者数字订阅线路)CE(Consumer Electronics,消费电子)CEA(Consumer Electronics Association,消费者电子协会)CEA(Critical Edge Angles,临界边角)CEM(cube environment mapping,立方环境映射)CEMA(Consumer Electronics Manufacturing Association,消费者电子制造业协会)Center Processing Unit Utilization,中央处理器占用率CEO(Chief Executive Officer,首席执行官)CF(CompactFlash Card,紧凑型闪存卡)CFM(cubic feet per minute,立方英尺/秒)CG(C for Graphics/GPU,用于图形/GPU的可编程语言)CG(Computer Graphics,计算机动画)CGI(Common Gateway Interface,通用网关接口)CG-Silicon(Continuous Grain Silicon,连续微粒硅)CHRP(Common Hardware Reference Platform,共用硬件平台)CHS(Cylinders、Heads、Sectors,柱面、磁头、扇区)CIEA(Commercial Internet Exchange Association,商业因特网交易协会)CIR(Committed Information Rate,约定信息速率)CIS(Contact Image Sensors,接触图像传感器)CISC(Complex Instruction Set Computing,复杂指令集计算机)CL(CAS Latency,CAS反应时间)Clipping(剪贴纹理)CLK(Clock Cycle,时钟周期)Clock Synthesizer,时钟合成器CLV(Constant Linear Velocity,恒定线速度)CMOS(Complementary Metal Oxide Semiconductor,互补金属氧化物半导体)CMOV(conditional move instruction,条件移动指令)CMP(on-chip multiprocessor,片内多重处理)CMR(Colossal Magneto Resistive,巨磁阻抗)CMS(Code Morphing Software,代码变形软件)CMSS(Creative Multi Speaker Surround,创新多音箱环绕)CMT(course-grained multithreading,过程消除多线程)CNPS(Computer Noise Prevention System,计算机噪音预防系统)CNR(Communication and Networking Riser,通讯和网络升级卡)CNT(carbon nano-tube,碳微管)COAST(Cache-on-a-stick,条状缓存)COB(Cache on board,板上集成缓存)co-CPU(cooperative CPU,协处理器)COD(Cache on Die,芯片内核集成缓存)COM(Component Object Model,组件对象模式)COMDEX(Computer Distribution Exposition,计算机代理分销业展览会)compressed textures(压缩纹理)Concurrent Command Engine,协作命令引擎COO(Chief Organizer Officer,首席管理官)Copper(铜)CP(command processor,指令处理器)CPA(Close Page Auto recharge,接近页自动预充电)CPE(Customer Premise Equipment,用户预定设备)CPGA(Ceramic Pin Grid Array,陶瓷针型栅格阵列)CPI(count per inch,每英寸计数)CPI(cycles per instruction,周期/指令)CPLD(Complex Programmable Logic Device,复杂可程序化逻辑组件)CPRM(Content Protection for record able media,记录媒体内容保护)CPS(Certification Practice Statement,使用证明书)CPU(Center Processing Unit,中央处理器)CRC(Cyclical Redundancy Check,循环冗余检查)CRM(Customer Relationship Management,顾客关系管理)CRT(Cathode Ray Tube,阴极射线管)CRT(Cooperative Redundant Threads,协同多余线程)CS(Channel Separation,声道分离)CSA(Canadian Standards Association,加拿大标准协会)CSA(Communication Streaming Architecture,通讯流架构)CSC(Colorspace Conversion,色彩空间转换)CSD(Circuit Switched Data,电路切换数据通话)CSE(Configuration Space Enable,可分配空间)CSG(constructive solid geometry,建设立体几何)CSP(Chip Scale Package,芯片比例封装)CSP(Chip Size Package,芯片尺寸封装)CSS(Cascading Style Sheets,层叠格式表)CSS(Common Command Set,通用指令集)CSS(Content Scrambling System,内容不规则加密)CTI(Computer Telephone Integration,计算机电话综合技术)CTO(Chief Technology Officer,首席技术官)CTR(CAS to RAS,列地址到行地址延迟时间)CTS(Carpal Tunnel Syndrome,计算机腕管综合症)CTS(Clear to Send,清除发送)CVS(Compute Visual Syndrome,计算机视觉综合症)CXT(Chooper eXTend,增强形K6-2内核)DA(Digital to Analog,数字到模拟转换)DAB(digital audio broadcast,数字音频广播)DAC(Digital to Analog Converter,数模转换器)DAC(Dual Address Cycle,双重地址周期)DAE(digital Audio Extraction,数据音频抓取)DAN(Dance,跳舞类游戏)DAO(Disc At Once,整盘刻录)DAO-RAW(Disc At Once Read after Write,整盘刻录-写后读)DASP(Dynamic Adaptive Speculative Pre-Processor,动态适应预测预处理器)Data Forwarding(数据前送)dB(decibel,分贝)DB(Deep Buffer,深度缓冲)DB(Device Bay,设备插架)DBBS(Dynamic Bass Boost System,动态低音增强系统)DBI(dynamic bus inversion,动态总线倒置)DBS(Direct Broadcast Satellite,直接卫星广播)DBS-PC(Direct Broadcast Satellite PC,人造卫星直接广播式PC)DC(Digital Camera,数码相机)DC(Dreamcast,世嘉64位游戏机)DCA(Defense Communication Agency,国防部通信局)DCC(Digital Compact Cassette,数字盒式磁带)DCC(Digital Content Creation,数字内容创造)DCD(Directional Corelational De-interlacing,方向关联解交错)DCD(Document Content Description for XML,XML文件内容描述)DCE(Data Circuit Terminal Equipment,数据通信设备)DCLK(Dot Clock,点时钟)DCOM(Distributing Component Object Model,构造物体模块)DCT(Display Compression Technology,显示压缩技术)DCT(DRAM Controller,DRAM控制器)DD(Double Side,双面内存)DDBGA(Die Dimension Ball Grid Array,内核密度球状矩阵排列)DDC(Display Data Channel,显示数据通道)DDC(Dynamic Depth Cueing,动态深度暗示)图像DDE(dynamic data exchange,动态数据交换)DDMA(Distributed DMA,分布式DMA)DDP(Digital Display Port,数字输出端口)DDR SDRAM(Double Date Rate,上下行双数据率SDRAM)DDR(Double Date Rate,上下行双数据率)DDS(Direct Draw Surface,直接绘画表面)DDSS II(Double Dynamic Suspension System II,第二代双层动力悬吊系统)DDSS(Dolby Digital Surround Sound,杜比数字环绕声)DDSS(Double Dynamic Suspension System,双悬浮动态减震系统)DDT(Dynamic Deferred Transaction,动态延期处理)DDWG(Digital Display Working Group,数字化显示工作组)DEC(Direct Etching Coatings,表面蚀刻涂层)Decal(印花法)Decode(指令解码)Deflection Coil(偏转线圈)DES(ata Encryption Standard,数据加密标准)DFL(Dynamic Focus Lens,动态聚焦)DFP(Digital Flat Panel,数字平面显示标准)DFPG(Digital Flat Panel Group,数字平面显示标准工作组)DFS(Digital Flex Scan,数字伸缩扫描)DFS(Dynamic Flat Shading,动态平面描影)DHCP(Dynamic Host Configuration Protocol,动态主机分配协议)DHHF(Dual Head - High Fidelity,高精度第四代双头)DHT(Dolby Headphone Technology,杜比耳机技术)DIB(Dual Independent Bus,双重独立总线)DIC(Digital Image Control,数字图像控制)DID(Device ID,设备ID)Digital Multiscan II(数字式智能多频追踪)DIL(dual-in-line)DIMM(Dual In-line Memory Modules,双重内嵌式内存模块)Directional Light(方向性光源)DiscWizard(磁盘控制软件)DIT(Disk Inspection Test,磁盘检查测试)Dithering(抖动)DIVA(Data IntensiVe Architecture,数据加强架构)DIY(Do it Yourself,自己装机)DLL(Delay-Locked Loop,延时锁定循环电路)dll(dynamic link library,动态链接库)DLP(digital Light Processing,数字光处理)DLS(Downloadable Sounds Level,可下载音色)DLS-2(Downloadable Sounds Level 2,第二代可下载音色)DM(Displacement mapping,位移贴图)DMA(Direct Memory Access,直接内存存取)DMAC(Direct Memory Access Controller,直接内存存取控制器)DME(Direct Memory Execute,直接内存执行)DMF(Distribution Media Format)DMI(Desktop Management Interface,桌面管理接口)DMT(Discreet Monitor Timing,智能型显示器调速)DMT(Discrete Multi - Tone,不连续多基频模式)DMT(Dynamic Multithreading Architecture,动态多线程结构)DNA(Distributed Internet Application,分布式因特网应用程序)DNS(Domain Name System,域名解析系统)DOA2 HC(Deal or Live 2 hardcore,生与死2完整版)DOC(Disk On Chip,芯片磁盘)DOCSIS(Data Over Cable Service Interface Specifications,线缆服务接口数据规格)DOF(Depth of Field,多重境深)DOJ(Department of Justice,反不正当竞争部门)DOM(Document Object Model,文档目标模型)DoS(Denial of Service,拒绝服务)DOS(Disk Operating System,磁盘操作系统)DOSD(Digital On Screen Display,同屏数字化显示)Dot Pitch(点距)dot texture blending(点型纹理混和)DOT(Dynamic Overcooking Technology,动态超频技术)DOT3(Dot product 3 bump mapping,点乘积凹凸映射)Double Buffering(双缓冲区)DP(Dual Processor,双处理器)DPBM(Dot Product Bump Mapping,点乘积凹凸映射)DPC(Desktop PC,桌面PC)dpi(dot per inch,每英寸的打印像素)DPMS(Display Power Management Signaling,显示能源管理信号)DPP(Direct print Protocol,直接打印协议DQL(Dynamic Quadra pole Lens,动态四极镜)DQS(Bidirectional data strobe,双向数据滤波)DQUICK(DVD Qualification and Integration Kit,DVD资格和综合工具包)DRA(deferred rendering architecture,延迟渲染架构)DRAM(Dynamic Random Access Memory,动态随机存储器)DRCG(Direct Rambus Clock Generator,直接Rambus时钟发生器)DRDRAM(Direct RAMBUS DRAM,直接内存总线DRAM)DRF(Digital radio frequency,数字无线电频率)DRI(Direct Rendering Infrastructure,基层直接渲染)DRM(Digital rights management,数字版权保护)DRSL(Differential Rambus Signaling Level,微分RAMBUS信号级)DRSL(Direct Rambus Signaling Level,直接RAMBUS信号级)DS3D(DirectSound 3D Streams)DSD(Direct Stream Digital,直接数字信号流)DSL(Data Strobe Link,数据选通连接DSL(Down Loadable Sample,可下载的取样音色)DSM(Dedicated Stack Manager,专门堆栈管理)DSM(Distributed shared memory,分布式共享内存)DSMT(Dynamic Simultaneous Multithreading,动态同步多线程)DSO(Dynamic Sound-stage Organizer,动态声音层组建)DSP(Delivery Service Partner,交付服务合伙人)DSP(Digital Signal Processing,数字信号处理)DSP(Digital Sound Field Processing,数字音场处理)DSP(Dual Streams Processor,双重流处理器)DST(Depleted Substrate Transistor,衰竭型底层晶体管)DST(Drive Self Test,磁盘自检程序)DSTN(Double layers Super Twisted Nematic,双层超扭曲向列,无源矩阵LCD)DSVD(Digital Simultaneous Voice and Data)DTD(Document Type Definition,文件类型定义)DTE(Data Terminal Equipment,数据终端设备)DTL(Developer Tool,发展工具包)DTR(Disk Transfer Rate,磁盘传输率)DTS(Digital Theater System,数字剧院系统)DTT(DeskTop Theater,桌面剧院)DTV(Digital TV,数字电视)DTV(Dual Threshold Voltage,双重极限电压)DTXS(Decryption Transform for XML Signature,XML签名解密转换)DUN(Dial-Up Networking,拨号网络)DUV(Deep Ultra-Violet,纵深紫外光)DV(Digital Vidicon,数码摄录机)DVB(Digital Video Broadcasting,数字视频广播DVC(Digital Vibrance Control,数字振动控制)DVD(Digital Video/Versatile Disk,数字视频/万能光盘)DVD-R(DVD Recordable,可记录DVD盘)DVD-RAM(Digital Video/Versatile Disk - Random Access Memory,随机存储数字视频/万能光盘)DVD-RW(DVD Rewritable,可重复刻录DVD盘)DVFM(Dynamic Voltage and Frequency Management,动态电压和频率管理)DVI(Digital Video Interface,数字视频接口)DVI(Digital Visual Interface,数字化视像接口)DVMT(Dynamic Video Memory Technology,动态视频内存技术)DWDM(Dense WaveLength Division Multiplex,波长密集型复用技术)DxR(DynamicXTended Resolution,动态可扩展分辨率)DXTC(Direct X Texture Compress,DirectX纹理压缩)Dynamic Z-buffering(动态Z轴缓冲区)E(Economy,经济,或Entry-level,入门级)E3(Electronic Entertainment Expo,电子娱乐展览会)EAP(Extensible Authentication Protocol,扩展证明协议)EAX(Environmental Audio Extensions,环境音效扩展技术)EB(Expansion Bus,扩展总线)EBGA(Enhanced Ball Grid Array,增强形球状网阵排列)EBL(electron beam lithography,电子束平版印刷)EBR(Excess Burst Rate,超额突发速率)EC(Early Childhood,学龄前儿童)EC(Embedded Controller,嵌入式控制器)ECC(Elliptic Curve Crypto,椭圆曲线加密)ECC(Error Checking and Correction,错误检查修正)ECD(Electro Chromic Display,电铬显示器)ECP(Extended Capabilities Port,延长能力端口)ED(Execution driven,执行驱动)EDA(Electronic Design Automatic,电子设计自动化)E-DDC(Enhanced Display Data Channel,增强形视频数据通道协议)EDEC(Early Decode,早期解码)Edge Anti-aliasing(边缘抗锯齿失真)EDO(Enhanced Data-Out RAM,数据增强输出内存)EE(Emotion Engine,情感引擎)E-EDID(Enhanced Extended Identification Data,增强形扩充身份辨识数据)EEPROM(Electrically Erasable Programmable ROM,电擦写可编程只读存储器)eFB(embedded Frame Buffer,嵌入式帧缓冲)EFEAL(Extended Field Elliptical Aperture Lens,可扩展扫描椭圆孔镜头)EFF(Electronic Frontier Foundation(电子前线基金会)EFI(Extensible Firmware Interface,扩展固件接口)EFM(Eight to Fourteen Modulation,8位信号转换为14位信号)EFU(Elemntary Functional Unit,增强功能单元)EHCI(Enhanced Host Controller Interface,加强型主机端控制接口)EHSDRAM(Enhanced High Speed DRAM,增强型超高速内存)EIDE(enhanced Integrated Drive Electronics,增强形电子集成驱动器)EISA(Enhanced Industry Standard Architecture,增强形工业标准架构)EL DDR(Enhanced Latency DDR,增强反应周期DDR内存)Embedded Chips(嵌入式)EMBM(environment mapped bump mapping,环境凹凸映射)Embosing(浮雕)EMC(Electron Magnetic Compatibility,电磁兼容)EMF(Electron Magnetic Field,电磁场)EMI(Electromagnetic Interference,电磁干扰)EMP(Emergency Management Port,紧急事件管理端口)EMS(Enhanced Memory System,增强内存系统)EMS(Enhanced Message Service,扩展型信息服务)EMS(Expanded Memory Specification,扩充内存规格)EOL(End of Life,最终完成产品)EOS(eBookMan Operating System,电子书操作系统)EPA(edge pin array,边缘针脚阵列)EPA(Environmental Protection Agency,美国环境保护局)EPF(Embedded Processor Forum,嵌入式处理器论坛)EPIC(explicitly parallel instruction code,并行指令代码)EPL(electron projection lithography,电子发射平版印刷)EPM(Enhanced Power Management,增强形能源管理)EPM(enterprise project manage)EPOC(Electronic Piece of Cheese,小型电子块)EPOC(Elevated Package Over CSP,CSP架空封装)EPP(Enhanced Parallel Port,增强形平行接口)EPROM(erasable,programmable ROM,可擦写可编程ROM)EPV(Extended Voltage Protection,扩展电压保护)ERD(Emergency Repair Disk,应急修理磁盘)ERP(Enterprise Requirement Planning,企业需求计划)ERP(Enterprise Resource Planning,企业资源计划)ERP(estimated retail price,估计零售价)ES(Energy Star,能源之星)ES(Engineering Sample,工程样品)eSATA(External Serial ATA,扩展型串行ATA)ESCD(Extended System Configuration Data,可扩展系统配置数据)ESD(electro-static discharge,静电释放)ESDJ(Easy Setting Dual Jumper,简化CPU双重跳线法)ESDRAM(Enhanced SDRAM,增强型SDRAM)ESER(EAC Secure Extract Ripping,EAC安全抓取复制)ESP(Electronic-Shock Protection,电子抗震系统)ESP(Embedded System Platform,嵌入式系统平台)ESP(Encapsulating Security Payload,压缩安全有效载荷)ESR(Equivalent Series Resistance,等价系列电阻)ESRAM(Enhanced SRAM,增强型SRAM)eTM(embedded Texture Buffer,嵌入式纹理缓冲)ETRI(Electronics and Telecommunications Research Institute,电子和电信研究协会)EULA(End-User License Agreement,最终用户释放协议)EUV(Extreme Ultra Violet,紫外光)EUV(extreme ultraviolet lithography,极端紫外平版印刷)EVF(Electronic Viewfinder,电子取景窗)E-WDM(Enhanced Windows Driver Model,增强型视窗驱动程序模块)Execute Buffers(执行缓冲区)Extended Burst Transactions(增强式突发处理)Extended Stereo(扩展式立体声)Factor Alpha Blending(因子阿尔法混合)FADD(Floationg Point Addition,浮点加)FAQ(Frequently Asked Questions,常见问题回答)Fast Z-clear(快速Z缓冲清除)FAT(File Allocation Tables,文件分配表)FB(fragment buffer,片段缓冲)FBC(Frame Buffer Cache,帧缓冲缓存)FBGA(Fine-Pitch Ball Grid Array,精细倾斜球状网阵排列)FBGA(flipchip BGA,轻型芯片BGA)F-Buffer(Fragment Stream FIFO Buffer,片段流先入先出缓冲区)FC(Famicom,任天堂8位游戏机)FC(Fibre Channel,光纤通道)FC-BGA(Flip-Chip Ball Grid Array,反转芯片球形栅格阵列)FCC(Federal Communications Commission,联邦通信委员会)FC-PGA(Flip-Chip Pin Grid Array,反转芯片针脚栅格阵列)FCRAM(Fast Cycle RAM,快周期随机存储器)FDB(Fluid Dynamic Bearing,非固定动态轴承)FDB(fluid-dynamic bearings,动态轴承)FDBM(Fluid dynamic bearing motors,液态轴承马达)FDC(Floppy Disk Controller,软盘驱动器控制装置)FDD(Floppy Disk Driver,软盘驱动器)FDIV(Floationg Point Divide,浮点除)FDM(Frequency Division Multi,频率分离)FED(Field Emission Displays,电场显示器)FEMMA(Foldable Electronic Memory Module Assembly,折叠电子内存模块装配)FEMMS(Fast Entry/Exit Multimedia State,快速进入/退出多媒体状态FFB(Force Feed Back,力反馈)FFJ(Force Feedback Joystick,力量反馈式操纵杆)FFT(fast Fourier transform,快速热欧姆转换)FGM(Fine-Grained Multithreading,高级多线程)FID(FID(Frequency identify,频率鉴别号码)FIFO(First Input First Output,先入先出队列)FIR(finite impulse response,有限推进响应)FireWire(火线,即IEEE1394标准)FISC(Fast Instruction Set Computer,快速指令集计算机)FL(fragment list,片段列表)FL(Function Lookup,功能查找)Flat(平面描影)FlexATX(Flexibility ATX,可扩展性ATX)flip double buffered(反转双缓存)flip-chip(芯片反转)FLIR(Forward Looking Infra-Red,前视红外)FLOPs(Floating Point Operations Per Second,浮点操作/秒)Flow-control(流控制)FLS(Front Light Screen,前发光屏幕)Flyback Transformer(回转变压器)FM(Flash Memory,快闪存储器)FM(Frequency Modulation,频率调制)FMA(full-motion animated backdrops)FMAC(Floating-Point Multiply-Accumulators,浮点累积乘单元)FMC(Frictionless Memory Control,无阻内存控制)FMD ROM(Fluorescent Material Read Only Memory,荧光质只读存储器)FMT(fine-grained multithreading,纯消除多线程)FMUL(Floationg Point Multiplication,浮点乘)Fog table quality(雾化表画质)Fog(雾化效果)FPD(flat panel display,平面显示器)FPM(Fast Page Mode,快页模式内存)FPRs(floating-point registers,浮点寄存器)FPS(First Person Shooters,第一人称射击游戏)FPS(FourPointSurround,创新的四点环绕扬声器系统)fps(frames per second,帧/秒)FPU(Float Point Unit,浮点运算单元)FR(Frames Rate,游戏运行帧数)FR(Frequence Response,频率响应)Frames rate is King(帧数为王)FRC(Frame Rate Control,帧比率控制)FRICC(Federal Research Internet Coordinating Committee,联邦调查因特网协调委员会)FRJS(Fully Random Jittered Super-Sampling,完全随机移动式超级采样)Front Buffer(前置缓冲)FSAA(Full Scene/Screen Anti-aliasing,全景/屏幕抗锯齿)FSB(Front Side Bus,前端总线)FSE(Frequency Shifter Effect,频率转换效果)FSR(force sensor resistance,动力感应电阻)FSTN(Film compensated Super Twisted liquid crystal,带补偿膜超扭曲相列)FSUB(Floationg Point Subtraction,浮点减)FTC(Federal Trade Commission,联邦商业委员会)FTG(Fighting Game,格斗类游戏)FTP(File Transfer Protocol,文件传输协议)Fur(软毛效果)FW(Fast Write,快写,AGP总线的特殊功能)FWH(Firmware Hub,固件中心)GART(Graphic Address Remappng Table,图形地址重绘表)GB(Game Boy,任天堂4位手提游戏机)GB(Garibaldi架构,Garibaldi基于ATX架构,但是也能够使用WTX构架的机箱)GBA(Game Boy Advanced,任天堂增强型手提游戏机)GBC(Game Boy Color,任天堂手提16色游戏机)GBL(GameBoy Light,GB夜光型)GBP(GameBoy Pocket,GB口袋型)GDC(Game Developer Conference,游戏发展商会议)GDI(Graphics Device Interface,图形设备接口)GFD(Gold finger Device,金手指超频设备)GG(Game Gear,世嘉彩色手提游戏机)GHC(Global History Counter,通用历史计数器)Ghost((General Hardware Oriented System Transfer,全面硬件导向系统转移)GI(Global Illumination,球形光照)GIC(Gold Immersion Coating,化金涂布技术)GIF(Graphics Interchange Format,图像交换格式)GIF(Graphics Interface unit,图形接口单元)GLV(grating-light-valve,光栅亮度阀)GM(General Midi,普通MIDI)GM(Glass Mould,玻璃铸制)GMCH(Graphics & Memory Controller Hub,图形和内存控制中心)GMR(giant magnetoresistive,巨型磁阻)Gouraud Shading,高洛德描影,也称为内插法均匀涂色GPA(Graphics Performance Accelerator,图形性能加速卡)GPF(General protect fault,一般保护性错误)GPIs(General Purpose Inputs,普通操作输入)GPL(GNU Public License,GNU公众授权)GPRS(General Packet Raice,整合封包无线服务)GPRs(General Purpose Registers,通用寄存器)GPS(Global Positioning System,全球定位系统)GPT(Graphics Performance Toolkit,图形性能工具包)GPU(Graphics Processing Unit,图形处理器)GS(Graphic Synthesizer,图形合成器)GSM(Galvanization Superconductive Material,电镀锌超导材料)GTF(General Timing Formula,普通调速方程式)GTL(Gunning Transceiver Logic,发射接收逻辑电路)GTS(Giga Textel Sharder,十亿像素填充率)Guard Band Support(支持保护带)GUI(Graphics User Interface,图形用户界面)GVPP(Generic Visual Perception Processor,常规视觉处理器)GWS(graphics workstations,图形工作站)HAL(Hardware Abstraction Layer,硬件抽像化层)HCF(Host Controller,主体控制处理)HCI(Host Controller Interface,主机控制接口HCL(Hardware Compatibility List,硬件兼容性列表)HCRP(Hardcopy Cable Replacement Profile,硬复制电缆复位协议子集)HCT(Hardware Compatibility Test,硬件兼容性测试HDA(Head Disk Assembly,头盘组件)HDA(high-efficiency Audax High Definition Aerogel,高效高清楚气动)HDIT(High Bandwidth Differential Interconnect Technology,高带宽微分互连技术)HDMI(High Definition Multimedia Interface,高精度多媒体接口)HDR(High Dynamic Range,高级动态范围)HDRL(high dynamic-range lighting,高动态范围光线)HDSL(High bit rate DSL,高比特率数字订阅线路)HDSS(Holographic Data Storage System,全息数据存储系统)HDTV(high definition television,高清晰度电视)HDVP(High-Definition Video Processor,高精度视频处理器)HE(Home Edition,家庭版)HEL(Hardware Emulation Layer(硬件模拟层)HID(Human Interface Device,人机对话接口设备)Hierarchical Z(Z分级)HiFD(high-capacity floppy disk,高容量软盘)Hi-fi(high fidelity,高精度设备)high triangle count(复杂三角形计数)HLL(high level language,高级语言)HLLCA(High-Level Language Computing Architecture,高级语言计算架构)HL-PBGA(表面黏著,高耐热、轻薄型塑胶球状网阵封装HLSL(High Level Shading Language,高级描影语言)HMC(hardware motion compensation,硬件运动补偿)HMC(holographic media card,全息媒体卡)HMD(holographic media disk,全息媒体磁盘)Home PNA(Home Private Network Adapter,家庭私人网络适配器)HOS(Higher-Order Surfaces,高次序表面)HPC(Hand held PC,手持电脑设备)HPDR(High-Precision Dynamic-Range,高精度动态范围)HPF(High-Pass Filter,高通滤波器)HPNA(home phoneline networking,家庭电话线网络)HPS(High Performance Server,高性能服务器)HPTC(high performance technical computing,高性能技术运算)HPW(High Performance Workstation,高性能工作站)HRAA(High Resolution Anti-aliasing,高分辨率抗锯齿)HRTF(Head Related Transfer Function,头部关联传输功能)。
音响设备术语中英对照
AGC:Automati Gain Control自动增益控制AHU:Air Handling Unit 空气处理机组A-I:Auto-iris自动光圈AIS:Alarm Indication Signal 告警指示信号AITS:Acknowledged Information Transfer Service确认操作ALC:Automati Level Control 自动平衡控制ALS:Alarm Seconds 告警秒ALU:Analogue Lines Unit 模拟用户线单元AM:Administration Module管理模块AN:Access Network 接入网A:Actuator 执行器A:Amplifier 放大器A:Attendance员工考勤A:Attenuation衰减AA:Antenna amplifier 开线放大器AA:Architectural Acoustics建筑声学AC:Analogue Controller 模拟控制器ACD:Automatic Call Distribution 自动分配话务ACS:Access Control System出入控制系统AD:Addressable Detector地址探测器ADM:Add/Drop Multiplexer分插复用器ADPCM:Adaptive Differential ulse Code Modulation 自适应差分脉冲编码调制AF:Acoustic Feedback 声反馈AFR:Amplitude /Frequency Response 幅频响应ANSI:American National Standards Institute美国国家标准学会APS:Automatic Protectiontching 自动保护倒换ASC:Automati Slope Control 自动斜率控制ATH:Analogue Trunk Unit 模拟中继单元ATM:Asynchrous Transfer Mode 异步传送方式AU- PPJE:AU Pointer Positive Justification 管理单元正指针调整AU:Administration Unit 管理单元AU-AIS:Administrative Unit Alarm Indication SignalAU告警指示信号AUG:Administration Unit Group 管理单元组AU-LOP:Loss of Administrative Unit Pointer AU指针丢失AU-NPJE:AU Pointer Negative Justification管理单元负指针调整AUP:Administration Unit Pointer管理单元指针A VCD:Auchio &Video Control Device 音像控制装置AWG:American Wire Gauge美国线缆规格BA:Bridge Amplifier桥接放大器TOPBAC:Building Automation & Control net建筑物自动化和控制网络BAM:Background Administration Module后管理模块BBER:Background Block Error Ratio背景块误码比BCC:B-channel Connect ControlB通路连接控制BD:Building DistributorBEF:Buiding Entrance Facilities 建筑物入口设施BFOC:Bayonet Fibre Optic Connector大口式光纤连接器BGN:Background Noise背景噪声BGS: Background Sound 背景音响BIP-N:Bit Interleaved Parity N code 比特间插奇偶校验N位码B-ISDN:Brand band ISDN 宽带综合业务数字网B-ISDN:Broad band -Integrated Services Digital Network 宽带综合业务数字网BMC:Burst Mode Controller 突发模式控制器BMS:Building Management System 智能建筑管理系统BRI:Basic Rate ISDN 基本速率的综合业务数字网BS:Base Station基站BSC:Base Station Controller基站控制器BUL:Back up lighting备用照明C/S: Client/Server客户机/服务器TOPC:Combines 混合器C:Container 容器CA:Call Accounting电话自动计费系统CA TV:Cable Television 有线电视CC:Call Control 呼叫控制CC:Coax cable 同轴电缆CCD:Charge coupled devices 电荷耦合器件CCF:Cluster Contril Function 簇控制功能CD:Campus Distributor 建筑群配线架CD:Combination detector 感温,感烟复合探测器CDCA:Continuous Dynamic Channel Assign 连续的动态信道分配CDDI:Copper Distributed Data 合同缆分布式数据接口CDES:Carbon dioxide extinguisbing system 二氧化碳系统CDMA:Code Division Multiplex Access 码分多址CF:Core Function 核心功能CFM:Compounded Frequency Modulation 压扩调频繁CIS:Call Information System 呼叫信息系统CISPR:Internation Special Conmittee On Radio Interference 国际无线电干扰专门委员会CLNP:Connectionless Network Protocol 无连接模式网络层协议CLP:Cell Loss Priority信元丢失优先权CM:Communication Module 通信模块CM:Configuration Management 配置管理CM:Cross-connect Matrix交叉连接矩阵CMI:Coded Mark Inversion传号反转码CMISE:Common Management Information Service公用管理信息协议服务单元CPE:Convergence protocol entity 会聚协议实体CR/E:card reader /Encoder (Ticket reader )卡读写器/编码器CRC:Cyclic Redundancy Check 循环冗佘校验CRT:Cathode Ray Tabe 显示器,监视器,阴极射线管CS: Convergence service 会聚服务CS:Cableron Spectrum 旧纳档块化技术CS:Ceiling Screen 挡烟垂壁CS:Convergence Sublayer合聚子层CSC:Combined Speaker Cabinet 组合音响CSCW:Computer supported collaborative work 计算机支持的协同工作CSES:Continuius Severely Errored Second 连续严重误码秒CSF:Cell Site Function 单基站功能控制CTB:Composite Triple Beat 复合三价差拍CTD:Cable Thermal Detector 缆式线型感温探测器CTNR:carrier to noise ratio 载波比CW:Control Word 控制字D:Directional 指向性TOPD:Distortion 失真度D:Distributive 分布式DA:Distribution Amplifier 分配的大器DBA:Database Administrator数据库管理者DBCSN:Database Control System Nucleus数据库控制系统核心DBOS:Database Organizing System 数据库组织系统DBSS:Database Security System 数据库安全系统DC:Door Contacts大门传感器DCC:Digital Communication Channel数字通信通路DCN:Data Communication Network 数据通信网DCP-I:Distributed Control Panel -Intelligent智能型分散控制器DCS:Distributed Control System集散型控制系统DDN:Digital Data Network 数字数据网DDS:Direct Dignital Controller直接数字控制器DDW:Data Describing Word 数据描述字DECT:Digital Enhanced Cordless Telecommunication增强数字无绳通讯DFB:Distributed Feedback 分布反馈DID:Direct Inward Dialing 直接中继方式,呼入直拨到分机用户DLC:Data Link Control Layer 数据链路层DLI:DECT Line InterfaceDODI:Direct Outward Dialing One 一次拨号音DPH:DECT PhoneDRC:Directional Response Cahracteristics 指向性响应DS:Direct Sound 直正声DSP:Digital signal Processing 数字信号处理DSS:Deiision Support System 决策支持系统DTMF:Dual Tone Multi-Frequency 双音多频DTS:Dual -Technology Sensor 双鉴传感器DWDM:Dense Wave-length Division Multiplexing 密集波分复用DXC:Digital Cross-Connect 数字交叉连接E:Emergency lighting照明设备TOPE:Equalizer 均衡器E:Expander 扩展器EA-DFB:Electricity Absorb-Distributed Feedback 电吸收分布反馈ECC:Embedded Control Channel 嵌入或控制通道EDFA:Erbium-Doped Fiber Amplifier掺饵光纤放大器EDI:Electronic Data Interexchange 电子数据交换EIC:Electrical Impedance Characteristics 电阻抗特性EMC:Electro Magnetic Compatibiloty 电磁兼容性EMI:Electro Magnetic Interference 电磁干扰EMS:Electromagnetic Sensitibility 电磁敏感性EN:Equivalent Noise 等效噪声EP:Emergency Power 应急电源ES:Emergency Sooket 应急插座ES:Evacuation Sigvial疏散照明ESA:Error SecondA 误码秒类型AESB:ErrorSecondB 误码秒类型BESD:Electrostatic Discharge静电放电ESR:Errored Second Ratio 误码秒比率ETDM:Electrical Time Division Multiplexing电时分复用ETSI:European Telecommunication Standards Institute欧洲电信标准协会F:Filter 滤波器TOPFAB:Fire Alarm Bell 火警警铃FACU:Fire Alarm Contrlol Unit 火灾自动报警控制装置FC:Failure Count 失效次数FC:Frequency Converter 频率变换器FCC:Fire Alarm System 火灾报警系统FCS:Field Control System 现场总线FCU:Favn Coil Unit风机盘管FD:Fire Door 防火门FD:Flame Detector 火焰探测器FD:Floor DistributorFD:Frequency Dirsder 分频器FDD:Frequency Division Dual 频分双工FDDI:Fiberdistributed Data Interface光纤缆分布式数据接口。
CTC Union 产品指南说明书
w w w.c t c u.c omISO 9001ISO 14001RoHSC o m p l i a n c eTelecom Ethernet▪ Web SmartView EMS ▪ L2+ 10G Switch ▪ 10G NID ▪ Protocol Gateway ▪ Multi-Service Platform ▪ 10G Aggregation Switch PlatformProduct Guidew w w.c t c u.c o mAs a socially responsible manufacturer, CTC Union is concerned with the environment and has taken active measures to reduce carbon emissions and eliminate hazardous materials in their products. None of CTC Union products use chlorofluorocarbons (CFC) in their production process and since 2007 all electronics use non-lead soldering according to RoHS and WEEE directives.SustainableBusinessOur AdvantagesGreen Care• Core TechnologiesIn-House hardware, software and mechanical design• Customer SupportProfessional pre/post sales technical support, 24/7 e-platform services• Quality Assurance ISO 9001, ISO-14001, CE, FCC and UL• Green CareWEEE and RoHS 2.0 Manufacturing Compliance• In-band Management • 10G Ethernet • Rugged Design• EMS• Multi-Service Platform • OAMCTC Union Technologies, founded in 1993, is an ISO9001/14001certified designer and manufacturer. CTC Union’s software development system follows the cybersecurity IEC62443 regulations for the design of Industrial & Telecom networking products. With their own in-house R&D and factory, CTC Union develops and manufactures high-quality products in Taiwan. CTC Union offers a full spectrum of products, including Industrial Ethernet, PoE, EN50155 and E-mark certified switches. CTC Union’s goal isto provide reliable, temperature resistant and rugged designs for mission critical systems used in harsh environments. With more than 30 years of experience in design of Telecom products, CTC Union is highly motivated to deliver various access switches and FTTP CPE products.Since 1993AboutCTC UnionC ommunication ex T ensionC onversion01SmartView TM WEB EMS .......................................................................................................01 02L2+ Ethernet Switch ..............................................................................................................02Carrier Ethernet Switch & NID/EDD ................................................................................02Access Switch ............................................................................................................03CPE Switch ............................................................................................................................04PoE S witch .. (04)04PoE Series ................................................................................................................................05 05Multi-Service Platform – FRM220.....................................................................................0606Ethernet Aggregation Switch Platform – FRM220A .......................................................08 07Serial Connectivity ................................................................................................................09 Serial Device Server .............................................................................................................09Protocol Gateway .. (09)08Media Converter Rack .........................................................................................................10 09WDM Multiplexer & LAN Extender (10)PageFRM220(A)Ethernet Switch CPE SwitchFRM220(A)Standalone Type Industrial Industrial Rackmount SwitchSmartView TM WEB EMSWeb ServerFunctions▪Web-based User Interface▪Remote Access and Centralized Device Management ▪Real-time visual representations & processing of alarms ▪Long term event storage (up to 1 year)Specifications & design are subject to change without prior notice. Please visit CTC Union website for more details. //**************32023 V 1.0CTC Union access switch series offer 10 ~ 32 fiber/UTP ports density option including 1Gbps Ethernet downlink speed and 1G or 10Gbps speed for uplink ports. They are suitable for the intranet network deployment of enterprise or treated as MDU(Multiple Dwelling Unit) deployment to provision internet service by ISP. This switch family supports complete L2 feature sets such as VLAN, QoS, IGMP multicast as well as robust security management to facilitate service provider’s build out of a secured and manageable Ethernet access network.Access SwitchTelecom Product Guide CTC Union’s CPE switch family mainly focuses on the P2P active Ethernet technology based FTTX market with overall port density from 6 to 10 ports Gigabit UTP/Fiber. Their design concept is well considered from the basis of stylish and elegant appearance for the residential user as well as the advantage of easy installation for the FTTH service provider. The whole CPE switch family adopts evolutionary cable tray structural design to help the installer more easily and protectively manage the excess fiber within the unit. Also, the CPE switch supports completely L2 feature sets and highly preferred zero touch provision (ZTP) function which is suitable for the verylarge scale deployment to avoid truck rolls and save OPEX for FTTH service providers or operators.CPE SwitchCTC Union's PoE switch series includes 8 ports and 24 ports density for small and medium network environment for deployment in office applications such as PoE powered IP telephony, WiFi access and IP surveillance. They support IEEE 802.3at/af PoE standard up to 30W per port and maximum 100m transmission distance. These PoE switch models support completely L2 management feature sets as wellas advanced PoE management functions to boost your network with optimal performance, efficiency and PoE power consumption.PoE SwitchSpecifications & design are subject to change without prior notice. Please visit CTC Union website for more details./**************/42023 V1.0Splits power and data from PoE InputComplies with IEEE 802.3af/atProvides 1 10/100/1000Mbps pass through data rate Conversion between 10/100Base-TX to 100Base-FX Conversion between 10/100/1000Base-T andSpecifications & design are subject to change without prior notice. Please visit CTC Union website for more details.FRM220-CH20 (2U 19” 20 Slots)NMC (1st slot)NMC (1st slot)Alarm RelayCooling Fan (Hot swappable)Cooling Fan (Hot swappable)Alarm RelayRedundant PowerMain FeaturesModule Cards for Deployment ScenariosThe FRM220-CH20, FRM220-CH08 and FRM220-CH04A have been designed as a Multi-service platform. This allows CWDM & DWDMCCF, Datacom, VoiceMux / DeMuxOptical Protection Switch (1+1 & 1:1 Optical Protection)● Contact Closure over Fiber ● RS232 / 485 over Fiber● V35 / X.21 / RS530 over FiberDS3 / E3 over Fiber 4 / 8 / 16 Inverse Mux ●4x FXO over Fiber ●4x FXS over Fiber ●FXO / FXS over FiberSingle Channel EDFA Booster & PreAmpa l T r a n s p o ra t a c o m a co m S o l u t i o n s/PD H /V i on sMulti-Service Platform – FRM220Specifications & design are subject to change without prior notice. Please visit CTC Union website for more details. //**************72023 V 1.0NMC• FRM220-NMC-R3Network Management ControllerTransponder• FRM220-100GE-2Q 100GE QSFP28 to QSFP28 3R Transponder • FRM220-40G-2Q 40G QSFP+ to QSFP+ 3R Transponder • FRM220-40G-1Q4S 40G QSFP+ to 4x 10G SFP+ Transponder• FRM220-16G-3R 16G 3R Multi-rate Transponder with Optical Line Protection • FRM220-10G-3R 10G 3R Multi-rate Transponder with Optical Line Protection • FRM220-4G-3R 4G 3R Multi-rate Transponder with Optical Line Protection • FRM220-4G-3S 4G 2R Multi-rate Transponder with Optical Line Protection • FRM220-4G-2S 4G 2R Multi-rate Transponder • FRM220-1000DS1G 2R MultI-rate Transponder Muxponder• FRM220-TM-10GMux7x GE to 10Gbps Muxponder EDFA• FRM220-OAP10Single Channel EDFA Preamp 10dB • FRM220-OAP17Single Channel EDFA Preamp 17dB • FRM220-OAB15Single Channel EDFA Booster 15dB • FRM220-OAB21A Single Channel EDFA Booster 21dB • FRM220-OAB21Single Channel EDFA Booster with AGC Optical Protection Switch• FRM220-OPS511:1 Single-mode Fiber Optical Protection Switch • FRM220-OPS521+1 Single-mode Fiber Optical Protection Switch • FRM220-OPS51M1:1 Multi-mode Optical Protection Switch WDM Optical Multiplexer• FRM220-DWMD DWDM Mux/DeMUX • FRM220-CWMDCWDM Mux/DeMUXEthernet Switch• FRM220A-2000EAS/4F 4x 100/1000Base-X SFP OAM/IP GbE Managed Switch• FRM220A-2000EAS/22x 100/1000Base-T + 2x 100/1000Base-X SFP OAM/IP GbE Managed Switch • FRM220A-2000EAS/1100/1000Base-T + 100/1000Base-X SFP OAM/IP GbE Managed Switch• FRM220-2000MS 100/1000Base–T to 100/1000Base–X SFP Web Smart In-Band OAM Managed GbE Switch • FRM220A-1002ES2x 100/1000Base-T + 2x 100/1000Base-X SFP GbE SwitchEthernet Media Converter• FRM220-10/100i In-Band Managed FE Media Converter, 100Base-TX to 100Base-FX• FRM220-10/100iS-2In-Band Managed FE \Media Converter, Dual Channel 10/100Base-TX to 100Base-X SFP • FRM220-1000TS Managed GbE Media Converter , 1000Base-TX to 1000Base-X SFP • FRM220-10/100Non-managed FE Media Converter , 100Base-TX to 100Base-FX• FRM220-10GCM10G Base-T to 10G Base-R SFP +(Contact Closure Fiber Converter)• FRM220-CCF202ch Contact Closure Fiber Converter, In-Band Managed • FRM220-CCF404ch Contact Closure Fiber Converter, In-Band Managed Voice over Fiber• FRM220-FXO/FXS FXO/FXS over Fiber In-Band Managed Converter • FRM220-FXO-44x FXO over Fiber In-Band Managed Converter • FRM220-FXS-44x FXS over Fiber In-Band Managed ConverterFRM220 Slide-in CardsStandaone ChassisTelecom Product GuideFRM220A-2000EAS/4F4x 100/1000Base-X SFP OAM/IP GbE managed switchFRM220A-2000EAS/22x 100/1000Base-T + 2x 100/1000Base-X SFP OAM/IP GbE managed switchFRM220A-2000EAS/1100/1000Base-T + 100/1000Base-X SFP OAM/IP GbE managed switch10G/1G Uplink Ethernet Aggregation Switch CardFRM220A-GSW/SNMP-10G10G uplink Ethernet Aggregation Switch Card withIn-Band ManagementGigabit uplink Ethernet Aggregation Switch Card withIn-Band ManagementFRM220A-GSW/SNMP-1G• Provides chassis aggregation via 4x1G/10Gigabit Base-X SFP/SFP+ plus 4x10/100/1000Base-T uplink ports• Supports IEEE 802.1p HW based 8 priority queues and L2~L4 QoS functions• Supports IPv6 management• Provides Web (https), Telnet, SSHv2, SNMP(V1, V2c, V3) management interfaces• Supports secure authentication by IEEE802.1x, RADIUS or TACACS+• Supports IEEE802.1D/802.1w/802.1s for ring protection on all interfaces• Supports IEEE 802.1Q tagged VLAN and IEEE 802.1ad Q-in-Q applicationFRM220A Switch CardsApplicationRingRecovery Time1-2 seconds (min.)FRM220A-CH20FRM220A-CH20FRM220A-CH20FRM220A-CH20■ Enabling IP Transportation Protection Mechanism- STP/RSTP Featured Ring Protection▪Standard based but advanced fault protection systems▪Rapidly recovery path from failed connection (1-2 seconds min. recovery time)Ethernet Aggregation Switch Platform – FRM220AThe FRM220A series is an Ethernet based aggregation platform, which incorporates a 24+4 port L2 Gigabit Ethernet switch (FRM220AGSW/SNMP(n) or a 20+4 port L2 Gigabit Ethernet switch with 4x10Gigabit uplink (FRM220A-GSW/ SNMP-10G). The FRM220A has a built-in Gigabit Ethernet backplane to interconnect the Ethernet access with the FRM220-GSW/SNMP card. The L2 switch card supports many advanced Layer 2 switch technologies including port and tag based VLAN, QoS, LACP, RSTP to name just a few. The FRM220A chassis solution significantly lowers the OPEX for operator and service provider when deploying fiber access networksSpecifications & design are subject to change without prior notice. Please visit CTC Union website for more details./**************/82023 V1.0STE400A-232STE800A-232 10/100TX18 ports Gigabit Media Converter Rack ─ FMC-18001U 19” 18 channels Managed Media Converter Rack▪Local configuration via USB port WDM Multiplexer LAN Extender Full native mode performancePassive model requires no powerProtocol transparent, no limitationUtilizes industry standard ITU CWDM OPC-1500/1400/1300LX1008/4 Ch. Dual Fiber CWDM Mux/Demux10/100 Base-TX LAN Extender CWDM-80/40The FMC-CH17 is a 2U high 19” 17 slots chassis and the FMC-CH08 is a 2U high 10” 8 slots cassis. The FMC chassis provides an economic solution in low density fiber converter installations where no management features are required. Each FMC converter is an independent Ethernet to fiber or Ethernet to copper media converter that may be used as a standalone converter or placed in the FMC-Copyright 2023 CTC UNION TECHNOLOGIES CO., LTD.2023。
LM2950 1 100mA 低掉电电压调节器商品说明书
FEATURES● High accuracy output voltage ● Guaranteed 100 mA output ● Very low quiescent current● Extremely tight load and line regulation ● Very low temperature coefficient ● Current and thermal limiting ● Low dropout voltage ● Need only 1uF for stability ● Error flag warns of output dropout Pin 1 : Output ● Logi-control electronic shutdown Pin 2 : Ground ● Output programmable from 1.24 to 29V Pin 3 : Input● Moisture Sensitivity Level 3ApplicationsORDERING INFORMATION● High-efficiency linear regulator, voltage reference ● Battery powered systems ● Portable consumer equipment● Portable / Parm, Desktop / Notebook computers ● Portable Instrumentation, cordless telephones (XX= 1.5, 1.8, 2.8, 2.85, 3.0, 3.3, 5.0V,● Automotive Electronics, Radio control systems Adjustable)● SMPS Post-Regulator, AvionicsDESCRIPTIONThe LM2950/1 is a low power voltage regulator. This device excellent choice for use in battery powered application such as cordless telephone, radio control systems, and portable computers. The LM2950/1 features very low quiescent current (75㎂ Typ.) and very low drop output voltage (Typ. 400㎷ at light load and 380㎷ at 100㎃).This includes a tight initial tolerance of 0.5% Typ., extremely good load and line regulation of 0.05% Typ., and very low output temperature coefficient, making the LM2950/1 useful as a low-power voltage reference.The error flag output feature is used as power-on reset for warn of a low output voltage, due to following batteries on input. Other feature is the logic-compatible shutdown input which enable the regulator to be switched on and off. The LM2950/1 is available in 8-pin plastic packages.The regulator output voltage may be pin-strapped for a -XX volt or programmed from 1.24 volt to 29 volts with external pair of resistors. The LM2950/1 is offered in 3-pin to-92 package compatible with other fixed regulator.Dec. 2015 - Rev. 1.3HTCLM2950TA-XX LM2950-XX DEVICE SOP-8TO-92 (Tape)TO-92 (Bulk)PKGLM2951D-XX TO- 92 PKG SOP- 8 PKGPin : 1. Output 2. Sense 3. Shutdown 4. Ground 5. Error 6. Tap7. Feedback 8. Input1 2 3BLOCK DIAGRAM AND TYPICAL APPLICATIONS (LM2950)BLOCK DIAGRAM AND TYPICAL APPLICATIONS (LM2951)ABSOLUTE MAXIMUM RATINGSLead Temperature (Soldering, 5 seconds)Storage Temperature RangeOperating Junction Temperature Range Input Supply Voltage Feedback Input Voltage Shutdown Input Voltage Error Comparator OutputDec. 2015 - Rev. 1.3HTC-55℃ to +150℃-65℃ to +150℃260℃INTERNALLY LIMITED-0.3 to +30V-0.3 to +30V -1.5 to +30V -0.3 to +30V POWER DISSIPATIONELECTRICAL CHARACTERISTICS (at T a =25℃, V IN =15V, unles otherwise specified)Dec. 2015 - Rev. 1.3HTCNote 1 : Output or reference voltage temperature coefficients defined as the worst case voltage change divided by the total temperature range.Note 2 : Unless otherwise specified all limits guaranteed for T J = 25℃, V IN = V0+1V, I L = 100㎂ and C L = 1㎌. Additional condition for the 8-pin versions are feedback tied to -XX V tap and output tied to output Sense (V OUT=XX V) and V SHOUTDOWN≤0.8VNote 3 : Regulations is measured at constant junction temperature, using pulse testing with a low duty cycle. Changes in output voltage due to heating effects are covered under the specification for thermal regulation.Note 4 : Dropout voltage is defined as the input to output differential at which the output voltage drops 100 ㎷ below its nominal value measured at 1V differential. At very low values of programmed output voltage, the minimum input supply voltage(2.3V over temperature)must be taken into account.Note 5 : V REF≤V OUT≤(V IN-1V), 2.3V≤V IN≤30V, 100㎂≤I L≤100㎃, T J≤T JMAXNote 6 : Comparator thresholds are expressed in terms of a voltage differential at the feedback terminal below the nominal reference voltage measured at V OUT+1V input. To express these thresholds in terms of output voltage changed,multiply by the error amplifier gain = V OUT/V REF= (R1+R2)/R2. For example, at a programmed output voltage of 5V, the error output is guaranteed to go low when the output drops by 95 ㎷ x 5V / 1.235V = 384 ㎷. Thresholds remain constant as a percent V OUT as V OUT is varied, with the dropout warning occurring at typically 5% below nominal, 7.5% guaranteed.Note 7 : V SHUTDOWN≥2V, V IN≤30V, V OUT=0, Feed-back pin tied to -XX V Tap.Dec. 2015 - Rev. 1.3HTC。
74AHC1G09-Q100 CMOS 2-输入 AND 门 IC 数据手册说明书
1. General descriptionThe 74AHC1G09-Q100 is a high-speed Si-gate CMOS device.The 74AHC1G09-Q100 provides the 2-input AND function with open-drain output.The output of the 74AHC1G09-Q100 is an open drain and can be connected to otheropen-drain outputs to implement active-LOW, wired-OR or active-HIGH wired-ANDfunctions. For digital operation, this device must have a pull-up resistor to establish a logic HIGH level.This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.2. Features and benefits⏹Automotive product qualification in accordance with AEC-Q100 (Grade 1)◆Specified from -40︒C to +85︒C and from -40︒C to +125︒C ⏹High noise immunity ⏹Low power dissipation⏹SOT353-1 and SOT753 package options ⏹ESD protection:◆MIL-STD-883, method 3015 exceeds 2000 V ◆HBM JESD22-A114F exceeds 2000V◆MM JESD22-A115-A exceeds 200V (C = 200 pF, R = 0 Ω)3. Ordering information74AHC1G09-Q1002-input AND gate with open-drain outputRev. 2 — 16 August 2012Product data sheetTable 1.Ordering informationType numberPackageTemperature range NameDescriptionVersion 74AHC1G09GW-Q100-40 ︒C to +125 ︒C TSSOP5plastic thin shrink small outline package; 5 leads;body width 1.25 mmSOT353-174AHC1G09GV-Q100-40 ︒C to +125 ︒CSC-74Aplastic surface-mounted package; 5 leadsSOT7534. MarkingTable 2.MarkingType number Marking code 74AHC1G09GW-Q100A974AHC1G09GV-Q100A095. Functional diagram6. Pinning information6.1Pinning6.2Pin descriptionTable 3.Pin descriptionSymbol Pin DescriptionB1data input BA2data input AGND3ground (0 V)Y4data output YV CC5supply voltage7. Functional descriptionTable 4.Function table[1]Input OutputA B YL L LL H LH L LH H Z[1]H=HIGH voltage level; L=LOW voltage level; Z = high-impedance OFF-state.8. Limiting valuesTable 5.Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage-0.5+7.0VV I input voltage[1]-0.5+7.0VV O output voltage active mode[1]-0.5+7.0Vhigh-impedance mode[1]-0.5+7.0VI IK input clamping current V I<-0.5V[1]--20mA I OK output clamping current V O<-0.5V[1]-±20mA I O output current V O>-0.5V-25mA I CC supply current-±75mA I GND ground current-±75mA T stg storage temperature-65+150︒CP tot total power dissipation T amb=-40︒C to+125︒C[2]-250mW[1]The input and output voltage ratings may be exceeded if the input and output current ratings are observed.[2]For TSSOP5 and SC-74A packages: above 87.5︒C the value of P tot derates linearly with 4.0mW/K.9. Recommended operating conditionsTable 6.Recommended operating operationsSymbol Parameter Conditions Min Typ Max Unit V CC supply voltage 2.0 5.0 5.5VV I input voltage0- 5.5VV O output voltage active mode0-V CC Vhigh-impedance mode0- 6.0VT amb ambient temperature-40+25+125︒C ∆t/∆V input transition rise and fall rate V CC=3.0V to3.6V--100ns/VV CC=4.5V to5.5V--20ns/V10. Static characteristics11. Dynamic characteristics[1]t pd is the same as t PZL and t PLZ .[2]Typical values are measured at V CC = 3.3 V.Table 7.Static characteristicsVoltages are referenced to GND (ground = 0 V).Symbol Parameter Conditions25 ︒C -40︒C to +85 ︒C -40︒C to +125 ︒C Unit MinTyp MaxMin MaxMin MaxV IHHIGH-level input voltageV CC = 2.0 V 1.5-- 1.5- 1.5-V V CC = 3.0 V 2.1-- 2.1- 2.1-V V CC = 5.5 V3.85-- 3.85- 3.85-V V ILLOW-level input voltageV CC = 2.0 V --0.5-0.5-0.5V V CC = 3.0 V --0.9-0.9-0.9V V CC = 5.5 V-- 1.65- 1.65- 1.65V V OLLOW-level output voltage V I = V IH or V IL I O = 50μA; V CC =2.0 V-00.1-0.1-0.1V I O = 50μA; V CC =3.0 V -00.1-0.1-0.1V I O = 50μA; V CC =4.5 V -00.1-0.1-0.1V I O = 4.0mA; V CC =3.0 V --0.36-0.44-0.55V I O = 8.0mA; V CC =4.5 V--0.36-0.44-0.55V I I input leakage current V I =5.5V or GND; V CC =0V to 5.5V --±0.1-±1.0-±2.0μA I OZ OFF-state output current V I = V IH or V IL ; V O = V CC or GND; V CC =5.5 V--±0.25±2.5±10.0μA I CC supply current V I =V CC or GND; I O = 0 A;V CC =5.5 V -- 1.0-10-20μA C Iinputcapacitance- 1.510-10-10pFTable 8.Dynamic characteristics GND = 0 V; for test circuit see Figure 6.Symbol Parameter Conditions25 ︒C -40︒C to +85 ︒C -40︒C to +125 ︒C Unit MinTyp MaxMinMaxMinMaxt pdpropagation delay A and B to Y;see Figure 5[1]V CC = 3.0 V to 3.6 V [2]C L =15 pF - 4.67.5 1.08.5 1.09.0ns C L =50 pF - 6.511.0 1.512.0 1.512.5ns V CC = 4.5 V to 5.5 V [3]C L =15 pF - 3.2 5.5 1.0 6.5 1.07.0ns C L =50 pF- 4.67.5 1.58.0 1.58.5ns C PDpower dissipation capacitance C L =50pF;f i =1MHz; V I =GND to V CC[4]-5-----pF[3]Typical values are measured at V CC = 5.0 V.[4]C PD is used to determine the dynamic power dissipation (P D inμW).P D=C PD⨯V CC2⨯f i⨯N +(C L⨯V CC2⨯f o)where:f i=input frequency in MHz;f o=output frequency in MHz;C L=output load capacitance in pF;V CC=supply voltage in V;N = number of inputs switching;(C L⨯V CC2⨯f o) = dissipation due to the output if the combination of the pull-up voltage and resistance results in V CC at the output.12. WaveformsTable 9.Measurement pointsInput OutputV M V M V X0.5V CC0.5V CC V OL + 0.3 VTable 10.Test dataInput Load S1V I t r, t f R L C L t PHZ, t PZH t PLZ, t PZL t PLH, t PHL GND to V CC≤ 3.0 ns1000 Ω15 pF GND V CC open GND to V CC≤ 3.0 ns1000 Ω50 pF GND V CC open13. Package outlineTSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1Fig 7.Package outline SOT353-1 (TSSOP5)Plastic surface-mounted package; 5 leads SOT753Fig 8.Package outline SOT753 (SC-74A)14. AbbreviationsTable 11.AbbreviationsAcronym DescriptionCDM Charged Device ModelDUT Device Under TestESD ElectroStatic DischargeHBM Human Body ModelMM Machine ModelMIL Military15. Revision historyTable 12.Revision historyDocument ID Release date Data sheet status Change notice Supersedes74AHC1G09_Q100 v.220120816Product data sheet-74AHC1G09_Q100 v.1 Modifications:•Features list corrected (errata).74AHC1G09_Q100 v.120120807Product data sheet--16. Legal information16.1 Data sheet status[1]Please consult the most recently issued document before initiating or completing a design.[2]The term ‘short data sheet’ is explained in section “Definitions”.[3]The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product statusinformation is available on the Internet at URL .16.2 DefinitionsDraft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give anyrepresentations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia salesoffice. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia andcustomer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product isdeemed to offer functions and qualities beyond those described in the Product data sheet.16.3 DisclaimersLimited warranty and liability — Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes noresponsibility for the content in this document if provided by an information source outside of Nexperia.In no event shall Nexperia be liable for any indirect, incidental,punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia.Right to make changes — Nexperia reserves the right to makechanges to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.Suitability for use in automotive applications — This Nexperiaproduct has been qualified for use in automotiveapplications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of a Nexperia product can reasonably be expectedto result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability forinclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperiaaccepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications andproducts planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.Nexperia does not accept any liability related to any default,damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications andthe products or of the application or use by customer’s third partycustomer(s). Nexperia does not accept any liability in this respect.Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.Terms and conditions of commercial sale — Nexperiaproducts are sold subject to the general terms and conditions of commercial sale, as published at /profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects toapplying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer.Document status[1][2]Product status[3]DefinitionObjective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.Product [short] data sheet Production This document contains the product specification.© Nexperia B.V. 2017. All rights reserved 74AHC1G09_Q100All information provided in this document is subject to legal disclaimers.Product data sheet Rev. 2 — 16 August 2012 11 of 12No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents orother industrial or intellectual property rights.Export control — This document as well as the item(s) described hereinmay be subject to export control regulations. Export might require a priorauthorization from competent authorities.Translations — A non-English (translated) version of a document is forreference only. The English version shall prevail in case of any discrepancybetween the translated and English versions.16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.17. Contact informationFor more information, please visit: For sales office addresses, please send an email to: ***************************18. Contents1 General description. . . . . . . . . . . . . . . . . . . . . . 12 Features and benefits . . . . . . . . . . . . . . . . . . . . 13 Ordering information. . . . . . . . . . . . . . . . . . . . . 14 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 26 Pinning information. . . . . . . . . . . . . . . . . . . . . . 26.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 27 Functional description . . . . . . . . . . . . . . . . . . . 38 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 39 Recommended operating conditions. . . . . . . . 310 Static characteristics. . . . . . . . . . . . . . . . . . . . . 411 Dynamic characteristics . . . . . . . . . . . . . . . . . . 412 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 714 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . 915 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 916 Legal information. . . . . . . . . . . . . . . . . . . . . . . 1016.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 1016.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 1016.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 1117 Contact information. . . . . . . . . . . . . . . . . . . . . 1118 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12© Nexperia B.V. 2017. All rights reserved For more information, please visit: Forsalesofficeaddresses,pleasesendanemailto:*************************** Date of release: 16 August 2012Mouser ElectronicsAuthorized DistributorClick to View Pricing, Inventory, Delivery & Lifecycle Information:N experia:74AHC1G09GV-Q100H74AHC1G09GW-Q100H。
计算机专业术语查询
AC-3(Audio Coding 3,第三代音响编码)
AC97(Audio Codec 97,多媒体数字信号解编码器1997年标准)
ACCP(Applied Computing Platform Providers,应用计算平台提供商)
APU(Audio Processing Unit,音频处理单元)
APX(All Position eXpansion,全方位扩展)
AR(Auto-Resume,自动恢复)
ARC(Anti Reflect Coating,防反射涂层)
ARF(Asynchronous Receive FIFO,异步接收先入先出)
计算机专业术语查询
3C(China Compulsory Certification,中国强制性产品认证制度)
3D(Three Dimensional,三维)
3DCG(3D computer graphics,三维计算机图形)
3DNow!(3D no waiting,无须等待的3D处理)
AGU(Address Generation Units,地址产成单元)
AH(Authentication Header,鉴定文件头)
AHA(Accelerated Hub Architecture,加速中心架构)
AI(Artificial Intelligence,人工智能)
AOL(Alert On LAN,局域网警告)
APC(Advanced Power Control,高级能源控制)
API(Application Programming Interfaces,应用程序接口)
罗姆 bd14210g-evk-001 电流检测放大器 用户手册说明书
Current Sense AmplifierBD14210G-EVK-001BD14210G-EVK-001 is an evaluation board for BD14210G-LA, which is ROHM’s current sense amplifier. This user’s guide explains BD14210G-EVK-001.About BD14210G-LABD14210G-LA is a current sense amplifier. This is the product guarantees long time support in Industrial market. This device operates from a single 2.7V to 5.5V power supply. It has wide common mode voltage range from -0.2V to +26V, outputs analog voltage. The gain is 20 V/V. The matched gain resistor minimizes gain error and realizes low offset voltage. The input bias current is 1 μA (Typ) at typical condition. There is no need to adjust the gain error.■Long Time Support Product for Industrial Applications■Wide Common Mode Voltage Range■High Accuracy■Low Offset Voltage■Low Input Bias CurrentFor more detailed information about the BD14210G-LA, refer to the datasheet.About BD14210G-EVK-0011.Board Information・Size:90mm x 80mm x 1.6mm・Number of Layers:2・Material:FR-4 (~125°C)・Copper Thickness:2oz (70μm)Figure 1. Pictures of BD14210G-EVK-0012.Schematic DiagramFigure 2. Schematic Diagram of BD14210G-EVK-0013.Bill of MaterialsTable 1. Bill of Materials of BD14210G-EVK-001Part Part Type Manufacturer Value Size/PackageDescription U1 BD14210G-LA ROHM Co., Ltd. - SSOP6 Current Sense Amplifier C1 GRM188B31H104KA92DMurata ManufacturingCo., Ltd.0.1uF 1608(0603) Capacitor C2, C3, C4 N.M.-- 1608(0603) Capacitor R1, R2 N.M.-- 1608(0603) Resistor R3, R4 MCR03EZPJ000ROHM Co., Ltd.0Ω 1608(0603) Resistor R5, R7 N.M.-- 5025(2010) Shunt Resistor R6 LTR50UZPFU10L0ROHM Co., Ltd.10mΩ 5025(2010) Shunt Resistor D1, D2 N.M. -- DO-214AA (SMB) /SOD-323FLZener Diode CN1PH-1x5SGUseconn ElectronicsLtd.-1x5 pinConnectorNote: Only the materials used in BD14210G-EVK-001 are listed. N.M. = Not Mounted4.Layout(Top View)Figure 3. Layouts of BD14210G-EVK-0015.Reference Application DataFigure 4. Thermal simulation resultNote: These data are reference using a thermal simulation tool. Please note that the temperature will change depending on the actual usage environment.Please use this board under the condition that the heat generated by the shunt resistor does not exceed the usable temperature of the board, 125°C.The current values listed are reference, so when changing the current value, please use this board within the rated power of the shunt resistor.NoticeROHM Customer Support System/contact/Thank you for your accessing to ROHM product informations.More detail product informations and catalogs are available, please contact us.N o t e sThe information contained herein is subject to change without notice.Before you use our Products, please contact our sales representative and verify the latest specifica-tions :Although ROHM is continuously working to improve product reliability and quality, semicon-ductors can break down and malfunction due to various factors.Therefore, in order to prevent personal injury or fire arising from failure, please take safety measures such as complying with the derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe procedures. ROHM shall have no responsibility for any damages arising out of the use of our Poducts beyond the rating specified by ROHM.Examples of application circuits, circuit constants and any other information contained herein areprovided only to illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production.The technical information specified herein is intended only to show the typical functions of andexamples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM or any other parties. ROHM shall have no responsibility whatsoever for any dispute arising out of the use of such technical information.The Products specified in this document are not designed to be radiation tolerant.For use of our Products in applications requiring a high degree of reliability (as exemplifiedbelow), please contact and consult with a ROHM representative : transportation equipment (i.e. cars, ships, trains), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems.Do not use our Products in applications requiring extremely high reliability, such as aerospaceequipment, nuclear power control systems, and submarine repeaters.ROHM shall have no responsibility for any damages or injury arising from non-compliance withthe recommended usage conditions and specifications contained herein.ROHM has used reasonable care to ensur e the accuracy of the information contained in thisdocument. However, ROHM does not warrants that such information is error-free, and ROHM shall have no responsibility for any damages arising from any inaccuracy or misprint of such information.Please use the Products in accordance with any applicable environmental laws and regulations,such as the RoHS Directive. For more details, including RoHS compatibility, please contact a ROHM sales office. ROHM shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations.W hen providing our Products and technologies contained in this document to other countries,you must abide by the procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act.This document, in part or in whole, may not be reprinted or reproduced without prior consent ofROHM.1) 2)3)4)5)6)7)8)9)10)11)12)13)。
Hi3510 HiBoot
文档版本 02 (2006-12-20)
深圳市海思半导体有限公司
i
Hi3510 HiBoot 移植应用 Application Notes
插图目录
插图目录
图 4-1 CodeWarrior 窗口 ..................................................................................................................................4-3 图 4-2 New 窗口 ...............................................................................................................................................4-4 图 4-3 flash_easy_prj 工程窗口 .......................................................................................................................4-4 图 4-4 Add Files 窗口 .......................................................................................................................................4-5 图 4-5 已添加文件的 flash_easy_prj 工程窗口..............................................................................................4-6 图 4-6 Debug 下拉组合框 ................................................................................................................................4-7 图 4-7 Debug 设置窗口 ....................................................................................................................................4-8 图 4-8 各种语言编译器设置...........................................................................................................................4-9 图 4-9 程序代码和数据代码地址设置窗口 .................................................................................................4-10 图 4-10 AXD Debugger 窗口.......................................................................................................................... 4-11 图 4-11 Command Line Interface 窗口...........................................................................................................4-12 图 4-12 Top 堆栈地址设置窗口.....................................................................................................................4-13 图 4-13 运行后的映象文件窗口...................................................................................................................4-14 图 4-14 再次运行后的命令窗口...................................................................................................................4-15 图 4-15 已指定 HiBoot 文件和 Flash 起始地址的命令窗口.......................................................................4-16 图 4-16 烧写 HiBoot 成功后的窗口 .............................................................................................................4-17 图 5-1 Magic-ICE 与主机连接示意图.............................................................................................................5-2 图 5-2 Multi-ICE Server 窗口...........................................................................................................................5-3 图 5-3 查找 ARM 芯片窗口............................................................................................................................5-4 图 5-4 AXD Debugger 窗口..............................................................................................................................5-5 图 5-5 Choose Target 窗口................................................................................................................................5-6 图 5-6 Mutil-ICE 配置信息提示框 ..................................................................................................................5-7 图 5-7 Target 配置窗口.....................................................................................................................................5-8
外文翻译--10Gbs的高性能PIN和APD光接收器
High Performance 10 Gb/s PIN and APD Optical Receivers Abstrac tThe increasing market demand for high-speed optical-transmission systems at rates of 10 Gb/s has resulted in technical challenges for suppliers of high-performance, manufacturable opto-electronic components and systems. In particular, the performance of the InP semiconductor devices, integrated circuits (ICs) and hybrid IC modules strongly influences the achievable transmission capability.An optical receiver design is presented which incorporates an InP-based p-i-n (positive-intrinsic-negative) photodetecto(PD) or avalanche photodetector (APD) and a GaAs high electron mobility transistor (HEMT) pre-amplifier integrated circuit. Several aspects of the receiver design are presented, including the p-i-n PD and APD structures and performance, pre-amplifier performance, hybrid module layout and electrical simulation and results. The use of analytical techniques and theory commonly used in the design of microwave amplifiers and circuits is emphasized. Receiver test results are included which are in close agreement with predicted theoretical performance.IntroductionOver the past 15 years the demand has continued to increase for higher speed and higher performing opto- electronic components. Components designed to operate at data rates of 155 Mb/s through 1 Gb/s are now used in high volume, are manufactured with high yields, and are available from several suppliers. Components designed for 2.5 Gb/s are fast approaching this manufacturing status as well. The emphasis now for new opto-electronic product development centers around performance requirements at transmission rates of 10 Gb/s and higher.The optical receiver represents one of the key components in optical-fiber based communication systems, and is generally considered as a component, or module, which is available with specified levels of electrical functionality or integration. The basic elements of an optical receiver module are a photodetector, pre-amplifier, limiting or AGC(automatic gain control) amplifier, and clock and data recovery circuitry. At data rates of 2.5 Gb/s and below, the system designer can currently purchase the optical receiver elements in various levels of integration, from a discrete photodetector module to a fully integrated clock and data recovery module.In many multi-element systems and circuits the performance is strongly influenced by those elements which are located near the input of the system or circuit. This is certainly true in a digital optical receiver where the performance of the photodetector and pre-amplifier elements will have a strong impact on receiver and system performance. In addition to the individual performance of these two elements, the electrical and physical design of the interface between them is equally critical.At speeds of 10 Gb/s, the current focus for suppliers of optical receivers is the development of modules, which incorporate the photodetector and pre-amplifier elements. Naturally as time progresses, the additional electrical functions will be incorporated into the modules as well. This paper focuses on the design and characterization of 10 Gb/s optical receiver modules that incorporate the photodetector and pre-amplifier elements.Optical Receiver BasicsBefore considering 10 Gb/s receiver design a brief review is presented of optical receivers for digital applications. A basic schematic of an optical receiver front-end is shown in Figure I. The schematic includes the photodetector and pre- amplifier elements.The key perfomance requirements of an optical receiver are high sensitivity, wide dynamic range and adequate bandwidth for the intended application. The purpose of the PD is to convert the incident optical signal to an electrical current. The photodiode should have the following performance characteristics: high responsivity (quantum efficiency), low dark current, low capacitance and wide bandwidth. For applications at optical wavelengths of 1310nm and 1550 nm, high quantum efficiency InGaAs / InP type photodetectors are commonly selected.The purpose of the pre-amplifier is to convert the photocurrent from the PD into a usable voltage that can be further processed. The common pre-amplifier technology used in optical receivers is transimpedance amplification, (TIA) due to its optimum trade-off between noise,dynamic range and bandwidth. Other types of pre-amplifiers include high-impedance and low-impedance (e.g. 50Ω) designs.p-i-n PhotodetectorsOur p-i-n photodiode is a double-heterojunction structure grown on an n+-InP substrate and consists of an n+-1nP buffer layer, an n--InGaAs active layer, and an n InP cap layer. The buffer growth precedes the active layer growth to provide a surface with fewer defects than exist on the bare substrate surface. The In0.53Ga0 .47As active layer is lattice-matched to InP and, with a bandgap εg ~ 0.75 eV, is sensitive to light with wavelengths shorter than ~1.65 µm. The device exhibits a short-wavelength cutoff at ~0.90µm since more energetic short-wavelength light is absorbed in the InP (εg ~1.35 eV) before it reaches the InGaAs. The larger-bandgap InP cap layer reduces surface leakage (relative to InGaAs) and is passivated using Si3N4. Using etched patterns in the Si3N4 as a mask, high-reliability planar diodes are created by diffusing a p-type dopant (Zn) to form one-sided p+-n-junctions just below the InP-InGaAs (cap-active) heterojunction (see Fig. 5a). Contact metallization alloyed to the diffused junction allows electrical contact to the p-side of the junction. After thinning the substrate to ~120 µm, the back side of the wafer is metallized to provide electrical connection to the n-side of the junction. Apertures in the backside metallization allow optical coupling to the active region in a back-illuminated geometry, and an anti-reflecting (AR) Si3N4 coating is present in the aperture to eliminate reflection from the air-InP interface.Several of the critical device characteristics pose conflicting design constraints that must be optimized for good high frequency performance. Of primary importance is the ability to achieve sufficient 3-dB bandwidth. The standard p- i-n diode has two fundamental bandwidth limitations: (i) finite carrier transit time and (ii) RC roll-off. The finite transit time taken by photon-induced carriers to traverse the active region can be shortened by reducing the thickness of the active region, but only at the expense of increased capacitance per unit area and lower quantum efficiency (which results in lower responsivity). The tendency towards increased capacitance for thinner active layers can be offset by reducing the total junction area, but this leads to greater difficulties in achieving high optical coupling efficiency and reliable electrical connections (e.g., by wire bonding).For 10 Gb/s performance, the conflicting requirements just described can be adequately resolved using a device diameter of 30 um. In this case, an active layer width W a ~ 2.3 um givesrise to average transit times of about 25 ps implying a maximum bandwidth f3-dB ~ 18 GHz. The resulting capacitance of ~ 0.15 pF contributes a bandwidth limitation of f3-dB ~ 21 GHz assuming a 50Ωload. (Note that low contact resistance is yet another device requirement necessary for minimizing RC bandwidth limitations.) Direct measurement of a wire-bonded photodiode using microwave probes has confirmed a device bandwidth of > 20 GHz. Finally, assuming an AR coating reduces surface reflections to negligible levels, the quantum efficiency, ηof such a device is still reasonably high:η= [l - exp(-αW a)] ~ 80% where the absorption coefficient α~ 0.70 um-1 for n--InGaAs and a wavelength of 1.55 um.Avalanche PhotodetectorsThe design of an avalanche photodiode for use at 10 Gb/s is considerably more difficult than for a p-i-n diode, but the benefits to receiver sensitivity can be substantial. The utility of the APD is that it provides a means of circumventing the basic quantum limitation of the p-i-n diode, which dictates that each photon can generate only a single electron-hole pair. The APD structure is designed to create a region of electric field sufficiently high that a single carrier is accelerated enough to generate additional electron-hole pairs through impact ionization. Newly generated carriers are similarly accelerated, and so a single carrier can trigger an avalanche effect, which provides internal gain resulting in many electron-hole pairs generated per absorbed photon.All InGaAs-InP APDs employ a separate absorption and multiplication (SAM) structure (see Fig. 2b) since high fields in the InGaAs absorption region would induce large tunneling currents before the onset of the avalanche effect. The low- doped InGaAs absorption and InP multiplication regions are spatially separated by a layer of n-doped InP used to maintain low field in the InGaAs and high field in the InP. The InP multiplication region is terminated by a p+-n- junction in InPcreated by a diffusion technique similar to that used in fabricating p-i-n diodes. The polarity of the device is determined by the fact that holes have a higher probability than electrons for ionizing collisions in InP; therefore, the structure is designed to inject photoexcited holes from the InGaAs into the InP multiplication region to seed the avalanche process. Although there is noise inherent in the avalanche effect (due to stochastic fluctuations in the number of carriers generated per photon), as long as this avalanche noise is no greater than the noise from other components in the receiver (such as amplifiers), the APD can provide a significant increase in the receiver signal-to-noise ratio. This is particularly attractive at higher frequencies at which increased amplifier noise is unavoidable.APD design is complicated by a number of factors. Foremost among these is the difficulty in controlling premature avalanche breakdown at the edge of the device.The geometry of planar diffused junctions includes inherent curvature at the junction periphery. This curvature typically causes locally enhanced electric fields, and the consequent enhanced avalanche at the junction periphery leads to an undesirable non-uniformity in the multiplication profile across the device. To solve this problem, we have used a novel double-diffusion technique to shape the diffusion profile so that edge fields are reduced.Achieving high bandwidth APD performance involves the same transit time and RC limitations described for the p-i-n diode. However, there is an additional bandwidth constraint imposed by the avalanche process itself in the form of a fixed gain-bandwidth (G-BW) product. The carrier acceleration and impact ionization involved in creating avalanche gain require an "avalanche build-up" time proportional to the gain, so the higher the operating gain is, the lower will be the device bandwidth. (Note that another new bandwidth-limiting process is introduced since all electrons created in the multiplication layer during the avalanche process must traverse the InGaAs absorption region to reach the n-contact.) Higher G-BW products result when thinner, higher-field multiplication regions are used. With a multiplication layer thickness of -0.2 µm, we have achieved G-BW products of about 90 GHz (see Fig. 3).A very attractive attribute of our APD design is the fact that it is based on well-established processes identical to those used in fabricating planar p-i-n diodes. This can be expected to result in favorable production yields and extremely high- reliability devices. We have confirmed that our 2.5 Gb/s APDs (based on a structure similar to that described above for the 10 Gb/s device) have reliability performance comparable to p-i-n diodes, and initial lifetesting on our 10 Gb/s APDs has provided similar results.ConclusionsThe design of manufacturable optical receiver modules has been presented for 10 Gb/s applications. Both a p-i-n or APD detector can be used, depending on sensitivity requirements. The design and fabrication of the planar InGaAs-InP photodetectors was presented along with a physical description of the optical module. A detailed electrical analysis based on microwave CAD simulation was presented with an emphasis on the identification of the critical circuit elements that effect the microwave performance. Finally, prototype p-i-n and APD receiver test results were presented and compared to the simulated results, showing a relatively strong correlation.作者:Jim Rue, Mark Mer, Nitish Agrawal, Stephen Bay and William Sherry国籍:美国出处:Electronic Components and Technology Conference,1999.10Gb/s的高性能PIN和APD光接收器摘要随着市场需求对传输速率为10Gb/s的高速光纤系统日益增长,使之对生产高性能,制造光电元件和系统的供应商的提出了更高的技术要求。
计算机术语辞海
3C(China Compulsory Certification,中国强制性产品认证制度)3D(Three Dimensional,三维)3DCG(3D computer graphics,三维计算机图形)3DNow!(3D no waiting,无须等待的3D处理)3DPA(3D Positional Audio,3D定位音频)3DS(3D SubSystem,三维子系统)3GIO(Third Generation Input/Output,第三代输入输出技术)AA(Accuview Antialiasing,高精度抗锯齿)AAC(Advanced Audio Compression,高级音频压缩)AAM(AMD Analyst Meeting,AMD分析家会议)AAM(Automatic Acoustic Management,自动机械声学管理)AAS(Automatic Area Segments)AAT(Average access time,平均存取时间)ABB(Advanced Boot Block,高级启动块)ABP(Address Bit Permuting,地址位序列改变)ABP(Advanced Branch Prediction,高级分支预测)ABS(Auto Balance System,自动平衡系统)A-Buffer(Accumulation Buffer,积聚缓冲)AC(Acoustic Edge,声学边缘)AC(Audio Codec,音频多媒体数字信号编解码器)AC-3(Audio Coding 3,第三代音响编码)AC97(Audio Codec 97,多媒体数字信号解编码器1997年标准)ACCP(Applied Computing Platform Providers,应用计算平台提供商)ACG(Aggressive Clock Gating,主动时钟选择)ACIRC(Advanced Cross Interleave Reed - Solomon Code,高级交叉插入里德所罗门代码)ACOPS(Automatic CPU OverHeat Prevention System(CPU过热预防系统)ACPI(Advanced Configuration and Power Interface,先进设置和电源管理)ACR(Advanced Communications Riser,高级通讯升级卡)ACS(Access Control Software,存取控制软件)ACT(Action,动作类游戏)AD(Analog to Digitalg,模拟到数字转换)ADC(Analog to Digital Converter,模数传换器)ADC(Apple Display Connector,苹果专用显示器接口)ADI(Adaptive De-Interlacing,自适应交错化技术)ADIMM(advanced Dual In-line Memory Modules,高级双重内嵌式内存模块)ADIP(Address In Pre-Groove,预凹槽寻址)ADSL(Asymmetric Digital Subscriber Line,不对称数字订阅线路)ADT(Advanced DRAM Technology,高级内存技术)AE(Atmospheric Effects,大气雾化效果)AE(Auto Focus,自动测光)AES-OCB(Advanced Encryption Standard-Operation Cipher Block,高级加密标准-操作密码块)AF(Auto Focus,自动对焦)AFC media(antiferromagnetically coupled media,反铁磁性耦合介质)AFC(Advanced Frame Capture、高级画面捕获)AFC(Amplitude-frequency characteristic,振幅频率特征)AFE(Analog Front End,模拟前置)AFM(Atomic Force Microscope,原子力显微镜)AFR(Alternate Frame Rendering,交替渲染技术)AG(Aperture Grills,栅条式金属板)AGBS(Advance GameBoy development System,高级GameBoy发展系统)AGC(Anti Glare Coatings,防眩光涂层)AGP(Accelerated Graphics Port,图形加速接口)AGPS(Assisted Global Positioning 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Calculator,分支目标寻址计算器)BTO(Build-To-Order,按序构建)BURN-Proof(Buffer UnderRuN-Proof,防止缓冲区溢出)C.O.P(CPU overheating protection,处理器过热保护)C2C(card-to-card interleaving,卡到卡交错存取CAD(computer-aided design,计算机辅助设计)CAM(Common Access Model,公共存取模型)CAM(Computer-aided manufacturing,计算机辅助制造)CAS(Column Address Strobe,列地址控制器)CAV(Constant Angular Velocity,恒定角速度)CBDS(Continuous Background Defect Scanning,连续后台错误扫描)CBF(Cable Broadband Forum,电缆宽带论坛)CBGA(Ceramic Ball Grid Array,陶瓷球状网阵排列)CBMC(Crossbar based memory controller,内存控制交叉装置)CBR(Committed Burst Rate,约定突发速率)CBR(Constant Bit Rate,固定比特率)CBU(color blending unit,色彩混和单位)CCD(Charge Coupled Device,电荷连接设备)CCIRN(Coordinating Committee for Intercontinental Research Networking,洲际研究网络协调委员会)CCM(Call Control Manager,拨号控制管理)cc-NUMA(cache-coherent non uniform memory access,连贯缓冲非统一内存寻址)CCS(Cross Capacitance Sensing,交叉电容感应)CCS(Cut Change System)CCT(Clock Cycle Time,时钟周期)CD(Compact Disc)cd/m^2(candela/平方米,亮度的单位)CDIP(Ceramic Dual-In-Line,陶瓷双重直线)CDPD(Cellular digital Packet data,细胞数字信息包数据)CDR(CD Recordable,可记录光盘)CDRAM(Cache DRAM,附加缓存型DRAM)CD-ROM/XA(CD-ROM eXtended Architecture,唯读光盘增强形架构)CDRS(Curved Directional Reflection Screen,曲线方向反射屏幕)CDRW(CD-Rewritable,可重复刻录光盘)CDSL(Consumer Digital Subscriber Line(消费者数字订阅线路)CE(Consumer Electronics,消费电子)CEA(Consumer Electronics Association,消费者电子协会)CEA(Critical Edge Angles,临界边角)CEM(cube environment mapping,立方环境映射)CEMA(Consumer Electronics Manufacturing Association(消费者电子制造业协会)Center Processing Unit Utilization,中央处理器占用率CEO(Chief Executive Officer,首席执行官)CF(CompactFlash Card,紧凑型闪存卡)CFM(cubic feet per minute,立方英尺/秒)CG(C for Graphics/GPU,用于图形/GPU的可编程语言)CG(Computer Graphics,计算机动画)CGI(Common Gateway Interface,通用网关接口)CG-Silicon(Continuous Grain Silicon,连续微粒硅)CHRP(Common Hardware Reference Platform,共用硬件平台)CHS(Cylinders、Heads、Sectors,柱面、磁头、扇区)CIEA(Commercial Internet Exchange Association,商业因特网交易协会)CIR(Committed Information Rate,约定信息速率)CIS(Contact Image Sensors,接触图像传感器)CISC(Complex Instruction Set Computing,复杂指令集计算机)CL(CAS Latency,CAS反应时间)Clipping(剪贴纹理)CLK(Clock Cycle,时钟周期)Clock Synthesizer,时钟合成器CLV(Constant Linear Velocity,恒定线速度)CMOS(Complementary Metal Oxide Semiconductor,互补金属氧化物半导体)CMOV(conditional move 包含uction,条件移动指令)CMP(on-chip multiprocessor,片内多重处理)CMR(Colossal Magneto Resistive,巨磁阻抗)CMS(Code Morphing Software,代码变形软件)CMSS(Creative Multi Speaker Surround,创新多音箱环绕)CMT(course-grained multithreading,过程消除多线程)CNPS(Computer Noise Prevention System,计算机噪音预防系统)CNR(Communication and Networking Riser,通讯和网络升级卡)CNT(carbon nano-tube,碳微管)COAST(Cache-on-a-stick,条状缓存)COB(Cache on board,板上集成缓存)co-CPU(cooperative CPU,协处理器)COD(Cache on Die,芯片内核集成缓存)COM(Component Object Model,组件对象模式)COMDEX(Computer Distribution Exposition,计算机代理分销业展览会)compressed textures(压缩纹理)Concurrent Command Engine,协作命令引擎COO(Chief Organizer Officer,首席管理官)Copper(铜)CP(command processor,指令处理器)CPA(Close Page Auto recharge,接近页自动预充电)CPE(Customer Premise Equipment,用户预定设备)CPGA(Ceramic Pin Grid Array,陶瓷针型栅格阵列)CPI(count per inch,每英寸计数)CPI(cycles per 包含uction,周期/指令)CPLD(Complex Programmable Logic Device,复杂可程序化逻辑组件)CPRM(Content Protection for record able media,记录媒体内容保护)CPS(Certification Practice Statement,使用证明书)CPU(Center Processing Unit,中央处理器)CRC(Cyclical Redundancy Check,循环冗余检查)CRM(Customer Relationship Management,顾客关系管理)CRT(Cathode Ray Tube,阴极射线管)CRT(Cooperative Redundant Threads,协同多余线程)CS(Channel Separation,声道分离)CSA(Canadian Standards Association,加拿大标准协会)CSA(Communication Streaming Architecture,通讯流架构)CSC(Colorspace Conversion,色彩空间转换)CSD(Circuit Switched Data,电路切换数据通话)CSE(Configuration Space Enable,可分配空间)CSG(constructive solid geometry,建设立体几何)CSP(Chip Scale Package,芯片比例封装)CSP(Chip Size Package,芯片尺寸封装)CSS(Cascading Style Sheets,层叠格式表)CSS(Common Command Set,通用指令集)CSS(Content Scrambling System,内容不规则加密)CTI(Computer Telephone Integration,计算机电话综合技术)CTO(Chief Technology Officer,首席技术官)CTR(CAS to RAS,列地址到行地址延迟时间)CTS(Carpal Tunnel Syndrome,计算机腕管综合症)CTS(Clear to Send,清除发送)CVS(Compute Visual Syndrome,计算机视觉综合症)CXT(Chooper eXTend,增强形K6-2内核)DA(Digital to Analog,数字到模拟转换)DAB(digital audio broadcast,数字音频广播)DAC(Digital to Analog Converter,数模传换器)DAC(Dual Address Cycle,双重地址周期)DAE(digital Audio Extraction,数据音频抓取)DAN(Dance,跳舞类游戏)DAO(Disc At Once,整盘刻录)DAO-RAW(Disc At Once Read after Write,整盘刻录-写后读)DASP(Dynamic Adaptive Speculative Pre-Processor,动态适应预测预处理器)Data Forwarding(数据前送)dB(decibel,分贝)DB(Deep Buffer,深度缓冲)DB(Device Bay,设备插架)DBBS(Dynamic Bass Boost System,动态低音增强系统)DBI(dynamic bus inversion,动态总线倒置)DBS(Direct Broadcast Satellite,直接卫星广播)DBS-PC(Direct Broadcast Satellite PC,人造卫星直接广播式PC)DC(Digital Camera,数码相机)DC(Dreamcast,世嘉64位游戏机)DCA(Defense Communication Agency,国防部通信局)DCC(Digital Compact Cassette,数字盒式磁带)DCC(Digital Content Creation,数字内容创造)DCD(Directional Corelational De-interlacing,方向关联解交错)DCD(Document Content De脚本ion for XML,XML文件内容描述)DCE(Data Circuit Terminal Equipment,数据通信设备)DCLK(Dot Clock,点时钟)DCOM(Distributing Component Object Model,构造物体模块)DCT(Display Compression Technology,显示压缩技术)DCT(DRAM Controller,DRAM控制器)DD(Double Side,双面内存)DDBGA(Die Dimension Ball Grid Array,内核密度球状矩阵排列)DDC(Display Data Channel,显示数据通道)DDC(Dynamic Depth Cueing,动态深度暗示)图像DDE(dynamic data exchange,动态数据交换)DDMA(Distributed DMA,分布式DMA)DDP(Digital Display Port,数字输出端口)DDR SDRAM(Double Date Rate,上下行双数据率SDRAM)DDR(Double Date Rate,上下行双数据率)DDS(Direct Draw Surface,直接绘画表面)DDSS II(Double Dynamic Suspension System II,第二代双层动力悬吊系统)DDSS(Dolby Digital Surround Sound,杜比数字环绕声)DDSS(Double Dynamic Suspension System,双悬浮动态减震系统)DDT(Dynamic Deferred Transaction,动态延期处理)DDWG(Digital Display Working Group,数字化显示工作组)DEC(Direct Etching Coatings,表面蚀刻涂层)Decal(印花法)Decode(指令解码)Deflection Coil(偏转线圈)DES(ata Encryption Standard,数据加密标准)DFL(Dynamic Focus Lens,动态聚焦)DFP(Digital Flat Panel,数字平面显示标准)DFPG(Digital Flat Panel Group,数字平面显示标准工作组)DFS(Digital Flex Scan,数字伸缩扫描)DFS(Dynamic Flat Shading,动态平面描影)DHCP(Dynamic Host Configuration Protocol,动态主机分配协议)DHHF(Dual Head - High Fidelity,高精度第四代双头)DHT(Dolby Headphone Technology,杜比耳机技术)DIB(Dual Independent Bus,双重独立总线)DIC(Digital Image Control,数字图像控制)DID(Device ID,设备ID)Digital Multiscan II(数字式智能多频追踪)DIL(dual-in-line)DIMM(Dual In-line Memory Modules,双重内嵌式内存模块)Directional Light(方向性光源)DiscWizard(磁盘控制软件)DIT(Disk Inspection Test,磁盘检查测试)Dithering(抖动)DIVA(Data IntensiVe Architecture,数据加强架构)DIY(Do it Yourself,自己装机)DLL(Delay-Locked Loop,延时锁定循环电路)dll(dynamic link library,动态链接库)DLP(digital Light Processing,数字光处理)DLS(Downloadable Sounds Level,可下载音色)DLS-2(Downloadable Sounds Level 2,第二代可下载音色)DM(Displacement mapping,位移贴图)DMA(Direct Memory Access,直接内存存取)DMAC(Direct Memory Access Controller,直接内存存取控制器)DME(Direct Memory Execute,直接内存执行)DMF(Distribution Media Format)DMI(Desktop Management Interface,桌面管理接口)DMT(Discreet Monitor Timing,智能型显示器调速)DMT(Discrete Multi - Tone,不连续多基频模式)DMT(Dynamic Multithreading Architecture,动态多线程结构)DNA(Distributed Internet Application,分布式因特网应用程序)DNS(Domain Name System,域名解析系统)DOA2 HC(Deal or Live 2 hardcore,生与死2完整版)DOC(Disk On Chip,芯片磁盘)DOCSIS(Data Over Cable Service Interface Specifications,线缆服务接口数据规格)DOF(Depth of Field,多重境深)DOJ(Department of Justice,反不正当竞争部门)DOM(Document Object Model,文档目标模型)DoS(Denial of Service,拒绝服务)DOS(Disk Operating System,磁盘操作系统)DOSD(Digital On Screen Display,同屏数字化显示)Dot Pitch(点距)dot texture blending(点型纹理混和)DOT(Dynamic Overcooking Technology,动态超频技术)DOT3(Dot product 3 bump mapping,点乘积凹凸映射)Double Buffering(双缓冲区)DP(Dual Processor,双处理器)DPBM(Dot Product Bump Mapping,点乘积凹凸映射)DPC(Desktop PC,桌面PC)dpi(dot per inch,每英寸的打印像素)DPMS(Display Power Management Signaling,显示能源管理信号)DPP(Direct print Protocol,直接打印协议DQL(Dynamic Quadra pole Lens,动态四极镜)DQS(Bidirectional data strobe,双向数据滤波)DQUICK(DVD Qualification and Integration Kit,DVD资格和综合工具包)DRA(deferred rendering architecture,延迟渲染架构)DRAM(Dynamic Random Access Memory,动态随机存储器)DRCG(Direct Rambus Clock Generator,直接Rambus时钟发生器)DRDRAM(Direct RAMBUS DRAM,直接内存总线DRAM)DRF(Digital radio frequency,数字无线电频率)DRI(Direct Rendering Infrastructure,基层直接渲染)DRM(Digital rights management,数字版权保护)DRM(Digital Rights Management,数字适当管理)DRSL(Differential Rambus Signaling Level,微分RAMBUS信号级)DRSL(Direct Rambus Signaling Level,直接RAMBUS信号级)DS3D(DirectSound 3D Streams)DSD(Direct Stream Digital,直接数字信号流)DSL(Data Strobe Link,数据选通连接DSL(Down Loadable Sample,可下载的取样音色)DSM(Dedicated Stack Manager,专门堆栈管理)DSM(Distributed shared memory,分布式共享内存)DSMT(Dynamic Simultaneous Multithreading,动态同步多线程)DSO(Dynamic Sound-stage Organizer,动态声音层组建)DSP(Delivery Service Partner,交付服务合伙人)DSP(Digital Signal Processing,数字信号处理)DSP(Digital Sound Field Processing,数字音场处理)DSP(Dual Streams Processor,双重流处理器)DST(Depleted Substrate Transistor,衰竭型底层晶体管)DST(Drive Self Test,磁盘自检程序)DSTN(Double layers Super Twisted Nematic,双层超扭曲向列,无源矩阵LCD)DSVD(Digital Simultaneous Voice and Data)DTD(Document Type Definition,文件类型定义)DTE(Data Terminal Equipment,数据终端设备)DTL(Developer Tool,发展工具包)DTR(Disk Transfer Rate,磁盘传输率)DTS(Digital Theater System,数字剧院系统)DTT(DeskTop Theater,桌面剧院)DTV(Digital TV,数字电视)DTV(Dual Threshold Voltage,双重极限电压)DTXS(Decryption Transform for XML Signature,XML签名解密转换)DUN(Dial-Up Networking,拨号网络)DUV(Deep Ultra-Violet,纵深紫外光)DV(Digital Vidicon,数码摄录机)DVB(Digital Video Broadcasting,数字视频广播DVC(Digital Vibrance Control,数字振动控制)DVD(Digital Video/Versatile Disk,数字视频/万能光盘)DVD-R(DVD Recordable,可记录DVD盘)DVD-RAM(Digital Video/Versatile Disk - Random Access Memory,随机存储数字视频/万能光盘)DVD-RW(DVD Rewritable,可重复刻录DVD盘)DVFM(Dynamic Voltage and Frequency Management,动态电压和频率管理)DVI(Digital Video Interface,数字视频接口)DVI(Digital Visual Interface,数字化视像接口)DVMT(Dynamic Video Memory Technology,动态视频内存技术)DVMT(Dynamic Video Memory Technology,动态视频内存技术)DWDM(Dense WaveLength Division Multiplex,波长密集型复用技术)DxR(DynamicXTended Resolution,动态可扩展分辨率)DXTC(Direct X Texture Compress,DirectX纹理压缩)Dynamic Z-buffering(动态Z轴缓冲区)E(Economy,经济,或Entry-level,入门级)E3(Electronic Entertainment Expo,电子娱乐展览会)EAP(Extensible Authentication Protocol,扩展证明协议)EAX(Environmental Audio Extensions,环境音效扩展技术)EB(Expansion Bus,扩展总线)EBGA(Enhanced Ball Grid Array,增强形球状网阵排列)EBL(electron beam lithography,电子束平版印刷)EBR(Excess Burst Rate,超额突发速率)EC(Early Childhood,学龄前儿童)EC(Embedded Controller,嵌入式控制器)ECC(Elliptic Curve Crypto,椭圆曲线加密)ECC(Error Checking and Correction,错误检查修正)ECD(Electro Chromic Display,电铬显示器)ECP(Extended Capabilities Port,延长能力端口)ED(Execution driven,执行驱动)EDA(Electronic Design Automatic,电子设计自动化)E-DDC(Enhanced Display Data Channel,增强形视频数据通道协议)EDEC(Early Decode,早期解码)Edge Anti-aliasing(边缘抗锯齿失真)EDO(Enhanced Data-Out RAM,数据增强输出内存)EE(Emotion Engine,情感引擎)E-EDID(Enhanced Extended Identification Data,增强形扩充身份辨识数据)EEPROM(Electrically Erasable Programmable ROM,电擦写可编程只读存储器)eFB(embedded Frame Buffer,嵌入式帧缓冲)EFEAL(Extended Field Elliptical Aperture Lens,可扩展扫描椭圆孔镜头)EFF(Electronic Frontier Foundation(电子前线基金会)EFI(Extensible Firmware Interface,扩展固件接口)EFM(Eight to Fourteen Modulation,8位信号转换为14位信号)EFU(Elemntary Functional Unit,增强功能单元)EHCI(Enhanced Host Controller Interface,加强型主机端控制接口)EHSDRAM(Enhanced High Speed DRAM,增强型超高速内存)EIDE(enhanced Integrated Drive Electronics,增强形电子集成驱动器)EISA(Enhanced Industry Standard Architecture,增强形工业标准架构)EL DDR(Enhanced Latency DDR,增强反应周期DDR内存)Embedded Chips(嵌入式)EMBM(environment mapped bump mapping,环境凹凸映射)Embosing(浮雕)EMC(Electron Magnetic Compatibility,电磁兼容)EMF(Electron Magnetic Field,电磁场)EMI(Electromagnetic Interference,电磁干扰)EMP(Emergency Management Port,紧急事件管理端口)EMS(Enhanced Memory System,增强内存系统)EMS(Enhanced Message Service,扩展型信息服务)EMS(Expanded Memory Specification,扩充内存规格)EOL(End of Life,最终完成产品)EOS(eBookMan Operating System,电子书操作系统)EPA(edge pin array,边缘针脚阵列)EPA(Environmental Protection Agency,美国环境保护局)EPF(Embedded Processor Forum,嵌入式处理器论坛)EPIC(explicitly parallel 包含uction code,并行指令代码)EPL(electron projection lithography,电子发射平版印刷)EPM(Enhanced Power Management,增强形能源管理)EPM(enterprise project manage)EPOC(Electronic Piece of Cheese,小型电子块)EPOC(Elevated Package Over CSP,CSP架空封装)EPP(Enhanced Parallel Port,增强形平行接口)EPROM(erasable,programmable ROM,可擦写可编程ROM)EPV(Extended Voltage Protection,扩展电压保护)ERD(Emergency Repair Disk,应急修理磁盘)ERP(Enterprise Requirement Planning,企业需求计划)ERP(Enterprise Resource Planning,企业资源计划)ERP(estimated retail price,估计零售价)ES(Energy Star,能源之星)ES(Engineering Sample,工程样品)eSATA(External Serial ATA,扩展型串行ATA)ESCD(Extended System Configuration Data,可扩展系统配置数据)ESD(electro-static discharge,静电释放)ESDJ(Easy Setting Dual Jumper,简化CPU双重跳线法)ESDRAM(Enhanced SDRAM,增强型SDRAM)ESER(EAC Secure Extract Ripping,EAC安全抓取复制)ESP(Electronic-Shock Protection,电子抗震系统)ESP(Embedded System Platform,嵌入式系统平台)ESP(Encapsulating Security Payload,压缩安全有效载荷)ESR(Equivalent Series Resistance,等价系列电阻)ESRAM(Enhanced SRAM,增强型SRAM)ETC(etc,其它类游戏,包括模拟飞行)eTM(embedded Texture Buffer,嵌入式纹理缓冲)ETRI(Electronics and Telecommunications Research Institute,电子和电信研究协会)EULA(End-User License Agreement,最终用户释放协议)EUV(Extreme Ultra Violet,紫外光)EUV(extreme ultraviolet lithography,极端紫外平版印刷)EVF(Electronic Viewfinder,电子取景窗)E-WDM(Enhanced Windows Driver Model,增强型视窗驱动程序模块)Execute Buffers(执行缓冲区)Extended Burst Transactions(增强式突发处理)Extended Stereo(扩展式立体声)Factor Alpha Blending(因子阿尔法混合)FADD(Floationg Point Addition,浮点加)FAQ(Frequently Asked Questions,常见问题回答)Fast Z-clear(快速Z缓冲清除)FAT(File Al本地 Tables,文件分配表)FB(fragment buffer,片段缓冲)FBC(Frame Buffer Cache,帧缓冲缓存)FBGA(Fine-Pitch Ball Grid Array,精细倾斜球状网阵排列)FBGA(flipchip BGA,轻型芯片BGA)F-Buffer(Fragment Stream FIFO Buffer,片段流先入先出缓冲区)FC(Famicom,任天堂8位游戏机)FC(Fibre Channel,光纤通道)FC-BGA(Flip-Chip Ball Grid Array,反转芯片球形栅格阵列)FCC(Federal Communications Commission,联邦通信委员会)FC-PGA(Flip-Chip Pin Grid Array,反转芯片针脚栅格阵列)FCRAM(Fast Cycle RAM,快周期随机存储器)FDB(Fluid Dynamic Bearing,非固定动态轴承)FDB(fluid-dynamic bearings,动态轴承)FDBM(Fluid dynamic bearing motors,液态轴承马达)FDC(Floppy Disk Controller,软盘驱动器控制装置)FDD(Floppy Disk Driver,软盘驱动器)FDIV(Floationg Point Divide,浮点除)FDM(Frequency Division Multi,频率分离)FED(Field Emission Displays,电场显示器)FEMMA(Foldable Electronic Memory Module Assembly,折叠电子内存模块装配)FEMMS(Fast Entry/Exit Multimedia State,快速进入/退出多媒体状态FFB(Force Feed Back,力反馈)FFJ(Force Feedback Joystick,力量反馈式操纵杆)FFT(fast Fourier transform,快速热欧姆转换)FGM(Fine-Grained Multithreading,高级多线程)FID(FID(Frequency identify,频率鉴别号码)FIFO(First Input First Output,先入先出队列)FIR(finite impulse response,有限推进响应)FireWire(火线,即IEEE1394标准)FISC(Fast Instruction Set Computer,快速指令集计算机)FL(fragment list,片段列表)FL(Function Lookup,功能查找)Flat(平面描影)FlexATX(Flexibility ATX,可扩展性ATX)flip double buffered(反转双缓存)flip-chip(芯片反转)FLIR(Forward Looking Infra-Red,前视红外)FLOPs(Floating Point Operations Per Second,浮点操作/秒)Flow-control(流控制)FLS(Front Light Screen,前发光屏幕)Flyback Transformer(回转变压器)FM(Flash Memory,快闪存储器)FM(Frequency Modulation,频率调制)FMA(full-motion animated backdrops)FMAC(Floating-Point Multiply-Accumulators,浮点累积乘单元)FMC(Frictionless Memory Control,无阻内存控制)FMD ROM(Fluorescent Material Read Only Memory,荧光质只读存储器)FMT(fine-grained multithreading,纯消除多线程)FMUL(Floationg Point Multiplication,浮点乘)Fog table quality(雾化表画质)Fog(雾化效果)FPD(flat panel display,平面显示器)FPM(Fast Page Mode,快页模式内存)FPRs(floating-point registers,浮点寄存器)FPS(First Person Shooters,第一人称射击游戏)FPS(FourPointSurround,创新的四点环绕扬声器系统)fps(frames per second,帧/秒)FPU(Float Point Unit,浮点运算单元)FR(Frames Rate,游戏运行帧数)FR(Frequence Response,频率响应)Frames rate is King(帧数为王)FRC(Frame Rate Control(帧比率控制)FRC(Frame Rate Control,帧率控制)FRICC(Federal Research Internet Coordinating Committee,联邦调查因特网协调委员会)FRJS(Fully Random Jittered Super-Sampling,完全随机移动式超级采样)Front Buffer(前置缓冲)FSAA(Full Scene/Screen Anti-aliasing,全景/屏幕抗锯齿)FSB(Front Side Bus,前端总线)FSE(Frequency Shifter Effect,频率转换效果)FSR(force sensor resistance,动力感应电阻)FSTN(Film compensated Super Twisted liquid crystal,带补偿膜超扭曲相列)FSUB(Floationg Point Subtraction,浮点减)FTC(Federal Trade Commission,联邦商业委员会)FTG(Fighting Game,格斗类游戏)FTP(File Transfer Protocol,文件传输协议)Fur(软毛效果)FW(Fast Write,快写,AGP总线的特殊功能)FWH(Firmware Hub,固件中心)GART(Graphic Address Remappng Table,图形地址重绘表)GB(Game Boy,任天堂4位手提游戏机)GB(Garibaldi架构,Garibaldi基于ATX架构,但是也能够使用WTX构架的机箱)GBA(Game Boy Advanced,任天堂增强型手提游戏机)GBC(Game Boy Color,任天堂手提16色游戏机)GBL(GameBoy Light,GB夜光型)GBP(GameBoy Pocket,GB口袋型)GDC(Game Developer Conference,游戏发展商会议)GDI(Graphics Device Interface,图形设备接口)GFD(Gold finger Device,金手指超频设备)GG(Game Gear,世嘉彩色手提游戏机)GHC(Global History Counter,通用历史计数器)Ghost((General Hardware Oriented System Transfer,全面硬件导向系统转移)GI(Global Illumination,球形光照)GIC(Gold Immersion Coating,化金涂布技术)GIF(Graphics Interchange Format,图像交换格式)GIF(Graphics Interface unit,图形接口单元)GLV(grating-light-valve,光栅亮度阀)GM(General Midi,普通MIDI)GM(Glass Mould,玻璃铸制)GMCH(Graphics & Memory Controller Hub,图形和内存控制中心)GMR(giant magnetoresistive,巨型磁阻)Gouraud Shading,高洛德描影,也称为内插法均匀涂色GPA(Graphics Performance Accelerator,图形性能加速卡)GPF(General protect fault,一般保护性错误)GPIs(General Purpose Inputs,普通操作输入)GPL(GNU Public License,GNU公众授权)GPRS(General Packet Raice,整合封包无线服务)GPRs(General Purpose Registers,通用寄存器)GPS(Global Positioning System,全球定位系统)GPT(Graphics Performance Toolkit,图形性能工具包)GPU(Graphics Processing Unit,图形处理器)GS(Graphic Synthesizer,图形合成器)GS(Graphics Synthesizer,图形合成器)GSM(Galvanization Superconductive Material,电镀锌超导材料)GTF(General Timing Formula,普通调速方程式)GTL(Gunning Transceiver Logic,发射接收逻辑电路)GTS(Giga Textel Sharder,十亿像素填充率)Guard Band Support(支持保护带)GUI(Graphics User Interface,图形用户界面)GVPP(Generic Visual Perception Processor,常规视觉处理器)GWS(graphics workstations,图形工作站)HAL(Hardware Abstraction Layer,硬件抽像化层)HCF(Host Controller,主体控制处理)HCI(Host Controller Interface,主机控制接口HCL(Hardware Compatibility List,硬件兼容性列表)HCRP(Hardcopy Cable Replacement Profile,硬复制电缆复位协议子集)HCT(Hardware Compatibility Test,硬件兼容性测试HDA(Head Disk Assembly,头盘组件)HDA(high-efficiency Audax High Definition Aerogel,高效高清楚气动)HDIT(High Bandwidth Differential Interconnect Technology,高带宽微分互连技术)HDMI(High Definition Multimedia Interface,高精度多媒体接口)HDR(High Dynamic Range,高级动态范围)HDRL(high dynamic-range lighting,高动态范围光线)HDSL(High bit rate DSL,高比特率数字订阅线路)HDSS(Holographic Data Storage System,全息数据存储系统)HDTV(high definition television,高清晰度电视)HDVP(High-Definition Video Processor,高精度视频处理器)HE(Home Edition,家庭版)HEL(Hardware Emulation Layer(硬件模拟层)HID(Human Interface Device,人机对话接口设备)Hierarchical Z(Z分级)HiFD(high-capacity floppy disk,高容量软盘)Hi-fi(high fidelity,高精度设备)high triangle count(复杂三角形计数)HLL(high level language,高级语言)HLLCA(High-Level Language Computing Architecture,高级语言计算架构)HL-PBGA(表面黏著,高耐热、轻薄型塑胶球状网阵封装HLSL(High Level Shading Language,高级描影语言)HMC(hardware motion compensation,硬件运动补偿)HMC(holographic media card,全息媒体卡)HMD(holographic media disk,全息媒体磁盘)Home PNA(Home Private Network Adapter,家庭私人网络适配器)HOS(Higher-Order Surfaces,高次序表面)HPC(Hand held PC,手持电脑设备)HPDR(High-Precision Dynamic-Range,高精度动态范围)HPF(High-Pass Filter,高通滤波器)HPNA(home phoneline networking,家庭电话线网络)HPS(High Performance Server,高性能服务器)HPTC(high performance technical computing,高性能技术运算)HPW(High Performance Workstation,高性能工作站)HRAA(High Resolution Anti-aliasing,高分辨率抗锯齿)HRTF(Head Related Transfer Function,头部关联传输功能)HSCSD(High-Speed Circuit-Switched Data,高速巡回开关数据)HSDRAM(High Speed DRAM,超高速内存)HSF(Host Signal,主体信号处理)HSI(High Speed Interconnect,高速内连)HSLB(High Speed Link Bus,高速链路总线)HSP(Host Signal Processing,主体信号处理)HSR(Hidden Surface Removal,隐藏表面移除)HT(Hyper Transport,超级传输)HTA(Hypertext Application,超文本应用程序)HTML(Hypertext Markup Language,超文本标记语言)HTP(Hyper Texel Pipeline,超级像素管道)HTT(Hyper Threading Technology,超级线程技术)HTTC(Hyper Transport Technology Consortium,Hyper Transport技术协会)HTTP(Hypertext Transfer Protocol,超文本传输协议)HVD(High Voltage Differential,高分差动)HWMC(Hardware Motion Compensation,硬件运动补偿)Hz(hertz,赫兹)I/O(Input/Output,输入/输出)I2C(Inter-IC)I2C(Inter-Integrated Circuit,内置集成电路)I3DL2(Interactive 3D Level 2,第二级交互式3D音效)IA(information appliance,信息器具)IA(Intel Architecture,英特尔架构)。
2071556-2功率开关,标准,单稳态,DC,150-200mW电磁铁功率等级类,200mW电磁铁
2071556-2Power Relays, Standard, Monostable, DC, 150 – 200mW Coil Power Rating Class, 200mW Coil Power Rating DC, 2880Ω Coil Resistance06/11/2021 11:00PM | Page 1For support call+1 800 522 6752Relays, Contactors & Switches > Relays >Power RelaysCoil Resistance:2880 ΩCoil Power Rating DC:200 mWCoil Power Rating Class:150 – 200 mWCoil Magnetic System:Monostable, DCPower Relay Type:StandardFeaturesProduct Type Features Enclosure Type Plastic Dust Cover Output Type AC Power Relay Type StandardConfiguration Features Output Switching RandomElectrical CharacteristicsInsulation Initial Dielectric Between Coil & Contact Class 3500 – 4000 V Output Current Rating 0 – 16 Arms Actuating SystemDC Insulation Initial Dielectric Between Open Contacts 750 Vrms Contact Limiting Short-Time Current 16 A Coil Power Rating .2 W Insulation Creepage Class7 – 11 mm Insulation Initial Dielectric Between Adjacent Contacts 750 Vrms Insulation Initial Resistance1000 MΩInsulation Initial Dielectric Between Contacts & Coil4000 Vrms2071556-2 ACTIVETE Internal #:2071556-2Power Relays, Standard, Monostable, DC, 150 – 200mW Coil Power Rating Class, 200mW Coil Power Rating DC, 2880Ω Coil ResistanceView on >Insulation Initial Dielectric Between Contacts & Coil4000 VrmsOutput Voltage (Max)250 VContact Limiting Making Current16 AInsulation Creepage Between Contact & Coil11 mm[.43 in]Contact Limiting Continuous Current16 AOutput Voltage Rating (AC Relays)0 – 250 VrmsOutput Current (Min).1 AContact Limiting Breaking Current16 ACoil Current.08 ACoil Magnetic System Monostable, DCCoil Power Rating Class150 – 200 mWCoil Power Rating DC200 mWCoil Resistance2880 ΩCoil Special Features UL Coil Insulation Class FCoil Voltage Rating24 VDCContact Switching Load (Min)100mA @ 5VContact Switching Voltage (Max)250 VACContact Voltage Rating250 VACBody FeaturesProduct Weight 5.8 gCase Color BlackContact FeaturesContact Plating Material AgSnOSwitch Arrangement 1 Form A (SPST-NO)Contact Arrangement 1 Form A (SPST-NO)Contact Current Class16 AContact Current Rating (Max)16 AContact Material AgSnOInOContact Number of Poles1Terminal Type PCB-THTTermination FeaturesRelay Termination Type Through HoleMechanical Attachment06/11/2021 11:00PM | Page 2 For support call+1 800 522 6752Mechanical AttachmentRelay Mounting Type Printed Circuit BoardDimensionsLength Class (Mechanical)16 – 20 mmHeight Class (Mechanical)14 – 15 mmInsulation Clearance Between Contact & Coil7 mm[.28 in]Insulation Clearance Class7 – 11 mmWidth Class (Mechanical)10 – 12 mmProduct Width10.2 mm[.4 in]Product Length18.2 mm[.717 in]Product Height14.8 mm[.579 in]Usage ConditionsEnvironmental Ambient Temperature (Max)85 °C[185 °F]Environmental Ambient Temperature Class70 – 85 °COperating Temperature Range-40 – 85 °C[-40 – 185 °F][-40 – 185 °F]Packaging FeaturesPackaging Method Tray/BoxProduct ComplianceFor compliance documentation, visit the product page on >EU RoHS Directive 2011/65/EU CompliantEU ELV Directive 2000/53/EC CompliantChina RoHS 2 Directive MIIT Order No 32, 2016No Restricted Materials Above ThresholdEU REACH Regulation (EC) No. 1907/2006Current ECHA Candidate List: JAN 2021(211)Candidate List Declared Against: JUN 2020(209)SVHC > Threshold:Not Yet ReviewedHalogen Content Not Low Halogen - contains Br or Cl > 900ppm.Solder Process Capability Wave solder capable to 265°CProduct Compliance DisclaimerThis information is provided based on reasonable inquiry of our suppliers and represents our current actual knowledgebased on the information they provided. This information is subject to change. The part numbers that TE has identified asEU RoHS compliant have a maximum concentration of 0.1% by weight in homogenous materials for lead, hexavalentchromium, mercury, PBB, PBDE, DBP, BBP, DEHP, DIBP, and 0.01% for cadmium, or qualify for an exemption to theselimits as defined in the Annexes of Directive 2011/65/EU (RoHS2). Finished electrical and electronic equipment products06/11/2021 11:00PM | Page 3 For support call+1 800 522 675206/11/2021 11:00PM | Page 4For support call+1 800 522 6752chromium, mercury, PBB, PBDE, DBP, BBP, DEHP, DIBP, and 0.01% for cadmium, or qualify for an exemption to these limits as defined in the Annexes of Directive 2011/65/EU (RoHS2). Finished electrical and electronic equipment products will be CE marked as required by Directive 2011/65/EU. Components may not be CE marked. Additionally, the part numbers that TE has identified as EU ELV compliant have a maximum concentration of 0.1% by weight in homogenous materials for lead, hexavalent chromium, and mercury, and 0.01% for cadmium, or qualify for an exemption to these limits as defined in the Annexes of Directive 2000/53/EC (ELV). Regarding the REACH Regulation, the information TE provides on SVHC in articles for this part number is based on the latest European Chemicals Agency (ECHA) ‘Guidance on requirements for substances in articles’ posted at this URL: https://echa.europa.eu/guidance-documents/guidance-on-reachTE Part #T1280242132-000H24B-TGBH-M32TE Part #HC5849INTEG.BATTERY POST CLAMP -VE WIT NUT & BTE Part #2-1624116-6BMB-A 0603 40R N8TE Part #9-1879129-8RN 0402 2K61 0.1% 10PPM 1K RLTE Part #2-2301994-3RJ45 JACK INT.MAG. 1GB LED 1X1TE Part #DTM1312PC12PDGR01DEUTSCH DTM HEADERSTE Part #DT04-2P-EE01DEUTSCH DT Series Housings & ConnectorsTE Part #2213765-7AV19 SPM 5A SPOT LED RED 24VTE Part #5-1609152-6CORCOM SRB SERIES IEC FILTERED INLETSTE Part #1-2071556-0OJS-SH-124HEF,00000Compatible PartsCustomers Also BoughtDocumentsCAD FilesCAD Files3D PDF3DCustomer View ModelENG_CVM_CVM_2071556-2_A.2d_dxf.zipEnglishCustomer View ModelENG_CVM_CVM_2071556-2_A.3d_igs.zipEnglishCustomer View ModelENG_CVM_CVM_2071556-2_A.3d_stp.zipEnglishTerms and ConditionsBy downloading the CAD file I accept and agree to the of use.Datasheets & Catalog PagesIndustrial Relays Quick Reference GuideEnglishOJS_10A/16AEnglishOJS Power Miniature PCB 10A / 16A RelaysEnglishIndustrial Relays Quick Reference GuideJapaneseIndustrial Relays Quick Reference GuideProduct SpecificationsDefinitions, Handling, Processing, Testing and Use of RelaysEnglish06/11/2021 11:00PM | Page 5 For support call+1 800 522 6752。
电力市场常用词汇
电力市场常用词汇(2008-05-29 21:37:49)英文缩写英文全称中文解释ATC Available Transmission Capability 可用输电容量ALM Active Load Management 有功负荷管理Active Power Market 有功市场AS Ancillary service 辅助服务Ancillary service charges 辅助服务费ASM Ancillary Service Market 辅助服务市场AS Ancillary Service Provider 辅助服务供应商Annual peak load curve 年最大负荷曲线Arbitrage 套利ACE Area control error 区域控制误差Area price 分区电价AR Area Regulation 区域管制Auction 拍卖、竞价Auction market 拍卖市场Auction Price 拍卖价格AMP Automated Mitigation Procedures 自动市场势力消除程序AGC Automatic generation control 自动发电控制ADP Availability Declaration Period 可用容量申报期Available capacity 可用发电容量ATC Available transfer capability 可用传输容量B TO B 企业对企业B TOC 企业对客户Bain index 贝恩指数BSC Balancing and settlement code 平衡与结算规则BME Balancing Market Evaluation 平衡市场计算Bid 竞价BS Bid Sufficiecy 申报充足率Bid—based 基于竞价的Bidder’s duration of validity 报价员有效期Bidding Price 竞标价格BPS Bidding Processing System 报价处理系统Bidding unit 报价机组Bids 报价Bilateral contract 双边合同Bilateral market 双边交易市场Bilateral Transaction 双边交易(即大用户直购电)Billing and Accounting 结算和结帐biomass 生物质能Block contracts 分段合同Boundary Flow 界面潮流CBM Capacity Benefit Margin 容量效益裕度Capacity factor 容量系数/容量因子Capacity payment 容量电价Capacity requirement market 容量需求市场Capacity Reservation Tariff 容量预定价格Cap-and-trade 限额交易Clearing 清算Clearing energy 出清电量Cogeneration 热电联产Competitive Electricity Market 竞争性电力市场Congestion 阻塞Congestion Cost 阻塞成本Congestion management 阻塞管理Congestion surplus 阻塞节余Congestion uplift 阻塞上抬费用CUSC Connection and use of system code 并网与网络使用规则Connection charge 并网费Consumer Surplus 消费者剩余CFD Contract for Difference 差价合同CMS Contract Management System 合同管理系统Contract price 合同电量CfDs Contracts for differences 差价和约CMS Contrat Management Subsystem 合同管理子系统Cooperative game 合作博弈Cost of service regulation 服务成本管制Cost of unit start-up 机组启动费用CSP Curtailment Service Provider 缩减负荷提供者Customer baseline load 用户基线负荷day-ahead 日前Decentralized trading model 分散交易模型Default provider 默认服务提供商Demand Curve 需求曲线DTC Demand for Transmission Capacity 输电容量需求DSM Demand-side management 需求侧管理deregulation 市场化dispatch 调度DPF Dispatcher Power Flow 调度员潮流DTS Dispatcher Training Simulator 调度员培训模拟Distribution 配电D Distribution Service Provide 配电商Economic Dispatch 经济调度Electric load management 电力负荷管理EDC Electrical Distribution Company 电力配电公司EFA Electricity Forward Agreement 电能远期合同EMOS Electricity Market Operation System 电力市场运营系统NETA electricity trading arrangement 电力交易协议Eligible customer 合格用户Spot market 现货市场Futures Market 期货交易市场EMC 节能服务公司EMS Energy Management System 能量管理系统EMOS Electricity market operation system 电力市场运营系统RES Renewable sources of energy 可再生能源Energy Spot Market 电能现货市场ERP Enterprise Resource Planning 企业资源计划Equilibrium Price 均衡价格ESCO 能源服务公司ETC Existing Transmission Commit-ments 现存输送协议Ex-post price 事后结算价格Federal Energy Regulatory Commission 联邦能源管理委员会feed-in systems 馈入系统Final closing price 最终收盘价格FTR Financial Transmission Right 金融输电权FTR Firm transmission right 固定输电权FD Fixed demand 固定需求FGR Flow-based Transmission Right 基于潮流的输电权Flowgate 关口输电权(潮流关口)FGR Flowgate Right 关口金融输电权Forced outage 强迫停机Forward Market 远期合同市场Fossil Fuel Levy 矿物燃料税Frequency Control Ancillary Service 频率控制辅助服务Future Market 期货市场Generation 发电量GBS generation bidding system 发电报价系统Generation market 发电市场G Generator 发电商Green certificate market “绿证”市场GC Grid code 输电网技术规范GC Grid Company 电网拥有者GMC Grid Management Charge 电网管理费Hedging 套利保值High and low matching method 高低匹配法hour-ahead 时前Hourly contracts 小时合同Illegal speculation 非法投机行为IMO Independent Market Operator 独立市场运营机构IPP Independent Power Producer 独立发电商ISO Independent System Operator 独立系统操作员Inflexible units 不可调度机组ICAP Installed capacity 装机容量installed generation capacity 装机容量Installed Reserve Margin 装机备用余量integrate resource planning 综合资源规划Integrated trading model 一体化交易模型Intelligent price caps 智能价格上限Interchange price 可中断电价Inter-change Schedule 交易计划Interruptible service 可中断的服务Load characteristics 负荷特性LF Load Forecasting 负荷预测LFC Load Frequency Control 负荷频率控制Load profiling 负荷拟合曲线LSE Load Serving Entity 负荷服务企业LBMP Marginal Price 节点边际电价Location Price 区域价格LMP Locational marginal price 分区边际电价LOLP Loss of Load Probility 电力不足概率losses 网损LVAC Low Voltage Access charge 低压连网费MCP Marginal Clearing Price 市场出清价格Marginal cost pricing 边际成本定价Marginal costs 边际成本Marginal Price 边际电价market Architecture 市场设计MCP Market Clearing Price 市场出清价格Market entry certification system 市场准入制度Market Equilibrium 市场均衡Market failure 市场失灵MMU Market monitoring unit 市场监察机构Market participant 市场参与者/市场成员/市场主体Market power 市场力MSO Market Service Organization 市场管理机构Merit order 优先顺序Merit order price 最优顺序价格Metering Data Acquisition System 电能量采集系统MAAC Mid-Atlantic Area Council 大西洋中部地区委员会Minimum daily load 日最小负荷Model of Transmission Right 输电权模型Monopoly 垄断MSS Multi-Settlement System 多结算系统Multi-part bidding 多部投标MW Daily MW 日报NE Nash equilibrium 纳什均衡network congestion 网络阻塞NETA New Electricity Trading Arrangements 新电力交易规则Nodal price 节点电价Non-bidding unit 非竞价机组NFFO Non-Fossil Fuel Obligation 非矿物燃料契约NERC North American Electric Reliability Council 北美电力可靠性委员会OI Office of Interconnection 办公互联网oligopolistic electricity market 卖方垄断电力市场Open access 开放接入OASIS Open Access Same-Time Information System 输电网实时信息发布系统Operating Agreement 运营协议Operation and Maintain 运行维护OPF Optimal Power Flow 最优潮流ORP Optimal Reactive Power 无功优化Optimization 最优化Option 期权合同Outage Scheduler 检修计划Partial Equilibrium 局部均衡Pattern of Transmission Right 输电权模式PAB Pay-as-bid Settlement 按报价结算Payment 支付PTR physical transmission right 物理输电权Point—to—Point Transmission Right 点对点式输电权Pool 电力库PPP Pool Purchase Price 市场购电价Pool Sale Price 市场售电价PSP Pool Sell Price 市场售电价power Broker 电力经纪人Power Exchange 短期现货交易power market 电力市场PM Power Marketer 发电经纪商Power Pool 电力交易所PPA Power Purchase Agreement 电力购销协议Power wheeling 电力转运Pre-dispatch 预调度Price cap 价格上限Price control 价格控制Price regulation 价格监管Price Sensitive Demand 价格敏感性需求Procurement auction 采购竞价Producer Surplus 生产者剩余Projected Assessment of System Adequacy 市场充裕性评估POLR Provider of last resort 收容性供电商RORC Rate of Response Compliance 负荷响应率Reactive Power Market 无功市场real time market 实时市场real-time balancing market 实时平衡市场Real-time prices 实时电价Reference bid 参考投标/报价RTO Regional Transmission organization 地区输电组织RMCP Regulation Market Clearing Price 调频市场出清价格RAA Reliability Assurance Agreement 可靠性协议RMR Reliability Must Run 由于可靠性原因必须运行机组Renewable geothermal 地热能RPS Renewable portfolio standard 可再生能源份额制标准RSI Residual Supply Index 供给剩余系统Retail access 零售准入Retail market 电力零售市场R Retail Service Provider 零售商SC Schedule Coordinators 计划协调员SCD Security Constrained Dispatch 安全约束经济调度SCUC Security-Constrained Unit Commitment 带安全约束机组组合settlement 结算SBS settlement and billing system 结算系统Settlement Day 结算日Shadow price 影子价格SFT Simultaneous Feasibility Test 可行性测试single buyer 单一买方solar photovoltaics 光电子能solar thermal 太阳能SM Spot Market 现货市场Spot price 现货价格Standard Market 标准电力市场State Estimation 状态估计Stranded costs 搁浅成本Strategic bid 报价策略SCADA Supervisory control and data acquisition 数据采集和监视系统Supply Curve 供给曲线SMP System marginal price 系统边际价格SMV system marginal value 系统边际价值System operator 系统调度机构System price 系统电价Tariff 目录电价VLL the Value of Loss of Load 失负荷电价Top-down pricing 自上而下的定价方法TTC Total transfer capability 最大输电能力Trading arrangement 交易规则Transmission and Ancillary Services Market 输电与辅助服务市场Transmission Congestion 输电阻塞TCCs Transmission Congestion Contracts 输电阻塞合同TCR Transmission Congestion Right 输电阻塞权TLR Transmission Loading Relief 输电负荷切除Transmission network or transmission system 输电网络或输电系统TO Transmission owner 输电业者TRM Transmission Reliability Margin 输电可靠性裕度TMS 交易管理系统TRR Transmission Revenue Requirement 输电收入要求Transmission Right 输电权Unconstrained Schedule 无约束计划UC unit commitment 机组组合UDS Unit Dispatch System 机组调度系统Uplift 上浮电价VLL Value of Lost Load 负荷停电损失Virtual bidding 虚拟投标/报价WSA Weather Sensitive Adjustment 天气—敏感性调整WSCC Western Systems Coordinating Council 西部电力协调委员会Wheeling trading model 过网模式Wholesale market 电力批发市场Zonal pricing 区域定价actual load curve 实际负荷曲线actual active power output curve 实际有功出力曲线actual reactive power output curve 实际无功出力曲线accounting cost 会计成本bid curve 报价曲线biding energy 竞价空间bi-directional contract for difference 双向差价合同bilateral contact for difference 双边差价合同black start service 黑启动服务block biding 分段竞价buying long 买空compesnation regulation 补偿调节competition energy 竞争电量constrained trading schedule 有约束交易计划contract-path method 合同路径法daily load factor 日负荷率day-ahead trading 日前交易DATS day-ahead trade subsystem 日前交易子系统dispatch interval 调度时段dispatch price 调度价格distribution price 配电电价DMIS dispatching management information system 调度管理信息系统efficiency market 有效市场electricity fee 电费electricity market model 电力市场模式electricity matket regulation 电力市场监管elementary ancillary services 基本辅助服务embedded cost pricing 会计成本定价emergency reserve 事故备用energy price 电量电价exclusive service tariff 专项服务价格feasible capacity 可调出力feasible hours 可调小时financial power trading 电力金融交易fixed cost 固定成本floody season-dry season price 丰枯电价frequency curve 频率曲线future contract 期货合同future trading 期货交易generation competition 发电竞争模式generation re-scheduling 发电再计划generation right transfer trading 发电权转让交易generation unit availability 发电机组可用率generation rated capacity 发电机额定容量high-reliability price 高可靠性电价imperfect competitive market 不完全竞争市场inter-connection tariff 联网价IRR internal rate of return 内部收益率lincense system for electric power business 电力业务许可证制度load coincidence factor 负荷同时率load factor 负荷因数load fluctuation 负荷波动long-run marginal cost pricing 长期边际成本定价loss allocation 网损分摊loss conversion 网损折算loss factor 网损系数LTS long-term trade subsystem 长期交易子系统marginal revenue 边际收益marginal utility 边际效用market intervention 市场干预market mechanism 市场机制MAS market analysis subsystem 市场分析子系统multi-block bidding 多段报价multilateral trading 多边交易must-run unit 强制运行机组nonlinear pricing 非线性定价off-grid energy 下网电量on-grid energy 上网电量on-grid price 上网电价one-part price 单一制电价opportunity cost 机会成本peak-valley price 峰谷电价perfect competitive market 完全竞争市场physical power trading 电力实物交易postage stamp method 邮票法power flow tracing method 潮流跟踪法power regulatory agency 电力监管机构power retailer 电力零售商principle of marginality 边际原则reserve capacity 备用容量reserve service 备用服务retail competition 零售竞争模式retail price 销售电价RTS real-time trade subsystem 实时交易子系统scheduled outage 计划停运seasonal price 季节电价sequential bidding 分次竞价single-block bidding 单段报价single-buyer 单一购买者模式time sharing bidding 分时竞价TMR tele-meter reading system 电能量计量系统two-part price 两部制电价uni-directional contract for difference 单项差价合同valid grid assets 电网有效资产variable cost 变动成本verticallty integrated monopoly 垂直垄断模式whole energy competition 批发竞争模式Active regulation 主动监管Annual contract on-grid energy 年度合同上网电量ACRS Accelerated Cost Recovery System 加速成本回收体系Balancing account 平衡帐户Budget line 预算线Capital & interest price 还本付息电价Ceiling and floor of market clearing price 市场出清价格的上下限Deregulation 放松管制Forced outrage 强迫停运Frequency regulation 一次调频Grid access tariff 接入价Grid security assessment 网络安全校核Grid security constraint 网络安全约束Hour-ahead trading 时前交易Indifference curve 无差异曲线Information asymmetry 信息不对称Initial margin 初始保证金Interruptible forward contract 可中断远期合同Interruptible service 可中断服务Investment regulation 投资监管Information publishing subsystem 信息发布子系统Monopoly market 垄断市场Natural monopoly 自然垄断Nodal pricing 节电电价法Payoff table 支付矩阵Property right 产权Public pricing 公共定价Quality regulation 质量监管Regional electricity market 区域电力市场Selling short 卖空Settlement account 结算帐户Supply-demand ratio 市场供需比Trading manner 交易方式Transaction cost 交易成本Whole energy competition 全电量竞争模式Unplanned outrage 非计划停运Variation margin 价格变动保证金Yearly regulation 年调节Zero-sum game 零和博弈Zonal pricing 区域电价法price elasticity of demand 需求的价格弹性No-load Cost 空载成本Quasi-fixed Cost 准固定成本Extra-marginal Production 边际外生产Deadweight Loss 无谓损失Option Markets 期权市场Swap Contracts 互换合约Option Valuation 期权估值Exotic Options 特种期权Economies of Scale 规模经济CPF continuation power flow 连续潮流PLF probabilistic load flow 概率潮流Reserved capacity 预留容量ETC existing transmission commitment. 现有输电协议forecasting time span 预测时间跨度PM Probabilistic margin 概率界限EDS economic dispatch system 经济调度系统21。
AD795
4
5
Figure 3. Typical Distribution of Average Input Offset Voltage Drift
Figure 2. Voltage Noise Spectral Density
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
50 SAMPLE SIZE = 570
VOLTAGE NOISE SPECTRAL DENSITY (nV/ Hz)
40
PERCENTAGE OF UNITS
30
100
20
10
10
–4
100 1k FREQUENCY (Hz)
TC7106_06资料
TC7106/A/TC7107/AFeatures:•Internal Reference with Low Temperature Drift: -TC7106/7: 80ppm/°C Typical-TC7106A/7A: 20ppm/°C Typical•Drives LCD (TC7106) or LED (TC7107)Display Directly•Zero Reading with Zero Input•Low Noise for Stable Display•Auto-Zero Cycle Eliminates Need for Zero Adjustment•True Polarity Indication for Precision Null Applications•Convenient 9V Battery Operation (TC7106A)•High-Impedance CMOS Differential Inputs: 1012Ω•Differential Reference Inputs Simplify Ratiometric Measurements•Low-Power Operation: 10mW Applications:•Thermometry•Bridge Readouts: Strain Gauges, Load Cells, Null Detectors•Digital Meters: Voltage/Current/Ohms/Power, pH •Digital Scales, Process Monitors•Portable InstrumentationDevice Selection Table General Description:The TC7106A and TC7107A 3-1/2 digit direct displaydrive Analog-to-Digital Converters allow existing 7106/7107 based systems to be upgraded. Each device has a precision reference with a 20ppm/°C max tempera-ture coefficient. This represents a 4 to 7 times improve-ment over similar 3-1/2 digit converters. Existing 7106 and 7107 based systems may be upgraded withoutchanging external passive component values. TheTC7107A drives common anode light emitting diode (LED) displays directly with 8mA per segment. A lowcost, high resolution indicating meter requires only adisplay, four resistors, and four capacitors.The TC7106A low-power drain and 9V battery operationmake it suitable for portable applications.The TC7106A/TC7107A reduces linearity error to lessthan 1 count. Rollover error – the difference in readings for equal magnitude, but opposite polarity input signals,is below ±1 count. High-impedance differential inputsoffer 1pA leakage current and a 1012Ω input imped-ance. The differential reference input allows ratiometricmeasurements for ohms or bridge transducermeasurements. The 15μV P–P noise performance ensures a “rock solid” reading. The auto-zero cycle ensures a zero display reading with a zero volts input.Package Code Package Pin LayoutTemperatureRangeCPI40-Pin PDIP Normal0°C to +70°CIPL40-Pin PDIP Normal-25°C to +85°CIJL40-Pin CERDIP Normal-25°C to +85°CCKW44-Pin PQFP FormedLeads0°C to +70°CCLW44-Pin PLCC —0°C to +70°C3-1/2 Digit Analog-to-Digital Converters© 2006 Microchip Technology Inc.DS21455C-page 1TC7106/A/TC7107/APackage TypeDS21455C-page 2© 2006 Microchip Technology Inc.TC7106/A/TC7107/A Typical Application© 2006 Microchip Technology Inc.DS21455C-page 3TC7106/A/TC7107/ADS21455C-page 4© 2006 Microchip Technology Inc.1.0ELECTRICALCHARACTERISTICSAbsolute Maximum Ratings*TC7106ASupply Voltage (V+ to V-).......................................15V Analog Input Voltage (either Input) (Note 1)...V+ to V-Reference Input Voltage (either Input)............V+ to V-Clock Input...................................................Test to V+Package Power Dissipation (T A ≤ 70°C) (Note 2):40-Pin CERDIP.......................................2.29W 40-Pin PDIP ............................................1.23W 44-Pin PLCC...........................................1.23W 44-Pin PQFP...........................................1.00W Operating Temperature Range:C (Commercial) Devices..............0°C to +70°C I (Industrial) Devices ................-25°C to +85°C Storage Temperature Range..............-65°C to +150°CTC7107ASupply Voltage (V+)...............................................+6V Supply Voltage (V-)..................................................-9V Analog Input Voltage (either Input) (Note 1)...V+ to V-Reference Input Voltage (either Input)............V+ to V-Clock Input..................................................GND to V+Package Power Dissipation (T A ≤ 70°C) (Note 2):40-Pin CERDip........................................2.29W 40-Pin PDIP ............................................1.23W 44-Pin PLCC...........................................1.23W 44-Pin PQFP...........................................1.00W Operating Temperature Range:C (Commercial) Devices..............0°C to +70°C I (Industrial) Devices ................-25°C to +85°C Storage Temperature Range..............-65°C to +150°C*Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.TC7106/A/TC7107/ATABLE 1-1:TC7106/A AND TC7107/A ELECTRICAL SPECIFICATIONSElectrical Characteristics: Unless otherwise noted, specifications apply to both the TC7106/A and TC7107/A at T A = 25°C,f CLOCK = 48kHz. Parts are tested in the circuit of the Typical Operating Circuit.Symbol Parameter Min Typ Max Unit Test ConditionsZ IR Zero Input Reading-000.0±000.0+000.0DigitalReading V IN = 0.0VFull Scale = 200.0mVRatiometric Reading999999/10001000DigitalReading V IN = V REFV REF = 100mVR/O Rollover Error (Difference in Reading forEqual Positive and NegativeReading Near Full Scale)-1±0.2+1Counts V IN- = + V IN+ ≅ 200mVLinearity (Max. Deviation from Best Straight Line Fit)-1±0.2+1Counts Full Scale = 200mV orFull Scale = 2.000VCMRR Common Mode Rejection Ratio (Note 3)—50—μV/V V CM = ±1V, V IN = 0V,Full Scale = 200.0mVe N Noise (Peak to Peak Value not Exceeded95% of Time)—15—μV V IN = 0VFull Scale - 200.0mVI L Leakage Current at Input—110pA V IN = 0VZero Reading Drift—0.21μV/°C V IN = 0V“C” Device = 0°C to +70°C— 1.02μV/°C V IN = 0V“I” Device = -25°C to +85°C TC SF Scale Factor Temperature Coefficient—15ppm/°C V IN = 199.0mV,“C” Device = 0°C to +70°C(Ext. Ref = 0ppm°C)——20ppm/°C V IN = 199.0mV“I” Device = -25°C to +85°C I DD Supply Current (Does not include LEDCurrent For TC7107/A)—0.8 1.8mA V IN = 0.8V C Analog Common Voltage(with Respect to Positive Supply)2.7 3.05 3.35V25kΩ Between Common andPositive SupplyV CTC Temperature Coefficient of AnalogCommon (with Respect to Positive Supply)————25kΩ Between Common andPositive Supply7106/7/A7106/7208050—ppm/°Cppm/°C0°C ≤ T A≤ +70°C(“C” Commercial TemperatureRange Devices)V CTC Temperature Coefficient of AnalogCommon (with Respect to Positive Supply)——75ppm/°C0°C ≤ T A≤ +70°C(“I” Industrial TemperatureRange Devices)V SD TC7106A ONLY Peak to Peak Segment Drive Voltage 456V V+ to V- = 9V(Note 4)V BD TC7106A ONLY Peak to Peak Backplane Drive Voltage 456V V+ to V- = 9V(Note 4)TC7107A ONLYSegment Sinking Current (Except Pin 19)58.0—mA V+ = 5.0VSegment Voltage = 3VTC7107A ONLYSegment Sinking Current (Pin 19)1016—mA V+ = 5.0VSegment Voltage = 3VNote1:Input voltages may exceed the supply voltages, provided the input current is limited to ±100μA.2:Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.3:Refer to “Differential Input” discussion.4:Backplane drive is in phase with segment drive for “OFF” segment, 180° out of phase for “ON” segment.Frequency is 20 times conversion rate. Average DC component is less than 50mV.© 2006 Microchip Technology Inc.DS21455C-page 5TC7106/A/TC7107/ADS21455C-page 6© 2006 Microchip Technology Inc.2.0PIN DESCRIPTIONSThe descriptions of the pins are listed in Table 2-1.TABLE 2-1:PIN FUNCTION TABLEPin Number (40-Pin PDIP)NormalPin No.(40-Pin PDIP)(ReversedSymbol Description1(40)V+Positive supply voltage.2(39)D 1Activates the D section of the units display.3(38)C 1Activates the C section of the units display.4(37)B 1Activates the B section of the units display.5(36)A 1Activates the A section of the units display.6(35)F 1Activates the F section of the units display.7(34)G 1Activates the G section of the units display.8(33)E 1Activates the E section of the units display.9(32)D 2Activates the D section of the tens display.10(31)C 2Activates the C section of the tens display.11(30)B 2Activates the B section of the tens display.12(29)A 2Activates the A section of the tens display.13(28)F 2Activates the F section of the tens display.14(27)E 2Activates the E section of the tens display.15(26)D 3Activates the D section of the hundreds display.16(25)B 3Activates the B section of the hundreds display.17(24)F 3Activates the F section of the hundreds display.18(23)E 3Activates the E section of the hundreds display.19(22)AB 4Activates both halves of the 1 in the thousands display.20(21)POL Activates the negative polarity display.21(20)BP/GND LCD Backplane drive output (TC7106A). Digital Ground (TC7107A).22(19)G 3Activates the G section of the hundreds display.23(18)A 3Activates the A section of the hundreds display.24(17)C 3Activates the C section of the hundreds display.25(16)G 2Activates the G section of the tens display.26(15)V-Negative power supply voltage.27(14)V INT Integrator output. Connection point for integration capacitor. See INTEGRATING CAPACITOR section for more details.28(13)V BUFF Integration resistor connection. Use a 47k Ω resistor for a 200mV full scale range and a 47k Ω resistor for 2V full scale range.29(12)C AZThe size of the auto-zero capacitor influences system noise. Use a 0.47μF capacitor for 200mV full scale, and a 0.047μF capacitor for 2V full scale. See Section 7.1 “Auto-Zero Capacitor (CAZ)” on Auto-Zero Capacitor for more details.30(11)V IN -The analog LOW input is connected to this pin.31(10)V IN +The analog HIGH input signal is connected to this pin.32(9)ANALOG COMMON This pin is primarily used to set the Analog Common mode voltage for battery opera-tion or in systems where the input signal is referenced to the power supply. It alsoacts as a reference voltage source. See Section 8.3 “Analog Common (Pin 32)” on ANALOG COMMON for more details. 33(8)C REF -See Pin 34.34(7)C REF +A0.1μF capacitor is used in most applications. If a large Common mode voltage exists (for example, the V IN - pin is not at analog common), and a 200mV scale is used, a 1μF capacitor is recommended and will hold the rollover error to 0.5 count.35(6)V REF -See Pin 36.© 2006 Microchip Technology Inc.DS21455C-page 7TC7106/A/TC7107/A36(5)V REF +The analog input required to generate a full scale output (1999 counts). Place 100mV between Pins 35 and 36 for 199.9mV full scale. Place 1V between Pins 35 and 36 for 2V full scale. See paragraph on Reference Voltage.37(4)TESTLamp test. When pulled HIGH (to V+) all segments will be turned on and the display should read -1888. It may also be used as a negative supply for externally generated decimal points. See paragraph under TEST for additional information.38(3)OSC3See Pin 40. 39(2)OSC2See Pin 40.40(1)OSC1Pins 40, 39, 38 make up the oscillator section. For a 48kHz clock (3 readings per section), connect Pin 40 to the junction of a 100k Ω resistor and a 100pF capacitor. The 100k Ω resistor is tied to Pin 39 and the 100pF capacitor is tied to Pin 38.TABLE 2-1:PIN FUNCTION TABLE (CONTINUED)Pin Number (40-Pin PDIP)NormalPin No.(40-Pin PDIP)(ReversedSymbol DescriptionTC7106/A/TC7107/ADS21455C-page 8© 2006 Microchip Technology Inc.3.0DETAILED DESCRIPTION(All Pin designations refer to 40-Pin PDIP .)3.1Dual Slope Conversion PrinciplesThe TC7106A and TC7107A are dual slope, integrating Analog-to-Digital Converters. An understanding of the dual slope conversion technique will aid in following the detailed operation theory.The conventional dual slope converter measurement cycle has two distinct phases:•Input Signal Integration•Reference Voltage Integration (De-integration)The input signal being converted is integrated for a fixed time period (T SI ). Time is measured by counting clock pulses. An opposite polarity constant reference voltage is then integrated until the integrator output voltage returns to zero. The reference integration time is directly proportional to the input signal (T RI ). See Figure 3-1.FIGURE 3-1:Basic Dual Slope ConverterIn a simple dual slope converter, a complete conver-sion requires the integrator output to “ramp-up” and “ramp-down.” A simple mathematical equation relates the input signal, reference voltage and integration time.EQUATION 3-1:For a constant V IN :EQUATION 3-2:The dual slope converter accuracy is unrelated to the integrating resistor and capacitor values as long as they are stable during a measurement cycle. An inher-ent benefit is noise immunity. Noise spikes are integrated or averaged to zero during the integration periods. Integrating ADCs are immune to the large conversion errors that plague successive approxima-tion converters in high noise environments. Interfering signals with frequency components at multiples of the averaging period will be attenuated. Integrating ADCs commonly operate with the signal integration period set to a multiple of the 50/60Hz power line period (see Figure 3-2).FIGURE 3-2:Normal Mode Rejection of Dual Slope Converter1RCV R T RI RCT SIV IN (t)dt =∫Where:V R =Reference voltageT SI =Signal integration time (fixed)T RI =Reference voltage integration time (variable).V IN = V RT RI T SITC7106/A/TC7107/A4.0ANALOG SECTIONIn addition to the basic signal integrate and de-integrate cycles discussed, the circuit incorporates an auto-zero cycle. This cycle removes buffer amplifier, integrator, and comparator offset voltage error terms from the conversion. A true digital zero reading results without adjusting external potentiometers. A complete conversion consists of three cycles: an auto-zero, signal integrate and reference integrate cycle.4.1Auto-Zero CycleDuring the auto-zero cycle, the differential input signal is disconnected from the circuit by opening internal analog gates. The internal nodes are shorted to analog common (ground) to establish a zero input condition. Additional analog gates close a feedback loop around the integrator and comparator. This loop permits comparator offset voltage error compensation. The voltage level established on C AZ compensates for device offset voltages. The offset error referred to the input is less than 10μV.The auto-zero cycle length is 1000 to 3000 counts. 4.2Signal Integrate CycleThe auto-zero loop is entered and the internal differen-tial inputs connect to V IN+ and V IN-. The differential input signal is integrated for a fixed time period. The TC7136/A signal integration period is 1000 clock periods or counts. The externally set clock frequency is divided by four before clocking the internal counters. The integration time period is:EQUATION 4-1:The differential input voltage must be within the device Common mode range when the converter and mea-sured system share the same power supply common (ground). If the converter and measured system do not share the same power supply common, V IN-should be tied to analog common.Polarity is determined at the end of signal integrate phase. The sign bit is a true polarity indication, in that signals less than 1LSB are correctly determined. This allows precision null detection limited only by device noise and auto-zero residual offsets.4.3Reference Integrate PhaseThe third phase is reference integrate or de-integrate. V IN- is internally connected to analog common and V IN+is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the input signal and is between 0 and 2000 counts.The digital reading displayed is:EQUATION 4-2:5.0DIGITAL SECTION (TC7106A) The TC7106A (Figure5-2) contains all the segment drivers necessary to directly drive a 3-1/2 digit liquid crystal display (LCD). An LCD backplane driver is included. The backplane frequency is the external clock frequency divided by 800. For three conversions/ second, the backplane frequency is 60Hz with a 5V nominal amplitude. When a segment driver is in phase with the backplane signal, the segment is “OFF.” An out of phase segment drive signal causes the segment to be “ON” or visible. This AC drive configuration results in negligible DC voltage across each LCD segment. This insures long LCD display life. The polarity segment driver is “ON” for negative analog inputs. If V IN+ and V IN-are reversed, this indicator will reverse. When the TEST pin on the TC7106A is pulled to V+, all segments are turned “ON.” The display reads -1888. During this mode, the LCD segments have a constant DC voltage impressed. DO NOT LEAVE THE DIS-PLAY IN THIS MODE FOR MORE THAN SEVERAL MINUTES! LCD displays may be destroyed if operated with DC levels for extended periods.The display font and the segment drive assignment are shown in Figure5-1.FIGURE 5-1:Display Font and Segment AssignmentIn the TC7106A, an internal digital ground is generated from a 6-volt zener diode and a large P channel source follower. This supply is made stiff to absorb the large capacitive currents when the backplane voltage is switched.T SI =4F OSCx 1000Where: F OSC = external clock frequency.1000 =V INV REF© 2006 Microchip Technology Inc.DS21455C-page 9TC7106/A/TC7107/AFIGURE 5-2:TC7106A Block DiagramDS21455C-page 10© 2006 Microchip Technology Inc.6.0DIGITAL SECTION (TC7107A) Figure6-2 shows a TC7107A block diagram. It is designed to drive common anode LEDs. It is identical to the TC7106A, except that the regulated supply and backplane drive have been eliminated and the segment drive is typically 8mA. The 1000’s output (Pin 19) sinks current from two LED segments, and has a 16mA drive capability.In both devices, the polarity indication is “ON” for negative analog inputs. If V IN- and V IN+ are reversed, this indication can be reversed also, if desired.The display font is the same as the TC7106A.6.1System TimingThe oscillator frequency is divided by 4 prior to clocking the internal decade counters. The four-phase measurement cycle takes a total of 4000 counts, or 16,000 clock pulses. The 4000-count cycle is indepen-dent of input signal magnitude.Each phase of the measurement cycle has the follow-ing length:1.Auto-zero phase: 1000 to 3000 counts (4000 to12000 clock pulses).For signals less than full scale, the auto-zero phase is assigned the unused reference integrate time period: 2.Signal integrate: 1000 counts (4000 clockpulses).This time period is fixed. The integration period is: EQUATION 6-1:3.Reference Integrate: 0 to 2000 counts (0 to 8000clock pulses).The TC7106A/7107A are drop-in replacements for the 7106/7107 parts. External component value changes are not required to benefit from the low drift internal reference.6.2Clock CircuitThree clocking methods may be used (see Figure6-1):1.An external oscillator connected to Pin 40.2. A crystal between Pins 39 and 40.3.An RC oscillator using all three pins.FIGURE 6-1:Clock CircuitsT SI = 40001F OSC ⎛⎝⎞⎠Where: F OSC is the externally set clock frequency.FIGURE 6-2:TC7107A Block Diagram7.0COMPONENT VALUESELECTION7.1Auto-Zero Capacitor (C AZ)The C AZ capacitor size has some influence on system noise. A 0.47μF capacitor is recommended for 200mV full scale applications where 1LSB is 100μV. A 0.047μF capacitor is adequate for 2.0V full scale applications. A mylar type dielectric capacitor is adequate.7.2Reference Voltage Capacitor(C REF)The reference voltage used to ramp the integrator out-put voltage back to zero during the reference integrate cycle is stored on C REF. A 0.1μF capacitor is acceptable when V IN- is tied to analog common. If a large Common mode voltage exists (V REF- – analog common) and the application requires 200mV full scale, increase C REF to1.0μF. Rollover error will be held to less than 1/2 count.A mylar dielectric capacitor is adequate.7.3Integrating Capacitor (C INT)C INT should be selected to maximize the integrator out-put voltage swing without causing output saturation. Due to the TC7106A/7107A superior temperature coefficient specification, analog common will normally supply the differential voltage reference. For this case, a ±2V full scale integrator output swing is satisfactory. For 3 readings/second (F OSC = 48kHz), a 0.22μF value is suggested. If a different oscillator frequency is used, C INT must be changed in inverse proportion to maintain the nominal ±2V integrator swing.An exact expression for C INT is:EQUATION 7-1:C INT must have low dielectric absorption to minimize rollover error. A polypropylene capacitor is recommended.7.4Integrating Resistor(R INT)The input buffer amplifier and integrator are designed with class A output stages. The output stage idling current is 100μA. The integrator and buffer can supply 20μA drive currents with negligible linearity errors. R INT is chosen to remain in the output stage linear drive region, but not so large that printed circuit board leakage currents induce errors. For a 200mV full scale, R INT is 47kΩ. 2.0V full scale requires 470kΩ.Note:F OSC = 48kHz (3 readings per sec).7.5Oscillator ComponentsR OSC (Pin 40 to Pin 39) should be 100kΩ. C OSC is selected using the equation:EQUATION 7-2:For F OSC of 48kHz, C OSC is 100pF nominally.Note that F OSC is divided by four to generate the TC7106A internal control clock. The backplane drive signal is derived by dividing F OSC by 800.To achieve maximum rejection of 60Hz noise pickup, the signal integrate period should be a multiple of 60Hz. Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz, etc. should be selected. For 50Hz rejection, oscillator frequencies of 200kHz, 100kHz, 66-2/3kHz, 50kHz, 40kHz, etc. would be suitable. Note that 40kHz (2.5 readings/second) will reject both 50Hz and 60Hz.7.6Reference Voltage SelectionA full scale reading (2000 counts) requires the input signal be twice the reference voltage.*V FS = 2V REF.C INT =(4000)V INT1F OSCV FSR INT⎛⎝⎞⎠⎛⎝⎞⎠Where:F OSC=Clock Frequency at Pin 38V FS=Full Scale Input VoltageR INT=Integrating ResistorV INT=Desired Full Scale Integrator Output Swing ComponentValueNominal Full Scale Voltage200.0mV 2.000VC AZ0.47μF0.047μFR INT47kΩ470kΩC INT0.22μF0.22μFRequired Full Scale Voltage*V REF200.0mV100.0mV2.000V 1.000VF OSC =0.45RCIn some applications, a scale factor other than unity may exist between a transducer output voltage and the required digital reading. Assume, for example, a pres-sure transducer output is 400mV for 2000 lb/in2. Rather than dividing the input voltage by two, the reference voltage should be set to 200mV. This permits the trans-ducer input to be used directly.The differential reference can also be used when a digital zero reading is required when V IN is not equal to zero. This is common in temperature measuring instru-mentation. A compensating offset voltage can be applied between analog common and V IN-. The trans-ducer output is connected between V IN+ and analogcommon.The internal voltage reference potential available at analog common will normally be used to supply the converter’s reference. This potential is stable when-ever the supply potential is greater than approximately 7V. In applications where an externally generated reference voltage is desired, refer to Figure7-1.FIGURE 7-1:External Reference8.0DEVICE PIN FUNCTIONALDESCRIPTION8.1Differential Signal InputsV IN+ (Pin 31), V IN- (Pin 30)The TC7106A/7017A is designed with true differential inputs and accepts input signals within the input stage common mode voltage range (V CM). The typical range is V+ – 1.0 to V+ + 1V. Common mode voltages are removed from the system when the TC7106A/ TC7107A operates from a battery or floating power source (isolated from measured system) and V IN- is connected to analog common (V COM) (see Figure8-2). In systems where Common mode voltages exist, the 86dB Common mode rejection ratio minimizes error. Common mode voltages do, however, affect the inte-grator output level. Integrator output saturation must be prevented. A worst-case condition exists if a large positive V CM exists in conjunction with a full scale negative differential signal. The negative signal drives the integrator output positive along with V CM (see Figure). For such applications the integrator output swing can be reduced below the recommended 2.0V full scale swing. The integrator output will swing within 0.3V of V+ or V-without increasing linearity errors.FIGURE 8-1:Common Mode VoltageReduces Available Integrator Swing (VCOM ≠ VIN)8.2Differential ReferenceV REF+ (Pin 36), V REF- (Pin 35)The reference voltage can be generated anywherewithin the V+ to V-power supply range.To prevent rollover type errors being induced by largeCommon mode voltages, C REF should be largecompared to stray node capacitance.The TC7106A/TC7107A circuits have a significantlylower analog common temperature coefficient. Thisgives a very stable voltage suitable for use as areference. The temperature coefficient of analogcommon is 20ppm/°C typically.8.3Analog Common (Pin 32)The analog common pin is set at a voltage potentialapproximately 3.0V below V+. The potential is between2.7V and3.35V below V+. Analog common is tied inter-nally to the N channel FET capable of sinking 20mA.This FET will hold the common line at 3.0V should anexternal load attempt to pull the common line towardV+. Analog common source current is limited to 10μA.Analog common is, therefore, easily pulled to a morenegative voltage (i.e., below V+ – 3.0V).The TC7106A connects the internal V IN+ and V IN-inputs to analog common during the auto-zero cycle.During the reference integrate phase, V IN- is con-nected to analog common. If V IN- is not externally con-nected to analog common, a Common mode voltageexists. This is rejected by the converter’s 86dB Com-mon mode rejection ratio. In battery operation, analogcommon and V IN- are usually connected, removingCommon mode voltage concerns. In systems where V-is connected to the power supply ground, or to a givenvoltage, analog common should be connected to V IN-. [INThe analog common pin serves to set the analog section reference or common point. The TC7106A is specifically designed to operate from a battery, or in any measure-ment system where input signals are not referenced (float), with respect to the TC7106A power source. The analog common potential of V+ – 3.0V gives a 6V end of battery life voltage. The common potential has a 0.001% voltage coefficient and a 15Ω output impedance.With sufficiently high total supply voltage (V+ – V- > 7.0V), analog common is a very stable potential with excellent temperature stability, typically 20ppm/°C. This potential can be used to generate the reference voltage. An external voltage reference will be unneces-sary in most cases because of the 50ppm/°C maximum temperature coefficient. See Internal Voltage Reference discussion.8.4TEST (Pin 37)The TEST pin potential is 5V less than V+. TEST may be used as the negative power supply connection for external CMOS logic. The TEST pin is tied to the inter-nally generated negative logic supply (Internal Logic Ground) through a 500Ω resistor in the TC7106A. The TEST pin load should be no more than 1mA.If TEST is pulled to V+ all segments plus the minus sign will be activated. Do not operate in this mode for more than several minutes with the TC7106A. With TEST=V+, the LCD segments are impressed with a DC voltage which will destroy the LCD.The TEST pin will sink about 10mA when pulled to V+.8.5Internal Voltage ReferenceThe analog common voltage temperature stability has been significantly improved (Figure8-3). The “A”version of the industry standard circuits allow users to upgrade old systems and design new systems without external voltage references. External R and C values do not need to be changed. Figure8-4 shows analog common supplying the necessary voltage reference for the TC7106A/TC7107A.FIGURE 8-3:Analog Common Temperature CoefficientFIGURE 8-4:Internal Voltage ReferenceConnection。
ANALOG DEVICES DC1019A Radio Magic用户指南说明书
Manuals+— User Manuals Simplified.ANALOG DEVICES DC1019A Radio Magic User Guide Home » Analog Devices » ANALOG DEVICES DC1019A Radio Magic User GuideContents1 ANALOG DEVICES DC1019A Radio Magic2 Product Information3 Product Usage Instructions4 DESCRIPTION5 QUICK START PROCEDURE6 QUICK START GUIDE FOR DEMONSTRATION CIRCUIT1019A7 Documents / ResourcesANALOG DEVICES DC1019A Radio MagicProduct InformationThe LT3497EDDB is a dual white LED driver converter designed for driving two strings of white LEDs. It features analog dimming control and high-side current sensing. The circuit is capable of producing bright light, so caution should be taken to avoid looking directly at the operating LED, as it can damage the eyes. The LT3497 datasheet provides a complete description of the part, its operation, and application information. It should be read in conjunction with this quick start guide when working on or modifying the demo circuit 1019A. The input supply range for the demo circuit is limited by the maximum input voltage of the LT3497. Always ensure that the input voltage does not exceed 10V to prevent any damage to the circuit.Product Usage Instructions1. Set up the measurement equipment according to Figure 1.2. Place jumpers in the following positions: JP1 ON, JP2 ON.3. Ensure that the power is off, then connect the input power supply to VIN and GND.4. Turn on the power at the input, making sure that the input voltage does not exceed 10V.5. Check for proper voltages and currents. If the LEDs do not light up, verify the jumper settings.6. Once proper operations are established, adjust the input within the operating range and observe theparameters of interest.7. To test filtered PWM dimming or direct DC dimming, remove jumper JP1 or JP2, apply PWM or DC signal toSHDN/DIMMING CTRL1 or SHDN/DIMMING CTRL2, and observe the brightness of the LED output.8. For direct PWM dimming, refer to the Direct PWM Dimming section in the datasheet.Refer to Figure 2 for proper technique when measuring input or output ripple.DESCRIPTIONWARNING! Do not look directly at the operating LED.This circuit produces light that can damage the eyes.Demonstration circuit 1019A is a Dual White LED Driver Converter featuring the LT®3497 in a 3mm x 2mm DFN package. The demo circuit demonstrates a small size and low component count in two independent Boost Circuits. It drives two independent LED strings at 20mA from a 3V-10V input. Other features of the LT3497, such as the internal Schottky di-odes, the high switching frequency, and the internal open circuit protection, allow the use of tiny components. Different dimming controls can be implemented on the demo board. Optional N-MOSFET placeholders are provided to test direct PWM dimming. Analog dimming is done via the SHDN/DIMMING CONTROL terminals. Please refer to the quick start procedure. The high side current sensing feature of theLT3497 allows a “one wire” current source, i.e. the low side of the LED string can return to ground anywhere. The LT3497 datasheet gives a complete description of the part, operation, and application information. The datasheet must be read in conjunction with this quick start guide for working on or modifying the demo circuit 1019A. Design files for this circuit board are available. Call the LTC factory.LTC, LT is a registered trademark of Linear Technology CorporationTable 1. Performance Summary (TA = 25°C)SYMBO L PARAMETER CONDITIONS MIN TYP MA X UNITS VIN Input Supply Range ** 3 10V IOUT Output Current 192021mA VOUT Output Voltage 19.5 V h EfficiencyV =3.6V 72.3 %VOPEN CAP pin Over voltage Protection LED Open303234V I Quiescent CurrentV = 4.2V, CTRL=ON, LEDs open 15mA IQSHDN Quiescent Current in Shutdown V = 4.2V, CTRL=OFF 10µA FsSwitching Frequency1.82.32.8MHz** The Input Supply Range of the Demo Circuit 1019A is limited by the Maximum Input Voltage of the LT3497.Always ensure that this level is not exceeded.QUICK START PROCEDUREDemonstration circuit 1019A is easy to set up to evaluate the performance of the LT3497. Refer to Figure 1 for proper measurement equipment setup and follow the procedure below:Note : when measuring the input or output voltage ripple, care must be taken to avoid a long ground lead on the oscilloscope probe. Measure the input or output voltage ripple by touching the probe tip directly across the Vin or Vout and GND terminals. See Figure 2 for the proper scope probe technique.1. Place jumpers in the following positions to test the circuit:ON ON2. With power off, connect the input power supply to VIN and GND.3. Turn on the power at the input.Note : Make sure that the input voltage does not exceed 10V.4. Check for the proper voltages and currents.Note : If the LEDs do not light up, check the jumper settings.5. Once the proper operations are established, adjust the input within the operating range and observe the parameters of interest.6. To test the filtered PWM dimming or the direct DC dimming, remove the jumper JP1 or JP2, apply the PWM or the DC signal to the SHDN/DIMMING CTRL1 or SHDN/DIMMING CTRL2 and observe the brightness of the LED output.7. To test the direct PWM dimming, follow the Direct PWM Dimming section in the datasheet.IN Q IN INFigure 1. Proper Measurement Equipment SetupQUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1019A DUAL WHITE LED DRIVER CONVERTERLTC CONFIDENTIAL – FOR CUSTOMER USE ONLYDocuments / ResourcesANALOG DEVICES DC1019A Radio Magic [pdf] User GuideDC1019A Radio Magic, DC1019A, Radio Magic, Magic Manuals+,。
ASA10B 10 Band Audio Spectrum Analyzer 操作手册说明书
OPERATOR'S MANUALModel ASA10B10 Band Audio Spectrum AnalyzerGENERAL:The ASA10B is a ten band single octave battery operated portable audio spectrum analyzer complete with built-in microphone, an accurate dB meter and will read Sound Pressure Levels in either "A" or "C" weighting.Pink Noise: The ASA10B is often used in conjunction with a pink noise generator such as the Gold Line PN2. Pink noise is a sound that has equal amount of energy per octave of bandwidth. By inputting pink noise to a sound system you are certain that the system is receiving a flat signal source. Pink noise is the basic reference for all measurements and adjustments to a system. Pink noise normally has a flatness of ±2dB with random waves that may be higher or lower.The Controls:Input Range: In addition to turning the analyzer on and off, the INPUT RANGE switch can be set for 0dB, the normal operating range or for -20dB which increases the maximum sensitivity setting from 75dB to 55dB. Keep in mind that the displayed SPLs are actually 20dB below the INPUT SENSITIVITY switch setting when INPUT RANGE is at -20dB.Input Sensitivity: The input sensitivity of the ASA10B can be adjusted over a wide range to match many different conditions and sound pressure levels (SPL). The sensitivity of the ASA10B is controlled with the INPUT SENSITIVITY switch which provides five 10dB steps from 75dB to 115dB for a 0 reference indication.Weight Curve: The ASA10B has three frequency response functions which are selected with the WEIGHT switch. In FLAT, there is no shaping of the response curve. In "C", C type weighting is applied to the response curve, and the 31.5Hz display channel is switched to broadband showing the overall level in dBC. In "A", A type weighting is used, and the 31.5Hz channel shows overall level in dBA. "A" weighting is often used when making speech interference measurements and "C" is often used for music and environmental noise measurements.Decay Time: The DECAY switch provides three functions; FAST, SLOW and HOLD. In FAST, a response at 0dB will fall to -10dB in from 2 seconds at 31.5Hz to 0.5 seconds or less at 500Hz and above. In SLOW, the same response for 10dB is about 20 seconds at 31.5Hz, to about 6 seconds at 500Hz and above. The response to a sudden increase in level, the attack time, is short in both FAST and SLOW. When monitoring music or speech, and you want to see the rapid level changes, use FAST. When using pink noise, use SLOW for a more stable display. HOLD is used to temporarily freeze the display.The Display is a matrix of 100 LEDs: a column for each of the ten filter bands, and 10 LEDs in each column with a linear scaling with turn-on thresholds at -15, -12.5, -10, -7.5, -5, -2.5, 0, + 2.5, +5, and +7.5dB. Each row of LEDs has precise thresholds to ensure and accurate indication of sound energy in each of the bands.If using the analyzer inside under bright lighting conditions, try to position the unit to minimize the effects of any light reflections. Add some display shielding for measurements outside, but make certain not to block the microphone in the end of the analyzer.Line Input: This jack is for connecting line-level signals for analysis. A 0dB indication on the ASA10B will be obtained from 0.069millivolts to 1.10V rms (-81dBm to +3dBm), depending upon the INPUT SENSITIVITY and INPUT GAIN settings. The microphone is automatically disconnected with plug insertion. The input impedance is 10kΩfor the ASA10B. The plug type is 3.5mm.Power: The ASA10B is powered by eight AA batteries. The batteries can be either alkaline or NiCad. There is an internal selector switch. Do not use any "regular" carbon-zinc types. At a nominal 12Vdc, the current drain is about 40mA (milliamperes) with no LEDs on the display to about 80mA with an LED on each filter band. If the ASA10B is to be used in a stationary position, it will be worthwhile to power the analyzer with an external supply or battery eliminator, such as the Gold Line model BE1. (Source requirements: at least 240mA at 8-15Vdc, 12Vdc nominal. Matching plug is 2.5mm) Alkaline batteries are disconnected when a battery eliminator is plugged in. Nicads are kept in circuit and can be recharged in the case. Access to the batteries is gained by removing the four screws holding on the back cover. Replacement (or NiCad recharging) is required when there is a noticeable drop in the brightness of the LEDs in the display.GENERAL GUIDELINES FOR USEThe sound energy in each of the ten octave bands is shown simultaneously and continuously - that is RTA or Real Time Analysis. Many tests are most easily run using a pink noise source (Gold Line model PN2) which puts out equal energy across each filter band. If it is fed directly to the unit the result will be a straight-line display. With the pink noise fed through a sound system, any deviations from flat response will be shown on the analyzer. The accuracy of a reading with pink noise will be improved by mentally averaging any level variations noted. Point the analyzer at the speakers keeping it away from the body for best accuracy. If outside, or the room permits, keep at least 20 ft. away at 31.5Hz, 10 ft. away at 63Hz, etc. Room effects may prevent following these guidelines. For actual SPLs, switch the ASA10B to C/SPL, or A/SPL for levels in dBC or dBA weighting.SOUND SYSTEM EQUALIZATION: Because the ASA10B has it's own built-in microphone, you can measure the sound output from any type of sound source. The response will be shown in the ten filter-band display whether the tests are made in a room, at a club, or even outdoors. The microphone of the ASA10B is positioned clear of the end of the analyzer case to minimize shielding effects. The ½ inch microphone diameter of the ASA10B facilitates checking SPL calibration with an acoustical calibrator. The ASA10B has been calibrated by the factory - but can be field calibrated.1. Turn off the sound system before making connections, and put all tone controls, EQ etc., to their flat positions. Set volume to zero.2.Connect the noise source to a line level input to one channel only.3.Turn the amplifier system on.4. Advance the volume to a medium-high sound level. Do not overdrive.5. Set the ASA10B to SLOW decay time with low gain and turn it on.6. Take a position in the center of the listening area.7. Increase the gain of the analyzer to put the majority of the filter band responses near 0dB. Make certain the unit is pointed at the speaker. Take note of the levels in each of the octaves.8. In the lowest bands there can be great deviations from flat response caused by speaker and room characteristics. Usually it is impossible to make the changes in room shape and size that might be desirable, but changes in speaker position are usually quite feasible.9. If inside, try different speaker positions along and up and down the back wall, and also try various distances from the wall. Use the combination that gives the best result, i.e., the flattest response, especially at the low-frequency end. Move around in the listening area to see if there are measurable room effects appearing in the lowest filters. Make certain the sound level from the system is high enough to cover over the normal room ambient noise.10. The high-frequency response of the system will be greatly affected by the speaker's angular positioning-how it is pointed back and forth and also up or down. Make such adjustments as necessary for maximum output in the highest frequencies.11. After completion of the above two steps, move around in the listening area while observing the analyzer display. Take note of any large shifts in the response. Use the HOLD function to make comparisons.12.Adjust the systems equalizers, tone and tweeter controls, etc., to obtain the flattest response in the listening area. Do not try to boost out deep notches in the response, such as might be caused by a poor crossover. In general, limit the amount of boost used in order to prevent overdriving amplifiers and speakers. Do use cut to bring down peaky areas. To the extent possible, use tone controls or other broad, shelving-type EQ to minimize the need and extent of narrow-band EQ.13.Recheck system response with the analyzer, and trim adjustments for the best compromises over all the bands and all-important listening areas.14. Repeat steps 6 to 13 for the other channels.15. With both channels driven equally (balance control centered) touch up low frequency EQ for flat performance up to 250Hz.16. The liveliness of a room will have an effect on the system response, primarily in the medium and high frequencies. Rugs, stuffed furniture, drapes and people are all absorbers of sound, and acoustically dead rooms require more sound from the speakers, with a need for more boost of medium/ high frequencies.17.CAUTION: Do not use extreme amounts of bass boost with small speakers. Destruction could be the result.Try to find the best speaker to wall distance to minimize the need for the boost.ELIMINATING FEEDBACK1. Feed pink noise into a system line input, and set the gain for a medium-high level from the speakers.2. Turn up gain on the main microphone input until feedback just starts.3. With the analyzer, look for evidence of one filter band peaking above all of the others. Increase the gain if necessary.4.Adjust the equalizer to put in just enough cut in that band to stop the feedback. A parametric EQ should be set at minimum bandwidth.5.Increase the gain and continue to trim the EQ to control feedback.6.When a second feedback frequency appears, use the analyzer to determine the adjustment needed. Increase gain further, and continue to trim the EQ.7.When there is feedback appearing at three or more frequencies with further increases in gain, the practical limit of feedback control with minimum effect on the music has been reached. The adjusted system will have higher output and will be easier to operate.8.Open any other mikes that will be on at the same time, and change settings as necessary for best overall performance.9.For the final adjustment, performers should stand at the microphones in normal performing position as their proximity can cause some shift in feedback modes.TAPE RECORDER ALIGNMENT1. Clean and demagnetize all heads.2. Connect one channel of the recorder output to the analyzer EXT (AUX) LINE IN. Turn the analyzer on with decay-time switch on SLOW.3. Play a pink-noise alignment tape (This must be of high quality!) with the recorder monitor switch on Tape. Adjust analyzer gain and/or recorder output level for a display at 0dB.4. Following the recorder manufacturer's instructions, adjust the azimuth of the play head for maximum output in the 16kHz channel.5. If the display is erratic, check for proper tape wrap and head tilt. Adjust if necessary and repeat azimuth check.6. If there are play equalization adjustments, make these while observing the effects on the levels in all ten filter channels.7. Change output connections and check alignment on other tracks.8. Make play equalization adjustments similarly for all other tracks.9. Repeat steps 2 to 8 for other tape speeds if necessary.10. If a pink noise alignment tape is not available, a discrete-tone test tape can be used, although it will be less convenient. Just use whichever analyzer channel covers the tone on the tape.11. Select tape type and length most frequently used, and set the bias and EQ switches to correspond. Select tape speed.12. Feed pink-noise to the recorder line input. Set record level to -10 VU for open-reel recorders at 7½ ips and to 20dB below Dolby reference level for cassette decks.13. If the unit is a three-head machine, record the pink noise, and simultaneously monitor the playback output with the analyzer. First, adjust the record head azimuth for maximum output in the 16kHz band. If the bias is adjustable, reduce it to near minimum and then increase it slowly. Stop where the outputs in the 500Hz and 1kHz bands reach a maximum. Trim the high-end response with record equalization, if possible. A fine bias adjustment can be made to get the best overall record/playback response.14. Check the results on other tracks, making necessary adjustments.15.Repeat adjustments for other tape speeds and tape types, if need be.16. If the recorder is a two-head unit, the approach is similar, but it is necessary to record, rewind and play after each adjustment is made. Make small changes to facilitate removing any errors made.17. If the heads are worn, the responses may be down noticeably at 16kHz. Even so, you will still want to adjust the heads for the maximum output. However, Bias and EQ adjustments will provide limited correction in this case. Do not reduce bias so much as to decrease the 500Hz level (and increase distortion) in an effort to try to force the high end up.18. You will find that alignment with the analyzer and pink noise is much faster and better than other methods. Dolby tracking is also very easy to check with the analyzer.OTHER EQUIPMENT TESTS: By using the line input capability of the analyzer, sometimes in combination with measurements with the microphone, it is possible to pin down the response of tone controls and equalizers before feeding to the loudspeakers. Looking at the output of preamps, mixers and other line level devices is very easy with the ASA10B analyzer. It is also possible to connect the analyzer to the output of a power amplifier, but BE CAREFUL! First of all, make any connections with the power amplifier turned off. Make certain that the amplifier, or the control section feeding it, is set to minimum gain. Power amplifiers can put out voltages that are much higher than the maximum level handled by the analyzers, so extra caution is in order. Set the analyzer sensitivity to minimum; increase amplifier gain very slowly until the display is close to 0dB, where further adjustments can be made.SPECIFICATIONSMEASUREMENT RANGE: Microphone input : 40dB - 122dB SPLLine input: -81dBm to +3dBm(.069mV to 1.10V rms)INPUTS: Microphone: Built-in omnidirectional electret condenser.Line: Unbalanced 3.5mm jack. 10kΩ impedanceSENSITIVITY SWITCH: 5 position 10dB / step attentuator .INPUT RANGE SWITCH: 0dB or -20dBCENTER FREQUENCIES (Hz): ISO 31.5, 63, 125, 250, 500, 1k, 2k, 4k, 8k,16kCENTER FREQUENCY ACCURACY: Typically ±3%FILTERS: ANSI Class IIRELATIVE FLATNESS CHANNEL TO CHANNEL:±1.0dBWEIGHTING: IEC A, C and FLAT.DECAY RATE @ 500Hz: SLOW 2.2dB/s, FAST 18dB/s. HOLD for short durationdisplay freeze.POWER REQUIREMENTS:Batteries - Eight AA alkaline or nicad.********************************Internal switch must be set to NICAD when recharging NICAD batteries.SIZE (W x H x D); WEIGHT: 3¼" x 8" x 2¼"; 12 oz.CASE MATERIAL: High impact ABSEnter your serial#_______________ date of purchase________________10-68 m_10b_2h22.docWARRANTY and Factory ServiceGOLD LINE products are proudly made in the USA and are covered by a one year limited warranty. For details of this warranty, consult the enclosed warranty registration card or your local dealer.GOLD LINE Customer Service will help you get the most from your new analyzer. For answers to questions regarding use of the unit, or for information not covered in this manual, please write us. If you are experiencing difficulties with your analyzer, please consult your dealer regarding factory service. If factory service is needed, you may call or fax us between 9:00am and 4:30pm US Eastern Time for instructions and a return authorization.Box 500 West Redding, CT. 06896203-938-2588 phone - 203-938-8740 faxhttp://******************************************。
Kingbright DSAC2643绿色LED说明书
DESCRIPTIONzThe Green source color devices are made with Gallium Phosphide Green Light Emitting DiodeFEATURESzLow power consumptionz Popular T-1 diameter package z General purpose leads z Reliable and ruggedz Long life - solid state reliability z Available on tape and reel z RoHS compliantAPPLICATIONSz Status indicator z Illuminatorz Signage applicationsz Decorative and entertainment lightingzCommercial and residential architectural lightingPACKAGE DIMENSIONSL-7104LGDT-1 (3mm) Solid State LampNotes:1. All dimensions are in millimeters (inches).2. Tolerance is ±0.25(0.01") unless otherwise noted.3. Lead spacing is measured where the leads emerge from the package.4. The specifications, characteristics and technical data described in the datasheet are subject to change without prior notice.SELECTION GUIDEPart Number Emitting Color(Material)Lens TypeIv (mcd) @ 2mA [2] Viewing Angle [1]Min.Typ.2θ1/2L-7104LGD■ Green (GaP)Green Diffused 1 50°3 Notes:1. θ1/2 is the angle from optical centerline where the luminous intensity is 1/2 of the optical peak value.2. Luminous intensity / luminous flux: +/-15%.3. Luminous intensity value is traceable to CIE127-2007 standards.Ki n gbParameterSymbol Value Unit Power Dissipation P D 62.5 mW Reverse Voltage V R 5 V Junction Temperature T j 110 °C Operating Temperature T op -40 To +85 °C Storage Temperature T stg -40 To +85°C DC Forward Current I F 25 mA Peak Forward CurrentI FM [1]140 mA Electrostatic Discharge Threshold (HBM) -8000 V Thermal Resistance (Junction / Ambient) R th JA [2] 650 °C/W Thermal Resistance (Junction / Solder point) R th JS [2]315°C/WLead Solder Temperature [3] 260°C For 3 Seconds Lead Solder Temperature [4]260°C For 5 SecondsABSOLUTE MAXIMUM RATINGS at T A =25°CELECTRICAL / OPTICAL CHARACTERISTICS at T A =25°CParameterSymbol Emitting ColorValue Unit Typ. Max. Wavelength at Peak Emission I F = 2mA λpeak Green 565 - nm Dominant Wavelength I F = 2mA λdom [1] Green 568 - nm Spectral Bandwidth at 50% Φ REL MAX I F = 2mA Δλ Green 30 - nm CapacitanceC Green 15 - pF Forward Voltage I F = 2mA V F [2] Green 2 2.25 V Reverse Current (V R = 5V)I RGreen-10uANotes:1. The dominant wavelength (λd) above is the setup value of the sorting machine. (Tolerance λd : ±1nm. )2. Forward voltage: ±0.1V.3. Wavelength value is traceable to CIE127-2007 standards.4. Excess driving current and / or operating temperature higher than recommended conditions may result in severe light degradation or premature failure.Notes:1. 1/10 Duty Cycle, 0.1ms Pulse Width.2. R t h JA ,R t h JS Results from mounting on PC board FR4 (pad size ≥ 16 mm 2 per pad).3. 2mm below package base.4. 5mm below package base.5. Relative humidity levels maintained between 40% and 60% in production area are recommended to avoid the build-up of static electricity – Ref JEDEC/JESD625-A and JEDEC/J-STD-033.Ki n g b r i g h tTECHNICAL DATAGREENRECOMMENDED WAVE SOLDERING PROFILENotes:1. Recommend pre-heat temperature of 105°C or less (as measured with a thermocoupleattached to the LED pins) prior to immersion in the solder wave with a maximum solder bathtemperature of 260°C2. Peak wave soldering temperature between 245°C ~ 255°C for 3 sec (5 sec max).3. Do not apply stress to the epoxy resin while the temperature is above 85°C.4. Fixtures should not incur stress on the component when mounting and during soldering process.5. SAC 305 solder alloy is recommended.6. No more than one wave soldering pass.PACKING & LABEL SPECIFICATIONSPRECAUTIONSStorage conditions1. Avoid continued exposure to the condensing moisture environment and keep the product away from rapid transitions in ambient temperature.2. LEDs should be stored with temperature ≤ 30°C and relative humidity < 60%.3. Product in the original sealed package is recommended to be assembled within 72 hours of opening. Product in opened package for more than a week should be baked for 30 (+10/-0) hours at 85 ~ 100°C.2. When soldering wires to the LED, each wire joint should be separately insulated with heat-shrink tube to prevent short-circuit contact.Do not bundle both wires in one heat shrink tube to avoid pinching the LED leads. Pinching stress on the LED leads may damage the internal structures and cause failure.3. Use stand-offs (Fig.1) or spacers (Fig.2) to securely position the LED above the PCB.4. Maintain a minimum of 3mm clearance between the base of the LED lens and the first lead bend (Fig. 3 ,Fig. 4).5. During lead forming, use tools or jigs to hold the leads securely so that the bending force will not be transmitted to the LED lens and its internal structures. Do not perform lead forming once the component has been mounted onto the PCB. (Fig. 5 )LED Mounting Method1. The lead pitch of the LED must match the pitch of the mounting holes on the PCB during component placement.Lead-forming may be required to insure the lead pitch matches the hole pitch.Refer to the figure below for proper lead forming procedures.Note 1-3: Do not route PCB trace in the contact area between the leadframe and the PCB to prevent short-circuits." ○" Correct mounting method " x " Incorrect mounting methodKi gb htLead Forming Procedures1. Do not bend the leads more than twice. (Fig. 6 )2. During soldering, component covers and holders should leave clearance to avoid placing damaging stress on the LED during soldering. (Fig. 7)3. The tip of the soldering iron should never touch the lens epoxy.4. Through-hole LEDs are incompatible with reflow soldering.5. If the LED will undergo multiple soldering passes or face other processes where the part may be subjected to intense heat, please check with Kingbright for compatibility.PRECAUTIONARY NOTES1. The information included in this document reflects representative usage scenarios and is intended for technical reference only.2. The part number, type, and specifications mentioned in this document are subject to future change and improvement without notice. Before production usage customer should refer tothe latest datasheet for the updated specifications.3. When using the products referenced in this document, please make sure the product is being operated within the environmental and electrical limits specified in the datasheet. Ifcustomer usage exceeds the specified limits, Kingbright will not be responsible for any subsequent issues.4. The information in this document applies to typical usage in consumer electronics applications. If customer's application has special reliability requirements or have life-threateningliabilities, such as automotive or medical usage, please consult with Kingbright representative for further assistance.5. The contents and information of this document may not be reproduced or re-transmitted without permission by Kingbright.6. All design applications should refer to Kingbright application notes available at /application_notesKi n gb ri g ht。
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II. AMPLIFIER ARCHITECTURE AND CIRCUIT DESIGN
An AGC amplifier architecture bas a jitter advantage. and it provides increased flexibility by allowing a dynamic tradeoff between gain and bandwidth. A block diagram of the postamplifier is shown in Fig. I .
Fig. 1.
AGC amplifier architecture.
The signal path is fully differential and consists of a low-noise input stage with a constant gain followed by three VGA stages independently controlled by an AGC circuit. Due to a high maximum gain of the amplifier, an offset cancellation loop is provided to compensate for device mismatches induced by process variations.
Abslrorl A 10Gb/s automatic gain control amplifier for use in optical receivers was implemented in a SiGe pmeess with f, = 4SCHz. Active peaking techniques were used to achieve a maximum gain of 48dB with 7.8GHz of bandwidth. The amplifier demonstrates less thuo 0.5dB of peak-to.peak output amplitude variation over a 50dB input amplitude range. It consumes 30mW o f power from a 3.3V supply and remains functional at voltages as low as 2 . 1 V . The amplifier core occupies O.lmm’ and requires no external components. Ider Termr - Optical communication, optical remivcrs, broadband amplifiers, gain control, BiCMOS integrated circuits.
A Low-Power lOGb/s AGC Optical Postamplifier in SiGe
Daniel Kucharski and Kevin T. Kornegay
Cornell Broadband Communications Research Laboratory Cornell University, 330 Phillips Hall, Ithaca, NY, 14853
25
0-7803-8333-8/04/$20.00 0 2004 IEEE
2004 IEEE Radio Frequency Integmee
A schematic diagram of the input stage is shown in Fig. 2. To avoid loading of the TIA, the input is buffered with emitter followers QI driving a differential pair Q2. The input stage was optimized for low noise performance and has a constant gain of 15dB.
level using a feedback loop to adjust gain. LAs are a popular choice for optical receivers due to their relative simplicity. However, 3 variable gain amplifier (VGA) with AGC offers certain advantages. First, it maintains gain stages in their linear region to achieve a linear phase response and low deterministic jitter. Second, the AGC reduces the gain when presented with a large input signal, which avoids excessive noise amplification during signal transitions and reduces random jitter compared to an LA with the same maximum gain. Low jitter is very important for CDR operation, because non-return to zero ( N U )data has no energy at the clock frequency, and the clock must be recovered from data transitions. The remainder of this paper is organized as follows. Amplifier architecture and circuit design are presented in 1 , while fabrication details and experimental section 1 results are presented in sections I11 and 1V respectively.
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1. INTROOUCTION
Data rates in optical communication systems are limited by the speed of available optoelectronic devices such as lasers and photodetectors as well as their electrical interfaces. This is particularly true for short-distance applications where dispersion and attenuation in optical fibers are secondary. Parallel data links can be used to increase data throughput and achieve very high aggregate data rates. However, to make such links economically feasible requires a high level of integration and area efficient design leading to high circuit density. Such circuits also benefit from low power consumption, which alleviates power dislribution and heat dissipation problems and simplifies array implementation. A signal path of an optical receiver begins with a photodetector, which produces a current that is proportional to the incident optical power. The photocurrent is subsequently amplified and converted to voltage by a transimpedance amplifier WA). However, a typical TIA is a single stage circuit with limited gain and an output amplitude on the order of a few tens of millivolts, which can vary over a wide range due lo variations in the transmitter’s output power as well as optical losses. Clock and data recovery (CDR) requires consistent, large signal levels to minimize bit error rate (BER). Consequently, a postamplifer is required with a high gain, a wide dynamic range, and a constant output swing. These requirements can be satisfied with a limiting amplifier (LA) or an automatic gain control (AGC) amplifier. An LA is designed to saturate at the desired signal level, while an AGC amplifier maintains the signal