B8049NL;中文规格书,Datasheet资料
Datasheet MLX90614 中文 数据手册 rev008
3901090614 Rev 008
第 2 / 52 页
数据手册 2013/2/28
应用实例
高精度非接触式温度测量 用于车用空调控制系统的温度舒适度传感器 住宅、商业和工业建筑的空调温度感应 挡风玻璃的除雾 汽车视野死角监测 工业上移动部件温度监测 打印机、复印机的温度控制 家电的温度控制单元 医疗保健 牲畜监控 移动物体的探测 多区域温度控制 – 2 线通信，读取多达 127 个
PWM 引脚也可配置为热继电器(输入是 To)，这样可以实现简单且性价比高的恒温控制器或温度报警(冰 点/沸点)应用，其中的温度临界值是用户可编程的。在 SMBus 系统里，这个功能可以作为处理器的中断信号， 以此触发读取主线上从动器的值，并确定精度条件。
传感器有两种供电电压选择：5V 或 3V(电池供电)。其中，5V 也可简便的从更高供电电压(例如 8 至 16V)上通过外接元件调制。(具体请参考“应用信息”)
第 1 / 52 页
数据手册 2013/2/28
LX90614 系列
单区视场和双区视场 TO-39 封装 红外温度传感器
概述(续)
MLX90614 集成了由 Melexis 研发生产的两款芯片： 红外热电堆探测器 MLX81101 专用信号处理芯片 MLX90302，专用于处理红外传感器的输出信号
传感器的测量结果均出厂校准化，数据接口为数字式的 PWM 和 SMBus(System Management Bus) 输出。
作为标准，PWM 为 10 位，且配置为-20˚C 至 120 ˚C 内，分辨率为 0.14 ˚C 的连续输出。
W947D6HBHX5E;W947D2HBJX5E;中文规格书,Datasheet资料
TABLE OF CONTENTS1. GENERAL DESCRIPTION (4)2. FEATURES (4)3. PIN CONFIGURATION (5)3.1 Ball Assignment: LPDDR X16 (5)3.2 Ball Assignment: LPDDR X32 (5)4. PIN DESCRIPTION (6)4.1 Signal Descriptions (6)4.2 Addressing Table (7)5. BLOCK DIAGRAM (8)5.1 Block Diagram (8)5.2 Simplified State Diagram (9)6. FUNCTION DESCRIPTION (10)6.1 Initialization (10)6.1.1 Initialization Flow Diagram (11)6.1.2 Initialization Waveform Sequence (12)6.2 Register Definition (12)6.2.1 Mode Register Set Operation (12)6.2.2 Mode Register Definition (13)6.2.3. Burst Length (13)6.3 Burst Definition (14)6.4 Burst Type (15)6.5 Read Latency (15)6.6 Extended Mode Register Description (15)6.6.1 Extended Mode Register Definition (16)6.7 Status Register Read (16)6.7.1 SRR Register (A[n:0] = 0) (17)6.7.2 Status Register Read Timing Diagram (18)6.8 Partial Array Self Refresh (19)6.9 Automatic Temperature Compensated Self Refresh (19)6.10 Output Drive Strength (19)6.11 Commands (19)6.11.1 Basic Timing Parameters for Commands (19)6.11.2 Truth Table - Commands (20)6.11.3 Truth Table - DM Operations (21)6.11.4 Truth Table - CKE (21)6.11.5 Truth Table - Current State BANKn - Command to BANKn (22)6.11.6 Truth Table - Current State BANKn, Command to BANKn (23)7. OPERATION (24)7.1. Deselect (24)7.2. No Operation (24)7.2.1 NOP Command (25)7.3 Mode Register Set (25)7.3.1 Mode Register Set Command (25)7.3.2 Mode Register Set Command Timing (26)7.4. Active (26)7.4.1 Active Command (26)7.4.2 Bank Activation Command Cycle (27)7.5. Read (27)7.5.1 Read Command (28)7.5.2 Basic Read Timing Parameters (28)7.5.3 Read Burst Showing CAS Latency (29)7.5.4 Read to Read (29)7.5.5 Consecutive Read Bursts (30)7.5.6 Non-Consecutive Read Bursts (30)7.5.7 Random Read Bursts (31)7.5.8 Read Burst Terminate (31)7.5.9 Read to Write (32)7.5.10 Read to Pre-charge (32)7.5.11 Burst Terminate of Read (33)7.6 Write (33)7.6.1 Write Command (34)7.6.2 Basic Write Timing Parameters (34)7.6.3 Write Burst (min. and max. tDQSS) (35)7.6.4 Write to Write (35)7.6.5 Concatenated Write Bursts (36)7.6.6 Non-Consecutive Write Bursts (36)7.6.7 Random Write Cycles (37)7.6.8 Write to Read (37)7.6.9 Non-Interrupting Write to Read (37)7.6.10 Interrupting Write to Read (38)7.6.11 Write to Precharge (38)7.6.12 Non-Interrupting Write to Precharge (38)7.6.13 Interrupting Write to Precharge (39)7.7 Precharge (39)7.7.1 Precharge Command (40)7.8 Auto Precharge (40)7.9 Refresh Requirements (40)7.10 Auto Refresh (40)7.10.1 Auto Refresh Command (41)7.11 Self Referesh (41)7.11.1 Self Refresh Command (42)7.11.2 Auto Refresh Cycles Back-to-Back (42)7.11.3 Self Refresh Entry and Exit (43)7.12 Power Down (43)7.12.1 Power-Down Entry and Exit (43)7.13 Deep Power Down (44)128Mb Mobile LPDDR7.13.1 Deep Power-Down Entry and Exit (44)7.14 Clock Stop (45)7.14.1 Clock Stop Mode Entry and Exit (45)8. ELECTRICAL CHARACTERISTIC (46)8.1 Absolute Maximum Ratings (46)8.2 Input/Output Capacitance (46)8.3 Electrical Characteristics and AC/DC Operating Conditions (47)8.3.1 Electrical Characteristics and AC/DC Operating Conditions (47)8.4 IDD Specification Parameters and Test Conditions (48)8.4.1 IDD Specification Parameters and Test Conditions (48)8.5 AC Timings (51)8.5.1 CAS Latency Definition (With CL=3) (54)8.5.2 Output Slew Rate Characteristics (55)8.5.3 AC Overshoot/Undershoot Specification (55)8.5.4 AC Overshoot and Undershoot Definition (55)9. PACKAGE DIMENSIONS (56)9.1: LPDDR X 16 (56)9.2: LPDDR X 32 (57)10. ORDERING INFORMATION (58)11. REVISION HISTORY (59)1. GENERAL DESCRIPTIONW947D6HB / W947D2HB is a high-speed Low Power double data rate synchronous dynamic random access memory (LPDDR SDRAM), An access to the LPDDR SDRAM is burst oriented. Consecutive memory location in one page can be accessed at a burst length of 2, 4, 8 and 16 when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the LPDDR SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the pre-charging time. By setting programmable Mode Registers, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. The device supports special low power functions such as Partial Array Self Refresh (PASR) and Automatic Temperature Compensated Self Refresh (ATCSR).2. FEATURESVDD = 1.7~1.95VVDDQ = 1.7~1.95V;Data width: x16 / x32Clock rate: 200MHz(-5),166MHz(-6),133MHz(-75)Partial Array Self-Refresh(PASR)Auto Temperature Compensated Self-Refresh(ATCSR) Power Down ModeDeep Power Down Mode (DPD Mode)Programmable output buffer driver strengthFour internal banks for concurrent operationData mask (DM) for write dataClock Stop capability during idle periodsAuto Pre-charge option for each burst accessDouble data rate for data outputDifferential clock inputs (CK and C K)Bidirectional, data strobe (DQS)C AS Latency: 2 and 3Burst Length: 2, 4, 8 and 16Burst Type: Sequential or Interleave 64 ms Refresh periodInterface: LVCMOS compatibleSupport package:Operating Temperature Range :3. PIN CONFIGURATION3.1 Ball Assignment: LPDDR X16(Top View) Pin Configuration 3.2 Ball Assignment: LPDDR X32(Top View) Pin Configuration4. PIN DESCRIPTION 4.1 Signal Descriptions4.2 Addressing Table5. BLOCK DIAGRAM 5.1 Block Diagram5.2 Simplified State Diagram6. FUNCTION DESCRIPTION6.1 InitializationLPDDR SDRAM must be powered up and initialized in a predefined manner. Operations procedures other than those specified may result in undefined operation. If there is any interruption to the device power, the initialization routine should be followed. The steps to be followed for device initialization are listed below.The Mode Register and Extended Mode Register do not have default values. If they are not programmed during the initialization sequence, it may lead to unspecified operation. The clock stop feature is not available until the device has been properly initialized from Step 1 through 11.●Step 1: Provide power, the device core power (VDD) and the device I/O power (VDDQ) must be brought upsimultaneously to prevent device latch-up. Although not required, it is recommended that VDD and VDDQ are from the same power source. Also Assert and hold Clock Enable (CKE) to a LVCMOS logic high level ●Step 2: Once the system has established consistent device power and CKE is driven high, it is safe to applystable clock.●Step 3: There must be at least 200μs of valid clocks before any command may be given to the DRAM. During thistime NOP or DESELECT commands must be issued on the command bus.●Step 4: Issue a PRECHARGE ALL command.●Step 5: Provide NOPs or DESELECT commands for at least tRP time.●Step 6: Issue an AUTO REFRESH command followed by NOPs or DESELECT command for at least tRFC time.Issue the second AUTO REFRESH command followed by NOPs or DESELECT command for at least tRFC time. Note as part of the initialization sequence there must be two Auto Refresh commands issued.The typical flow is to issue them at Step 6, but they may also be issued between steps 10 and 11.●Step 7: Using the MRS command, program the base mode register. Set the desired operation modes.●Step 8: Provide NOPs or DESELECT commands for at least tMRD time.●Step 9: Using the MRS command, program the extended mode register for the desired operating modes. Note theorder of the base and extended mode register programmed is not important.●Step 10: Provide NOP or DESELECT commands for at least tMRD time.●Step 11: The DRAM has been properly initialized and is ready for any valid command.分销商库存信息:WINBONDW947D6HBHX5E W947D2HBJX5E。
B82793S0513N201;B82793C475N265;中文规格书,Datasheet资料
Data and signal line chokesCommon-mode chokes, ring core0.005 … 47 mH, 100 … 1200 mA, 60 °CSeries/Type:B82793C0/S0Date:July 2010¤ EPCOS AG 2010. Reproduction, publication and dissemination of this publication, enclosures hereto and the information contained therein without EPCOS’ prior express consent is prohibited.Rated voltage 42 V AC/80 V DCRated inductance 0.005 mH to 47 mH Rated current 100 mA to 1200 mA Construction■Current-compensated double choke ■Ferrite core■LCP case (UL 94 V-0), silicone potting ■Bifilar winding (B82793C0)■Sector winding (B82793S0)Features■High rated currents, reduced components height ■Qualified to AEC-Q200 (L d 4.7 mH)■Suitable for reflow soldering ■RoHS-compatibleFunction■B82793C0:Suppression of asymmetrical interference coupled in on lines,whereas data signals up to some MHz can pass unaffectedly.■B82793S0:Suppression of asymmetrical and symmetrical interference (by L stray )coupled in on lines. The high-frequency portions of the symmetrical data signal are decreased so far that EMC problems can be significantly reduced.Applications■Automotive applications, e.g. CAN bus ■Industrial applications■Types with L R ! 4.7 mH only for telecom applicationsTerminals■Base material CuSn6■Layer composition Ni, Sn ■Hot-dippedMarking■Marking on component: Manufacturer, process location (coded),winding method (coded), ordering code (short form), date of manufacture (YWWD)■Minimum data on reel: Manufacturer, ordering code,L value and tolerance, quantity, date of packing Delivery mode and packing unit■16-mm blister tape, wound on 330-mm reel ■Packing unit: 1500 pcs./reel Common-mode chokes, ring coreDimensional drawing and pin configurationLayout recommendationTaping and packing Blister tapeReelDimensions in mmDimensions in mmCommon-mode chokes, ring coreCommon-mode chokes, ring coreTechnical data and measuring conditionsRated voltage V R42 V AC (50/60 Hz) / 80 V DCRated temperature T R60 °CRated current I R Referred to 50 Hz and rated temperatureRated inductance L R Measured with Agilent 4284A, 0.1 mA, 20 °CMeasuring frequency:L R d 1 mH = 100 kHzL R! 1 mH = 10 kHzInductance is specified per winding.Inductance tolerance r30% (L R d0.47mH), –30/+50% (L R t1mH) at 20 °C Inductance decrease 'L/L 10% at DC magnetic bias with I R, 20 °CStray inductance L stray,typ Measured with Agilent 4284A, 5 mA, 20 °C, typical valuesMeasuring frequency:L R d 11 P H = 1 MHzL R! 11 P H = 100 kHzDC resistance R typ Measured at 20q C, typical values, specified per winding Solderability SnPb:(215 r3) °C, (3 r0.3) sSn96.5Ag3.0Cu0.5:(245 r5) °C, (3 r0.3) sWetting of soldering area t 95%(to IEC 60068-2-58)Resistance to soldering heat(260 r5) °C, (10 r1) s (to IEC 60068-2-58)Climatic category 40/125/56 (to IEC 60068-1)Storage conditions (packaged)–25 °C … +40 °C, d 75% RHWeight Approx. 0.25 gCharacteristics and ordering codes Sample kit available. Ordering code: B82793X001.For more information refer to chapter “Sample kits”.L R mH L stray,typ nH I R mA R typ m :V test V DC, 2 s Ordering code 0.005 40120060250B82793C0502N2010.011 50 80080250B82793C0113N2010.025 60 800110250B82793C0253N2010.0251400 800110250B82793S0253N2010.051 70 800140250B82793C0513N2010.0512300 800140250B82793S0513N2010.10 100 500180250B82793C0104N2010.47 100 700170750B82793C0474N2151.0 70 700140750B82793C0105N2652.2 120 500400750B82793C0225N2654.7 250 400550750B82793C0475N265For telecommunications203001001800750B82793C0206N2654712001003700750B82793C0476N265Common-mode chokes, ring coreInsertion loss D (typical values at |Z| = 50 :, 20 °C)asymmetrical, all branches in parallel (common mode)symmetrical (differential mode)L R = 0.005 mHL R = 0.025 mH (low L stray)L R = 0.011 mHL R = 0.025 mH (high L stray)Common-mode chokes, ring coreInsertion loss D (typical values at |Z| = 50 :, 20 °C)asymmetrical, all branches in parallel (common mode)symmetrical (differential mode)L R = 0.051 mH (low L stray) L R = 0.10 mH L R = 0.051 mH (high L stray) L R = 0.47 mHCommon-mode chokes, ring coreInsertion loss D (typical values at |Z| = 50 :, 20 °C)asymmetrical, all branches in parallel (common mode)symmetrical (differential mode)L R =1.0 mH L R = 4.7 mH L R = 2.2 mH L R = 20 mHCommon-mode chokes, ring coreInsertion loss D (typical values at |Z| = 50 :, 20 °C)asymmetrical, all branches in parallel (common mode)symmetrical (differential mode)L R = 47 mH Current derating I op/I R versus ambient temperatureCommon-mode chokes, ring coreRecommended reflow soldering curvePb containing solder material (based on CECC 00802 edition 2)Pb-free solder material (based on JEDEC J-STD 020C)Time from 25 °C to T 4: max 300 s Maximal numbers of reflow cycles: 3T 1°C T 2°C T 3°C T 4°C t 1s t 2s t 3s150200217250< 110< 90< 40 @ T 4 –5 °CCommon-mode chokes, ring core分销商库存信息:EPCOSB82793S0513N201B82793C475N265。
IXYB82N120C3H1;中文规格书,Datasheet资料
CES I C110= 82A V CE(sat) ≤ 3.2V t fi(typ)= 93nsHigh-Speed IGBTfor 20-50 kHz SwitchingFeaturesz Optimized for Low Switching Losses zSquare RBSOA zAnti-Parallel Ultra Fast Diode zPositive Thermal Coefficient of Vce(sat)zAvalanche Rated zHigh Current Handling Capability zInternational Standard PackageAdvantagesz High Power DensityzLow Gate Drive RequirementApplicationsz High Frequency Power Inverters z UPSz Motor Drives z SMPSz PFC Circuits z Battery Chargers z Welding Machines zLamp BallastsSymbol Test Conditions Characteristic Values (T J = 25°C, Unless Otherwise Specified) Min. Typ. Max.BV CES I C = 250μA, V GE = 0V 1200 VV GE(th)I C= 250μA, V CE = V GE3.05.0VI CES V CE = V CES , V GE = 0V50μA T J = 125°C 3 mA I GES V CE = 0V, V GE = ±20V±100 nAV CE(sat)I C = 82A, V GE = 15V, Note 12.753.20 V T J = 125°C3.50 VSymbol Test ConditionsMaximum Ratings V CES T J = 25°C to 150°C1200V V CGR T J = 25°C to 150°C, R GE = 1M Ω 1200V V GES Continuous ±20V V GEM Transient ±30V I C25T C = 25°C 160A I C110T C = 110°C 82A I F110T C = 110°C 42A I CM T C= 25°C, 1ms 320AI A T C = 25°C 41 A E AST C = 25°C 800 mJSSOA V GE = 15V, T VJ = 125°C, RG = 2Ω I CM = 164A (RBSOA) Clamped Inductive Load @V CE ≤ V CES P C T C = 25°C1040W T J -55 ... +150°C T JM 150°C T stg -55 ... +150°CT LMaximum Lead Temperature for Soldering 300°CT SOLD 1.6 mm (0.062in.) from Case for 10s 260°CF C Mounting Force 30..120 / 6.7..27N/lb.Weight10g1200V XPT TM IGBT GenX3TM w/ DiodeG = Gate C = Collector E = EmitterTab = CollectorEPLUS264TMG CIXYS Reserves the Right to Change Limits, Test Conditions, and Dimensions.Symbol Test Conditions (T J = 25°C Unless Otherwise Specified)fs I C = 60A, V CE = 10V, Note 1 30 50C ie sC oes V CE = 25V, V GE C resQ g(on)Q ge I C = 82A, V GE = 15V, V Q gc d(on)Pin 1 = Gate Pin 2,4 = Emitter Pin 3 = CollectorNotes:1. Pulse test, t ≤ 300μs, duty cycle, d ≤ 2%.2. Switching times & energy losses may increase for higher V CE (clamp), T J or R G .Reverse Diode (FRED)Symbol Test ConditionsCharacteristic ValuesFig. 1. Output Characteristics @ T 6080100120140160I C - A m p e r e sIXYS Reserves the Right to Change Limits, Test Conditions, and Dimensions.Fig. 7. Transconductance304050607080g f s - S i e m e n sFig. 12. Inductive Switching Energy Loss vs.Gate Resistance345678E o f f - M i l l i J o u l e sE off E on - - - - T J = 125ºC , V GE = 15V V CE = 600VIXYS Reserves the Right to Change Limits, Test Conditions, and Dimensions.Fig. 18. Inductive Turn-on Switching Times vs.Gate Resistance6080100120140160r i - N a n o s e c o n d st r i t d(on) - - - -T J = 125ºC, V GE = 15V V CE = 600VI CFig. 21.Fig. 22.Fig. 23.Fig. 24.Fig. 25.Fig. 26. transient thermal impedance分销商库存信息: IXYSIXYB82N120C3H1。
FDS8949;中文规格书,Datasheet资料
tmOctober 2006FDS8949 Dual N-Channel Logic Level PowerTrench®MOSFET FDS8949Dual N-Channel Logic Level PowerTrench® MOSFET40V, 6A, 29mΩFeaturesMax r DS(on)= 29mΩ at V GS = 10VMax r DS(on)= 36mΩ at V GS = 4.5VLow gate chargeHigh performance trench technology for extremely lowr DS(on)High power and current handling capabilityRoHS compliantGeneral DescriptionThese N-Channel Logic Level MOSFETs are producedusing Fairchild Semiconductor’s advancedPowerTrench® process that has been especially tailoredto minimize the on-state resistance and yet maintainsuperior switching performance.These devices are well suited for low voltage andbattery powered applications where low in-line powerloss and fast switching are required.ApplicationsInverterPower suppliersMOSFET Maximum Ratings TA = 25°C unless otherwise notedThermal CharacteristicsPackage Marking and Ordering InformationSymbol Parameter Ratings UnitsV DS Drain to Source Voltage40VV GS Gate to Source Voltage±20VI DDrain Current -Continuous (Note 1a)6A -Pulsed 20E AS Drain-Source Avalanche Energy (Note 3)26mJP DPower Dissipation for Dual Operation 2W Power Dissipation for Single Operation (Note 1a)(Note 1b)1.60.9T J, T STG Operating and Storage Junction Temperature Range-55 to 150°CRθJA Thermal Resistance-Single operation, Junction to Ambient (Note 1a)81°C/WRθJA Thermal Resistance-Single operation, Junction to Ambient (Note 1b)135RθJC Thermal Resistance, Junction to Case (Note 1)40Device Marking Device Reel Size Tape Width Quantity FDS8949FDS894913’’12mm2500 unitsPin 1SO-8D1D1D2D2S2S1G1G2FDS8949 Dual N-Channel Logic Level PowerTrench ® MOSFETElectrical Characteristics TJ = 25°C unless otherwise notedSymbolParameterTest ConditionsMinTypMaxUnitsOff Characteristics BV DSS Drain to Source Breakdown Voltage I D = 250µA, V GS = 0V 40 V ∆BV DSS ∆T J Breakdown Voltage Temperature CoefficientI D = 250µA, referenced to 25°C33mV/°C I DSS Zero Gate Voltage Drain Current V DS = 32V, V GS = 0V1µA T J = 55°C10µA I GSSGate to Source Leakage CurrentV GS = ±20V,V DS = 0V±100nAOn Characteristics V GS(th)Gate to Source Threshold Voltage V GS = V DS , I D = 250µA 1 1.93V ∆V GS(th) ∆T J Gate to Source Threshold Voltage Temperature Coefficient I D = 250µA, referenced to 25°C -4.6 mV/°Cr DS(on)Drain to Source On Resistance V GS = 10V, I D = 6A2129m ΩV GS = 4.5V, I D = 4.5A 2636V GS = 10V, I D = 6A,T J = 125°C 2943g FSForward TransconductanceV DS = 10V,I D = 6A22S (Note 2)Dynamic CharacteristicsC iss Input Capacitance V DS = 20V, V GS = 0V,f = 1MHz 715955pF C oss Output Capacitance105140pF C rss Reverse Transfer Capacitance6090pF R gGate Resistancef = 1MHz1.1ΩSwitching Characteristicst d(on)Turn-On Delay Time V DD = 20V, I D = 1A V GS = 10V, R GEN = 6Ω918ns t r Rise Time510ns t d(off)Turn-Off Delay Time 2337ns t f Fall Time36ns Q g Total Gate ChargeV DS = 20V, I D = 6A,V GS = 5V 7.711nC Q gs Gate to Source Gate Charge 2.4nC Q gdGate to Drain “Miller”Charge2.8nCDrain-Source Diode Characteristics V SD Source to Drain Diode Forward Voltage V GS = 0V, I S = 6A (note 2) 0.8 1.2V t rr Reverse Recovery Time (note 3)I F = 6A, d iF /d t = 100A/µs1726ns Q rrReverse Recovery Charge711nCand Maximum RatingsNotes:1: R θJA is the sum of the junction-to-case and case-to- ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R θJC is guaranteed by design while R θJA is determined by the user’s board design.2: Pulse Test: Pulse Width < 300 us, Duty Cycle < 2.0%.3: Starting T J = 25°C, L = 1mH, I AS = 7.3A, V DD = 40V, V GS = 10V.Scale 1:1 on letter size papera) 81°C/W when mounted on a 1in 2 pad of 2 oz copperb) 135°C/W when mounted on a minimum pad .MOSFETMOSFETMOSFETFDS8949 Rev. 6FDS8949 Dual N-Channel Logic Level PowerTrench ® MOSFETTRADEMARKSThe following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.DISCLAIMERFAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.As used herein:1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.PRODUCT STATUS DEFINITIONS Definition of TermsACEx™ActiveArray™Bottomless™Build it Now™CoolFET™CROSSVOLT ™DOME™EcoSPARK™E 2CMOS™EnSigna™FACT™FAST ®FASTr™FPS™FRFET™FACT Quiet Series™ GlobalOptoisolator™GTO™HiSeC™I 2C™i-Lo ™ImpliedDisconnect ™IntelliMAX™ISOPLANAR™LittleFET™MICROCOUPLER™MicroFET™MicroPak™MICROWIRE™MSX ™MSXPro ™OCX ™OCXPro ™OPTOLOGIC ®OPTOPLANAR™PACMAN™POP™Power247™PowerEdge™PowerSaver™PowerTrench ®QFET ®QS™QT Optoelectronics™Quiet Series™RapidConfigure ™RapidConnect ™µSerDes ™ScalarPump ™SILENT SWITCHER ®SMART START™SPM™Stealth™SuperFET™SuperSOT™-3SuperSOT™-6SuperSOT™-8SyncFET™TCM™TinyBoost™TinyBuck™TinyPWM™TinyPower™TinyLogic ®TINYOPTO™TruTranslation™UHC™UniFET™UltraFET ®VCX™Wire™Across the board. Around the world.™The Power Franchise ®Programmable Active Droop™Datasheet Identification Product Status DefinitionAdvance InformationFormative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.PreliminaryFirst ProductionThis datasheet contains preliminary data, andsupplementary data will be published at a later date.Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.No Identification Needed Full ProductionThis datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In ProductionThis datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor.The datasheet is printed for reference information only.Rev. I20分销商库存信息: FAIRCHILDFDS8949。
CD4029BM,CD4029BM96,CD4029BM96E4,CD4029BM96G4,CD4029BPWRE4,CD4029BPWRG4, 规格书,Datasheet 资料
The CD4029B-series types are supplied in16-lead hermetic dual-in-line ceramicpackages (F3A suffix), 16-lead dual-in-lineplastic packages (E suffix), 16-leadsmall-outline packages (M, M96, MT, and NSRsuffixes), and 16-lead thin shrink small-outlinepackages (PW and PWR suffixes).Copyright © 2003, Texas Instruments IncorporatedAddendum-Page 1PACKAGING INFORMATIONOrderable Device Status(1)Package Type PackageDrawingPins Package QtyEco Plan(2)Lead/Ball Finish MSL Peak Temp (3)Samples (Requires Login)8101602EA ACTIVE CDIP J 161TBDCall TICall TICD4029BE ACTIVE PDIP N 1625Pb-Free (RoHS)CU NIPDAU N / A for Pkg Type CD4029BEE4ACTIVE PDIP N 1625Pb-Free (RoHS)CU NIPDAU N / A for Pkg TypeCD4029BF ACTIVE CDIP J 161TBD A42N / A for Pkg Type CD4029BF3A ACTIVE CDIP J 161TBD A42N / A for Pkg TypeCD4029BM ACTIVE SOIC D 1640Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD4029BM96ACTIVE SOIC D 162500Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD4029BM96E4ACTIVE SOIC D 162500Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD4029BM96G4ACTIVE SOIC D 162500Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD4029BME4ACTIVE SOIC D 1640Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD4029BMG4ACTIVE SOIC D 1640Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD4029BMT ACTIVE SOIC D 16250Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD4029BMTE4ACTIVE SOIC D 16250Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD4029BMTG4ACTIVE SOIC D 16250Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD4029BNSR ACTIVE SO NS 162000Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD4029BNSRE4ACTIVE SO NS 162000Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD4029BNSRG4ACTIVE SO NS 162000Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD4029BPWR ACTIVE TSSOP PW 162000Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CD4029BPWRE4ACTIVETSSOPPW162000Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM芯天下--/Addendum-Page 2Orderable Device Status(1)Package Type PackageDrawingPins Package QtyEco Plan(2)Lead/Ball FinishMSL Peak Temp(3)Samples (Requires Login)CD4029BPWRG4ACTIVETSSOPPW162000Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM(1)The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.(2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check /productcontent for the latest availability information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)(3)MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.OTHER QUALIFIED VERSIONS OF CD4029B, CD4029B-MIL :•Catalog: CD4029B •Military: CD4029B-MILNOTE: Qualified Version Definitions:•Catalog - TI's standard catalog product芯天下--/•Military - QML certified for Military and Defense ApplicationsAddendum-Page 3芯天下--/TAPE AND REELINFORMATION*Alldimensions are nominalDevicePackage Type Package Drawing Pins SPQReel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant CD4029BM96SOIC D 162500330.016.4 6.510.3 2.18.016.0Q1CD4029BNSR SO NS 162000330.016.48.210.5 2.512.016.0Q1CD4029BPWRTSSOPPW162000330.012.46.95.61.68.012.0Q1PACKAGE MATERIALS INFORMATION14-Jul-2012Pack Materials-Page 1*All dimensionsare nominalDevice Package TypePackage DrawingPins SPQ Length (mm)Width (mm)Height (mm)CD4029BM96SOIC D 162500333.2345.928.6CD4029BNSR SO NS 162000367.0367.038.0CD4029BPWRTSSOPPW162000367.0367.035.0PACKAGE MATERIALS INFORMATION14-Jul-2012Pack Materials-Page 2IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,enhancements,improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B.Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All semiconductor products(also referred to herein as“components”)are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its components to the specifications applicable at the time of sale,in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by applicable law,testing of all parameters of each component is not necessarily performed.TI assumes no liability for applications assistance or the design of Buyers’products.Buyers are responsible for their products and applications using TI components.To minimize the risks associated with Buyers’products and applications,Buyers should provide adequate design and operating safeguards.TI does not warrant or represent that any license,either express or implied,is granted under any patent right,copyright,mask work right,or other intellectual property right relating to any combination,machine,or process in which TI components or services are rmation published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement e of such information may require a license from a third party under the patents or other intellectual property of the third party,or a license from TI under the patents or other intellectual property of TI.Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties,conditions,limitations,and notices.TI is not responsible or liable for such altered rmation of third parties may be subject to additional restrictions.Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.Buyer acknowledges and agrees that it is solely responsible for compliance with all legal,regulatory and safety-related requirements concerning its products,and any use of TI components in its applications,notwithstanding any applications-related information or support that may be provided by TI.Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures,monitor failures and their consequences,lessen the likelihood of failures that might cause harm and take appropriate remedial actions.Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications.In some cases,TI components may be promoted specifically to facilitate safety-related applications.With such components,TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements.Nonetheless,such components are subject to these terms.No TI components are authorized for use in FDA Class III(or similar life-critical medical equipment)unless authorized officers of the parties have executed a special agreement specifically governing such use.Only those TI components which TI has specifically designated as military grade or“enhanced plastic”are designed and intended for use in military/aerospace applications or environments.Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk,and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use.TI has specifically designated certain components which meet ISO/TS16949requirements,mainly for automotive ponents which have not been so designated are neither designed nor intended for automotive use;and TI will not be responsible for any failure of such components to meet such requirements.Products ApplicationsAudio /audio Automotive and Transportation /automotiveAmplifiers Communications and Telecom /communicationsData Converters Computers and Peripherals /computersDLP®Products Consumer Electronics /consumer-appsDSP Energy and Lighting /energyClocks and Timers /clocks Industrial /industrialInterface Medical /medicalLogic Security /securityPower Mgmt Space,Avionics and Defense /space-avionics-defense Microcontrollers Video and Imaging /videoRFID OMAP Mobile Processors /omap TI E2E Community Wireless Connectivity /wirelessconnectivityMailing Address:Texas Instruments,Post Office Box655303,Dallas,Texas75265Copyright©2012,Texas Instruments Incorporated。
BD809G;BD810G;BD810;中文规格书,Datasheet资料
BD809 (NPN), BD810 (PNP)Plastic High Power Silicon TransistorThese devices are designed for use in high power audio amplifiers utilizing complementary or quasi complementary circuits.Features•DC Current Gain − h FE = 30 (Min) @ I C = 2.0 Adc •Pb −Free Packages are Available*MAXIMUM RATINGSRatingSymbol Value Unit Collector −Emitter Voltage V CEO 80Vdc Collector −Base Voltage V CBO 80Vdc Emitter −Base Voltage V EBO 5.0Vdc Collector Current I C 10Adc Base CurrentI B 6.0Adc Total Device Dissipation @ T C = 25°C Derate above 25°CPD 90720W W/°C Operating and Storage Junction Temperature RangeT J , T stg−55 to +150°CTHERMAL CHARACTERISTICSCharacteristicsSymbol Max Unit Thermal Resistance, Junction −to −Caseq JC1.39°C/WStresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.*For additional information on our Pb −Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.10 AMPEREPOWER TRANSISTORS80 VOLTS 90 WATTSTO −220AB CASE 221A −09STYLE 1MARKING DIAGRAMBD8xx =Device Code x = 09 or 10A =Assembly Location Y =YearWW =Work WeekG=Pb −Free PackageSee detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.ORDERING INFORMATIONELECTRICAL CHARACTERISTICS (T C = 25°C unless otherwise noted)CharacteristicSymbol Min Max Unit Collector −Emitter Sustaining Voltage (Note 1)(I C = 0.1 Adc, I B = 0)BV CEO 80−−VdcCollector Cutoff Current(V CB = 80 Vdc, I E = 0)I CBO − 1.0mAdc Emitter Cutoff Current(V BE = 5.0 Vdc, I C = 0)I EBO −2.0mAdcDC Current Gain(I C = 2.0 A, V CE = 2.0 V)(I C = 4.0 A, V CE = 2.0 V)h FE3015−−Collector −Emitter Saturation Voltage (Note 1)(I C = 3.0 Adc, I B = 0.3 Adc)V CE(sat)− 1.1Vdc Base −Emitter On Voltage (Note 1)(I C = 4.0 Adc, V CE = 2.0 Vdc)V BE(on)−1.6VdcCurrent −Gain Bandwidth Product(I C = 1.0 Adc, V CE = 10 Vdc, f = 1.0 MHz)f T1.5−MHz1.Pulse Test: Pulse Width x 300 m s, Duty Cycle x2.0%.Figure 1. Active Region DC Safe Operating Area(see Note 1)10V CE , COLLECTOR-EMITTER VOLTAGE (VOLTS)310.10.3I C , C O L L E C T O R C U R R E N T (A M P )9080002550100125150175Figure 2. Power −Temperature Derating CurveT C , CASE TEMPERATURE (°C)P D , P O W E R D I S S I P A T I O N (W A T T S )7510706050403020V C E , C O L L E C T O R -E M I T T E R V O L T A G E (V O L T S )V C E , C O L L E C T O R -E M I T T E R V O L T A G E (V O L T S )Figure 3. DC Current GainIC , COLLECTOR CURRENT (AMP)h F E , D C C U R R E N T G A I NNPN BD809PNP BD810I C , COLLECTOR CURRENT (AMP)h F E , D C C U R RE N T G A I N50010050200205.010Figure 4. Collector Saturation Region2.0I B , BASE CURRENT (mA)1.81.61.41.201.00.20.60.80.4 2.01.81.61.41.201.00.20.60.80.4I B , BASE CURRENT (mA)2.81.61.22.400.80.42.0I C , COLLECTOR CURRENT (AMP)V , V O L T A G E (V O L T S )Figure 5. “On” VoltagesI C , COLLECTOR CURRENT (AMP)V , V O L T A G E (V O L T S )2.81.61.22.400.80.42.0Figure 6. Thermal Responset, PULSE WIDTH (ms)1.00.010.70.50.30.20.10.070.050.030.02r (t ), N O R M A L I Z E D E F F E C T I V E T R A N S I E N T T H E R M A L R E S I S T A N C ENote 1:There are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. Safe operating area curves indicate I C − V CE limits of the transistor that must be observed for reliable operation, i.e., the transistor must not be subjected to greater dissipation than the curves indicate.The data of Figure 1 is based on T J(pk) = 150°C; T C is variable depending on conditions. Second breakdown pulse limits are valid for duty cycles to 10% provided T J(pk)v 150°C. At high case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdown.ORDERING INFORMATIONDevicePackage Shipping †BD809TO −22050 Units / Rail BD809G TO −220(Pb −Free)BD810TO −22050 Units / Rail BD810GTO −220(Pb −Free)†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.PACKAGE DIMENSIONSTO −220CASE 221A −09ISSUE AGNOTES:1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3.DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED.DIM MIN MAX MIN MAX MILLIMETERS INCHES A 0.5700.62014.4815.75B 0.3800.4059.6610.28C 0.1600.190 4.07 4.82D 0.0250.0360.640.91F 0.1420.161 3.61 4.09G 0.0950.105 2.42 2.66H 0.1100.161 2.80 4.10J 0.0140.0250.360.64K 0.5000.56212.7014.27L 0.0450.060 1.15 1.52N 0.1900.210 4.83 5.33Q 0.1000.120 2.54 3.04R 0.0800.110 2.04 2.79S 0.0450.055 1.15 1.39T 0.2350.255 5.97 6.47U 0.0000.0500.00 1.27V 0.045--- 1.15---Z---0.080--- 2.04FSEATING PLANESTYLE 1:PIN 1.BASE2.COLLECTOR3.EMITTER4.COLLECTORON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATION分销商库存信息:ONSEMIBD809G BD810G BD810。
BUK136-50L,118;中文规格书,Datasheet资料
Philips Semiconductors Product specificationLogic level TOPFETBUK136-50LSMD version of BUK125-50LDESCRIPTIONQUICK REFERENCE DATAMonolithic logic level protected SYMBOL PARAMETERMAX.UNIT power MOSFET using TOPFET2technology assembled in a 5 pin V DS Continuous drain source voltage 50V surface mounting plastic package.I D Continuous drain current 40A P tot Total power dissipation107W APPLICATIONST jContinuous junction temperature 150˚C R DS(ON)Drain-source on-state resistance 20m ΩGeneral purpose switch for automotive systems and other SYMBOL PARAMETERNOM.UNIT applications.V PSProtection supply voltage5VFEATURESTrenchMOS output stage with Separate input pin for higher 5 V logic compatible input Separate supply pin for logic Overtemperature protection Drain current limitingShort circuit load protectionLatched overload trip state reset Diagnostic flag pin indicates overtemperature condition,overload tripped state, or open circuit load ESD protection on all pins Overvoltage clampingPINNING - SOT426PIN CONFIGURATIONSYMBOLPhilips Semiconductors Product specification Logic level TOPFET BUK136-50L SMD version of BUK125-50LLIMITING VALUESLimiting values in accordance with the Absolute Maximum Rating System (IEC 134)SYMBOL PARAMETER CONDITIONS MIN.MAX.UNIT Continuous voltageVDS Drain source voltage1VIS= 0 V-50V Continuous currentsI D Drain current VPS= 5 V; Tmb=25˚C-self -AlimitedVPS= 0 V; Tmb=80˚C-40AI I Input current-55mAI F Flag current-55mAIPProtection supply current-55mAThermalPtot Total power dissipation Tmb= 25˚C-107WT stg Storage temperature-55175˚CT j Junction temperature2continuous-150˚CTsoldMounting base temperature during soldering-260˚C ESD LIMITING VALUESYMBOL PARAMETER CONDITIONS MIN.MAX.UNITVCElectrostatic discharge capacitor Human body model;-2kVvoltage C = 250 pF; R = 1.5 kΩOVERLOAD PROTECTION LIMITING VALUEWith an adequate protection supply For overload conditions an n-MOS The drain current is limited to connected, TOPFET can protect transistor turns on between the reduce dissipation in case of short itself from two types of overload -input and source to quickly circuit load. Refer to OVERLOAD overtemperature and short circuit discharge the power MOSFET CHARACTERISTICS.load.gate capacitance.SYMBOL PARAMETER REQUIRED CONDITION MIN.MAX.UNIT Overload protection3protection supplyVDS Drain source voltage VPS≥ 4 V035VOVERVOLTAGE CLAMPING LIMITING VALUESAt a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients. SYMBOL PARAMETER CONDITIONS MIN.MAX.UNITInductive load turn off IDM = 25 A; VDD≤ 20 VEDSM Non-repetitive clamping energy Tmb= 25˚C-550mJEDRM Repetitive clamping energy Tmb≤ 95˚C; f = 250 Hz-60mJ1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.2 A higher Tj is allowed as an overload condition but at the threshold Tj(TO)the over temperature trip operates to protect the switch.3 All control logic and protection functions are disabled during conduction of the source drain diode. If the protection circuit was previouslylatched, it would be reset by this condition.Philips Semiconductors Product specification Logic level TOPFET BUK136-50L SMD version of BUK125-50LTHERMAL CHARACTERISTICSYMBOL PARAMETER CONDITIONS MIN.TYP.MAX.UNIT Thermal resistanceRth j-mbJunction to mounting base--0.94 1.17K/W OUTPUT CHARACTERISTICSLimits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb= 25˚C unless otherwise specified.SYMBOL PARAMETER CONDITIONS MIN.TYP.MAX.UNIT Off-state VIS= 0 VV(CL)DSS Drain-source clamping voltage ID= 10 mA50-70VIDM= 5 A; tp ≤ 300 µs; δ≤ 0.01506070VI DSS Drain source leakage current1VPS= 0 V; VDS= 40 V--100µATmb= 25˚C-0.110µAOn-state tp≤ 300 µs; δ≤ 0.01; VPS≥ 4 VRDS(ON)Drain-source resistance IDM= 15 A; VIS≥ 4.4 V--40mΩTmb= 25˚C-1520mΩINPUT CHARACTERISTICSLimits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb= 25˚C unless otherwise specified.SYMBOL PARAMETER CONDITIONS MIN.TYP.MAX.UNIT Normal operationVIS(TO)Input threshold voltage2ID= 1 mA0.6- 2.6VTmb= 25˚C 1.1 1.6 2.1VI IS Input current VIS= 5 V-16100µAV(CL)IS Input clamping voltage II= 1 mA 5.5 6.48.5VRIGInternal series resistance3to gate of power MOSFET- 1.7-kΩOverload protection latched VPS≥ 4 VI ISL Input current VIS= 5 V1 2.74mA1 The drain current required for open circuit load detection is switched off when there is no protection supply, in order to ensure a low off-statequiescent current. Refer to OPEN CIRCUIT LOAD DETECTION CHARACTERISTICS.2 The measurement method is simplified if VPS = 0 V, in order to distinguish IDfrom IDSP. Refer to OPEN CIRCUIT LOAD DETECTIONCHARACTERISTICS.3 This is not a directly measurable parameter.Philips Semiconductors Product specificationLogic level TOPFETBUK136-50LSMD version of BUK125-50LPROTECTION SUPPLY CHARACTERISTICSLimits are for -40˚C ≤ T mb ≤ 150˚C; typicals are for T mb = 25˚C.SYMBOL PARAMETERCONDITIONSMIN.TYP.MAX.UNIT Protection & detection V PSF Threshold voltage 1I F = 100 µA; V DS = 5 V 2.53.454VNormal operation or protection latched I PS , I PSL Supply current V PS = 4.5 V -210450µA V (CL)PS Clamping voltageI P = 1.5 mA5.56.58.5V Overload protection latched V PSR Reset voltage 1 1.83V t prReset timeV PS ≤ 1 V1045120µsOPEN CIRCUIT LOAD DETECTION CHARACTERISTICSAn open circuit load condition can be detected while the TOPFET is in the off-state. Refer to TRUTH TABLE .V PS = 5 V. Limits are for -40˚C ≤ T mb ≤ 150˚C and typicals are for T mb = 25˚C.SYMBOL PARAMETER CONDITIONSMIN.TYP.MAX.UNIT I DSP Off-state drain current 2V IS = 0 V; 2 V ≤ V DS ≤ 40 V 0.9 1.8 2.7mA V DSF Drain threshold voltage 3V IS = 0 V 0.212V V ISFInput threshold voltage 4I D = 100 µA0.30.81.1VOVERLOAD CHARACTERISTICST mb = 25˚C unless otherwise specified.SYMBOL PARAMETERCONDITIONS MIN.TYP.MAX.UNITShort circuit load protection V PS > 4 VI DDrain current limiting 5V IS = 5 V;-40˚C ≤ T mb ≤ 150˚C 406284A P D(TO)Overload power threshold for protection to operate 90220330W T DSC Characteristic timewhich determines trip time 6250500700µs Overtemperature protection V PS = 5 VT j(TO)Threshold temperaturefrom I D ≥ 4 A or V DS > 0.2 V150170-˚C1 When V PS is less than V PSF the flag pin indicates low protection supply voltage. Refer to TRUTH TABLE.2 The drain source current which flows in a normal load when the protection supply is high and the input is low.3 If V DS < V DSF then the flag indicates open circuit load.4 For open circuit load detection, V IS must be less than V ISF .5 Product specification will include curve showing output characteristics.6 Trip time t d sc varies with overload dissipation P D according to the formula t d sc ~ T DSC / ln[ P D / P D(TO)].Philips Semiconductors Product specificationLogic level TOPFETBUK136-50LSMD version of BUK125-50LTRUTH TABLEFor normal, open-circuit load and overload conditions or inadequate protection supply voltage.Assumes proper external pull-up for flag pin. Refer to FLAG CHARACTERISTICS .CONDITIONPROTECTIONINPUT FLAG OUTPUT Normal on-state 110ON Normal off-state 100OFF Open circuit load 110ON Open circuit load 101OFF Short circuit load 1111OFF Over temperature1X 1OFF Low protection supply voltage 011ON Low protection supply voltage1OFFKEY ‘0’ equals low‘1’ equals high‘X’ equals don’t care.FLAG CHARACTERISTICSThe flag is an open drain transistor which requires an external pull-up circuit.Limits are for -40˚C ≤ T mb ≤ 150˚C; typicals are for T mb = 25˚C.SYMBOL PARAMETER CONDITIONSMIN.TYP.MAX.UNITFlag ‘low’normal operation; V PS = 5 V V FSF Flag voltageI F = 100 µA -0.81V I FSF Flag saturation current V FS = 5 V -10-mAFlag ‘high’overload or fault I FSO Flag leakage current V FS = 5 V -0.110µA V (CL)FS Flag clamping voltage I F = 100 µA5.56.28.5VApplication information R FSuitable external pull-up V FF = 5 V-47-k ΩresistanceSWITCHING CHARACTERISTICST mb = 25˚C; R I = 50 Ω; R IS = 50 Ω; V DD = 15 V; resistive load R L = 10 Ω.SYMBOL PARAMETER CONDITIONS MIN.TYP.MAX.UNIT t d on Turn-on delay time V IS : 0 V ⇒ 5 V- 1.85µs t r Rise time- 3.58µs t d off Turn-off delay time V IS : 5 V ⇒ 0 V -1130µs t fFall time-512µs1 In this condition the protection circuit is latched. To reset the latch the protection pin must be taken low. Refer to PROTECTION SUPPLYCHARACTERISTICS.Philips Semiconductors Product specificationLogic level TOPFETBUK136-50LSMD version of BUK125-50LMECHANICAL DATA1 Epoxy meets UL94 V0 at 1/8". Net mass: 1.5 g.For soldering guidelines and SMD footprint design, please refer to Data Handbook SC18.Philips Semiconductors Product specification Logic level TOPFET BUK136-50L SMD version of BUK125-50LDEFINITIONSDATA SHEET STATUSDATA SHEET PRODUCT DEFINITIONSSTATUS1STATUS2Objective data Development This data sheet contains data from the objective specification forproduct development. Philips Semiconductors reserves the right tochange the specification in any manner without noticePreliminary data Qualification This data sheet contains data from the preliminary specification.Supplementary data will be published at a later date. PhilipsSemiconductors reserves the right to change the specification withoutnotice, in order to improve the design and supply the best possibleproductProduct data Production This data sheet contains data from the product specification. PhilipsSemiconductors reserves the right to make changes at any time inorder to improve the design, manufacturing and supply. Changes willbe communicated according to the Customer Product/ProcessChange Notification (CPCN) procedure SNW-SQ-650ALimiting valuesLimiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections ofthis specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application informationWhere application information is given, it is advisory and does not form part of the specification.Philips Electronics N.V. 2002All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.LIFE SUPPORT APPLICATIONSThese products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.1 Please consult the most recently issued datasheet before initiating or completing a design.2 The product status of the device(s) described in this datasheet may have changed since this datasheet was published. The latest information isavailable on the Internet at URL .分销商库存信息: NXPBUK136-50L,118。
SAE AS 8049B 中文版
AEROSPACESTANDARD® AS8049BIssued 1990-07Revised 2005-01Superseding AS8049APerformance Standard for Seatsin Civil Rotorcraft, Transport Aircraft, and General Aviation Aircraft民用旋翼类/运输类和通用航空类飞机座椅的性能标准1.范围1.1 通则本SAE宇航标准（AS）规定了在民用旋翼类、运输类和通用航空类飞机中乘客和机组成员座椅的最低性能标准、鉴定要求及记录文件的最低要求。
制定本文的目的是使座椅在正常工作载荷条件下到达舒适耐用和保护乘员的作用。
本文对座椅/乘员/约束系统在联邦航空条例（14CFR）第23、25、27或29部中公布的静态极限载荷和动态冲击试验条件下保护乘员的验证试验和评估判据进行了规定。
为了促进试验技术的统一和达到合格的数据，同时也提出了试验程序、测试方法、设备和试验结果说明的指南。
本文还叙述了区分座椅供应商和安装座椅的申请者之间对座椅系统性能应负的责任。
座椅供应商的责任包括满足所有座椅系统的性能要求和获得本文叙述的全部数据并提供给安装座椅的申请者。
而安装座椅的申请者则在保证满足座椅安全的全部要求方面对最终系统负责。
1.2 适用性本文论述了用于民用旋翼航空器、运输机和通用航空飞机钟要求的动态试验的座椅系统的性能判据。
1.3 座椅类型本文包括了在飞机型号合格审定钟，用于下列各类飞机的所有乘客和机组成员座椅：表1: 适用座椅类型座椅类型飞机类型 适用FARA 运输类飞机 14 CFR 25部14 CFR 27部B 普通类旋翼航空器14 CFR 29部B 运输类旋翼航空器C 通用航空飞机 14 CFR 23部1.4 单位本文采用了美国习惯的英制单位（磅）和国际系统的公制单位（SI）。
在所有情况，英制优先，公制为近似和保守的换算。
P89LPC935FA,129,P89LPC936FDH系列,P89LPC935FDH,529,P89LPC933FDH系列规格书,Datasheet 资料
1. General descriptionThe P89LPC933/934/935/936 is a single-chip microcontroller, available in low costpackages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC933/934/935/936 in order to reduce component count, board space, and system cost.2. Features and benefits2.1Principal features4kB/8kB/16kB byte-erasable flash code memory organized into 1kB/2 kB sectorsand 64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.256-byte RAM data memory. Both the P89LPC935 and P89LPC936 also include a512-byte auxiliary on-chip RAM.512-byte customer data EEPROM on chip allows serialization of devices, storage ofsetup parameters, etc. (P89LPC935/936).Dual 4-input multiplexed 8-bit A/D converters/DAC outputs (P89LPC935/936, singleA/D on P89LPC933/934).Two analog comparators with selectable inputs and reference source.Two 16-bit counter/timers (each may be configured to toggle a port output upon timeroverflow or to become a PWM output) and a 23-bit system timer that can also be used as an RTC.Enhanced UART with fractional baud rate generator, break detect, framing errordetection, and automatic address detection; 400kHz byte-wide I 2C-bus communication port and SPI communication port.Capture/Compare Unit (CCU) provides PWM, input capture, and output comparefunctions (P89LPC935/936).High-accuracy internal RC oscillator option allows operation without external oscillatorcomponents. The RC oscillator option is selectable and fine tunable.2.4V to3.6V V DD operating range. I/O pins are 5V tolerant (may be pulled up ordriven to 5.5V).28-pin TSSOP , PLCC, and HVQFN packages with 23 I/O pins minimum and up to 26I/O pins while using on-chip oscillator and reset options.P89LPC933/934/935/9368-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCsRev. 8 — 12 January 2011Product data sheet2.2Additional featuresA high performance 80C51 CPU provides instruction cycle times of 111ns to 222nsfor all instructions except multiply and divide when executing at 18MHz. This is sixtimes the performance of the standard 80C51 running at the same clock frequency. Alower clock frequency for the same performance results in power savings and reduced EMI.Serial flash In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitiveapplication programs.Serial flash In-System Programming (ISP) allows coding while the device is mounted in the end application.In-Application Programming (IAP) of the flash code memory. This allows changing the code in a running application.Watchdog timer with separate on-chip oscillator, requiring no external components.The watchdog prescaler is selectable from eight values.Low voltage reset (brownout detect) allows a graceful system shutdown when power fails. May optionally be configured as an interrupt.Idle and two different power-down reduced power modes. Improved wake-up from Power-down mode (a LOW interrupt input starts execution). Typical power-downcurrent is 1μA (total power-down with voltage comparators disabled).Active-LOW reset. On-chip power-on reset allows operation without external reset components. A reset counter and reset glitch suppression circuitry prevent spuriousand incomplete resets. A software reset function is also available.Configurable on-chip oscillator with frequency range options selected by user programmed flash configuration bits. Oscillator options support frequencies from20kHz to the maximum operating frequency of 18MHz.Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator allowing it to perform an oscillator fail detect function.Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only.Port ‘input pattern match’ detect. Port0 may generate an interrupt when the value of the pins match or do not match a programmable pattern.LED drive capability (20mA) on all port pins. A maximum limit is specified for the entire chip.Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10ns minimum ramp times.Only power and ground connections are required to operate theP89LPC933/934/935/936 when internal reset option is selected.Four interrupt priority levels.Eight keypad interrupt inputs, plus two additional external interrupt inputs.Schmitt trigger port inputs.Second data pointer.Emulation support.3. Product comparison overviewTable 1 highlights the differences between the four devices. For a complete list of device features please see Section 2 “Features and benefits”.4. Ordering information4.1Ordering optionsTable 1.Product comparison overviewDeviceFlash memory Sector size ADC1ADC0CCU Data EEPROM P89LPC933 4 kB 1 kB X ---P89LPC9348 kB 1 kB X ---P89LPC9358 kB 1 kB X X X X P89LPC93616 kB2 kBXXXXTable 2.Ordering informationType number Package NameDescriptionVersion P89LPC935FA PLCC28plastic leaded chip carrier; 28 leads SOT261-2P89LPC933HDH TSSOP28plastic thin shrink small outlinepackage; 28leads; body width 4.4mmSOT361-1P89LPC933FDH P89LPC934FDH P89LPC935FDH P89LPC936FDH P89LPC935FHNHVQFN28plastic thermal enhanced very thin quad flat package; no leads;28terminals; body 6×6×0.85mmSOT788-1Table 3.Ordering optionsType number Flash memory Temperature range Frequency P89LPC933HDH 4 kB −40°C to +125°C 0MHz to 18MHzP89LPC933FDH 4kB −40°C to +85°CP89LPC935FA 8kBP89LPC934FDH P89LPC935FDH P89LPC935FHN P89LPC936FDH16kB5. Block diagram6. Pinning information6.1Pinning6.2Pin descriptionTable 4.Pin descriptionSymbol Pin Type DescriptionTSSOP28,PLCC28HVQFN28P0.0 to P0.7I/O Port0: Port0 is an 8-bit I/O port with a user-configurable output type.During reset Port0 latches are configured in the input only mode with theinternal pull-up disabled. The operation of Port0 pins as inputs andoutputs depends upon the port configuration selected. Each port pin isconfigured independently. Refer to Section 8.13.1 “Port configurations”and Table 11 “Static characteristics” for details.The Keypad Interrupt feature operates with Port0 pins.All pins have Schmitt trigger inputs.Port0 also provides various special functions as described below:P0.0/CMP2/ KBI0/AD01327I/O P0.0 — Port0 bit0.O CMP2 — Comparator2 output.I KBI0 — Keyboard input0.I AD01 — ADC0 channel 1 analog input. (P89LPC935/936)P0.1/CIN2B/ KBI1/AD102622I/O P0.1 — Port0 bit1.I CIN2B — Comparator2 positive input B.I KBI1 — Keyboard input1.I AD10 — ADC1 channel 0 analog input.P0.2/CIN2A/ KBI2/AD112521I/O P0.2 — Port0 bit2.I CIN2A — Comparator2 positive input A.I KBI2 — Keyboard input2.I AD11 — ADC1 channel 1 analog input.P0.3/CIN1B/ KBI3/AD122420I/O P0.3 — Port0 bit3.I CIN1B — Comparator1 positive input B.I KBI3 — Keyboard input3.I AD12 — ADC1 channel 2 analog input.P0.4/CIN1A/ KBI4/DAC1/ AD132319I/O P0.4 — Port0 bit4.I CIN1A — Comparator1 positive input A.I KBI4 — Keyboard input4.O DAC1 — Digital-to-analog converter output 1.I AD13 — ADC1 channel 3 analog input.P0.5/ CMPREF/ KBI52218I/O P0.5 — Port0 bit5.I CMPREF — Comparator reference (negative) input.I KBI5 — Keyboard input5.P0.6/CMP1/ KBI62016I/O P0.6 — Port0 bit6.O CMP1 — Comparator1 output.I KBI6 — Keyboard input6.P0.7/T1/ KBI71915I/O P0.7 — Port0 bit7.I/O T1 — Timer/counter1 external count input or overflow output.I KBI7 — Keyboard input7.P1.0 to P1.7I/O, I [1]Port1: Port1 is an 8-bit I/O port with a user-configurable output type,except for three pins as noted below. During reset Port1 latches areconfigured in the input only mode with the internal pull-up disabled. Theoperation of the configurable Port1 pins as inputs and outputs dependsupon the port configuration selected. Each of the configurable port pinsare programmed independently. Refer to Section 8.13.1 “Portconfigurations” and Table 11 “Static characteristics” for details. P1.2 andP1.3 are open drain when used as outputs. P1.5 is input only.All pins have Schmitt trigger inputs.Port1 also provides various special functions as described below:P1.0/TXD1814I/O P1.0 — Port1 bit0.O TXD — Transmitter output for the serial port.P1.1/RXD1713I/O P1.1 — Port1 bit1.I RXD — Receiver input for the serial port.P1.2/T0/SCL128I/O P1.2 — Port1 bit2 (open-drain when used as output).I/O T0 — Timer/counter0 external count input or overflow output (open-drainwhen used as output).I/O SCL — I2C serial clock input/output.P1.3/INT0/ SDA 117I/O P1.3 — Port1 bit3 (open-drain when used as output).I INT0 — External interrupt0 input.I/O SDA — I2C serial data input/output.P1.4/INT1106I P1.4 — Port1 bit4.I INT1 — External interrupt1 input.P1.5/RST62I P1.5 — Port1 bit5 (input only).I RST — External reset input during power-on or if selected via UCFG1.When functioning as a reset input, a LOW on this pin resets themicrocontroller, causing I/O ports and peripherals to take on their defaultstates, and the processor begins execution at address0. Also used duringa power-on sequence to force ISP mode. When using an oscillatorfrequency above 12MHz, the reset input function of P1.5 must beenabled. An external circuit is required to hold the device in reset atpower-up until VDD has reached its specified level. When systempower is removed VDD will fall below the minimum specifiedoperating voltage. When using an oscillator frequency above12MHz, in some applications, an external brownout detect circuitmay be required to hold the device in reset when VDD falls below theminimum specified operating voltage.P1.6/OCB51I/O P1.6 — Port1 bit6.O OCB — Output Compare B. (P89LPC935/936)P1.7/OCC/ AD00428I/O P1.7 — Port1 bit7.O OCC — Output Compare C. (P89LPC935/936)I AD00 — ADC0 channel 0 analog input. (P89LPC935/936)Table 4.Pin description …continuedSymbol Pin Type Description TSSOP28,PLCC28HVQFN28P2.0 to P2.7I/OPort 2: Port 2 is an 8-bit I/O port with a user-configurable output type. During reset Port 2 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.13.1 “Port configurations” and Table 11 “Static characteristics” for details.All pins have Schmitt trigger inputs.Port 2 also provides various special functions as described below:P2.0/ICB/ DAC0/AD03125I/O P2.0 — Port 2 bit 0.I ICB — Input Capture B. (P89LPC935/936)I DAC0 — Digital-to-analog converter output.IAD03 — ADC0 channel 3 analog input. (P89LPC935/936)P2.1/OCD/ AD02226I/O P2.1 — Port 2 bit 1.O OCD — Output Compare D. (P89LPC935/936)IAD02 — ADC0 channel 2 analog input. (P89LPC935/936)P2.2/MOSI 139I/O P2.2 — Port 2 bit 2.I/OMOSI — SPI master out slave in. When configured as master, this pin is output; when configured as slave, this pin is input.P2.3/MISO 1410I/O P2.3 — Port 2 bit 3.I/OMISO — When configured as master, this pin is input, when configured as slave, this pin is output.P2.4/SS 1511I/O P2.4 — Port 2 bit 4.I SS — SPI Slave select.P2.5/ SPICLK 1612I/O P2.5 — Port 2 bit 5.I/OSPICLK — SPI clock. When configured as master, this pin is output; when configured as slave, this pin is input. P2.6/OCA 2723I/O P2.6 — Port 2 bit 6.O OCA — Output Compare A. (P89LPC935/936)P2.7/ICA2824I/O P2.7 — Port 2 bit 7.IICA — Input Capture A. (P89LPC935/936)Table 4.Pin description …continuedSymbolPinTypeDescriptionTSSOP28, PLCC28HVQFN28[1]Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.P3.0 to P3.1I/OPort 3: Port 3 is a 2-bit I/O port with a user-configurable output type.During reset Port 3 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.13.1 “Port configurations” and Table 11 “Static characteristics” for details.All pins have Schmitt trigger inputs.Port 3 also provides various special functions as described below:P3.0/XTAL2/ CLKOUT95I/O P3.0 — Port 3 bit 0.O XTAL2 — Output from the oscillator amplifier (when a crystal oscillator option is selected via the flash configuration.OCLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the RTC/system timer.P3.1/XTAL184I/O P3.1 — Port 3 bit 1.IXTAL1 — Input to the oscillator circuit and internal clock generator circuits (when selected via the flash configuration). It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not used to generate the clock for the RTC/system timer.V SS 73I Ground: 0V reference.V DD2117IPower supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes.Table 4.Pin description …continuedSymbolPinTypeDescriptionTSSOP28, PLCC28HVQFN287. Logic symbols8. Functional descriptionRemark: Please refer to the P89LPC933/934/935/936 User manual for a more detailedfunctional description.8.1Special function registersRemark: SFR accesses are restricted in the following ways:•User must not attempt to access any SFR locations not defined.•Accesses to any defined SFR locations must be strictly for the functions for the SFRs.•SFR bits labeled ‘-’, logic 0 or logic 1 can only be written and read as follows:–‘-’ Unless otherwise specified, must be written with logic 0, but can return anyvalue when read (even if it was written with logic 0). It is a reserved bit and may beused in future derivatives.–Logic 0 must be written with logic 0, and will return a logic 0 when read.–Logic 1 must be written with logic 1, and will return a logic 1 when read.P89LPC933_934_935_936All information provided in this document is subject to legal disclaimers.© NXP B.V. 2011. All rights reserved.Product data sheet Rev. 8 — 12 January 2011 13 of 77NXP Semiconductors P89LPC933/934/935/9368-bit microcontroller with accelerated two-clock 80C51 coreTable 5.Special function registers - P89LPC933/934* indicates SFRs that are bit addressable. Name Description SFR addr.Bit functions and addresses Reset valueMSB LSB Hex Binary Bit address E7E6E5E4E3E2E1E0ACC*Accumulator E0H 0000000000ADCON0A/D control register 08EH -----ENADC0--0000000000ADCON1A/D control register 197H ENBI1ENADCI 1TMM1EDGE1ADCI1ENADC1ADCS11ADCS100000000000ADINS A/D input select A3H ADI13ADI12ADI11ADI10----0000000000ADMODA A/D mode register A C0H BNDI1BURST1SCC1SCAN1----0000000000ADMODB A/D mode register B A1H CLK2CLK1CLK0-ENDAC1ENDAC0BSA1-00000x 0000AD0DAT3A/D_0 data register 3F4H 0000000000AD1BH A/D_1 boundary high register C4H FF 11111111AD1BL A/D_1 boundary low register BCH 0000000000AD1DAT0A/D_1 data register 0D5H 0000000000AD1DAT1A/D_1 data register 1D6H 0000000000AD1DAT2A/D_1 data register 2D7H 0000000000AD1DAT3A/D_1 data register 3F5H 0000000000AUXR1Auxiliary function register A2H CLKLP EBRR ENT1ENT0SRST 0-DPS 00[1]000000x0Bit address F7F6F5F4F3F2F1F0B* B register F0H 0000000000BRGR0Baud rate generator rate low BEH 00[2]00000000BRGR1Baud rate generator rate high BFH 00[1][2]00000000BRGCON Baudrate generator control BDH ------SBRGS BRGEN 00[2]xxxx xx00CMP1Comparator 1 control register ACH --CE1CP1CN1OE1CO1CMF100[1]xx000000CMP2Comparator 2 control register ADH --CE2CP2CN2OE2CO2CMF200[1]xx000000DIVM CPU clock divide-by-M control95H 0000000000DPTR Data pointer (2bytes)DPH Data pointer high 83H 0000000000DPL Data pointer low 82H 0000000000FMADRH Program flash address high E7H 0000000000芯天下--/P89LPC933_934_935_936All information provided in this document is subject to legal disclaimers.© NXP B.V. 2011. All rights reserved.Product data sheet Rev. 8 — 12 January 2011 14 of 77NXP Semiconductors P89LPC933/934/935/9368-bit microcontroller with accelerated two-clock 80C51 core FMADRL Program flash address low E6H 0000000000FMCON Program flash control (Read)E4H BUSY ---HVA HVE SV OI 7001110000Program flash control (Write)E4H FMCMD.7FMCMD.6FMCMD.5FMCMD.4FMCMD.3FMCMD.2FMCMD.1FMCMD.FMDATA Program flash data E5H 0000000000I2ADR I 2C slave address register DBH I2ADR.6I2ADR.5I2ADR.4I2ADR.3I2ADR.2I2ADR.1I2ADR.0GC 0000000000Bit address DF DE DD DC DB DA D9D8I2CON*I 2C control register D8H -I2EN STA STO SI AA -CRSEL 00x00000x0I2DAT I 2C data register DAHI2SCLH Serial clock generator/SCL duty cycle register highDDH 0000000000I2SCLL Serial clock generator/SCL duty cycle register lowDCH 0000000000I2STAT I 2C status register D9H STA.4STA.3STA.2STA.1STA.0000F811111000ICRAH Input capture A register high ABH 0000000000ICRAL Input capture A register low AAH 0000000000ICRBH Input capture B register high AFH 0000000000ICRBL Input capture B register low AEH 0000000000Bit address AF AE AD AC AB AA A9A8IEN0*Interrupt enable 0A8H EA EWDRT EBO ES/ESR ET1EX1ET0EX00000000000Bit address EF EE ED EC EB EA E9E8IEN1*Interrupt enable 1E8H EAD EST --ESPI EC EKBI EI2C 00[3]00x00000Bit address BF BE BD BC BB BA B9B8IP0*Interrupt priority 0B8H -PWDRT PBO PS/PSR PT1PX1PT0PX000[3]x0000000IP0H Interrupt priority 0 high B7H -PWDRT H PBOH PSH/ PSRHPT1H PX1H PT0H PX0H 00[3]x0000000Bit address FF FE FD FC FB FA F9F8IP1*Interrupt priority 1F8H PAD PST --PSPI PC PKBI PI2C 00[3]00x00000IP1H Interrupt priority 1 high F7H PADH PSTH --PSPIH PCH PKBIH PI2CH 00[3]00x00000Table 5.Special function registers - P89LPC933/934 …continued* indicates SFRs that are bit addressable.Name Description SFR addr.Bit functions and addresses Reset valueMSB LSB Hex Binary芯天下--/P89LPC933_934_935_936All information provided in this document is subject to legal disclaimers.© NXP B.V. 2011. All rights reserved.Product data sheet Rev. 8 — 12 January 2011 15 of 77NXP Semiconductors P89LPC933/934/935/9368-bit microcontroller with accelerated two-clock 80C51 core KBCON Keypad control register 94H ------PATN _SELKBIF 00[3]xxxx xx00KBMASK Keypad interrupt mask register 86H 0000000000KBPATN Keypad pattern register 93H FF 11111111Bit address 8786858483828180P0*Port 080H T1/KB7CMP1/KB6CMPREF /KB5CIN1A /KB4CIN1B /KB3CIN2A /KB2CIN2B /KB1CMP2/KB0[3]Bit address 9796959493929190P1*Port 190H --RST INT1INT0/ SDAT0/SCL RXD TXD [3]Bit address A7A6A5A4A3A2A1A0P2*Port 2A0H --SPICLK SS MISO MOSI --[3]Bit address B7B6B5B4B3B2B1B0P3*Port 3B0H ------XTAL1XTAL2[3]P0M1Port 0 output mode 184H (P0M1.7)(P0M1.6)(P0M1.5)(P0M1.4)(P0M1.3)(P0M1.2)(P0M1.1)(P0M1.0)FF [3]11111111P0M2Port 0 output mode 285H (P0M2.7)(P0M2.6)(P0M2.5)(P0M2.4)(P0M2.3)(P0M2.2)(P0M2.1)(P0M2.0)00[3]00000000P1M1Port 1 output mode 191H (P1M1.7)(P1M1.6)-(P1M1.4)(P1M1.3)(P1M1.2)(P1M1.1)(P1M1.0)D3[3]11x1xx11P1M2Port 1 output mode 292H (P1M2.7)(P1M2.6)-(P1M2.4)(P1M2.3)(P1M2.2)(P1M2.1)(P1M2.0)00[3]00x0xx00P2M1Port 2 output mode 1A4H (P2M1.7)(P2M1.6)(P2M1.5)(P2M1.4)(P2M1.3)(P2M1.2)(P2M1.1)(P2M1.0)FF [3]11111111P2M2Port 2 output mode 2A5H (P2M2.7)(P2M2.6)(P2M2.5)(P2M2.4)(P2M2.3)(P2M2.2)(P2M2.1)(P2M2.0)00[3]00000000P3M1Port 3output mode 1B1H ------(P3M1.1)(P3M1.0)03[3]xxxx xx11P3M2Port 3 output mode 2B2H ------(P3M2.1)(P3M2.0)00[3]xxxx xx00PCON Power control register 87H SMOD1SMOD0BOPD BOI GF1GF0PMOD1PMOD00000000000PCONA Power control register A B5H RTCPD -VCPD ADPD I2PD SPPD SPD -00[3]00000000Bitaddress D7D6D5D4D3D2D1D0PSW*Program status word D0H CY AC F0RS1RS0OV F1P 0000000000PT0AD Port 0 digital input disable F6H --PT0AD.5PT0AD.4PT0AD.3PT0AD.2PT0AD.1-00xx00000x RSTSRC Reset source register DFH --BOF POF R_BK R_WD R_SF R_EX [4]RTCCON Real-time clock control D1H RTCF RTCS1RTCS0---ERTC RTCEN 60[3][5]011x xx00Table 5.Special function registers - P89LPC933/934 …continued* indicates SFRs that are bit addressable.Name Description SFR addr.Bit functions and addresses Reset valueMSB LSB Hex Binary芯天下--/P89LPC933_934_935_936All information provided in this document is subject to legal disclaimers.© NXP B.V. 2011. All rights reserved.Product data sheet Rev. 8 — 12 January 2011 16 of 77NXP Semiconductors P89LPC933/934/935/9368-bit microcontroller with accelerated two-clock 80C51 core RTCH Real-time clock register high D2H 00[5]00000000RTCL Real-time clock register low D3H 00[5]00000000SADDR Serial port address register A9H 0000000000SADEN Serial port address enable B9H 0000000000SBUF Serial Port data buffer register 99H xx xxxx xxxxBit address 9F 9E 9D 9C 9B 9A 9998SCON*Serial port control 98H SM0/FE SM1SM2REN TB8RB8TI RI 0000000000SSTAT Serial port extended status registerBAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 0000000000SP Stack pointer 81H 0700000111SPCTL SPI control register E2H SSIG SPEN DORD MSTR CPOL CPHA SPR1SPR00400000100SPSTAT SPI status register E1H SPIF WCOL ------0000xx xxxx SPDAT SPI data register E3H 0000000000TAMOD Timer 0 and 1 auxiliary mode 8FH ---T1M2---T0M200xxx0xxx0Bit address 8F 8E 8D 8C 8B 8A 8988TCON*Timer 0 and 1 control 88H TF1TR1TF0TR0IE1IT1IE0IT00000000000TH0Timer 0 high 8CH 0000000000TH1Timer 1 high 8DH 0000000000TL0Timer 0 low 8AH 0000000000TL1Timer 1 low 8BH 0000000000TMOD Timer 0 and 1 mode 89H T1GATE T1C/T T1M1T1M0T0GATE T0C/T T0M1T0M00000000000TRIM Internal oscillator trim register 96H RCCLK ENCLK TRIM.5TRIM.4TRIM.3TRIM.2TRIM.1TRIM.0[6] [5]WDCON Watchdog control register A7H PRE2PRE1PRE0--WDRUN WDTOF WDCLK [7] [5]Table 5.Special function registers - P89LPC933/934 …continued* indicates SFRs that are bit addressable.Name Description SFR addr.Bit functions and addresses Reset valueMSB LSB Hex Binary芯天下--/P89LPC933_934_935_936All information provided in this document is subject to legal disclaimers.© NXP B.V. 2011. All rights reserved.Product data sheet Rev. 8 — 12 January 2011 17 of 77NXP Semiconductors P89LPC933/934/935/9368-bit microcontroller with accelerated two-clock 80C51 core[1]Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise specified, ones should not be written to these bits since they may be used for otherpurposes in future derivatives. The reset values shown for these bits are logic 0s although they are unknown when read.[2]BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN =1, the result is unpredictable.[3]All ports are in input only (high-impedance) state after power-up.[4]The RSTSRC register reflects the cause of the P89LPC933/934/935/936 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on resetvalue is xx110000.[5]The only reset source that affects these SFRs is power-on reset.[6]On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.[7]After reset, the value is 111001x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN =1 and WDCLK =1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.Other resets will not affect WDTOF.WDL Watchdog load C1H FF 11111111WFEED1Watchdog feed 1C2HWFEED2Watchdog feed 2C3HTable 5.Special function registers - P89LPC933/934 …continued* indicates SFRs that are bit addressable.Name Description SFR addr.Bit functions and addresses Reset valueMSB LSB Hex Binary芯天下--/P89LPC933_934_935_936All information provided in this document is subject to legal disclaimers.© NXP B.V. 2011. All rights reserved.Product data sheet Rev. 8 — 12 January 2011 18 of 77NXP Semiconductors P89LPC933/934/935/9368-bit microcontroller with accelerated two-clock 80C51 coreTable 6.Special function registers - P89LPC935/936* indicates SFRs that are bit addressable. Name Description SFR addr.Bit functions and addresses Reset valueMSB LSB Hex BinaryBit address E7E6E5E4E3E2E1E0ACC*Accumulator E0H 0000000000ADCON0A/D control register 08EH ENBI0ENADCI 0TMM0EDGE0ADCI0ENADC0ADCS01ADCS000000000000ADCON1A/D control register 197H ENBI1ENADCI 1TMM1EDGE1ADCI1ENADC1ADCS11ADCS100000000000ADINS A/D input select A3H ADI13ADI12ADI11ADI10ADI03ADI02ADI01ADI000000000000ADMODA A/D mode register A C0H BNDI1BURST1SCC1SCAN1BNDI0BURST0SCC0SCAN00000000000ADMODB A/D mode register B A1H CLK2CLK1CLK0-ENDAC1ENDAC0BSA1BSA000000x 0000AD0BH A/D_0 boundary high register BBH FF 11111111AD0BL A/D_0 boundary low register A6H 0000000000AD0DAT0A/D_0 data register 0C5H 0000000000AD0DAT1A/D_0 data register 1C6H 0000000000AD0DAT2A/D_0 data register 2C7H 0000000000AD0DAT3A/D_0 data register 3F4H 0000000000AD1BH A/D_1 boundary high register C4H FF 11111111AD1BL A/D_1 boundary low register BCH 0000000000AD1DAT0A/D_1 data register 0D5H 0000000000AD1DAT1A/D_1 data register 1D6H 0000000000AD1DAT2A/D_1 data register 2D7H 0000000000AD1DAT3A/D_1 data register 3F5H 0000000000AUXR1Auxiliary function register A2H CLKLP EBRR ENT1ENT0SRST 0-DPS 00000000x0Bit address F7F6F5F4F3F2F1F0B* B register F0H 0000000000BRGR0[2]Baud rate generator rate low BEH 0000000000BRGR1[2]Baud rate generator rate high BFH 0000000000BRGCON Baudrate generator control BDH ------SBRGS BRGEN 00[2]xxxx xx00CCCRA Capture compare A control registerEAH ICECA2ICECA1ICECA0ICESA ICNFA FCOA OCMA1OCMA00000000000芯天下--/P89LPC933_934_935_936All information provided in this document is subject to legal disclaimers.© NXP B.V. 2011. All rights reserved.Product data sheet Rev. 8 — 12 January 2011 19 of 77NXP Semiconductors P89LPC933/934/935/9368-bit microcontroller with accelerated two-clock 80C51 core CCCRB Capture compare B control registerEBH ICECB2ICECB1ICECB0ICESB ICNFB FCOB OCMB1OCMB00000000000CCCRC Capture compare C control register ECH -----FCOC OCMC1OCMC000xxxx x000CCCRD Capture compare D control registerEDH -----FCOD OCMD1OCMD000xxxx x000CMP1Comparator 1 control register ACH --CE1CP1CN1OE1CO1CMF100[3]xx000000CMP2Comparator 2 control register ADH --CE2CP2CN2OE2CO2CMF200[3]xx000000DEECON Data EEPROM control registerF1H EEIF HVERR ECTL1ECTL0---EADR80E 00001110DEEDAT Data EEPROM data register F2H 0000000000DEEADR Data EEPROM address registerF3H 0000000000DIVM CPU clock divide-by-M control95H 0000000000DPTR Data pointer (2bytes)DPH Data pointer high 83H 0000000000DPL Data pointer low 82H 0000000000FMADRH Program flash address high E7H 0000000000FMADRL Program flash address low E6H 0000000000FMCON Program flash control (Read)E4H BUSY ---HVA HVE SV OI 7001110000Program flash control (Write)E4H FMCMD.7FMCMD.6FMCMD.5FMCMD.4FMCMD.3FMCMD.2FMCMD.1FMCMD.FMDATA Program flash data E5H 0000000000I2ADR I 2C slave address register DBH I2ADR.6I2ADR.5I2ADR.4I2ADR.3I2ADR.2I2ADR.1I2ADR.0GC 0000000000Bitaddress DF DE DD DC DB DA D9D8I2CON*I 2C control register D8H -I2EN STA STO SI AA -CRSEL 00x00000x0I2DAT I 2C data register DAHI2SCLH Serial clock generator/SCL duty cycle register highDDH 0000000000Table 6.Special function registers - P89LPC935/936 …continued* indicates SFRs that are bit addressable.Name Description SFR addr.Bit functions and addresses Reset valueMSB LSB Hex Binary芯天下--/。
E2SCA18-7.999M中文资料(ECLIPTEK)中文数据手册「EasyDatasheet - 矽搜」
(5 DigitsMaximum + Decimal)
HC-49/UP
规格如有更改,恕不另行通知.
CR44
.
08/08
包装选择
空白=散装,TR =卷带式
频率
负载电容
S =串联谐振 XX = XXpF并联谐振
动作模式 /水晶切割 A =基本/ AT, B =三次泛音/ AT D =基本/ BT
外形尺寸 ALL DIMENSIONS IN MILLIMETERS
建议焊盘布局 ALL DIMENSIONS IN MILLIMETERS
电气特性
频率范围频率ຫໍສະໝຸດ 差 /稳定性在工作温 度范围
工作温度范围
老化（ 25°C）
存储温度范围
并联电容
绝缘电阻
驱动电平
负载电容（C
)
3.579545MHz为50.000MHz
为±50ppm /±100ppm（标准）,±30ppm/为±50ppm（AT切割只）,±15ppm/±30ppm（AT切割只）,
环境/机械特性
PARAMETER
ESD敏感性
精细泄漏测试 可燃性 总泄漏测试 机械冲击 耐湿性 湿度敏感度 耐焊接热 抗溶剂 可焊性 温度循环 振荡
SPECIFICATION
MIL-STD-883,方法3015,1级,HBM：1500V MIL-STD-883,方法1014,条件A UL94-V0 MIL-STD-883,方法1014,条件C MIL-STD-202,方法213,条件C MIL-STD-883,法1004 J-STD-020, MSL1 MIL-STD-202,方法210,满足条件K MIL-STD-202,方法215 MIL-STD-883,方法2003 MIL-STD-883,方法1010,条件B MIL-STD-883,方法2007条件A
8339;中文规格书,Datasheet资料
info@ 1-800-201-8822 1-604-888-3084 1-800-708-9888 1-604-888-7754
For technical specifications, MSDS, tech support and more
To customize this AppGuide for your own use please email
分销商库存信息:
MG-CHEMICALS 8339
info@
ISO 9001:2000
R e g i s t e r e d Q u a l i t y S y s t e m . Q M I C e r t i f i c a t e # 0 0 4 0 0 8 To r o n t o , C a n a d a .
Directions
1. Clean defective contact with Contact Cleaner. 2. Apply Primer Prep onto contacts. 3. Use applicator to apply a thin even coat of Super Glue Liquid onto contact. 4. Wait for Super Glue Liquid to dry; approximately 5 to 10 minutes. 5. Thoroughly stir container of Conductive Coating using stir stick. 6. Using the swab from step 2, apply a thin even coat of the Conductive Coating over contact. 7. Allow to cure for 24 hours before returning to service. 8. Securely tighten lids and store kit in room temperature till next use.
BUX98A;中文规格书,Datasheet资料
November 2008 Rev 5 1/11BUX98AHigh power NPN transistorFeatures■High voltage capability ■High current capability ■Fast switching speedApplications■High frequency and efficency converters ■Linear and switching industrial equipmentDescriptionThe BUX98A is a multi-epitaxial mesa NPN transistor in TO-3 metal case, intended for industrial applications from single and three-phase mains operation.Table 1.Device summaryOrder codes Marking Package PackagingBUX98ABUX98ATO-3T rayO b s o l et e Pr o du c t(s ) -Content BUX98A2/11Content1Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.1Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10O b s o l et e Pr o du c t(s ) - O bs o l e t eP ro d u ct(s )BUX98A Electrical ratings3/111 Electrical ratingsTable 2.Absolute maximum ratingsSymbol ParameterValueUnit V CER Collector-emitter voltage (R BE ≤ 10 Ω) 1000V V CES Collector-emitter voltage (V BE = 0) 1000V V CEO Collector-emitter voltage (I B = 0) 450VV EBO Emitter-base voltage (I C = 0)7VI C Collector current30A I CM Collector peak current (t p ≤ 5ms)60A I CP Collector peak current non repetitive (t p ≤ 20 µs)80A IB Base current8A I BM Base peak current (t p ≤ 5ms) 30A P TOT Total power dissipation at T c = 25 °C 250W T stg Storage temperature-65 to 200°CT JMax. operating junction temperature200Table 3.Thermal dataSymbolParameterValue Unit R thj-case Thermal resistance junction-case max.0.7°C/WO b s o l et e Pr o du c t(s ) - O bs o l et e Pr o du ct(s )4/112 Electrical characteristics(T case = 25 °C ; unless otherwise specified)Table 4.Electrical characteristicsSymbol ParameterTest conditions Min.Typ.Max.Unit I CES Collector cut-off current(V BE = 0)V CE = 1000 VV CE = 1000 V T C = 125 °C 4004µA mA I CER Collector cut-off current (R BE = 10 Ω)V CE = 1000 VV CE = 1000 V T C = 125 °C 18µA µAI CEO Collector cut-off current (I B = 0)V CE = 1000 V 2mA I EBO Emitter cut-off current (I C = 0)V EB = 5 V2mA V CEO(sus)(1)1.Pulsed duration = 300 µs, duty cycle ≤ 1.5%Collector-emittersustaining voltage (I B = 0)I C = 200 mA450VV CER(sus)(1)Collector-emitter sustaining voltage (R BE = 10 Ω)I C = 1 A L= 2 mH 1000V V CE(sat)(1)Collector-emitter saturation voltageI C = 16 A I B = 3.2 A I C = 24 A I B = 5 A 1.55V V V BE(sat)(1)Base-emitter saturation voltage I C = 16 A I B = 3.2 A1.6V t ont s t fResistive load Turn-on time Storage time Fall timeI C = 16 A V CC = 150 V I B(on) = -I B(off) = 3.2 A130.8µs µs µsO b s o l et e Pr o du c t(s ) - O bs o l et e Pr o du ct(s )2.1 Electrical characteristics (curves)Figure 2.Safe operating area Figure 3.Derating curveFigure 4.DC current gain Figure 5.Collector-emitter saturation voltageFigure 6.Base-emitter saturation voltageFigure 7.Resistive load switching times (on)5/11Figure 8.Resistive load switching times (off)Figure 9.Reverse biased SOAO b s ol e te Pr o du ct(s)-O bs ol e te Pr o d6/11BUX98A Test circuits7/113 Test circuitsO b s o l et e Pr o du c t(s ) - O4 Package mechanical dataIn order to meet environmental requirements, ST offers these devices in ECOPACK®packages. These packages have a lead-free second level interconnect . The category ofsecond level interconnect is marked on the package and on the inner box label, incompliance with JEDEC Standard JESD97. The maximum ratings related to solderingconditions are also marked on the inner box label. ECOPACK is an ST trademark.ECOPACK specifications are available at: O b s ol e te Pr o du ct(s)-O bs ol e te Pr o du ct(s)8/11O b s ol9/11Revision history BUX98A10/115 Revision historyTable 5.Document revision historyDate RevisionChanges21-Jun-2004424-Nov-20085Inserted new Section 2.1: Electrical characteristics (curves)O b s o l et e Pr o du c t(s ) - O bs o l e t eP ro d u ct(s )分销商库存信息: STMBUX98A。
744770133;中文规格书,Datasheet资料
Bezeichnung :description := Start of winding Marking = Inductance code33% Umgebungstemperatur / temperature:+20°C100% SnMST 04-10-11MST 03-12-10RT 03-03-03MST02-03-27JH 00-12-06NameDatum / dateIt is recommended that the temperature of the part does not exceed 125°C under worst case operating conditions.Anbindung an Elektrode / soldering wire to plating:Sn/Ag/Cu - 96.5/3.0/0.5%Draht / wire:2SFBW 155°CUmgebungstemp. / ambient temperature: -40°C - + 85°C Freigabe erteilt / general release:Kunde / customerWürth Elektronik....................................................................................................................................................................Unterschrift / signature Ferrit/ferrite F Werkstoffe & Zulassungen / material & approvals :G Eigenschaften / general specifications :D Prüfgeräte / test equipment :E Testbedingungen / test conditions :Basismaterial / base material:Betriebstemp. / operating temperature: -40°C - + 125°C D-74638 Waldenburg · Max-Eyth-Strasse 1 - 3 · Germany · Telefon (+49) (0) 7942 - 945 - 0 · Telefax (+49) (0) 7942 - 945 - 400Geprüft / checked ..........................................................................................................................Kontrolliert / approvedWürth Elektronik eiSos GmbH & Co. KG744770133SPEICHERDROSSEL WE-PDPOWER-CHOKE WE-PDArtikelnummer / part number : Luftfeuchtigkeit / humidity:HP 4274 A für/for L und/and Q HP 34401 A für/for I DC und/and R DCÄnderung / modificationVersion 1Version 2Version 3Version 4Version 5 Datum / dateEndoberfläche / finishing electrode:• MarkingRoHS compliantLFdescription :MST 04-10-11MST 03-12-10RT 03-03-03MST02-03-27JH 00-12-06NameDatum / dateH Induktivitätskurve / Inductance curve :POWER-CHOKE WE-PDDATUM / DATE : 2004-10-11Kontrolliert / approvedDatum / dateUnterschrift / signature Würth ElektronikWürth Elektronik eiSos GmbH & Co. KGD-74638 Waldenburg · Max-Eyth-Strasse 1 - 3 · Germany · Telefon (+49) (0) 7942 - 945 - 0 · Telefax (+49) (0) 7942 - 945 - 400Freigabe erteilt / general release:Kunde / customer..................................................................................................................................................................................................................................................................................Geprüft / checked Version 4Version 5Änderung / modificationVersion 1Version 2Version 3a 330,0± 0,5mmb 20,20± 0,2mm+ 0,5- 1,0d 100,0± 0,2mmMST 04-10-11MST 03-12-10RT 03-03-03MST02-03-27JH 00-12-06NameDatum / dateRollenspezifikation / Reel specification:Freigabe erteilt / general release:Kunde / customerc 13,00mm....................................................................................................................................................................Datum / dateUnterschrift / signature Würth Elektronik..........................................................................................................................Würth Elektronik eiSos GmbH & Co. KGGeprüft / checked Kontrolliert / approvedD-74638 Waldenburg · Max-Eyth-Strasse 1 - 3 · Germany · Telefon (+49) (0) 7942 - 945 - 0 · Telefax (+49) (0) 7942 - 945 - 400Änderung / modificationVersion 1Version 2Version 3Version 4Version 5The force for tearing off cover tape is 10 to 130 grams in arrow direction165 to 180°feeding directionThis electronic component is designed and developed with the intention for use in general electronics equipments. Before incorporating the components into any equipments in the field such as aerospace, aviation, nuclear control, submarine, transportation, (automotive control, train control, ship control), transportation signal, disaster prevention, medical, public information network etc. where higher safety and reliability are especially required or if there is possibility of direct damage or injury to human body. In addition, even electronic component in general electronic equipments, when used in electrical circuits that require high safety, reliability functions or performance, the sufficient reliability evaluation-check for the safety must be performed before use. It is essential to give consideration when to install a protective circuit at the design stage.分销商库存信息: WURTH-ELECTRONICS 744770133。
H7018NLT;H7018NL;中文规格书,Datasheet资料
.640 [16.26]
H7037NL
CNTRY OF MFG
.015 [0.38]
.024 [0.61] 14X .040 [1.02] .560 [14.22] ( .040 [1.02]) 14X.04(= .560 [14.22])
SUGGESTED LAND PATTERN
.623 [15.83] .120 [3.05] .285 [7.24] .004 30 SURFACES
/
10GBase-T Magnetics Modules
Designed to Support 10GBase-T Transceivers
Mechanicals
H7800NL
Weight ..............................1.0 grams Tape & Reel ...............................700 Tube .............................................20
Tel: 49 7032 7806
Performance warranty of products offered on this data sheet is limited to the parameters specified. Data is subject to change without notice. Other brand and product names mentioned herein may be trademarks or registered trademarks of their respective owners. © Copyright, 2012. Pulse Electronics, Inc. All rights reserved.
SXB-4089Z;SXB-4089;中文规格书,Datasheet资料
Product DescriptionSXB-4089(Z)Absolute Maximum RatingsMax Device Current (l D )500mA Max Device Voltage (V D )6V Max RF Input Power 18dBm Max Dissipated Power2WMax Junction Temperature (T J )165°C Operating Temperature Range (T L )-40 to + 85°C Max Storage Temperature 150°CESD Rating - Human Body Model(HBM)Class 2Moisture Sensitivity LevelMSL2Operation of this device beyond any one of these limits may cause permanent dam-age. For reliable continuous operation, the device voltage and current must not exceed the maximum operating values specified in the table on page one.Bias Conditions should also satisfy the following expression:I D V D <(T J -T L )/R TH , j-l and T L =T LEADCaution! ESD sensitive device.Exceeding any one or a combination of the Absolute Maximum Rating conditions may cause permanent damage to the device. Extended application of Absolute Maximum Rating conditions to the device may reduce device reliability. Specified typical perfor-mance or functional operation of the device under Absolute Maximum Rating condi-tions is not implied.RoHS status based on EUDirective2002/95/EC (at time of this document revision).The information in this publication is believed to be accurate and reliable. However, no responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any infringement of patents, or other rights of third parties, resulting from its use. No license is granted by implication or otherwise under any patent or patent rights of RFMD. RFMD reserves the right to change component circuitry, recommended appli-cation circuitry and specifications at any time without prior notice.SXB-4089(Z)SXB-4089(Z)SXB-4089(Z)Part IdentificationAlternate marking is SXB4089 or SXB4089Z on line 1 with Trace Code on line 2.Ordering InformationPart Number Reel Size Devices/ReelSXB-40897”1000SXB-4089Z7”1000分销商库存信息:RFMDSXB-4089Z SXB-4089。
杜肯8049B投影机说明书
PLEASE READThis manual is provided as a free service by .We are in no way responsible for the contents of the manual. We do not guarantee its accuracy and we do not make any claimof copyright. The copyright remains the property of their respective owners.ABOUT () is your review and buying guide resource for DLP and LCD video projectors.Visit the site to read the latest projector news and reviews, read and comment on projector specifications, download user manuals and much more.w nl o ad edf r o mPr o j e ct o r .cLiquid Crystal ProjectorModel 28A8049BUSER'S MANUALw nl o ad ed f r o m P r o je ct o r .cf r o mBefore replacing the lamp, check the serial number of the replacement lamp bulb then contact your local dealer. Before replacing power cord, then wait at least 45 minutes, in order to Removing the lamp bulb while it is still hot could cause The LCD projector uses a glass lamp bulb. It is a mercury lamp with high internal pressure. High-pressure mercury lamps can break with a loudbang, or burn out, if jolted or scratched, or through wear over time. Each lamp has a different lifetime, and some may burst or burn out soon after you start using them. In addition, when the bulb bursts, it is possible for shards of glass to fly into the lamp housing,and for gas containing mercury to escape from the projector Handle with care: jolting or scratching could cause the lamp bulb to burst during use.If the replace lamp indicator (see "Related Messages" (Vol.2 ) and "Regarding theindicator Lamps" (Vol.2 )) comes on, replace the lamp as soon as possible. Using thelamp for long periods of time, or past the replacement date, could cause it to burst. Do not use old (used) lamps; this is a cause of breakage.If the lamp breaks soon after the first time it is used, it is possible that there are electrical problems elsewhere besides the lamp. If this happens, contact your local dealer.If the lamp should break (it will make a loud bang when it does), ventilate the room well, and make sure not to breathe the gas that comes out of the projector vents, or get it in your eyes or mouth.If the lamp should break (it will make a loud bang when it does), unplug the power cord from the outlet, and make sure to request a replacement lamp from your local dealer. Note that shards of glass could damage the projector please do not try to clean the projector or replace the lamp yourself.w nl o ad edf r o mPr o j e ct o r .c26• The LAMP indicator is also red when the lamp unit reaches high temperature.Before replacing the lamp, switch power OFF, wait approximately 20 minutes, and switch power ON again. If the LAMP indicator is still red, replace the lamp.NOTETHE LAMP (continued)Replacing the lamp7ATTENTION • Make sure that the screws are screwed in firmly. Loose screws could result in damage or injury.•Do not use with lamp cover removed.•Do not reset the lamp timer without replacing the lamp. Reset the lamp timer always when replacing the lamp. The message functions will not operate properly if the lamp timer is not reset correctly.•When the lamp has been replaced after the message of "CHANGE THE LAMP ...THE POWER WILL TURN OFF AFTER 0 hr." is displayed, or the LAMP indicator is red, complete the following operation within 10 minutes of switching power ON.8Turn on the projector power, and using the menu, reset the lamp timer• To reset the lamp timer, from the OPTION menu, select LAMP TIME.。
WP934EB2GD;中文规格书,Datasheet资料
Description
The Green source color devices are made with Gallium Phosphide Green Light Emitting Diode.
Package Dimensions
Notes: 1. All dimensions are in millimeters (inches). 2. Tolerance is ±0.25(0.01") unless otherwise noted. 3. Lead spacing is measured where the leads emerge from the package. 4. The specifications, characteristics and technical data described in the datasheet are subject to change without prior notice.
T-1 (3mm) BI-LEVEL LED INDICATOR
Part Number: WP934EB/2GD Green
Features
z Pre-trimmed leads for pc mounting. z Black case enhances contrast ratio. z High reliability life measured in years. z Housing UL rating:94V-0. z Housing material: type 66 nylon. z RoHS compliant.
/
SPEC NO: DSAE9268 APPROVED: WYNEC
REV NO: V.7 CHECKED: Allen Liu
BC04蓝牙模块规格书
3. PIO2 ——连接状态指示输出引脚，用于指示模块的连接状态：
(a)：连接状态：高电平 (b)：未连接状态：低电平
7
八、外观尺寸
技 科 帆 捷
8
九、应用接线图
有线AT指令模式： ................................................................................................................ 11 无线AT指令模块....................................................................................................................12 AT指令表................................................................................................................................12
3. 通过串口与PC连接...........................................................................................................10 十、PCB-layout注意事项..............................................................................................................10 十一、AT指令说明 ........................................................................................................................ 11
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USA 858 674 8100Germany 49 7032 7806 0Singapore 65 6287 8998Shanghai 86 21 62787060China 86 755 33966678Taiwan 886 3 4356768
1
/
Shanghai 200336 China
Taiwan R. O. C. Tel: 886 3 4356768
Tel: 858 674 8100 Fax: 858 674 8262
Tel: 49 7032 7806 0 Tel: 86 755 33966678 Fax: 49 7032 7806 135 Fax: 86 755 33966700
Tel: 86 21 62787060 Fax: 86 2162786973
Tel: 65 6287 8998 Fax: 65 6287 8998
Fax: 886 3 4356823 (Pulse) Fax: 886 3 4356820 (FRE)
Performance warranty of products offered on this data sheet is limited to the parameters specified. Data is subject to change without notice. Other brand and product
12220 World Trade Dr. D-71083 Herrenberg Aerospace Technology Bldg. Super Ocean Finance #03-02
Zhongyuan Rd.
San Diego, CA 92128 Germany
10th Kejinan Rd.
B8049NL
Mechanical
270 Ω + 750 Ω / 150nF -1.0 dB MAX -1.0 dB MAX -14 dB MIN -12 dB MIN -8 dB MIN 250 µs MAX -46 dB MIN -55 dB MIN 80 mA MAX
40 Ω MAX 1.0 kΩ MIN -45 dB MIN -30 dB MIN
2
/
B826.D (4/10)
分销商库存信息:
PULSE B8049NL
B826.D (4/10)
XDSL SPLITTER FILTER MODULE
B8049NL
SMART Series
B80Байду номын сангаас9NL
Schematic
2
ADSL &
LINE
1
3 PHONE 4
For More Information:
Pulse Worldwide Pulse Europe
Headquarters
FREQUENCY 100 Hz to 4 kHz
1 kHz 200 Hz to 4 kHz 300 Hz to 2 kHz 2k Hz to 3.4 kHz 3.4 kHz to 4 kHz 200 Hz to 4 kHz 100 Hz to 3.4 kHz 32 kHz to 2.2 MHz
40 kHz to 2.2 MHz 2.2 MHz to 12 MHz 12 MHz to 30 MHz
XDSL SPLITTER FILTER MODULE
B8049NL
SMART Series
Complies with option A of ETSI specification TS 101-952-1-1 Part of a standard series which has footprint compatibility ADSL2+ compatible POTS Central Office Splitter for standard ADSL applications
Ctr.
PM Industrial Bldg. Zhongli City
U.S.A.
High-Tech Zone
2067 Yan An Rd. West Singapore 368363 Taoyuan County 320
Nanshan District Shenzen, PR China 518057
Zeppelinstrasse 15
Pulse China Headquarters Pulse North China Pulse South Asia Pulse North Asia
B402, Shenzhen Academy of Room 2704/2705
135 Joo Seng Rd. 3F, No. 198
names mentioned herein may be trademarks or registered trademarks of their respective owners.
© Copyright, 2010. Pulse Engineering, Inc. All rights reserved.
Electrical Specifications @ 25°C
PARAMETER POTS Impedance POTS Insertion Loss POTS Insertion Loss Distortion relative to 1 kHz
POTS Return Loss
POTS Group Delay Longitudinal Balance ADSL Insertion Loss DC Current Total DC Resistance Line Side Impedance For Information - behavior at VDSL frequencies: ADSL Insertion Loss