数字钟VHDL代码
VHDL 数字时钟
VHDL数字时钟秒、分、时计数模块。
（也可以将秒、分、时分成三个模块）。
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity Counter_m_f_s isport(clk,reset : in std_logic ;bcd_h_m : out std_logic_vector(3 downto 0); --秒钟个位输出bcd_l_m : out std_logic_vector(3 downto 0); --秒钟十位输出bcd_l_f : out std_logic_vector(3 downto 0); --分钟个位输出bcd_h_f : out std_logic_vector(3 downto 0); --分钟十位输出bcd_l_s : out std_logic_vector(3 downto 0); --时钟个位输出bcd_h_s : out std_logic_vector(3 downto 0); --时钟十位输出up : out std_logic);end Counter_m_f_s ;architecture behav of Counter_m_f_s issignal bcd_h_m_r : std_logic_vector(3 downto 0); --秒钟个位内部信号signal bcd_l_m_r : std_logic_vector(3 downto 0); --秒钟十位内部信号signal bcd_h_f_r : std_logic_vector(3 downto 0); --分钟个位内部信号signal bcd_l_f_r : std_logic_vector(3 downto 0); --分钟十位内部信号signal bcd_h_s_r : std_logic_vector(3 downto 0); --时钟个位内部信号signal bcd_l_s_r : std_logic_vector(3 downto 0); --时钟个位内部信号signal up_r1 : std_logic;signal up_r2 : std_logic;beginU1: process (clk, reset) --秒钟beginif reset='0' thenbcd_h_m_r <="0000"; bcd_l_m_r <="0000"; up_r1 <='0';elseif clk'event and clk='1' thenif bcd_h_m_r ="0101" and bcd_l_m_r ="1001" thenbcd_h_m_r <="0000"; --59秒，分钟进一bcd_l_m_r <="0000";up_r1 <= '1' ;elseif bcd_l_m_r(3 downto 0) = "1001" then --秒的个位为9，十位进一，分钟不进为bcd_l_m_r(3 downto 0)<= "0000" ;bcd_h_m_r(3 downto 0) <= bcd_h_m_r(3 downto 0) + 1 ;up_r1 <= '0';elsebcd_l_m_r(3 downto 0) <= bcd_l_m_r(3 downto 0) + 1 ;up_r1 <= '0';end if;end if;end if;end if;end process;bcd_h_m <= bcd_h_m_r;bcd_l_m <= bcd_l_m_r;U2: process (up_r1 , reset) --分钟beginif reset='0' thenbcd_h_f_r <="0000"; bcd_l_f_r <="0000"; up_r2 <='0';elseif up_r1'event and up_r1='1' thenif bcd_h_f_r ="0101" and bcd_l_f_r ="1001" then --59分，时钟进一bcd_h_f_r <="0000";bcd_l_f_r <="0000";up_r2 <= '1' ;elseif bcd_l_f_r(3 downto 0) = "1001" then --分的个位为9，十位进一，时钟不进位bcd_l_f_r(3 downto 0) <= "0000" ;bcd_h_f_r(3 downto 0) <= bcd_h_f_r(3 downto 0) + 1 ;up_r2 <= '0';elsebcd_l_f_r(3 downto 0) <= bcd_l_f_r(3 downto 0) + 1 ;up_r2 <= '0';end if;end if;end if;end if;end process;bcd_h_f <= bcd_h_f_r;bcd_l_f <= bcd_l_f_r;U3: process ( up_r2 , reset) -- 时钟beginif reset='0' thenbcd_h_s_r <="0000"; bcd_l_s_r <="0000"; up <='0';elseif up_r2'event and up_r2='1' thenif bcd_h_s_r ="0010" and bcd_l_s_r ="0011" then --23时，时钟进一。
基于vhdl时钟的设计与制作(附完整代码)
三、实验程序及部分仿真波形图library ieee;use ieee。
std_logic_1164。
all；use ieee.std_logic_unsigned.all;entity colock isport(clk1，clk2，key1，key2: in std_logic;abc:out std_logic_vector（2 downto 0）;led7s:out std_logic_vector(6 downto 0) );end entity;architecture one of colock issignal ctrl:std_logic_vector(3 downto 0）；signal clk02，cs02,cm02,cs1,cs2，cm1,cm2,ch1，cp,k2，ck1，ck2:std_logic；signal s1，s2,m1，m2,h1,h2，s01，s02,m01,m02，h01，h02，s001,s002，m001，m002，h001，h002，p1，p2,disp：std_logic_vector（3 downto 0）；signal ctrl0：std_logic_vector(8 downto 0）;signal tmp1，tmp2:std_logic_vector（9 downto 0);signal k1:std_logic_vector（1 downto 0）；begin--当处于按键调时状态时,根据K1的值来确定所调整的位，被调整的位送按键2产生的脉冲（CK2),其余进位脉冲赋0屏蔽掉process(k1，clk2，clk02,cs2,cm2,ck2）begincase k1 iswhen "00" => clk02〈=clk2;cs02〈=cs2;cm02<=cm2；when "01" =〉clk02〈=ck2；cs02<='0';cm02<='0';when "10” => clk02〈=’0';cs02〈=ck2;cm02<='0’；when "11” => clk02〈='0';cs02<=’0';cm02〈=ck2;when others =〉clk02<=clk2；cs02<=cs2；cm02<=cm2;end case ;end process；--500进制计数器,每500ms对CP进行取反一次，用于闪烁控制process(clk1）beginif rising_edge(clk1) thenif ctrl0<499 then ctrl0<=ctrl0+1；else ctrl0<="000000000"；cp〈=not cp；end if；end process;——数码管动态扫描,接138的输入端process（clk1)beginif rising_edge(clk1）thenif ctrl<9 then ctrl<=ctrl+1;else ctrl〈="0000"；end if ；end if ；end process；abc<=ctrl（2 downto 0);——秒个位的计数process(clk02）beginif rising_edge（clk02) thenif s01<”1001" then s01〈=s01+1;cs1<=’0';else s01〈="0000”;cs1<=’1'；end if；end if；end process；--秒十位的计数process（cs1)beginif rising_edge(cs1）thenif s02〈"0101” then s02<=s02+1；cs2<='0';else s02〈=”0000";cs2〈='1’；end if；end if;end process;-—分个位的计数process(cs02）beginif rising_edge（cs02）thenif m01〈"1001" then m01<=m01+1;cm1<='0’；else m01<=”0000";cm1<='1’；end if;end if；-—分十位的计数process（cm1）beginif rising_edge（cm1) thenif m02〈”0101" then m02<=m02+1；cm2<='0';else m02<=”0000”;cm2<='1’；end if;end if；end process；-—小时个位的计数process（cm02)beginif rising_edge（cm02）thenif h02<”0010” thenif h01〈"1001” then h01<=h01+1;ch1〈='0’；else h01<="0000”;ch1<=’1’；end if ;elsei f h01<”0011"then h01〈=h01+1；ch1〈='0';else h01〈=”0000"；ch1〈=’1’;end if;end if；end if；end process；--小时十位的计数process（ch1)beginif rising_edge（ch1）thenif h02<”0010" then h02<=h2+1；else h02〈="0000”；end if;end if;end process;——按键一去抖动process(clk1）beginif rising_edge（clk1）thentmp1（0)<=key1;tmp1(9 downto 1）〈=tmp1(8 downto 0);1.第五章心得体会通过此次课程设计使我更加深刻的认识EDA电子电路设计的各个模块。
VerilogHDL语言数字时钟
VerilogHDL语言数字时钟EDA与数字系统设计报告实验名称：带有设臵时间功能和闹钟功能的数字钟一、设计内容和要求实验要求使用Verilog HDL进行多功能时钟的设计具体要求如下：1.能将基本的小时、分钟、及秒钟显示在数码管上2．能利用拨码开关进行时间的校正3.具有整点报时和闹钟的功能二、设计原理1．工作原理多功能数字钟系统共包括三个模块，即分频器模块、计数器模块和显示译码模块。
多功能数字钟的功能可以从整体上分为三类，分别是正常计时、时钟校对和闹钟设臵，所以考虑在系统中设臵一个模式控制信号mode。
模式控制信号对应一个按键，每按一次按键相当于工作模式进行一次变换，多次按下则数字钟将在正常计时、时间校对和闹钟设臵三个工作模式下依次循环。
在设计中，时钟校对和闹钟设臵工作模式都需要对时间进行设臵，通常是对小时和分钟进行设臵，所以需要在系统中设臵一个时间设臵信号set，对应一个按键，每按一次相当于在小时设臵和分钟设臵之间进行转换。
时间设臵时，分钟和小时计时单位之间互相独立，不存在进位关系。
同时设臵一个时间调整信号accum，每按一次与accum对应的按键，相当于对需要调整的分钟或小时的数字进行加1操作。
数字钟的计时输出信号时必不可少的，用hour，min和sec信号分别表示需要显示的小时、分钟和秒钟的计时结果，上述计时结果将通过译码显示模块进行译码后，连接到外部的七段数码显示器。
在带有闹钟设臵功能的数字钟中，闹钟输出信号也是必不可少的，到达到闹钟设臵的时间后，要向外部扬声器发送一个闹铃信号，设臵alert。
另外，我们还提供了闹钟铃声信号voice，当voice为0的时候，闹钟处于静音状态下，即使时间达到闹钟设定的时间也不会发声，当voice为1的时候，可以正常闹铃，voice信号对应一个拨码开关。
本设计中的小时、分钟和秒钟的计时结果采用BCD码表示方法。
采用这种表示方法便于对数结果的高位和低位分别进行译码。
数字钟vhdl代码
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity shuzizhong isport(clk : in std_logic; ‐‐‐时钟信号choose,set,s1,s2:in std_logic; ‐‐‐‐12/24 时制选择，设置，时设置，分设置 am,pm,spk:out std_logic; ‐‐‐‐上午，下午，报时信号b:out std_logic_vector(6 downto 0); ‐‐‐‐七段数码管cat:out std_logic_vector(5 downto 0) ‐‐‐数码管选通控制信号);end shuzizhong;architecture a of shuzizhong issignal hou1 : integer range 0 to 23; ‐‐‐24 时制小时信号signal hou2 : integer range 0 to 11; ‐‐‐12 时制小时信号signal min : integer range 0 to 59; ‐‐‐分信号signal sec : integer range 0 to 59; ‐‐‐秒信号signal temp: integer range 0 to 19;signal clk0:std_logic; ‐‐‐‐‐计时时钟信号signal tmp:integer range 0 to 999999;signal a:std_logic_vector(1 downto 0);type str is array (0 to 5) of integer range 0 to 9; ‐‐‐定义整型数组signal timeout : str;signal count : integer range 0 to 5;beginp1:process(clk) ‐‐‐‐分频模块beginif clk'event and clk='1' thenif tmp= 999999 then ‐‐‐1M 分频；tmp<=0;elsetmp<=tmp+1;end if;if tmp<500000 thenclk0<='0';elseclk0<='1';end if;end if;end process p1;p2: process(clk0,choose,set,s1,s2)beginif clk0'event and clk0='1' thenif set='0' then ‐‐‐‐计时模块sec<=sec+1; ‐‐‐‐秒计时if sec=59 thensec<=0; ‐‐‐‐‐秒进位min<=min+1; ‐‐‐‐分计时if min=59 thenmin<=0;hou1<=hou1+1; ‐‐‐‐24 小时进制小时位计时if hou1=23 thenhou1<=0;end if;hou2<=hou2+1; ‐‐‐‐12 小时进制小时位计时if hou2=11 thenhou2<=0;end if;end if;end if;if choose='0' then ‐‐‐‐‐12 时制am/pm 显示控制if hou1>=12 thena<="01";elsif hou1<12 thena<="10";end if;else a<="00";end if;elsif set='1' then ‐‐‐‐‐设置时间模式if s2='1' then ‐‐‐‐‐设置分if min=59 thenmin<=0;elsemin<=min+1;end if;end if;if s1='1' then ‐‐‐‐‐设置时hou1<=hou1+1; ‐‐‐‐24 时制if hou1=23 thenhou1<=0;end if;hou2<=hou2+1; ‐‐‐‐‐12 时制if hou2=11 thenhou2<=0;end if;if choose='0' then ‐‐‐‐‐12 时制am/pm 显示控制if hou1>=12 thena<="01";elsif hou1<12 thena<="10";end if;else a<="00";end if;end if;end if;if min=0 then ‐‐‐‐‐整点报时if timeout(0)<=5 and timeout(1)=0 then ‐‐‐‐蜂鸣器响5 秒spk<='1';elsespk<='0';end if;elsespk<='0';end if;end if;end process p2;p3:process(clk,choose) ‐‐‐‐‐译码显示模块begintimeout(0)<=sec rem 10; ‐‐‐‐‐‐秒后一位timeout(1)<=sec/10; ‐‐‐‐‐‐秒前一位timeout(2)<=min rem 10; ‐‐‐‐‐分后一位timeout(3)<=min/10; ‐‐‐‐‐‐分前一位if choose='0' then ‐‐‐‐‐‐‐根据choose 信号选择输出时制timeout(4)<=hou2 rem 10;timeout(5)<=hou2/10;elsif choose='1' thentimeout(4)<=hou1 rem 10;timeout(5)<=hou1/10;end if;if clk'event and clk='1' thenif count=5 thencount<=0;elsecount<=count+1;end if;case count iswhen 0=>cat<="011111"; temp<=timeout(5); ‐‐‐‐‐选通控制信号控制对when 1=>cat<="101111"; temp<=timeout(4); 应输出位数when 2=>cat<="110111"; temp<=timeout(3);when 3=>cat<="111011"; temp<=timeout(2);when 4=>cat<="111101"; temp<=timeout(1);when 5=>cat<="111110"; temp<=timeout(0);when others=>cat<="111111"; temp<=0;end case;case temp iswhen 0=>b<="1111110"; ‐‐‐‐‐输出0when 1=>b<="0110000"; ‐‐‐‐‐输出1when 2=>b<="1101101"; ‐‐‐‐‐输出2when 3=>b<="1111001"; ‐‐‐‐‐输出3when 4=>b<="0110011"; ‐‐‐‐‐输出4when 5=>b<="1011011"; ‐‐‐‐‐输出5when 6=>b<="1011111"; ‐‐‐‐‐输出6when 7=>b<="1110000"; ‐‐‐‐‐输出7when 8=>b<="1111111"; ‐‐‐‐‐输出8when 9=>b<="1111011"; ‐‐‐‐‐输出9when others=>b<="0000000"; ‐‐‐‐‐错误，输出0end case;end process p3;am<=a(1);pm<=a(0);end a;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity shuzizhong isport(clk:in std_logic;clear:in std_logic;choose:in std_logic;c:out std_logic_vector(6 downto 0);cat:out std_logic_vector(5 downto 0));end shuzizhong;architecture b of shuzizhong issignal tmp1:integer range 0 to 49999;signal tmp2:integer range 0 to 99999;signal m_flag,s_flag:integer range 0 to 59;signal h_flag1:integer range 0 to 23;signal h_flag2:integer range 0 to 11;signal clk1:std_logic;signal temp: integer range 0 to 19;type str is array(0 to 5)of integer range 0 to 9;signal timeout:str;signal count:integer range 0 to 5;beginp1:process(clear,clk)beginif clear='0' thentmp1<=0;elsif clk'event and clk='1' thenif tmp1=49999 thentmp1<=0;else tmp1<=tmp1+1;end if;if tmp1=49999 thentmp2<=tmp2+1;if tmp2=9999 thentmp2<=0;end if;end if;end process p1;p2:process(tmp2)beginif tmp2=99999 thenclk1<='1';elseclk1<='0';end if;end process p2;p3:process(all)beginif clk1'event and clk1='0'thens_flag<=s_flag+1;ifs_flag=59 thens_flag<=0;m_flag<=m_flag+1;if m_flag=59 thenm_flag<=0;h_flag1<=h_flag1+1;if h_flag1=23 thenh_flag1<=0;end if;h_flag2<=h_flag2+1;if h_flag2=11 thenh_flag2<=0;end if;end if;end if;end if;end process p3;p4:process(clk,choose)begintimeout(0)<=s_flag rem 10;timeout(1)<=s_flag/10;timeout(2)<=m_flag rem 10;timeout(3)<=m_flag/10;if choose='0' thentimeout(4)<=h_flag2 rem 10;timeout(5)<=h_flag2/10;elsif choose='1' thentimeout(4)<=h_flag1 rem 10;timeout(5)<=h_flag1/10;end if;if clk'event and clk='1' thenif count=5 thencount<=0;elsecount<=count+1;end if;end if;case count iswhen 0=>cat<="011111"; temp<=timeout(5);when 1=>cat<="101111"; temp<=timeout(4);when 2=>cat<="110111"; temp<=timeout(3);when 3=>cat<="111011"; temp<=timeout(2);when 4=>cat<="111101"; temp<=timeout(1);when 5=>cat<="111110"; temp<=timeout(0);when others=>cat<="111111"; temp<=0;end case;case temp iswhen 0=>c<="1111110";when 1=>c<="0110000";when 2=>c<="1101101";when 3=>c<="1111001";when 4=>c<="0110011";when 5=>c<="1011011";when 6=>c<="1011111";when 7=>c<="1110000";when 8=>c<="1111111";when 9=>c<="1111011";when others=>c<="0000000";end case;end process p4;end b;。
数字时钟的Verilog代码
数字时钟的Verilog代码一、功能说明：1.可准确计时2.可按键复位3.可模式切换是正常计数还是调整秒位，或调整分位或小时位，再按置数键可调整4.切换为调整模式时，相应的被调整位会2Hz的闪烁注：我的FPGA开发板时钟为33.8688Mhz我的主体代码里的信号都是1有效，但开发板按键按下去时是置0，所以我在主体代码的前面都使用了反相器。
代码均调试成功，没有任何问题，同学们可以放心复制粘贴。
二、模块说明1.主体代码2.按键消抖模块3.分频器模块我的主题代码中嵌入了按键消抖模块，按键消抖中又嵌入了分频器。
请阅读此文档的同学不要漏加，否则不能正常工作三、代码(1)主体代码module clock(seg7,scan,clk,clr1,mode2,inc2);output[7:0] seg7;output[5:0] scan;input clk; //时钟输入20MHzinput clr1; //清零端input mode2; //控制信号，用于选择模式input inc2; //置数信号//按键全部反逻辑wire clr,mode,inc;assign clr=~clr1;wire mode1,inc1;assign mode=~mode1;assign inc=~inc1;reg[7:0] seg7; //8段显示控制信号（abcdefg.dp）reg[5:0] scan; //数码管地址选择信号reg[1:0] state; //定义4种状态reg[3:0] qhh,qhl,qmh,qml,qsh,qsl; //小时、分、秒的高位和低位reg[3:0] data;reg[2:0] cnt; //扫描数码管的计数器reg clk1khz,clk1hz,clk2hz; //1kHz、1Hz、2Hz的分频信号reg[2:0] blink; //闪烁信号reg inc_reg;//按键置数寄存器reg[7:0] sec,min;//定义按键置数时的时分秒寄存器reg[7:0] hour;parameter state0=2'b00,state1=2'b01,state2=2'b10,state3=2'b11;//状态0-3定义reg[14:0] n1;reg[24:0] n2;reg[23:0] n3;//----------------------按键消抖-----------------------------IP_ButtonDebounce m1(.clk(clk),.rst(clr),.BTN0(mode2),.BTN_DEB(mode1));IP_ButtonDebounce m2(.clk(clk),.rst(clr),.BTN0(inc2),.BTN_DEB(inc1));assign mode=~mode1;assign inc=~inc1;//-----------------------------800Hz分频，用于扫描数码管地址--------always@(posedge clk or posedge clr)beginif(clr) beginclk1khz<=0;n1<=0;endelse if(n1==42336/2-1) beginclk1khz<=~clk1khz;n1<=0;endelse n1<=n1+1;end//---------------------- 1Hz分频，用于计时-----------------------------always@(posedge clk or posedge clr)beginif(clr) beginclk1hz<=0;n2<=0;endelse if(n2==33868800/2-1) beginclk1hz<=~clk1hz;n2<=0;endelse n2<=n2+1;end//---------------------- 2Hz分频，用于闪烁----------------------------- always@(posedge clk or posedge clr)beginif(clr) beginclk2hz<=0;n3<=0;endelse if(n3==16934400/2-1) beginclk2hz<=~clk2hz;n3<=0;endelse n3<=n3+1;end//-------------------------模式转换-------------------------always @(posedge mode or posedge clr)beginif(clr) beginstate<=2'b00;endelse beginif(state==2'b11) beginstate<=2'b00;endelse beginstate<=state+1;endendend//-------------------------状态控制-----------------------------always @(posedge clk1hz or posedge clr)beginif(clr) beginhour<=7'b0000000;min<=7'b0000000;sec<=7'b0000000;inc_reg<=0;endelse begincase(state)state0:begin //模式0，正常计时if(sec==8'd59)beginsec<=8'd0;if(min==8'd59) beginmin<=8'd0;if(hour==8'd23) beginhour<=8'd0;endelse beginhour<=hour+1;endendelse beginmin<=min+1;endendelse beginsec<=sec+1;endendstate1:begin //模式1，设定小时时间if(inc)b egin//如果置数键按下if(!inc_reg) begin //如果置数寄存器值为0inc_reg<=1;//置数寄存器值置1if(hour==8'd23) beginhour<=8'd0;endelse beginhour<=hour+1;endendendelse begin//如果置数键未按下inc_reg<=0; //置数寄存器还是为0endendstate2:begin //模式2，设定分钟时间if(inc) beginif(!inc_reg) begininc_reg<=1;if(min==8'd59) beginmin<=8'd0;endelse beginmin<=min+1;endendendelse begininc_reg<=0;endendstate3:begin //模式3，设定秒钟时间if(inc) beginif(!inc_reg) begininc_reg<=1;if(sec==8'd59) beginsec<=8'd0;endelse beginsec<=sec+1;endendendelse begininc_reg<=0;endendendcaseendend//--------------------------------当进行时间设定时，令数码管闪烁----------------------- always @(state,clk2hz,clr) beginif(clr) beginblink[2:0]<=3'b111;endelse begincase(state)state0:blink[2:0]<=3'b111;//正常计数时，闪烁信号全为1state1:blink[2]<=clk2hz;state2:blink[1]<=clk2hz;state3:blink[0]<=clk2hz;default:blink[2:0]<=3'b111;//默认为1endcaseendend//--------------------------秒计数的十进制转BCD码---------------------------always @(sec,clr) beginif(clr) beginqsh[3:0]<=4'b0000;qsl[3:0]<=4'b0000;endelse begincase(sec[7:0])8'd0:begin qsh[3:0]<='b0000;qsl[3:0]<='b0000; end 8'd1:begin qsh[3:0]<='b0000;qsl[3:0]<='b0001; end 8'd2:begin qsh[3:0]<='b0000;qsl[3:0]<='b0010; end 8'd3:begin qsh[3:0]<='b0000;qsl[3:0]<='b0011; end 8'd4:begin qsh[3:0]<='b0000;qsl[3:0]<='b0100; end 8'd5:begin qsh[3:0]<='b0000;qsl[3:0]<='b0101; end 8'd6:begin qsh[3:0]<='b0000;qsl[3:0]<='b0110; end 8'd7:begin qsh[3:0]<='b0000;qsl[3:0]<='b0111; end 8'd8:begin qsh[3:0]<='b0000;qsl[3:0]<='b1000; end 8'd9:begin qsh[3:0]<='b0000;qsl[3:0]<='b1001; end 8'd10:begin qsh[3:0]<='b0001;qsl[3:0]<='b0000; end 8'd11:begin qsh[3:0]<='b0001;qsl[3:0]<='b0001; end 8'd12:begin qsh[3:0]<='b0001;qsl[3:0]<='b0010; end 8'd13:begin qsh[3:0]<='b0001;qsl[3:0]<='b0011; end 8'd14:begin qsh[3:0]<='b0001;qsl[3:0]<='b0100; end 8'd15:begin qsh[3:0]<='b0001;qsl[3:0]<='b0101; end 8'd16:begin qsh[3:0]<='b0001;qsl[3:0]<='b0110; end 8'd17:begin qsh[3:0]<='b0001;qsl[3:0]<='b0111; end 8'd18:begin qsh[3:0]<='b0001;qsl[3:0]<='b1000; end 8'd19:begin qsh[3:0]<='b0001;qsl[3:0]<='b1001; end 8'd20:begin qsh[3:0]<='b0010;qsl[3:0]<='b0000; end 8'd21:begin qsh[3:0]<='b0010;qsl[3:0]<='b0001; end 8'd22:begin qsh[3:0]<='b0010;qsl[3:0]<='b0010; end 8'd23:begin qsh[3:0]<='b0010;qsl[3:0]<='b0011; end 8'd24:begin qsh[3:0]<='b0010;qsl[3:0]<='b0100; end 8'd25:begin qsh[3:0]<='b0010;qsl[3:0]<='b0101; end 8'd26:begin qsh[3:0]<='b0010;qsl[3:0]<='b0110; end 8'd27:begin qsh[3:0]<='b0010;qsl[3:0]<='b0111; end 8'd28:begin qsh[3:0]<='b0010;qsl[3:0]<='b1000; end 8'd29:begin qsh[3:0]<='b0010;qsl[3:0]<='b1001; end 8'd30:begin qsh[3:0]<='b0011;qsl[3:0]<='b0000; end 8'd31:begin qsh[3:0]<='b0011;qsl[3:0]<='b0001; end 8'd32:begin qsh[3:0]<='b0011;qsl[3:0]<='b0010; end 8'd33:begin qsh[3:0]<='b0011;qsl[3:0]<='b0011; end 8'd34:begin qsh[3:0]<='b0011;qsl[3:0]<='b0100; end 8'd35:begin qsh[3:0]<='b0011;qsl[3:0]<='b0101; end 8'd36:begin qsh[3:0]<='b0011;qsl[3:0]<='b0110; end 8'd37:begin qsh[3:0]<='b0011;qsl[3:0]<='b0111; end 8'd38:begin qsh[3:0]<='b0011;qsl[3:0]<='b1000; end 8'd39:begin qsh[3:0]<='b0011;qsl[3:0]<='b1001; end 8'd40:begin qsh[3:0]<='b0100;qsl[3:0]<='b0000; end 8'd41:begin qsh[3:0]<='b0100;qsl[3:0]<='b0001; end 8'd42:begin qsh[3:0]<='b0100;qsl[3:0]<='b0010; end8'd44:begin qsh[3:0]<='b0100;qsl[3:0]<='b0100; end8'd45:begin qsh[3:0]<='b0100;qsl[3:0]<='b0101; end8'd46:begin qsh[3:0]<='b0100;qsl[3:0]<='b0110; end8'd47:begin qsh[3:0]<='b0100;qsl[3:0]<='b0111; end8'd48:begin qsh[3:0]<='b0100;qsl[3:0]<='b1000; end8'd49:begin qsh[3:0]<='b0100;qsl[3:0]<='b1001; end8'd50:begin qsh[3:0]<='b0101;qsl[3:0]<='b0000; end8'd51:begin qsh[3:0]<='b0101;qsl[3:0]<='b0001; end8'd52:begin qsh[3:0]<='b0101;qsl[3:0]<='b0010; end8'd53:begin qsh[3:0]<='b0101;qsl[3:0]<='b0011; end8'd54:begin qsh[3:0]<='b0101;qsl[3:0]<='b0100; end8'd55:begin qsh[3:0]<='b0101;qsl[3:0]<='b0101; end8'd56:begin qsh[3:0]<='b0101;qsl[3:0]<='b0110; end8'd57:begin qsh[3:0]<='b0101;qsl[3:0]<='b0111; end8'd58:begin qsh[3:0]<='b0101;qsl[3:0]<='b1000; end8'd59:begin qsh[3:0]<='b0101;qsl[3:0]<='b1001; enddefault: begin qsh[3:0]<=4'b0000;qsl[3:0]<='b0; endendcaseendend//---------------------------分计数的十进制转BCD码-------------------- always @(min,clr)beginif(clr) beginqmh[3:0]<='b0000;qml[3:0]<='b0000;endelse begincase(min[7:0])8'd0:begin qmh[3:0]<='b0000;qml[3:0]<='b0000; end8'd1:begin qmh[3:0]<='b0000;qml[3:0]<='b0001; end8'd2:begin qmh[3:0]<='b0000;qml[3:0]<='b0010; end8'd3:begin qmh[3:0]<='b0000;qml[3:0]<='b0011; end8'd4:begin qmh[3:0]<='b0000;qml[3:0]<='b0100; end8'd5:begin qmh[3:0]<='b0000;qml[3:0]<='b0101; end8'd6:begin qmh[3:0]<='b0000;qml[3:0]<='b0110; end8'd7:begin qmh[3:0]<='b0000;qml[3:0]<='b0111; end8'd8:begin qmh[3:0]<='b0000;qml[3:0]<='b1000; end8'd9:begin qmh[3:0]<='b0000;qml[3:0]<='b1001; end8'd10:begin qmh[3:0]<='b0001;qml[3:0]<='b0000; end8'd11:begin qmh[3:0]<='b0001;qml[3:0]<='b0001; end8'd12:begin qmh[3:0]<='b0001;qml[3:0]<='b0010; end8'd13:begin qmh[3:0]<='b0001;qml[3:0]<='b0011; end8'd15:begin qmh[3:0]<='b0001;qml[3:0]<='b0101; end 8'd16:begin qmh[3:0]<='b0001;qml[3:0]<='b0110; end 8'd17:begin qmh[3:0]<='b0001;qml[3:0]<='b0111; end 8'd18:begin qmh[3:0]<='b0001;qml[3:0]<='b1000; end 8'd19:begin qmh[3:0]<='b0001;qml[3:0]<='b1001; end 8'd20:begin qmh[3:0]<='b0010;qml[3:0]<='b0000; end 8'd21:begin qmh[3:0]<='b0010;qml[3:0]<='b0001; end 8'd22:begin qmh[3:0]<='b0010;qml[3:0]<='b0010; end 8'd23:begin qmh[3:0]<='b0010;qml[3:0]<='b0011; end 8'd24:begin qmh[3:0]<='b0010;qml[3:0]<='b0100; end 8'd25:begin qmh[3:0]<='b0010;qml[3:0]<='b0101; end 8'd26:begin qmh[3:0]<='b0010;qml[3:0]<='b0110; end 8'd27:begin qmh[3:0]<='b0010;qml[3:0]<='b0111; end 8'd28:begin qmh[3:0]<='b0010;qml[3:0]<='b1000; end 8'd29:begin qmh[3:0]<='b0010;qml[3:0]<='b1001; end 8'd30:begin qmh[3:0]<='b0011;qml[3:0]<='b0000; end 8'd31:begin qmh[3:0]<='b0011;qml[3:0]<='b0001; end 8'd32:begin qmh[3:0]<='b0011;qml[3:0]<='b0010; end 8'd33:begin qmh[3:0]<='b0011;qml[3:0]<='b0011; end 8'd34:begin qmh[3:0]<='b0011;qml[3:0]<='b0100; end 8'd35:begin qmh[3:0]<='b0011;qml[3:0]<='b0101; end 8'd36:begin qmh[3:0]<='b0011;qml[3:0]<='b0110; end 8'd37:begin qmh[3:0]<='b0011;qml[3:0]<='b0111; end 8'd38:begin qmh[3:0]<='b0011;qml[3:0]<='b1000; end 8'd39:begin qmh[3:0]<='b0011;qml[3:0]<='b1001; end 8'd40:begin qmh[3:0]<='b0100;qml[3:0]<='b0000; end 8'd41:begin qmh[3:0]<='b0100;qml[3:0]<='b0001; end 8'd42:begin qmh[3:0]<='b0100;qml[3:0]<='b0010; end 8'd43:begin qmh[3:0]<='b0100;qml[3:0]<='b0011; end 8'd44:begin qmh[3:0]<='b0100;qml[3:0]<='b0100; end 8'd45:begin qmh[3:0]<='b0100;qml[3:0]<='b0101; end 8'd46:begin qmh[3:0]<='b0100;qml[3:0]<='b0110; end 8'd47:begin qmh[3:0]<='b0100;qml[3:0]<='b0111; end 8'd48:begin qmh[3:0]<='b0100;qml[3:0]<='b1000; end 8'd49:begin qmh[3:0]<='b0100;qml[3:0]<='b1001; end 8'd50:begin qmh[3:0]<='b0101;qml[3:0]<='b0000; end 8'd51:begin qmh[3:0]<='b0101;qml[3:0]<='b0001; end 8'd52:begin qmh[3:0]<='b0101;qml[3:0]<='b0010; end 8'd53:begin qmh[3:0]<='b0101;qml[3:0]<='b0011; end 8'd54:begin qmh[3:0]<='b0101;qml[3:0]<='b0100; end 8'd55:begin qmh[3:0]<='b0101;qml[3:0]<='b0101; end 8'd56:begin qmh[3:0]<='b0101;qml[3:0]<='b0110; end 8'd57:begin qmh[3:0]<='b0101;qml[3:0]<='b0111; end8'd59:begin qmh[3:0]<='b0101;qml[3:0]<='b1001; enddefault:begin qmh[3:0]<='b0;qml[3:0]<='b0; endendcaseendend//----------------------------小时计数的十进制转BCD码------------------------ always @(hour,clr)beginif(clr) beginqhh[3:0]<='b0000;qhl[3:0]<='b0000;endelse begincase(hour)8'd0:begin qhh[3:0]<='b0000;qhl[3:0]<='b0000; end8'd1:begin qhh[3:0]<='b0000;qhl[3:0]<='b0001; end8'd2:begin qhh[3:0]<='b0000;qhl[3:0]<='b0010; end8'd3:begin qhh[3:0]<='b0000;qhl[3:0]<='b0011; end8'd4:begin qhh[3:0]<='b0000;qhl[3:0]<='b0100; end8'd5:begin qhh[3:0]<='b0000;qhl[3:0]<='b0101; end8'd6:begin qhh[3:0]<='b0000;qhl[3:0]<='b0110; end8'd7:begin qhh[3:0]<='b0000;qhl[3:0]<='b0111; end8'd8:begin qhh[3:0]<='b0000;qhl[3:0]<='b1000; end8'd9:begin qhh[3:0]<='b0000;qhl[3:0]<='b1001; end8'd10:begin qhh[3:0]<='b0001;qhl[3:0]<='b0000; end8'd11:begin qhh[3:0]<='b0001;qhl[3:0]<='b0001; end8'd12:begin qhh[3:0]<='b0001;qhl[3:0]<='b0010; end8'd13:begin qhh[3:0]<='b0001;qhl[3:0]<='b0011; end8'd14:begin qhh[3:0]<='b0001;qhl[3:0]<='b0100; end8'd15:begin qhh[3:0]<='b0001;qhl[3:0]<='b0101; end8'd16:begin qhh[3:0]<='b0001;qhl[3:0]<='b0110; end8'd17:begin qhh[3:0]<='b0001;qhl[3:0]<='b0111; end8'd18:begin qhh[3:0]<='b0001;qhl[3:0]<='b1000; end8'd19:begin qhh[3:0]<='b0001;qhl[3:0]<='b1001; end8'd20:begin qhh[3:0]<='b0010;qhl[3:0]<='b0000; end8'd21:begin qhh[3:0]<='b0010;qhl[3:0]<='b0001; end8'd22:begin qhh[3:0]<='b0010;qhl[3:0]<='b0010; end8'd23:begin qhh[3:0]<='b0010;qhl[3:0]<='b0011; enddefault:begin qhh[3:0]<='b0;qhl[3:0]<='b0; endendcaseendend//------------------------------数码管动态扫描-------------------------------------always @(posedge clk1khz or posedge clr) beginif(clr) begincnt<=3'b000;scan<=6'b111111;data<=4'b0000;endelse if(clk1khz) beginif(cnt==3'b101) cnt<=3'b000;else cnt<=cnt+1;case(cnt)3'b000:begin data[3:0]<=qsl[3:0];scan[5:0]<=6'b000001&{6{blink[0]}}; end3'b001:begin data[3:0]<=qsh[3:0];scan[5:0]<=6'b000010&{6{blink[0]}}; end3'b010:begin data[3:0]<=qml[3:0];scan[5:0]<=6'b000100&{6{blink[1]}}; end3'b011:begin data[3:0]<=qmh[3:0];scan[5:0]<=6'b001000&{6{blink[1]}}; end3'b100:begin data[3:0]<=qhl[3:0];scan[5:0]<=6'b010000&{6{blink[2]}}; end3'b101:begin data[3:0]<=qhh[3:0];scan[5:0]<=6'b100000&{6{blink[2]}}; endendcaseendend//-----------------------------------7段译码----------------------------------------always @(data)begincase(data[3:0])4'b0000:seg7[7:0]=8'b00111111; //04'b0001:seg7[7:0]=8'b00000110; //14'b0010:seg7[7:0]=8'b01011011; //24'b0011:seg7[7:0]=8'b01001111; //34'b0100:seg7[7:0]=8'b01100110; //44'b0101:seg7[7:0]=8'b01101101; //54'b0110:seg7[7:0]=8'b01111101; //64'b0111:seg7[7:0]=8'b00000111; //74'b1000:seg7[7:0]=8'b01111111; //84'b1001:seg7[7:0]=8'b01101111; //9default:seg7[7:0]=8'b00111111; //0endcaseendendmodule(2)按键消抖模块module IP_ButtonDebounce( clk,rst,BTN0,BTN_DEB );input clk;input rst;input BTN0;output BTN_DEB;//分频得200HZ，5ms时钟wire clk_169344;IP_1Hz #(169344) U1(.clk(clk),.rst(rst),.clk_N(clk_169344));reg BTN_r,BTN_rr,BTN_rrr;always@(posedge rst,posedge clk_169344 ) beginif(rst) beginBTN_rrr<=1'b1;BTN_rr<=1'b1;BTN_r<=1'b1;endelse beginBTN_rrr<=BTN_rr;BTN_rr<=BTN_r;BTN_r<=BTN0;endendassign BTN_DEB=BTN_r&BTN_rr&BTN_rrr;endmodule(3)分频器模块module IP_1Hz(clk,rst,clk_N); //clk=33.8688MHz,N分频模块input clk;input rst;output reg clk_N;parameter N=4;integer count;always@(posedge clk or posedge rst)beginif(rst) beginclk_N<=0;count<=0;endelse if(count==N/2-1) beginclk_N<= ~clk_N;count<=0;end。
#基于VHDL语言的数字钟设计
一．程序代码及其仿真：1．cnt60子模块代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY V_cnt60 ISPORT ( clk :IN std_logic;Q0,Q1,Q2,Q3,Q4,Q5,Q6,QC :OUT std_logic);END V_cnt60;ARCHITECTURE func OF V_cnt60 ISSIGNAL count1 :std_logic_vector(3 downto 0);SIGNAL count2 :std_logic_vector(3 downto 0);SIGNAL carryin:std_logic;BEGINQ0 <= count1(0);Q1 <= count1(1);Q2 <= count1(2);Q3 <= count1(3);Q4 <= count2(0);Q5 <= count2(1);Q6 <= count2(2);QC <= carryin;process(clk)BEGINif (clk'event AND clk='1') thencarryin<='0';if(count1="1001")thencount1<="0000";count2<=count2+1;elsecount1<=count1+1;END if;if(count2="0101"AND count1="1001")thencount2<="0000";count1<="0000";carryin<='1';END if;END if;END process;END func;cnt60仿真波形：2．cnt24子模块代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY V_cnt24 ISPORT ( clk :IN std_logic;Q0,Q1,Q2,Q3,Q4,Q5:OUT std_logic); END V_cnt24;ARCHITECTURE func_cnt24 OF V_cnt24 IS SIGNAL count1 :std_logic_vector(3 downto 0); SIGNAL count2 :std_logic_vector(3 downto 0); SIGNAL carryin:std_logic;BEGINQ0 <= count1(0);Q1 <= count1(1);Q2 <= count1(2);Q3 <= count1(3);Q4 <= count2(0);Q5 <= count2(1);process(clk)BEGINif (clk'event and clk='1') thenif(count1="1001")thencount1<="0000";count2<=count2+1;elsecount1<=count1+1;END if;if(count2="0010" AND count1="0011")thencount2<="0000";count1<="0000";END if;END if;END process;END func_cnt24;cnt24仿真波形：3．cnt1000字模块代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity V_cnt1000 isport( clk :in std_logic;cnt1000 :out std_logic;clk_c :out std_logic);end V_cnt1000;architecture bhv of V_cnt1000 issignal tmp:std_logic_vector(9 downto 0);signal amp:std_logic_vector(8 downto 0);beginprocess(clk)beginif (clk'event and clk='1') thenif (tmp=1023)then tmp<="0000000000";else tmp<=tmp+1;end if;if (tmp<511) then cnt1000<='0';else cnt1000<='1';end if;end if;end process;process(clk)beginif (clk'event and clk='1') thenif (amp=511)then amp<="000000000";else amp<=amp+1;end if;if (amp<255) then clk_c<='0';else clk_c<='1';end if;end if;end process;end bhv;cnt1000仿真波形：4．clk_c子模块代码：library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;ENTITY V_clk_c ISPORT(clk,CLK_C,M1,S1,SS,MM,HH,CTRL : IN STD_LOGIC;CLKS,CLKM,CLKH : OUT STD_LOGIC);END V_clk_c;ARCHITECTURE func OF V_clk_c ISBEGINprocessbeginCLKS<=(CTRL AND CLK) OR((NOT CTRL) AND HH AND MM AND (NOT SS) AND CLK_C);CLKM<=(CTRL AND S1) OR((NOT CTRL) AND HH AND (NOT MM) AND SS AND CLK_C);CLKH<=(CTRL AND M1) OR((NOT CTRL) AND (NOT HH) AND MM AND SS AND CLK_C);END process;END func;5．display子模块代码：library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;ENTITY display ISPORT( clk : IN std_logic;LED1Q_0,LED1Q_1,LED1Q_2,LED1Q_3: IN std_logic;LED2Q_0,LED2Q_1,LED2Q_2,LED2Q_3: IN std_logic;LED3Q_0,LED3Q_1,LED3Q_2,LED3Q_3: IN std_logic;LED4Q_0,LED4Q_1,LED4Q_2,LED4Q_3: IN std_logic;LED5Q_0,LED5Q_1,LED5Q_2,LED5Q_3: IN std_logic;LED6Q_0,LED6Q_1,LED6Q_2,LED6Q_3: IN std_logic;LED1,LED2,LED3,LED4,LED5,LED6: OUT std_logic;SE_A,SE_B,SE_C,SE_D,SE_E,SE_F,SE_G: OUT std_logic); END display;ARCHITECTURE func OF display ISSIGNAL ctrl : std_logic_vector(2 downto 0);SIGNAL code : std_logic_vector(3 downto 0);BEGINprocess(ctrl)BEGINCASE ctrl ISWHEN "000"=> L ED1<='1';LED2<='0';LED3<='0';LED4<='0';LED5<='0';LED6<='0';code(0)<=LED1Q_0;code(1)<=LED1Q_1;code(2)<=LED1Q_2;code(3)<=LED1Q_3; WHEN"001"=> L ED1<='0';LED2<='1';LED3<='0';LED4<='0';LED5<='0';LED6<='0';code(0)<=LED2Q_0;code(1)<=LED2Q_1;code(2)<=LED2Q_2;code(3)<=LED2Q_3; WHEN "010"=> L ED1<='0';LED2<='0';LED3<='1';LED4<='0';LED5<='0';LED6<='0';code(0)<=LED3Q_0;code(1)<=LED3Q_1;code(2)<=LED3Q_2;code(3)<=LED3Q_3; WHEN "011"=>LED1<='0';LED2<='0';LED3<='0';LED4<='1';LED5<='0';LED6<='0';code(0)<=LED4Q_0;code(1)<=LED4Q_1;code(2)<=LED4Q_2;code(3)<=LED4Q_3; WHEN "100"=>LED1<='0';LED2<='0';LED3<='0';LED4<='0';LED5<='1';LED6<='0';code(0)<=LED5Q_0;code(1)<=LED5Q_1;code(2)<=LED5Q_2;code(3)<=LED5Q_3; WHEN "101"=> L ED1<='0';LED2<='0';LED3<='0';LED4<='0';LED5<='0';LED6<='1';code(0)<=LED6Q_0;code(1)<=LED6Q_1;code(2)<=LED6Q_2;code(3)<=LED6Q_3;WHEN OTHERS => NULL;END CASE;END process;process(code)BEGINCASE code ISWHEN "0000"=>SE_A<='1';SE_B<='1';SE_C<='1';SE_D<='1';SE_E<='1';SE_F<='1';SE_G<='0'; WHEN "0001"=>SE_A<='0';SE_B<='1';SE_C<='1';SE_D<='0';SE_E<='0';SE_F<='0';SE_G<='0'; WHEN "0010"=>SE_A<='1';SE_B<='1';SE_C<='0';SE_D<='1';SE_E<='1';SE_F<='0';SE_G<='1'; WHEN "0011"=>SE_A<='1';SE_B<='1';SE_C<='1';SE_D<='1';SE_E<='0';SE_F<='0';SE_G<='1'; WHEN "0100"=>SE_A<='0';SE_B<='1';SE_C<='1';SE_D<='0';SE_E<='0';SE_F<='1';SE_G<='1'; WHEN "0101"=>SE_A<='1';SE_B<='0';SE_C<='1';SE_D<='1';SE_E<='0';SE_F<='1';SE_G<='1'; WHEN "0110"=>SE_A<='1';SE_B<='0';SE_C<='1';SE_D<='1';SE_E<='1';SE_F<='1';SE_G<='1'; WHEN "0111"=>SE_A<='1';SE_B<='1';SE_C<='1';SE_D<='0';SE_E<='0';SE_F<='0';SE_G<='0'; WHEN "1000"=>SE_A<='1';SE_B<='1';SE_C<='1';SE_D<='1';SE_E<='1';SE_F<='1';SE_G<='1'; WHEN "1001"=>SE_A<='1';SE_B<='1';SE_C<='1';SE_D<='1';SE_E<='0';SE_F<='1';SE_G<='1'; WHEN "1010"=>SE_A<='1';SE_B<='1';SE_C<='1';SE_D<='0';SE_E<='1';SE_F<='1';SE_G<='1'; WHEN "1011"=>SE_A<='0';SE_B<='0';SE_C<='1';SE_D<='1';SE_E<='1';SE_F<='1';SE_G<='1'; WHEN "1100"=>SE_A<='1';SE_B<='0';SE_C<='0';SE_D<='1';SE_E<='1';SE_F<='1';SE_G<='0'; WHEN "1101"=>SE_A<='0';SE_B<='1';SE_C<='1';SE_D<='1';SE_E<='1';SE_F<='0';SE_G<='1'; WHEN "1110"=>SE_A<='1';SE_B<='0';SE_C<='0';SE_D<='1';SE_E<='1';SE_F<='1';SE_G<='1';WHEN "1111"=>SE_A<='1';SE_B<='0';SE_C<='0';SE_D<='0';SE_E<='1';SE_F<='1';SE_G<='1'; WHEN OTHERS=>SE_A<='0';SE_B<='0';SE_C<='0';SE_D<='0';SE_E<='0';SE_F<='0';SE_G<='0'; END CASE;END process;process(clk)BEGINif(clk'event and clk='1') thenctrl<=ctrl+1;if(ctrl="101")thenctrl<="000";END if;END if;END process;END func;display仿真波形：6．de4_7子模块代码：library ieee;use ieee.STD_logic_1164.ALL;use ieee.STD_logic_unsigned.ALL;ENTITY V_de4_7 ISPORT ( a,b,c,d : in std_logic;se_a,se_b,se_c,se_d,se_e,se_f,se_g : out std_logic); END V_de4_7;ARCHITECTURE actde4_7 OF V_de4_7 ISsignal segment : std_logic_vector(6 downto 0 );signal input : std_logic_vector(3 downto 0 );beginse_a<=segment(0);se_b<=segment(1);se_c<=segment(2);se_d<=segment(3);se_e<=segment(4);se_f<=segment(5);se_g<=segment(6);input(0)<=d;input(1)<=c;input(2)<=b;input(3)<=a;process(a,b,c,d)begincase input iswhen"0000"=> segment<="1111110";when"0001"=> segment<="0110000";when"0010"=> segment<="1101101";when"0011"=> segment<="1111001";when"0100"=> segment<="0110011";when"0101"=> segment<="1011011";when"0110"=> segment<="1011111";when"0111"=> segment<="1110000";when"1000"=> segment<="1111111";when"1001"=> segment<="1111011";when"1010"=> segment<="1110111";when"1011"=> segment<="0011111";when"1100"=> segment<="1001110";when"1101"=> segment<="0111101";when"1110"=> segment<="1001111";when"1111"=> segment<="1000111";when others=> segment<="0000000";end case;end process;end actde4_7;de4_7仿真波形：7.mul8_1子模块代码：LIBRARY IEEE;use ieee.STD_LOGIC_1164.ALL;ENTITY V_mul8_1 ISPORT( ST: IN STD_LOGIC;A: IN STD_LOGIC_VECTOR(2 DOWNTO 0);D: IN STD_LOGIC_VECTOR(7 DOWNTO 0);Q: OUT STD_LOGIC);END V_mul8_1;ARCHITECTURE HBV OF V_mul8_1 ISSIGNAL Q1: STD_LOGIC;BEGINPROCESS(a)BEGINIF ST='1' THEN Q1<='0';ELSECASE a ISWHEN "000"=> Q1 <= D(0);WHEN "001"=> Q1 <= D(1);WHEN "010"=> Q1 <= D(2);WHEN "011"=> Q1 <= D(3);WHEN "100"=> Q1 <= D(4);WHEN "101"=> Q1 <= D(5);WHEN "110"=> Q1 <= D(6);WHEN "111"=> Q1 <= D(7);WHEN OTHERS => NULL;END CASE;END IF;END PROCESS;Q<= Q1;END HBV;mul8_1仿真波形：二．总体资源占用率：50%三．11。
VHDL语言实现24制数字电子钟的设计程序
VHDL 语言实现24制数字电子钟的设计原理框图：系统构成图：各模块程序：秒计数Second 模块：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity second isport(clk: in std_logic;reset: in std_logic;setmin: in std_logic;enmin: out std_logic;daout: out integer range 0 to 59);end entity second;architecture art of second issignal count:integer range 0 to 59;signal enmin_1,enmin_2:std_logic;begindaout<=count;enmin_2<=(setmin and clk);enmin<=(enmin_1 or enmin_2);process(clk,reset,setmin)beginif(reset='0')thencount<=0;enmin_1<='0';elsif(clk'event and clk='1')thenif(count<59) thencount<=count+1; enmin_1<='0';elsecount<=0;enmin_1<='1';end if;end if;end process;end art;分计数minute模块：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity minute isport(clk: in std_logic;clks: in std_logic;reset: in std_logic;sethour:in std_logic;enhour: out std_logic;daout: out integer range 0 to 59);end entity minute;architecture art of minute issignal count:integer range 0 to 59;signal enhour_1,enhour_2:std_logic;begindaout<=count;enhour_2<=(sethour and clks);enhour<=(enhour_1 or enhour_2);process(clk,reset,sethour)beginif(reset='0')thencount<=0;enhour_1<='0';elsif(clk'event and clk='1')thenif(count<59) thencount<=count+1; enhour_1<='0';elsecount<=0;enhour_1<='1';end if;end if;end process;end art;时计数hour模块：LIBRARY IEEE;USE IEEE.std_logic_1164.all;USE IEEE.std_logic_unsigned.all;entity hour isport ( clk : in std_logic;reset: in std_logic;daout: out integer range 0 to 11);end entity hour;architecture zrt of hour issignal count:integer range 0 to 11;begindaout<=count;process(clk,reset)beginif(reset='0') thencount<=0;elsif (clk'event and clk='1') thenif(count<11) thencount<=count+1;elsecount<=0;end if;end if;end process;end zrt;时间调整及多路选择settime模块;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity settime isport(clk1: in std_logic;reset: in std_logic;sec,min:in integer range 0 to 59;hour: in integer range 0 to 11;daout: out integer range 0 to 9;dp: out std_logic;sel: out std_logic_vector(5 downto 0)); end settime;architecture art of settime issignal count:std_logic_vector(2 downto 0); beginprocess(clk1,reset)beginif(reset='0')thencount<="000";elsif(clk1'event and clk1='1')thenif(count>="101")thencount<="000";elsecount<=count+1;end if;end if;end process;process(clk1,reset)variable a ,b:integer range 0 to 9;beginif(reset='0')thendaout<=0;dp<='0';sel<="111111";elsif(clk1'event and clk1='1')thencase count iswhen"000"=>a:=sec rem 10;daout<=a;dp<='0';sel<="000001";when"001"=>b:=sec /10;daout<=b;dp<='0';sel<="000010";when"010"=>a:=min rem 10;daout<=a;dp<='1';sel<="000100";when"011"=>b:=min / 10;daout<=b;dp<='0';sel<="001000";when"100"=>a:=hour rem 10;daout<=a;dp<='1';sel<="010000";when"101"=>b:=hour / 10;daout<=b;dp<='0';sel<="100000";when others=>null;end case;end if;end process;end art;报时alert模块：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity alert isport ( clk,clk1,reset,stop:in std_logic;dainm:in integer range 0 to 59;dains:in integer range 0 to 59;speak:out std_logic);end alert;architecture art of alert issignal s_speak,enspeak:std_logic;beginspeak<=enspeak and s_speak;process(clk1,reset)beginif(reset='0')thens_speak<='0';elsif(clk1'event and clk1='1')thenif(dainm=0)thenif(dains>10)thens_speak<='0';elses_speak<=clk;end if;elses_speak<='0';end if;end if;end process;process(stop,reset,dains)beginif(reset='0' or dains>10)thenenspeak<='1';elsif(stop'event and stop='1')thenenspeak<='0';end if;end process;end art;译码deled模块：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity deled isport(num: in integer range 0 to 9;led: out std_logic_vector(6 downto 0)); end entity deled;architecture art of deled isbeginled<="1111110"when num=0 else"0110000"when num=1 else"1101101"when num=2 else"1111001"when num=3 else"0110011"when num=4 else"1011011"when num=5 else"1011111"when num=6 else"1110000"when num=7 else"1111111"when num=8 else"1111011"when num=9 else"0000000";end art;顶层文件clock：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity clock isport (clk1,stop,clk,reset,setmin,sethour:in std_logic;dp,speak:out std_logic;led:out std_logic_vector(6 downto 0);sel:out std_logic_vector(5 downto 0));end entity clock;architecture one of clock iscomponent second isport(clk: in std_logic;reset: in std_logic;setmin: in std_logic;enmin: out std_logic;daout: out integer range 0 to 59);end component second;component minute isport(clk: in std_logic;clks: in std_logic;reset: in std_logic;sethour:in std_logic;enhour: out std_logic;daout: out integer range 0 to 59);end component minute;component hour isport ( clk : in std_logic;reset: in std_logic;daout: out integer range 0 to 11);end component hour;component alert isport ( clk,clk1,reset,stop:in std_logic;dainm:in integer range 0 to 59;dains:in integer range 0 to 59;speak:out std_logic);end component alert;component settime isport(clk1: in std_logic;reset: in std_logic;sec,min:in integer range 0 to 59;hour: in integer range 0 to 11;daout: out integer range 0 to 9;dp: out std_logic;sel: out std_logic_vector(5 downto 0));end component settime;component deled isport(num: in integer range 0 to 9;led: out std_logic_vector(6 downto 0));end component deled;signal min:std_logic;signal secondout:integer range 0 to 59;signal hour1:std_logic;signal minuteout:integer range 0 to 59;signal hourout:integer range 0 to 11;signal settimeout:integer range 0 to 9;beginu1:second port map(clk=>clk,reset=>reset,setmin=>setmin,enmin=>min,daout=>secondout);u2:minute port map(clk=>min,clks=>clk,reset=>reset,sethour=>sethour,enhour=>hour1,daout=>minuteout);u3:hour port map(clk=>hour1,reset=>reset,daout=>hourout);u4:alert port map(clk=>clk,clk1=>clk1,reset=>reset,stop=>stop,dainm=>minuteout,dains=>secondout,speak=> speak);u5:settime port map(clk1=>clk1,reset=>reset,sec=>secondout,min=>minuteout,hour=>hourout,daout=>settimeou t,dp=>dp,sel=>sel);u6:deled port map(num=>settimeout,led=>led);end architecture one;。
数字时钟VHDL程序
数字时钟VHDL程序注意：此程序已经通过编译，并进行下载验证无误.谢谢！library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity dzsz isport(clk,clkscan:in std_logic;reset:in std_logic;k1:in std_logic;k2:in std_logic;sel :out std_logic_vector(7 downto 0);seg :out std_logic_vector(6 downto 0));end entity ;architecture one of dzsz issignal sl: integer range 0 to 9;signal sh: integer range 0 to 5;signal ml: integer range 0 to 9;signal mh: integer range 0 to 5;signal hl: integer range 0 to 9;signal hh: integer range 0 to 2;signal num: std_logic_vector(2 downto 0);signal w: std_logic_vector(7 downto 0);signal M : integer range 0 to 11;beginREG:process(clkscan)beginif clkscan'event and clkscan='1' thennum<=num+1;if num="111" then num<="000";end if;end if;end process REG;COM:process(clk,reset)beginif reset='0' then sl<=0;sh<=0;ml<=0;mh<=0;hl<=0;hh<=0;elsif clk'event and clk='1' thenif k1='1' then ml<=ml+1;if ml=9 then mh<=mh+1;ml<=0;if ml=9 and mh=5 then hl<=hl+1;ml<=0;mh<=0;end if;end if;elsif k2='1' then hl<=hl+1;if hl=9 then hh<=hh+1;hl<=0;end if;if hh=2 and hl=3 then hh<=0;hl<=0;end if;else sl<=sl+1;if sl=9 then sh<=sh+1;sl<=0;end if;if sh=5 and sl=9then ml<=ml+1;sh<=0;end if;if ml=9 and sh=5 and sl=9then mh<=mh+1;ml<=0;end if;if mh=5 and ml=9 and sh=5 and sl=9then hl<=hl+1;mh<=0;end if;if hl=9 and mh=5 and ml=9 and sh=5 and sl=9then ml<=ml+1;sh<=0;end if;if hh=2 and hl=3 and mh=5 and ml=9 and sh=5 and sl=9 then hh<=0;end if;end if;end if;end process COM;M<=sl when w="11111110" elsesh when w="11111101" elseml when w="11110111" elsemh when w="11101111" elsehl when w="10111111" elsehh when w="01111111" else10 when w="11111011" else11 when w="11011111" else0;sel<=w;COM0:process(M)begincase M iswhen 0=>seg<="1000000";when 1=>seg<="1111001";when 2=>seg<="0100100";when 3=>seg<="0110000";when 4=>seg<="0011001";when 5=>seg<="0010010";when 6=>seg<="0000010";when 7=>seg<="1111000";when 8=>seg<="0000000";when 9=>seg<="0010000";when 10=>seg<="0111111";when 11=>seg<="0111111";when others=>seg<="1111111"; end case;end process COM0;w<="11111110" when num="000" else "11111101" when num="001" else"11111011" when num="010" else"11110111" when num="011" else"11101111" when num="100" else"11011111" when num="101" else"10111111" when num="110" else"01111111" ;end;。
用VHDL语言编写的数字钟程序
永州职业技术学院课程设计课程名称：EDA技术实用教程题目：基于FPGA的数字钟设计系、专业：电子技术系应用电子年级、班级：07级电子大专学生姓名：**指导老师：***时间：2008年12月目录一、系统设计………………………………………………………..1.1设计要求……………………………………………………1.1.1任务………………………………………………..1.1.2要求……………………………………………….1.1.3题目分析…………………………………………二．方案论证与比较…………………………………2.1方案一…………………………………………2.2 方案二…………………………………………2.3 方案三…………………………………………三、设计思路……………………………………………………3.1硬件模块………………………………………………3.2软件模块………………………………………………….四、调试情况………………………………………………….五、系统调试…………………………………………………六、心得体会……………………………………………………... 附：参考文献……………………………………………………..用VHDL语言编写的数字钟程序摘要：本设计要求一个12进制或24进制的具有时、分、秒计时功能的数字钟，并要求能进行时、分、秒调整，每逢时有报时功能。
数字钟是一种用数字电路技术实现时、分、秒计时的装置，与机械式时钟相比具有更高的准确性和直观性，且无机械装置，具有更更长的使用寿命，因此得到了广泛的使用。
本设计基于FPGA芯片的数字钟的设计，通过多功能数字钟的设计思路，详细叙述了整个系统的硬件、软件实现过程，实现了时间的显示和修改功能、报时功能等，并尽可能的减少误差，使得系统可以达到实际数字钟的允许误差范围内。
关键词：FBGA、数码管、按键一、系统设计1．1 设计要求1．1．1 任务设计并制作一个数字钟，通过设计,掌握电子设计的一般思路,学习电子设计的一般方法。
基于VHDL的数字时钟设计
目录1 概述...................................................................... 错误！未定义书签。
1.1数字时钟的工作原理 (1)1.2设计任务 (1)2 系统总体方案设计 (2)3 VHDL模块电路设计 (3)3.1模块实现 (3)3.1.1分频模块pinlv (3)3.1.2按键去抖动模块qudou (5)3.1.3按键控制模块self1 (6)3.1.4秒、分六十进制模块cantsixty (7)3.1.5时计数模块hourtwenty (9)3.1.6秒、分、时组合后的模块 (9)3.1.7数码管显示模块 (10)3.2数字时钟的顶层设计原理图 (13)3.3系统仿真与调试 (14)结束语 (16)参考文献 (17)致谢 (18)附录源程序代码 (19)1 概述1.1数字时钟的工作原理数字钟电路的基本结构由两个60进制计数器和一个24进制计数器组成，分别对秒、分、小时进行计时，当计时到23时59分59秒时，再来一个计数脉冲，则计数器清零，重新开始计时。
秒计数器的计数时钟CLK为1Hz的标准信号，可以由晶振产生的50MHz信号通过分频得到。
当数字钟处于计时状态时，秒计数器的进位输出信号作为分钟计数器的计数信号，分钟计数器的进位输出信号又作为小时计数器的计数信号，每一秒钟发出一个中断给CPU，CPU采用NIOS，它响应中断，并读出小时、分、秒等信息。
CPU对读出的数据译码，使之动态显示在数码管上。
1.2 设计任务设计一个基于VHDL的数字时钟，具体功能要求如下：1．在七段数码管上具有时--分--秒的依次显示。
2．时、分、秒的个位记满十向高位进一，分、秒的十位记满五向高位进一，小时按24进制计数，分、秒按60进制计数。
3．整点报时，当计数到整点时扬声器发出响声。
4．时间设置：可以通过按键手动调节秒和分的数值。
此功能中可通过按键实现整体清零和暂停的功能。
数字钟VHDL
VHDL实验报告：数字钟一：数字钟的功能1：具有以二十四小时计时、显示、整点报时、时间设置和闹钟的功能。
设计精度要求为1S。
二．功能描述1 . 系统输入：系统状态及校时、定时转换的控制信号为k、trans、set；时钟信号clk,采用1024Hz；系统复位信号reset。
输入信号均由按键产生。
系统输出：LED显示输出，蜂鸣器声音信号输出。
2. 计时：正常工作状态下，每日按24h计时制计时并显示，蜂鸣器无声，逢整点报时。
3. 校时：在计时状态显示下，按下“set键”，进入“小时”校准状态，之后按下“k键”则进入“分”校准状态，继续按下“k 键”则进入“秒复零”状态，第三次按下“k 键”又恢复到正常计时显示状态。
A:“小时”校准状态：在“小时”校准状态下，显示“小时”数码管以1Hz的频率递增计数。
B:“分”校准状态：在“分”校准状态下，显示“分”的数码管以1Hz的频率递增计数。
C:“秒”复零状态：在“秒复零”状态下，显示“秒”的数码管复零。
4. 整点报时：蜂鸣器在“59”分钟的第“51”、“53”、“55”、“57‘秒发频率为512Hz的低音，在“59”分钟的第“59”秒发频率为1024Hz的高音，结束时为整点。
5. 显示：要求采用扫描显示方式驱动6个LED数码管显示小时、分、秒。
闹钟：闹钟定时时间到，蜂鸣器发出周期为1s的“滴”、“滴”声，持续时间为10s；闹钟定时显示。
6. 闹钟定时设置：在闹钟定时显示状态下，按下“set键”，进入闹钟的“时”设置状态，之后按下“k键”进入闹钟的“分”设置状态，继续按下“k 键”则进入“秒”设置状态，第三次按下“k键”又恢复到闹钟定时显示状态。
A:闹钟“小时”设置状态：在闹钟“小时”设置状态下，显示“小时”的数码管以1Hz的频率递增计数。
B:闹钟：“分”设置状态：在闹钟“分”设置状态下，显示“分”的数码管以1Hz的频率递增计数。
三：仿真。
分主控模块、计时校时模块、闹钟设定模块、选择显示模块、整点报时及闹铃模块、分频模块、动态显示模块。
基于VHDL语言的二十四进制数字钟
module clock(clk,ena,tt5,tt4,tt3,tt2,tt1,tt0,speak); input clk,ena; output [7:0]tt5; output [7:0]tt4; output [7:0]tt3; output [7:0]tt2; output [7:0]tt1; output [7:0]tt0; reg [7:0]tt5; reg [7:0]tt4; reg [7:0]tt3; reg [7:0]tt2; reg [7:0]tt1; reg [7:0]tt0; reg [3:0]t5; reg [3:0]t4; reg [3:0]t3; reg [3:0]t2; reg [3:0]t1; reg [3:0]t0; output speak; wire x,xa,xb,xc,xd,xe;
闹钟在 23 点 59 分 module example6(clk,clr,ena,cout,t); input clk ,clr,ena; output [3:0] t; output cout; reg cout; reg [3:0] t; always @(posedge clr or posedge clk) begin if (clr) t='b0000; else if (ena) begin if(t<='b0100) begin t=t+1; cout=0; end else begin t=0; cout=1; end end end endmodule module example10(clk,clr,ena,cout,t); input clk ,clr,ena; output [3:0] t; output cout; reg cout; reg [3:0] t; alwaysk) begin if (clr) t='b0000; else if (ena) begin if(t<='b1000) begin t=t+1; cout=0;
VHDL数字时钟
一、功能要求：1、能够分别显示时、分、秒，以24小时循环设计；2、能够对小时、分钟进行调时；3、能够设置闹钟，使其能够在指定时间响；二、设计原理：该数字时钟有三个状态，分别是正常显示状态、调时状态和闹钟设置状态，每当来到一个z的上升沿时，状态改变一次；正常显示状态：对输入的频率clk1进行分频，产生一个与秒的频率相等的频率信号clk,用clk来控制秒的走时，秒的个位每到10往秒的十位进位，秒的十位每到6就往分的个位进位，分的个位十位进位和秒一样，时的个位每到10就往时的十位进位，时的十位每到2就为0；当时间为23:59:59时，全部清零，重新开始计时；调时状态：当处于调时状态时，可对时间进行调整，先选择对哪位进行调整，可分别对分和时的个位和十位进行调整，每当来到一个md2的上升沿时可选中其中一位，每来到一个md3的上升沿时对其进行加“1”操作并设置一个开关allow1，当allow1接通一次时可把设置的时间赋给正常显示的时间，否则不影响正常显示的时间；闹钟设置状态：当处于闹钟设置状态时，同样通过md2选择要调整的位，并通过md3对其进行加“1”操作，并设置一个闹钟开关allow2，接通时闹钟开启；数字显示：对6个显示器用一个频率进行循环扫描，利用人眼停留的效果使其达到同时显示的效果；三、变量说明：端口说明：clk1:输入频率md1:负责对时钟状态的切换，每接通一次，状态就切换一次md2:在调时状态和闹钟设置状态时，负责选定对那个位进行操作（时的个位和十位，分的个位和十位）md3:负责对所选中的位进行加“1”操作，每接通一次，就加“1”allow1:负责是否确定对时钟的设置，设置好时钟后，若allow1接通一次，时钟就被修改；若allow1没有接通，则所调整的时间对原来的时钟没有影响allow2:负责是否确定开启闹钟，当allow2处于接通状态时，时钟到了设置的时间闹钟会响，断开allow2闹钟关闭speak:负责闹钟的发声dout,sellout:负责板子上显示管的显示数字内部变量说明：sel:选择哪个位置显示数counter:对输入频率进行分频，得出秒的频率clkcounter1:对输入频率进行分频，得出闹钟发声的频率z:选择时钟的状态，“00”为正常显示状态，“01”为调整状态，“10”为闹钟设置状态k:选择要对哪位进行操作，“00”为分的个位，“01”为分的十位，“10”为时的个位，“11”为时的十位hou1,hou2,min1,min2,sec1,sec2:分别代表正常显示状态下的时的十位，个位；分的十位，个位；秒的十位，个位；hou1n,hou2n,min1n,min2n,:分别代表处于调时状态时的时和分的十位和个位；seth1,seth2,setm1,setm2:分别代表处于闹钟设置状态的时和分的十位和个位；h1,h2,m1,m2,s1,s2:分别代表最终显示在板子上的时、分、秒的十位和个位；四、源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity zhong isport(clk1:in std_logic;md1:in std_logic;-----xuan ze zhuang taimd2:in std_logic;------xuan ze she zhi na ge wei zhimd3:in std_logic;------jia yiallow1:in std_logic;allow2:in std_logic;speak:out std_logic;-----nao zhongdout:out std_logic_vector(6 downto 0);-------shu chuselout:out std_logic_vector(5 downto 0));-----xuan ze xian shi end zhong;architecture one of zhong issignal sel:std_logic_vector(2 downto 0);signal hou1:std_logic_vector(3 downto 0);signal hou2:std_logic_vector(3 downto 0);signal min1:std_logic_vector(3 downto 0);signal min2:std_logic_vector(3 downto 0);signal hou1n:std_logic_vector(3 downto 0);signal hou2n:std_logic_vector(3 downto 0);signal min1n:std_logic_vector(3 downto 0);signal min2n:std_logic_vector(3 downto 0);signal seth1:std_logic_vector(3 downto 0);signal seth2:std_logic_vector(3 downto 0);signal setm1:std_logic_vector(3 downto 0);signal setm2:std_logic_vector(3 downto 0);signal sec1:std_logic_vector(3 downto 0);signal sec2:std_logic_vector(3 downto 0);signal h1:std_logic_vector(3 downto 0);signal h2:std_logic_vector(3 downto 0);signal m1:std_logic_vector(3 downto 0);signal m2:std_logic_vector(3 downto 0);signal s1:std_logic_vector(3 downto 0);signal s2:std_logic_vector(3 downto 0);signal counter:std_logic_vector(8 downto 0);-----------secondsignal countern1:std_logic_vector(7 downto 0);----------speakersignal clk:std_logic;----------secondsignal clkn1:std_logic;-----speakersignal k:std_logic_vector(1 downto 0);---------xuan ze xian shisignal z:std_logic_vector(1 downto 0);------00 zheng chang ;01 tiao zheng;10 nao ling;-------------------------------------------------beginfen:process(clk1)beginif(clk1'event and clk1='1')thenif(counter="110000000")thencounter<="000000000";clk<=not clk;elsecounter<=counter+'1';end if;if(countern1="10000000")thencountern1<="00000000";elseclkn1<=not clkn1;end if;end if;end process fen;-------------------------------------------kong:process(md2)beginif( md2'event and md2='1')thenif(k="11")thenk<="00";elsek<=k+1;end if;end if;end process kong;process(md1)beginif(md1'event and md1='1')thenif(z="10")thenz<="00";elsez<=z+1;end if;end if;end process;----------------------------------------------choice:process(clk1)beginif clk1'event and clk1='1' thenif sel="101" thensel<="000";elsesel<=sel+1;end if;end if;end process choice;-------------------------------------------zheng chang xian shi-----------------------------------------------hour1hou_1:process(clk,hou2,min1,min2,sec1,sec2)beginif clk'event and clk='1' thenif (hou1="0010" and hou2="0011" and min1="0101" and min2="1001" and sec1="0101" andsec2="1001") thenhou1<="0000";elsif (hou2="1001"and min1="0101" and min2="1001" and sec1="0101" and sec2="1001") thenhou1<=hou1+1;end if;end if;if(allow1='1' and z="01")thenhou1<=hou1n;end if;end process hou_1;-----------------------------------------------hour2hou_2:process(clk,min1,min2,sec1,sec2,hou1)beginif clk'event and clk='1' thenif (hou1="0010" and hou2="0011"and min1="0101" and min2="1001" and sec1="0101" andsec2="1001") thenhou2<="0000";elsif hou2="1001"and(min1="0101" and min2="1001" and sec1="0101" and sec2="1001") thenhou2<="0000";elsif (min1="0101" and min2="1001" and sec1="0101" and sec2="1001")thenhou2<=hou2+1;end if;end if;if(allow1='1' and z="01")thenhou2<=hou2n;end if;end process hou_2;-----------------------------------------------min1min_1:process(clk,min2,sec1,sec2)beginif clk'event and clk='1' thenif (min1="0101" and min2="1001" and sec1="0101" and sec2="1001") then min1<="0000";elsif (min2="1001"and sec1="0101" and sec2="1001") thenmin1<=min1+1;end if;end if;if(allow1='1' and z="01")thenmin1<=min1n;end if;end process min_1;----------------------------------------------min2min_2:process(clk,sec1,sec2)beginif clk'event and clk='1' thenif (min2="1001" and sec1="0101" and sec2="1001")thenmin2<="0000";elsif (sec1="0101" and sec2="1001")thenmin2<=min2+1;end if;end if;if(allow1='1' and z="01")thenmin2<=min2n;end if;end process min_2;---------------------------------------------second1sec_1:process(clk)beginif clk'event and clk='1' thenif (sec1="0101" and sec2="1001")thensec1<="0000";elsif sec2="1001"thensec1<=sec1+1;end if;end if;if(allow1='1' and z="01")thensec1<="0000";end if;end process sec_1;--------------------------------------------second2sec_2:process(clk)beginif clk'event and clk='1' thenif sec2="1001" thensec2<="0000";else sec2<=sec2+1;end if;end if;if(allow1='1' and z="01")thensec2<="0000";end if;end process sec_2;-----------------------------------------------------------------------------------shi jian tiao zheng process(md3)-----------hour1beginif(z="01")thenif(k="11")thenif(md3'event and md3='1')thenif(hou1n="0010")thenhou1n<="0000";elsehou1n<=hou1n+1;end if;end if;end if;end if;end process;process(md3)-----------hour2beginif(z="01")thenif(k="10")thenif(md3'event and md3='1')thenif(hou2n="1001")or(hou1n="0010" and hou2n="0011")then hou2n<="0000";elsehou2n<=hou2n+1;end if;end if;end if;end if;end process;process(md3)-----------min1beginif(z="01")thenif(k="01")thenif(md3'event and md3='1')thenif(min1n="0110")thenmin1n<="0000";elsemin1n<=min1n+1;end if;end if;end if;end if;end process;process(md3)------------min2beginif(z="01")thenif(k="00")thenif(md3'event and md3='1')thenif(min2n="1001")thenmin2n<="0000";elsemin2n<=min2n+1;end if;end if;end if;end if;end process;--------------------------------------------------------------------------------------she zhi nao zhong sethour1:process(md3)beginif(z="10")thenif(k="11")thenif(md3'event and md3='1')thenif(seth1="0010")thenseth1<="0000";elseseth1<=seth1+1;end if;end if;end if;end if;end process sethour1;-------------------------------------------sethour2:process(md3)beginif(z="10")thenif(k="10")thenif(md3'event and md3='1')thenif(seth2="1001")or(seth2="0010" and seth2="0100")then seth2<="0000";elseseth2<=seth2+1;end if;end if;end if;end if;end process sethour2;-------------------------------------------setmin1:process(md3)beginif(z="10")thenif(k="01")thenif(md3'event and md3='1')thenif(setm1="0110")thensetm1<="0000";elsesetm1<=setm1+1;end if;end if;end if;end if;end process setmin1;----------------------------------------------setmin2:process(md3)beginif(z="10")thenif(k="00")thenif(md3'event and md3='1')thenif(setm2="1001")thensetm2<="0000";elsesetm2<=setm2+1;end if;end if;end if;end if;end process setmin2;----------------------------------------------------------------------------------------nao zhongspeaker:process(clk1,hou1,hou2,min1,min2)beginif clk1'event and clk1='1'thenif(allow2='1')thenif seth1=hou1 and seth2=hou2 and setm1=min1 and setm2=min2 thenspeak<=clkn1;elsespeak<='0';end if;end if;end if;end process speaker;--------------------------------------------------------------------------------------disp:process(sel,md1,hou1,hou2,min1,min2,sec1,sec2,seth1,seth2,setm1,setm2) beginif sel="000" thenselout<="111110";case h1 iswhen "0000"=>dout<="1000000";--0when "0001"=>dout<="1111001";--1when "0010"=>dout<="0100100";--2when others =>dout<="1000000";--0end case;elsif sel="001" thenselout<="111101";case h2 iswhen "0000"=>dout<="1000000";--0when "0001"=>dout<="1111001";--1when "0010"=>dout<="0100100";--2when "0011"=>dout<="0110000";--3when "0100"=>dout<="0011001";--4when "0101"=>dout<="0010010";--5when "0110"=>dout<="0000010";--6when "0111"=>dout<="1111000";--7when "1000"=>dout<="0000000";--8when "1001"=>dout<="0010000";--9when others=>dout<="1000000";end case;elsif sel="010" thenselout<="111011";case m1 iswhen "0000"=>dout<="1000000";--0 when "0001"=>dout<="1111001";--1 when "0010"=>dout<="0100100";--2 when "0011"=>dout<="0110000";--3 when "0100"=>dout<="0011001";--4 when "0101"=>dout<="0010010";--5 when others=>dout<="1000000";--0 end case;elsif sel="011" thenselout<="110111";case m2 iswhen "0000"=>dout<="1000000";--0 when "0001"=>dout<="1111001";--1 when "0010"=>dout<="0100100";--2 when "0011"=>dout<="0110000";--3 when "0100"=>dout<="0011001";--4 when "0101"=>dout<="0010010";--5 when "0110"=>dout<="0000010";--6 when "0111"=>dout<="1111000";--7 when "1000"=>dout<="0000000";--8 when "1001"=>dout<="0010000";--9 when others=>dout<="1000000";--0 end case;elsif sel="100" thenselout<="101111";case s1 iswhen "0000"=>dout<="1000000";--0 when "0001"=>dout<="1111001";--1 when "0010"=>dout<="0100100";--2 when "0011"=>dout<="0110000";--3 when "0100"=>dout<="0011001";--4 when "0101"=>dout<="0010010";--5 when others=>dout<="1000000";--0 end case;elsif sel="101" thenselout<="011111";case s2 iswhen "0000"=>dout<="1000000";--0 when "0001"=>dout<="1111001";--1 when "0010"=>dout<="0100100";--2 when "0011"=>dout<="0110000";--3 when "0100"=>dout<="0011001";--4 when "0101"=>dout<="0010010";--5when "0110"=>dout<="0000010";--6when "0111"=>dout<="1111000";--7when "1000"=>dout<="0000000";--8when "1001"=>dout<="0010000";--9when others=>dout<="1000000";--0end case;end if;if z="00" then---------------zheng chang xian shih1<=hou1;h2<=hou2;m1<=min1;m2<=min2;s1<=sec1;s2<=sec2;elsif z="01"thenh1<=hou1n;h2<=hou2n;m1<=min1n;m2<=min2n;s1<="0000";s2<="0000";elsif z="10" then ----------------nao zhong xian shi h1<=seth1;h2<=seth2;m1<=setm1;m2<=setm2;s1<="0000";s2<="0000";end if;end process disp;------------------------------------------end one;11。
VHDL编程数字钟
一、数字钟要求：1、能进行正常的时、分、秒计时功能，分别由6个数码管显示24h、60min、60s。
2、可以进行当前时间设置。
二、应用系统功能的详细说明该数字钟使用的是二十四时计时制。
计时时间范围从00：00：00到23：59：59。
当时间及时到23:59:59时，钟面跳转到00：00：00重新下一轮计时。
该数字钟总共有三个按钮，分别是md1控制数字钟的开关，md2(1)控制数字钟的正常运行还是时间设置和md2(0)控制对时还是对分的设置。
md1：为0时，数字钟电源关闭；为1时，数字钟电源开启。
md2(1)：为0时，数字钟正常运行；为1时，数字钟进入设置状态。
md2(0)：为0时，数字钟对时进行设置；为1时，数字钟对分进行设置。
三、主要模块的算法描述1、扫描显示模块scan6由于试验箱上的8只显示数码管只有16个接脚，当显示四个以上时，每次只能显示一位，所以要显示六位要轮流输出，即扫描显示。
人的视觉暂留大约为1/30s，所以每只数码管闪动频率为32Hz即可。
那么8只数码管轮流显示一遍，2、计时模块hourten,huoroen,minten,minone,secten,secone计时模块共分为6个部分，分别是时、分、秒的十位和个位。
由每位之间的逻辑关系以及md1和md2来控制正常计数、进位和对小时分钟的设置。
3、译码模块dec7s把计时模块输出的时、分、秒各位的二进制数翻译成能在七段数码管上显示的七位二进制码，能够显示0~9各个数字。
四、程序的源代码清单library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity digital_clock isport(clk:in std_logic; --扫描频率,>=256Hz clk1:in std_logic; --计时频率,1Hzmd1:in std_logic; --开关，0时有效md2:in std_logic_vector(1 downto 0); --时间设置dout:out std_logic_vector(6 downto 0); --译码显示ms:out std_logic_vector(5 downto 0)); --扫描控制end digital_clock;architecture one of digital_clock issignal sel:std_logic_vector(2 downto 0);signal hou1,hou2,min1,min2,sec1,sec2:std_logic_vector(3 downto 0);signal time:std_logic_vector(3 downto 0);begin---------------------------------------------scan6scan6:process(clk1,hou1,hou2,min1,min2,sec1,sec2)beginif clk1'event and clk1='1' thenif sel="101" thensel<="000";elsesel<=sel+1;end if;end if;case sel iswhen "000"=>ms<="000001";time<=hou1;when "001"=>ms<="000010";time<=hou2;when "010"=>ms<="000100";time<=min1;when "011"=>ms<="001000";time<=min2;when "100"=>ms<="010000";time<=sec1;when "101"=>ms<="100000";time<=sec2;when others=>ms<="100000";time1=sec2;end case;end process scan6;---------------------------------------------hourtenhourten:process(clk,hou2,min1,min2,sec1,sec2,md1,md2)beginif clk'event and clk='1' thenif(hou1&hou2&min1&min2&sec1&sec2="11")thenhou1<="0000"; --当23:59:59时，时十位归0elsif(hou1&hou2="00100011"and md1&md2="001")thenhou1<="0000"; --当设置小时,时位是23时,时十位归0elsif((hou2&min1&min2&sec1&sec2="101011001")or(hou2="1001"and md1&md2="001"))thenhou1<=hou1+1; --当正常计时，时间是x9:59:59时，或设置小时，end if; --时位是x9时，时十位加1end if;end process hourten;---------------------------------------------houronehourone:process(clk,min1,min2,sec1,sec2,md1,md2,hou1)beginif clk'event and clk='1' thenif(hou1&hou2&min1&min2&sec1&sec2="11") thenhou2<="0000"; --当23:59:59时，时个位归0elsif (hou2&min1&min2&sec1&sec2="11")thenhou2<="0000"; --当x9:59:59时，时个位归0elsif((hou2="1001"orhou1&hou2="00100011")and(md1&md2="001"))thenhou2<="0000"; --当设置小时，时位是x9或23时，时个位归0 elsif(min1&min2&sec1&sec2="11001)or(md1&md2="001")thenhou2<=hou2+1; --当正常计时,时间是xx:59:59时,或设置小时,时个位加1 end if;end if;end process hourone;---------------------------------------------mintenminten:process(clk,min2,sec1,sec2,md1,md2)beginif clk'event and clk='1' thenif(min1&min2&sec1&sec2="11001")thenmin1<="0000"; --当xx:59:59时，分十位归0elsif (min1&min2="01011001"andmd1&md2="000")thenmin1<="0000"; --当设置分钟，分位是59时，分十位归0elsif(min2&sec1&sec2="1")or--正常计时,时间是xx:x9:59时,或(min2="1001"and md1&md2="000")then --设置分钟,时间是x9,分十位加1min1<=min1+1;end if;end if;end process minten;---------------------------------------------minoneminone:process(clk,sec1,sec2,md1,md2)beginif clk'event and clk='1' thenif (min2&sec1&sec2="1")thenmin2<="0000"; --当xx:x9:59时，分个位归0elsif (min2="1001"andmd1&md2="000")thenmin2<="0000"; --当设置分钟，分位是x9时分个位归0elsif (sec1&sec2="01011001")or(md1&md2="000")thenmin2<=min2+1; --正常计时,时间是xx:xx:59时,或设置分钟,分个位加1 end if;end if;end process minone;---------------------------------------------sectensecten:process(clk)beginif clk'event and clk='1' thenif(sec1&sec2="01011001")then --当时间是xx:xx:59时，秒十位归0sec1<="0000";elsif sec2="1001"then --当秒位是x9时，秒十位加1sec1<=sec1+1;end if;end if;end process secten;--------------------------------------------seconesecone:process(clk)beginif clk'event and clk='1' thenif sec2="1001" then --当秒位是x9时，秒个位归0sec2<="0000";else sec2<=sec2+1; --否则加1end if;end if;end process secone;------------------------------------------dec7sdec7s:process(time)begincase time iswhen "0000"=>dout<="0111111";when "0001"=>dout<="0000110";when "0010"=>dout<="1011011";when "0011"=>dout<="1001111";when "0100"=>dout<="1100110";when "0101"=>dout<="1101101";when "0110"=>dout<="1111101";when "0111"=>dout<="0000111";when "1000"=>dout<="1111111";when "1001"=>dout<="1101111";when others=>dout<="";end case;end process dec7s;end one;。
VHDL语言编写数字钟源代码
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity clock isport (clk,clr,a,c,e,f,g:in std_logic;led_sel:out std_logic_vector( 2 downto 0);led:out std_logic_vector( 0 to 6);p:in std_logic_vector( 3 downto 0);b:in std_logic_vector(1 downto 0);d:out std_logic );end entity clock;architecture bhv of clock issignal m: integer range 0 to 999;signal hou1,hou0,min1,min0,sec1,sec0,s2:std_logic_vector(3 downto 0);signal rhou1,rhou0,rmin1,rmin0,rsec1,rsec0:std_logic_vector(3 downto 0);signal s1: std_logic_vector(2 downto 0);signal clk1,clk2,d1,d2:std_logic;signal n : integer range 0 to 1;beginp1:process(clk) --二分频beginif (rising_edge(clk)) thenif n=1 then n<=0;clk2<='1';else n<=n+1; clk2<='0';end if;end if ;end process;p2:process(clk)beginif (rising_edge(clk)) thenif m=999 then m<=0;clk1<='1';else m<=m+1; clk1<='0';end if;end if ;end process P2;p3: process(clk1,clr) ---时间设置beginif (clr='1') then sec0<="0000";sec1<="0000";min0<="0000";min1<="0000";hou0<="0000";hou1<="0000";elsif rising_edge(clk1) thenif a='1' then --校时if b="00" then hou1<=p;elsif b="01" then hou0<=p;elsif b="10" then min1<=p;elsif b="11" then min0<=p;end if;end if;if sec0>="1001" thensec0<="0000";if sec1>="0101" thensec1<="0000";if min0>="1001" thenmin0<="0000";if min1>="0101" thenmin1<="0000";if g='0'thenif hou1<"0010" thenif hou0="1001" thenhou0<="0000";hou1<=hou1+1 ;else hou0<=hou0+1;elsif hou1="0010" and hou0="0011" thenhou1<="0000";hou0<="0000";else hou0<=hou0+1;end if ;end if;if g='1'thenif hou1<"0001" thenif hou0="1001" thenhou0<="0000";hou1<=hou1+1 ;else hou0<=hou0+1;end if;elsif hou1="0001" and hou0="0001" thenhou1<="0000";hou0<="0000";else hou0<=hou0+1;end if ;end if;else min1<=min1+1;end if;else min0<=min0+1;else sec1<=sec1+1;end if;else sec0<=sec0+1;end if;end if ;end process P3;p4:process(clk) --数码管选通beginif(rising_edge (clk)) thenif s1="111" thens1<="000";else s1<=s1+1;end if;end if;-- led_sel<=s1;end process;p5:process(s1,f) ---闹铃显示beginif f='0'thencase s1 iswhen "000"=>s2<=sec0;led_sel<="000";when "001"=>s2<=sec1;led_sel<="001";when "010"=>s2<=min0;led_sel<="010";when "011"=>s2<=min1;led_sel<="011";when "100"=>s2<=hou0;led_sel<="100";when "101"=>s2<=hou1;led_sel<="101";when others=>null;end case;elsif f='1' thencase s1 iswhen "010"=>s2<=rmin0;led_sel<="010";when "011"=>s2<=rmin1;led_sel<="011";when "100"=>s2<=rhou0;led_sel<="100";when "101"=>s2<=rhou1;led_sel<="101";when others=>null;end case;end if;end process;p6:process(s2) --七段译码器beginif(s1<6) thencase s2 iswhen "0000"=>led<="0111111"; when "0001"=>led<="0000110"; when "0010"=>led<="1011011"; when "0011"=>led<="1001111"; when "0100"=>led<="1100110"; when "0101"=>led<="1101101"; when "0110"=>led<="1111101"; when "0111"=>led<="0000111"; when "1000"=>led<="1111111"; when "1001"=>led<="1101111"; when others=>null;end case ;else led<="0000000";end if;end process;p7:process(clk1,c) --整点报时beginif (rising_edge(clk))thenif c='1' thenif (min1="0101" and min0="1001" and sec1="0101") then if(sec0="0000"or sec0="0010" or sec0="0100" orsec0="0110" or sec0="1000")thend1<='1'and clk2;else d1<='0';end if;elsif (min1="0000" and min0="0000" and sec0="0000" andsec1="0000") thend1<='1';else d1<='0';end if ;end if ;end if ;end process;p8:process(clk,e) ---闹铃设置beginif (rising_edge(clk))thenif e='1' thenif b="000"then rhou1<=p;elsif b="001"then rhou0<=p;elsif b="010"then rmin1<=p;elsif b="011"then rmin0<=p;end if;end if;end if;end process;p9:process(clk) ---闹铃比较beginif(rising_edge(clk))thenif e='1'thenif(rhou1=hou1 and rhou0=hou0 and rmin1=min1 and rmin0=min0)then if(sec0="0001"or sec0="0010" or sec0="0011" orsec0="0011" or sec0="0100" )thend2<='1'and clk2;else d2<='0';end if;else d2<='0';end if;end if;end if;end process;d<=d1 or d2;end architecture bhv;。
VHDL语言写的电子钟程序(XTS江科大)
实验目的：实现时钟显示，1——12——1——11——0——1循环，时钟调时，闹铃，闹铃定时等功能。
程序和注释：<code1.vhd>LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.ALL;entity code1 isport (clk : in std_logic;reset : in std_logic;shi_key : in std_logic;fen_key : in std_logic;set_mode_key:in std_logic;en:out std_logic_vector(7 downto 0);y :out std_logic_vector(7 downto 0);beep_s:out std_logic);end code1 ;ARCHITECTURE code2 of code1 issignal a:integer:=0; --ji shisignal d:integer:=0; --xian shisignal b,b0,b1,b3,b4,b5,b6:std_logic:='1';signal e:std_logic:='0';--xian shisignal c:integer:=9; --miao geweisignal ch:integer:=5; --miao shiweisignal eight,eight1:integer:=0; --8 ge shu ma guansignal fg:integer:=9; --fen ge weisignal fs:integer:=5; --fen shi weisignal sg:integer:=1; --shi ge weisignal ss:integer:=1; --shi shi weisignal p:std_logic:='0';--zantingsignal set_mode :std_logic_vector(1 downto 0);signal beep_m1,beep_m2,beep_h1,beep_h2:integer:=1;signal AM_PM:std_logic:='0';signal beep_count:integer:=0;signal beep_clk: std_logic:='1';signal c1,c2,c3,c4,c5,c6:integer:=0;component set0port ( set_clk:in std_logic;m_key:in std_logic;h_key:in std_logic;mode_key:in std_logic;mode:out std_logic_vector(1 downto 0);set_out_m:out std_logic;set_out_h:out std_logic;beep_key_m:out std_logic;beep_key_h:out std_logic);end component;beginprocess(clk)beginif clk'event and clk='1' thend<=d+1;beep_count<=beep_count+1;if set_mode="01" thenb0<=b3;b1<=b4;elsea<=a+1;if a=30000000 then b<=not b;b1<=not b1;b0<=not b0;a<=0;end if;end if;if beep_count=15000000 thenbeep_clk<=not beep_clk;beep_count<=0;-- if beep_count=35000000 then beep_clk<=not beep_clk;beep_count<=0;end if;end if;if d=5000 then e<=not e;d<=0;end if;end if;end process;process(e)--variable c1,c2,c3,c4,c5,c6:integer:=0;beginif e'event and e='1' thenif set_mode="00"or set_mode="01" thenc1<=c;c2<=ch;c3<=fg;c4<=fs;c5<=sg;c6<=ss;end if;if set_mode="10" thenc1<=0;c2<=0;c3<=beep_m1;c4<=beep_m2;c5<=beep_h1;c6<=beep_h2;--c3<=3;--c4<=2;--c5<=5;--c6<=0;end if;case eight iswhen 0 =>en<="11111110";case c1 iswhen 0 => y<="11000000"; when 1 => y<="11111001"; when 2 => y<="10100100"; when 3 => y<="10110000"; when 4 => y<="10011001"; when 5 => y<="10010010"; when 6 => y<="10000010"; when 7 => y<="11111000"; when 8 => y<="10000000"; when 9 => y<="10010000"; when others =>y<="11000000"; end case;eight<=1;when 1 =>en<="11111101";case c2 iswhen 0 => y<="11000000"; when 1 => y<="11111001"; when 2 => y<="10100100";when 3 => y<="10110000"; when 4 => y<="10011001"; when 5 => y<="10010010"; when others =>y<="11000000"; end case;eight<=2;when 2 =>en<="11111011";y<="10111111";eight<=3;when 3 =>en<="11110111";case c3 iswhen 0 => y<="11000000"; when 1 => y<="11111001"; when 2 => y<="10100100"; when 3 => y<="10110000"; when 4 => y<="10011001"; when 5 => y<="10010010"; when 6 => y<="10000010"; when 7 => y<="11111000"; when 8 => y<="10000000"; when 9 => y<="10010000"; when others =>y<="11000000"; end case;eight<=4;when 4 =>en<="11101111";case c4 iswhen 0 => y<="11000000"; when 1 => y<="11111001"; when 2 => y<="10100100"; when 3 => y<="10110000"; when 4 => y<="10011001"; when 5 => y<="10010010"; when others =>y<="11000000"; end case;eight<=5;when 5 =>en<="11011111";y<="10111111";eight<=6;when 6 =>en<="10111111";case c5 iswhen 0 => y<="11000000"; when 1 => y<="11111001"; when 2 => y<="10100100"; when 3 => y<="10110000"; when 4 => y<="10011001"; when 5 => y<="10010010"; when 6 => y<="10000010"; when 7 => y<="11111000"; when 8 => y<="10000000"; when 9 => y<="10010000"; when others =>y<="11000000"; end case;eight<=7;when 7 =>en<="01111111";case c6 iswhen 0 => y<="11000000"; when 1 => y<="11111001"; when others =>y<="11000000"; end case;eight<=0;when others => eight<=0;end case;end if ;end process;miao:process(b,reset)beginif reset='0' thenc<=0;ch<=0;elseif b'event and b='0' thenif c=9 thenc<=0;elsec<=c+1;end if;if ch=5 and c=9 thench<=0;elseif c=9 thench<=ch+1;end if;end if;end if;end if;end process;fen:process(b0,reset,ch,c,b3)beginif reset='0' thenfg<=0;fs<=0;elseif b0'event and b0='0' thenif (((ch=5)and(c=9)) or (set_mode="01" and b3='0'))then if fg=9 thenfg<=0;elsefg<=fg+1;end if;if fs=5 and fg=9 thenfs<=0;elseif fg=9 thenfs<=fs+1;end if;end if;end if;end if;end if;end process;shi:process(b1,reset,fg,fs,ch,c,b4)beginif reset='0' thensg<=0;ss<=0;elseif b1'event and b1='0' thenif ((c=9) and (ch=5) and (fg=9) and (fs=5))or (set_mode="01" and b4='0') then--if ((ss=1 and sg=1) or sg=9) then-- sg<=0;--else-- sg<=sg+1;--end if;if sg=9 thensg<=0;elsesg<=sg+1;end if;if (ss=1 and sg=1 and AM_PM='0')thenss<=0;sg<=0;AM_PM<=not AM_PM;elseif sg=9 thenss<=ss+1;end if;end if;if (ss=1 and sg=2 and AM_PM='1')thenss<=0;sg<=1;AM_PM<=not AM_PM;elseif sg=9 thenss<=ss+1;end if;end if;end if;end if;end if;end process;set_time:set0 port map( set_clk=>clk,m_key=>fen_key,h_key=>shi_key,mode_key=>set_mode_key,mode=>set_mode,set_out_m=>b3,set_out_h=>b4,beep_key_m=>b5,beep_key_h=>b6);beep_set_fen:process(set_mode_key,b5)beginif b5'event and b5='0' thenif set_mode="10" thenif b5='0' thenif beep_m1=9 thenbeep_m1<=0;elsebeep_m1<=beep_m1+1;end if;if beep_m2=5 and beep_m1=9 thenbeep_m2<=0;elseif beep_m1=9 thenbeep_m2<=beep_m2+1;end if;end if;end if;end if;end if;end process;beep_set_shi:process(set_mode_key,b6)beginif b6'event and b6='0' thenif set_mode="10" thenif b6='0' thenif ((beep_h2=1 and beep_h1=1) or beep_h1=9) thenbeep_h1<=0;elsebeep_h1<=beep_h1+1;end if;if beep_h2=1 and beep_h1=1 thenbeep_h2<=0;elseif beep_h1=9 thenbeep_h2<=beep_h2+1;end if;end if;end if;end if;end if;end process;beep:process(e)beginif e'event and e='1' thenif beep_m1=fg thenif beep_m2=fs thenif beep_h1=sg thenif beep_h2=ss thenbeep_s<=beep_clk;end if;end if;end if;elsebeep_s<='1';end if;end if;end process;end code2;<set0.vhd>LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.ALL;entity set0 isport ( set_clk:in std_logic;m_key:in std_logic;h_key:in std_logic;mode_key:in std_logic;mode:out std_logic_vector(1 downto 0);set_out_m:out std_logic;set_out_h:out std_logic;beep_key_m:out std_logic;beep_key_h:out std_logic);end set0;ARCHITECTURE set1 of set0 issignal s1:std_logic_vector (1 downto 0);beginprocess(mode_key) --模式设定beginif mode_key'event and mode_key='1' thens1<=s1+'1';mode<=s1;if s1="10" thens1<="00";end if;end if;end process;process(m_key,set_clk) --传递调时按键信号beginif set_clk'event and set_clk='1' then-- if s1="01" thenset_out_m<=m_key;-- else-- set_out_m<='1';-- end if;-- if s1="10" thenbeep_key_m<=m_key;-- else-- set_out_m<='1';-- end if;end if;end process;process(h_key,set_clk) --传递调时按键信号beginif set_clk'event and set_clk='1' then-- if s1="01" thenset_out_h<=h_key;-- else-- set_out_h<='1';-- end if;-- if s1="10" thenbeep_key_h<=h_key; -- else-- beep_key_h<='1';-- end if;end if;end process;end set1;引脚：clk input PIN_31en[7] output PIN_226 en[6] output PIN_230 en[5] output PIN_231 en[4] output PIN_232 en[3] output PIN_221 en[2] output PIN_222 en[1] output PIN_223 en[0] output PIN_224y[7] output PIN_233 y[6] output PIN_234 y[5] output PIN_235 y[4] output PIN_236 y[3] output PIN_237 y[2] output PIN_238 y[1] output PIN_239 y[0] output PIN_240实验中的注意的问题：1、数码管动态显示时，要对时钟信号进行分频，而且，分频计数最好在5000个时钟信号以上，否则数码管显示的可能是模糊的数字8；2、时间计数进程中的if语句要进行嵌套，否则，计数的更新会有一秒的滞后。
VHDL数字钟代码
use ieee.std_logic_1164.all;--顶层实体，用的是20Mhz的时钟use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity clock_shu isport(clk : in std_logic;reset : in std_logic;duan : out std_logic_vector(5 downto 0);data_o : out std_logic_vector(7 downto 0) );end;architecture a of clock_shu iscomponent count60port(carry : std_logic;rst : std_logic;times : out integer range 0 to 59;full : out std_logic);end component;component count24port(carry : in std_logic;rst : in std_logic;times : out integer range 0 to 23--full : out std_logic);end component;component i60bcdport(interg : in integer range 0 to 59;ten : out std_logic_vector(7 downto 0);one : out std_logic_vector(7 downto 0) );end component;component i24bcdport(interg : in integer range 0 to 23;ten : out std_logic_vector(7 downto 0);one : out std_logic_vector(7 downto 0) );end component;signal carry1,carry2 : std_logic;signal abin1,abin2 : integer range 0 to 59; signal abin3 : integer range 0 to 23; signal clk_1h : std_logic;signal sh,sl,mh,ml,hh,hl : std_logic_vector(7 downto 0); signal cnt : integer range 0 to 5 :=0; beginprocess(clk)--分频为1hzconstant counter_len:integer:=19999999;variable cnt:integer range 0 to counter_len;beginif clk'event and clk='1' thenif cnt=counter_len thencnt:=0;elsecnt:=cnt+1;end if;case cnt iswhen 0 to counter_len/2=>clk_1h<='0';when others =>clk_1h<='1';end case;end if;end process;process(clk)variable cnt1 : integer range 0 to 200;variable cnt2 : integer range 0 to 10;beginif clk'event and clk='1' thenif cnt1=200 thencnt1:=0;if cnt2=10 thencnt2:=0;if(cnt=5)thencnt<=0;elsecnt<=cnt+1;end if;elsecnt2:=cnt2+1;end if;elsecnt1:=cnt1+1;end if;end if;end process;process(clk)beginif clk='1' thencase cnt iswhen 0 => duan<="000001";data_o<=sl;when 1 => duan<="000010";data_o<=sh;when 2 => duan<="000100";data_o<=ml;when 3 => duan<="001000";data_o<=mh;when 4 => duan<="010000";data_o<=hl;when 5 => duan<="100000";data_o<=hh;when others=>duan<="000000";end case;end if;end process;u1 : count60 port map(carry=>clk_1h,rst=>reset,times=>abin1,full=>carry1); u2 : count60 port map(carry=>carry1,rst=>reset,times=>abin2,full=>carry2); u3 : count24 port map(carry=>carry2,rst=>reset,times=>abin3);u4 : i60bcd port map(interg=>abin1,ten=>sh,one=>sl);u5 : i60bcd port map(interg=>abin2,ten=>mh,one=>ml);u6 : i24bcd port map(interg=>abin3,ten=>hh,one=>hl);end;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity count60 is--分，秒计数器port(carry : std_logic;rst : std_logic;times : out integer range 0 to 59;full : out std_logic);end;architecture a of count60 issignal time_s : integer range 0 to 59;beginprocess(rst,carry)beginif rst='1' thentime_s<=0;full<='0';elsif rising_edge(carry) thenif time_s=59 thentime_s<=0;full<='1';elsetime_s<=time_s+1;full<='0';end if;end if;end process;times<=time_s;end;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity count24 is--时计数器port(carry : in std_logic;rst : in std_logic;times : out integer range 0 to 23--full : out std_logic);end;architecture a of count24 issignal time_s : integer range 0 to 23; beginprocess(rst,carry)beginif rst='1' thentime_s<=0;--full<='0';elsif rising_edge(carry) thenif time_s=23 thentime_s<=0;--full<='1';elsetime_s<=time_s+1;--full<='1';end if;end if;end process;times<=time_s;end;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity i60bcd is--分，秒显示port(interg : in integer range 0 to 59;ten : out std_logic_vector(7 downto 0);one : out std_logic_vector(7 downto 0));end;architecture a of i60bcd isbeginprocess(interg)begincase interg iswhen 0|10|20|30|40|50 => one<="11000000";when 1|11|21|31|41|51 => one<="11111001";when 2|12|22|32|42|52 => one<="10100100";when 3|13|23|33|43|53 => one<="10110000";when 4|14|24|34|44|54 => one<="10011001";when 5|15|25|35|45|55 => one<="10010010";when 6|16|26|36|46|56 => one<="10000011";when 7|17|27|37|47|57 => one<="11111000";when 8|18|28|38|48|58 => one<="10000000";when 9|19|29|39|49|59 => one<="10011000";when others => one<=null;end case;case interg iswhen 0|1|2|3|4|5|6|7|8|9 =>ten<="11000000";when 10|11|12|13|14|15|16|17|18|19 =>ten<="11111001";ten<="10100100";when 30|31|32|33|34|35|36|37|38|39 => ten<="10110000";when 40|41|42|43|44|45|46|47|48|49 => ten<="10011001";when 50|51|52|53|54|55|56|57|58|59 => ten<="10010010";when others => ten<=null;end case;end process;end;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity i24bcd is--时显示port(interg : in integer range 0 to 23;ten : out std_logic_vector(7 downto 0);one : out std_logic_vector(7 downto 0) );end;architecture a of i24bcd isbeginprocess(interg)begincase interg iswhen 0|10|20 => one<="11000000";when 1|11|21 => one<="11111001";when 2|12|22 => one<="10100100";when 3|13|23 => one<="10110000";when 4|14 => one<="10011001";when 5|15 => one<="10010010";when 6|16 => one<="10000011";when 7|17 => one<="11111000";when 8|18 => one<="10000000";when 9|19 => one<="10011000";when others => one<=null;end case;case interg isten<="11000000";when 10|11|12|13|14|15|16|17|18|19 => ten<="11111001";when 20|21|22|23 => ten<="10100100";when others => ten<=null;end case;end process;end;回答者：ail傻大个|三级| 2010-12-29 17:19library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity MINSECONDb isport(clk,clrm,stop:in std_logic;----时钟/清零信号secm1,secm0:out std_logic_vector(3 downto 0);----秒高位/低位co:out std_logic);-------输出/进位信号end MINSECONDb;architecture SEC of MINSECONDb issignal clk1,DOUT2:std_logic;beginprocess(clk,clrm)variable cnt1,cnt0:std_logic_vector(3 downto 0);---计数VARIABLE COUNT2 :INTEGER RANGE 0 TO 10 ;beginIF CLK'EVENT AND CLK='1'THENIF COUNT2>=0 AND COUNT2<10 THENCOUNT2:=COUNT2+1;ELSE COUNT2:=0;DOUT2<= NOT DOUT2;END IF;END IF;if clrm='1' then----当clr为1时，高低位均为0cnt1:="0000";cnt0:="0000";elsif clk'event and clk='1' thenif stop='1' thencnt0:=cnt0;cnt1:=cnt1;end if;if cnt1="1001" and cnt0="1000" then----当记数为98（实际是经过59个记时脉冲）co<='1';----进位cnt0:="1001";----低位为9elsif cnt0<"1001" then----小于9时cnt0:=cnt0+1;----计数--elsif cnt0="1001" then--clk1<=not clk1;elsecnt0:="0000";if cnt1<"1001" then----高位小于9时cnt1:=cnt1+1;elsecnt1:="0000";co<='0';end if;end if;end if;secm1<=cnt1;secm0<=cnt0;end process;end SEC;秒模块程序清单library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity SECOND isport(clk,clr:in std_logic;----时钟/清零信号sec1,sec0:out std_logic_vector(3 downto 0);----秒高位/低位co:out std_logic);-------输出/进位信号end SECOND;architecture SEC of SECOND isbeginprocess(clk,clr)variable cnt1,cnt0:std_logic_vector(3 downto 0);---计数beginif clr='1' then----当ckr为1时，高低位均为0cnt1:="0000";cnt0:="0000";elsif clk'event and clk='1' thenif cnt1="0101" and cnt0="1000" then----当记数为58（实际是经过59个记时脉冲）co<='1';----进位cnt0:="1001";----低位为9elsif cnt0<"1001" then----小于9时cnt0:=cnt0+1;----计数elsecnt0:="0000";if cnt1<"0101" then----高位小于5时cnt1:=cnt1+1;elsecnt1:="0000";co<='0';end if;end if;end if;sec1<=cnt1;sec0<=cnt0;end process;end SEC;分模块程序清单library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity MINUTE isport(clk,en:in std_logic;min1,min0:out std_logic_vector(3 downto 0);co:out std_logic);end MINUTE;architecture MIN of MINUTE isbeginprocess(clk)variable cnt1,cnt0:std_logic_vector(3 downto 0);beginif clk'event and clk='1' thenif en='1' thenif cnt1="0101" and cnt0="1000" thenco<='1';cnt0:="1001";elsif cnt0<"1001" thencnt0:=cnt0+1;elsecnt0:="0000";if cnt1<"0101" thencnt1:=cnt1+1;elsecnt1:="0000";co<='0';end if;end if;end if;end if;min1<=cnt1;min0<=cnt0;end process;end MIN;时模块程序清单library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity HOUR isport(clk,en:in std_logic;----输入时钟/高电平有效的使能信号h1,h0:out std_logic_vector(3 downto 0));----时高位/低位end HOUR;architecture hour_arc of HOUR isbeginprocess(clk)variable cnt1,cnt0:std_logic_vector(3 downto 0);----记数beginif clk'event and clk='1' then---上升沿触发if en='1' then---同时“使能”为1if cnt1="0010" and cnt0="0011" thencnt1:="0000";----高位/低位同时为0时cnt0:="0000";elsif cnt0<"1001" then----低位小于9时，低位记数累加cnt0:=cnt0+1;elsecnt0:="0000";cnt1:=cnt1+1;-----高位记数累加end if;end if;end if;h1<=cnt1;h0<=cnt0;end process;end hour_arc;动态扫描模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity SELTIME isport(clk:in std_logic;------扫描时钟secm1,secm0,sec1,sec0,min1,min0,h1,h0:in std_logic_vector(3 downto 0);-----分别为秒个位/时位；分个位/daout:out std_logic_vector(3 downto 0);----------------输出sel:out std_logic_vector(2 downto 0));-----位选信号end SELTIME;architecture fun of SELTIME issignal count:std_logic_vector(2 downto 0);----计数信号beginsel<=count;process(clk)beginif(clk'event and clk='1') thenif(count>="111") thencount<="000";elsecount<=count+1;end if;end if;case count iswhen"111"=>daout<= secm0;----秒个位when"110"=>daout<= secm1;----秒十位when"101"=>daout<= sec0;----分个位when"100"=>daout<= sec1;----分十位when"011"=>daout<=min0; ----时个位when"010"=>daout<=min1;----时十位when"001"=>daout<=h0;when others =>daout<=h1;end case;end process;end fun;报时模块library ieee;use ieee.std_logic_1164.all;entity ALERT isport(m1,m0,s1,s0:in std_logic_vector(3 downto 0);------输入秒、分高/低位信号clk:in std_logic;------高频声控制q500,qlk:out std_logic);----低频声控制end ALERT;architecture sss_arc of ALERT isbeginprocess(clk)beginif clk'event and clk='1' thenif m1="0101" and m0="1001" and s1="0101" then----当秒高位为5，低位为9时且分高位为5if s0="0001" or s0="0011" or s0="0101" or s0="0111" then---当分的低位为1或3或5或7时q500<='1';----低频输出为1elseq500<='0';----否则输出为0end if;end if;if m1="0101" and m0="1001" and s1="0101" and s0="1001" then---当秒高位为5，低位为9时且分高位为5，----分低位为9时，也就是“59分59秒”的时候“报时”qlk<='1';-----高频输出为1elseqlk<='0';end if;end if;end process;end sss_arc;显示模块library ieee;use ieee.std_logic_1164.all;entity DISPLAY isport(d:in std_logic_vector(3 downto 0);----连接seltime扫描部分d信号q:out std_logic_vector(6 downto 0));----输出段选信号（电平）end DISPLAY;architecture disp_are of DISPLAY isbeginprocess(d)begincase d iswhen"0000" =>q<="0111111";--显示0when"0001" =>q<="0000110";--显示1when"0010" =>q<="1011011";--显示2when"0011" =>q<="1001111";--显示3when"0100" =>q<="1100110";--显示4when"0101" =>q<="1101101";--显示5when"0110" =>q<="1111101";--显示6when"0111" =>q<="0100111";--显示7when"1000" =>q<="1111111";--显示8when others =>q<="1101111";--显示9end case;end process;end disp_are;顶层文件（原理图输入）******************************************************************** 数字钟设计模块与程序（不含秒表）*********************************************************************1.分频模块（原理图输入）2. 秒模块程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity SECOND isport(clk,clr:in std_logic;sec1,sec0:out std_logic_vector(3 downto 0);co:out std_logic);end SECOND;architecture SEC of SECOND isbeginprocess(clk,clr)variable cnt1,cnt0:std_logic_vector(3 downto 0); beginif clr='1' thencnt1:="0000";cnt0:="0000";elsif clk'event and clk='1' thenif cnt1="0101" and cnt0="1000" thenco<='1';cnt0:="1001";elsif cnt0<"1001" thencnt0:=cnt0+1;elsecnt0:="0000";if cnt1<"0101" thencnt1:=cnt1+1;elsecnt1:="0000";co<='0';end if;end if;end if;sec1<=cnt1;sec0<=cnt0;end process;end SEC;3.分模块程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity MINUTE isport(clk,en:in std_logic;min1,min0:out std_logic_vector(3 downto 0);co:out std_logic);end MINUTE;architecture MIN of MINUTE isbeginprocess(clk)variable cnt1,cnt0:std_logic_vector(3 downto 0); beginif clk'event and clk='1' thenif en='1' thenif cnt1="0101" and cnt0="1000" thenco<='1';cnt0:="1001";elsif cnt0<"1001" thencnt0:=cnt0+1;elsecnt0:="0000";if cnt1<"0101" thencnt1:=cnt1+1;elsecnt1:="0000";co<='0';end if;end if;end if;end if;min1<=cnt1;min0<=cnt0;end process;end MIN;4.时模块程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity HOUR isport(clk,en:in std_logic;h1,h0:out std_logic_vector(3 downto 0)); end HOUR;architecture hour_arc of HOUR isbeginprocess(clk)variable cnt1,cnt0:std_logic_vector(3 downto 0);beginif clk'event and clk='1' thenif en='1' thenif cnt1="0010" and cnt0="0011" thencnt1:="0000";cnt0:="0000";elsif cnt0<"1001" thencnt0:=cnt0+1;end if;end if;end if;h1<=cnt1;h0<=cnt0;end process;end hour_arc;5.扫描模块程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity SELTIME isport(clk:in std_logic;sec1,sec0,min1,min0,h1,h0:in std_logic_vector(3 downto 0);daout:out std_logic_vector(3 downto 0);sel:out std_logic_vector(2 downto 0));end SELTIME;architecture fun of SELTIME issignal count:std_logic_vector(2 downto 0);beginsel<=count;process(clk)beginif(clk'event and clk='1') thenif(count>="101") thencount<="000";elsecount<=count+1;end if;end if;case count iswhen"000"=>daout<= sec0; when"001"=>daout<= sec1; when"010"=>daout<= min0; when"011"=>daout<= min1; when"100"=>daout<=h0;when others =>daout<=h1;end case;end process;end fun;6.显示模块程序library ieee;use ieee.std_logic_1164.all;entity DISPLAY isport(d:in std_logic_vector(3 downto 0);q:out std_logic_vector(6 downto 0)); end DISPLAY;architecture disp_are of DISPLAY isbeginprocess(d)begincase d iswhen"0000" =>q<="0111111";when"0001" =>q<="0000110";when"0010" =>q<="1011011";when"0011" =>q<="1001111";when"0100" =>q<="1100110";when"0101" =>q<="1101101";when"0110" =>q<="1111101";when"0111" =>q<="0100111";when"1000" =>q<="1111111";when others =>q<="1101111";end case;end process;end disp_are;7.定时闹钟模块程序library ieee;use ieee.std_logic_1164.all;entity ALERT isport(m1,m0,s1,s0:in std_logic_vector(3 downto 0);clk:in std_logic;q500,qlk:out std_logic);end ALERT;architecture sss_arc of ALERT isbeginprocess(clk)beginif clk'event and clk='1' thenif m1="0101" and m0="1001" and s1="0101" thenif s0="0001" or s0="0011" or s0="0101" or s0="0111" thenq500<='1';elseq500<='0';end if;end if;if m1="0101" and m0="1001" and s1="0101" and s0="1001" then qlk<='1';elseqlk<='0';end if;end if;end process;end sss_arc;。
VHDL电子时钟程序
VHDL电子时钟程序最近收到网上朋友们来信咨询如何设计电子时钟，也有很多热心朋友把他设计的时钟或时钟程序发给我。
因时间和水平有限不能一一回复和审查到底哪些是合格或是网络转载的。
但是感觉可能对部分网友会有所用处，就把自己手头已有的一些时钟设计的相关资料放到网上，希望大家能多多包涵。
我会不定时的把一些时钟设计资料上传到本博客，希望多多关注。
下面是电子时钟设计的部分VHDL程序代码。
VHDL电子钟程序（小时和分钟）library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity hours isPort ( rst4,selector3,ky_3j : in STD_LOGIC;C10 : in std_logic;dat40 : out std_logic_vector(7 downto 0));end hours;architecture Behavioral of hours issignal dat41,dat42 : std_logic_vector(7 downto 0):=(others =>'0');beginprocess(rst4,C10,ky_3j)begincase selector3 iswhen '1' => dat42<=dat41; if ky_3j'event and ky_3j='1' thenif dat41(7 downto 4)="0010" and dat41(3 downto 0)="0011"then dat41<="00000000";elsif dat41(3 downto 0)<"1001" then dat41(3 downto 0)<=dat41(3 downto 0)+1;else dat41(3 downto 0)<="0000";dat41(7 downto 4)<=dat41(7 downto 4)+ 1;end if ;end if ;dat40<=dat41;when '0' => dat41<=dat42; if(rst4 = '0') then dat42<=(others =>'0');elsif C10'event and C10='1' thenif dat42(7 downto 4)="0010" and dat42(3 downto 0)="0011"then dat42<="00000000";elsif dat42(3 downto 0)<"1001" then dat42(3 downto 0)<=dat42(3 downto 0)+1;else dat42(3 downto 0)<="0000";dat42(7 downto 4)<=dat42(7 downto 4)+ 1;end if;end if;dat40<=dat42;when others =>null;end case;end process;end Behavioral;VHDL电子钟程序（分频和秒计数）library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity miseconds isPort ( clk_100HZ,rst1 : in STD_LOGIC;A : out std_logic;dat10 : out std_logic_vector(7 downto 0));end miseconds;architecture Behavioral of miseconds issignal dat1 : std_logic_vector(7 downto 0):=(others =>'0');beginprocess(clk_100HZ,rst1)beginif(rst1 = '0') then dat1<=(others =>'0');elsif clk_100HZ'event and clk_100HZ='1' thenif dat1(7 downto 4)="1001" and dat1(3 downto 0)="1001"then A<='1'; dat1(7 downto 0)<="00000000";else A<='0';if dat1(3 downto 0)<"1001" then dat1(3 downto 0)<=dat1(3 downto 0)+1; else dat1(3 downto 0)<="0000";if dat1(7 downto 4)<"1001" then dat1(7 downto 4)<=dat1(7 downto 4)+1; else dat1(7 downto 4)<="0000";end if;end if;end if;end if;end process;dat10<=dat1;end Behavioral;VHDL电子钟程序（数码管显示扫描程序）library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity scannor isPort ( clk_1MHZ,T : in std_logic;clks : in std_logic_vector(5 downto 0);D : in std_logic_vector(31 downto 0);positions : out std_logic_vector(7 downto 0);segments : out std_logic_vector(7 downto 0));end scannor;architecture Behavioral of scannor issignal cnt8:STD_LOGIC_vector(2 downto 0);signal sin :STD_LOGIC_vector(7 downto 0);signal d1 : STD_LOGIC_vector(3 downto 0);signal bt1 : std_logic_vector(7 downto 0);beginP1: process(clk_1MHZ)beginif (clk_1MHZ'event and clk_1MHZ='1') thencase cnt8 iswhen "000" => sin <= "00000001" ; d1 <= D(3 downto 0) ; led8s(7) <= '0';when "001" => sin <= "00000010" ; d1 <= D(7 downto 4) ; led8s(7) <= '0';when "010" => sin <= "00000100" ; d1 <= D(11 downto 8) ; led8s(7) <= '1';when "011" => sin <= "00001000" ; d1 <= D(15 downto 12) ; led8s(7) < = '0';when "100" => sin <= "00010000" ; d1 <= D(19 downto 16) ; led8s(7) < = '1';when "101" => sin <= "00100000" ; d1 <= D(23 downto 20) ; led8s(7) < = '0';when "110" => sin <= "01000000" ; d1 <= D(27 downto 24) ; led8s(7) < = '1';when "111" => sin <= "10000000" ; d1 <= D(31 downto 28) ; led8s(7) < = '0';when others => null ;end case ;end if ;end process P1;P2 : process(clk_1MHZ)beginif clk_1MHZ'event and clk_1MHZ ='1' then cnt8 <= cnt8+1; end if ;end process P2;P3 : process(d1)begincase d1 iswhen "0000" => led8s(6 downto 0) <= "0111111" ;when "0001" => led8s(6 downto 0) <= "0000110" ;when "0010" => led8s(6 downto 0) <= "1011011" ;when "0011" => led8s(6 downto 0) <= "1001111" ;when "0100" => led8s(6 downto 0) <= "1100110" ;when "0101" => led8s(6 downto 0) <= "1101101" ;when "0110" => led8s(6 downto 0) <= "1111101" ;when "0111" => led8s(6 downto 0) <= "0000111" ;when "1000" => led8s(6 downto 0) <= "1111111" ;when "1001" => led8s(6 downto 0) <= "1101111" ;when others => null ;end case ;end process P3;bt1(0) <= sin(0) ;bt1(1) <= sin(1) ;bt1(2) <= sin(2) and clks(0) ;bt1(3) <= sin(3) and clks(1) ;bt1(4) <= sin(4) and clks(2) ;bt1(5) <= sin(5) and clks(3) ;bt1(6) <= sin(6) and clks(4) ;bt1(7) <= sin(7) and clks(5) ;bt(0)<=not(bt1(0)and T);bt(1)<=not(bt1(1)and T);bt(2)<=not(bt1(2)and T);bt(3)<=not(bt1(3)and T);bt(4)<=not(bt1(4)and T);bt(5)<=not(bt1(5)and T);bt(6)<=not(bt1(6)and T);bt(7)<=not(bt1(7)and T);end Behavioral;。
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LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;--****************************************ENTITY TIMER_SET ISPORT( CP :IN STD_LOGIC;SEGOUT :OUT STD_LOGIC_VECTOR(7 DOWNTO 0);SELOUT :OUT STD_LOGIC_VECTOR(2 DOWNTO 0);KEY:IN STD_LOGIC_VECTOR(2 DOWNTO 0) ); END TIMER_SET;--*******************************************ARCHITECTURE A OF TIMER_SET ISCOMPONENT COUNTER60PORT( CP :IN STD_LOGIC;BIN :OUT STD_LOGIC_VECTOR(5 DOWNTO 0);S :IN STD_LOGIC;CLR :IN STD_LOGIC;EC :IN STD_LOGIC;CY60:OUT STD_LOGIC );END COMPONENT;COMPONENT COUNTER24PORT( CP :IN STD_LOGIC;BIN :OUT STD_LOGIC_VECTOR(5 DOWNTO 0);S :IN STD_LOGIC;CLR :IN STD_LOGIC;EC :IN STD_LOGIC;CY24:OUT STD_LOGIC );END COMPONENT;SIGNAL BIN :STD_LOGIC_VECTOR(5 DOWNTO 0);SIGNAL DBS :STD_LOGIC_VECTOR(5 DOWNTO 0);SIGNAL DBM :STD_LOGIC_VECTOR(5 DOWNTO 0);SIGNAL DBH :STD_LOGIC_VECTOR(5 DOWNTO 0);SIGNAL ENB :STD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL SEC :STD_LOGIC;SIGNAL BCD :STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL CLR :STD_LOGIC;SIGNAL CYS,CYM,CYH :STD_LOGIC;SIGNAL S :STD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL NUM :STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL SEG :STD_LOGIC_VECTOR(6 DOWNTO 0);SIGNAL SEL :STD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL SAMPLE,DLY_OUT,DIFF:STD_LOGIC;SIGNAL STA TE:STD_LOGIC_VECTOR(1 DOWNTO 0);SIGNAL MA TCH :STD_LOGIC;SIGNAL GLITTER:STD_LOGIC;BEGINCONNECTION:BLOCKSIGNAL ADJ,ECS,ECM,ECH,SC :STD_LOGIC;BEGINU1:COUNTER60 PORT MAP(CP,DBS,ENB(0),CLR,ECS,CYS);U2:COUNTER60 PORT MAP(CP,DBM,ENB(1),CLR,ECM,CYM);U3:COUNTER24 PORT MAP(CP,DBH,ENB(2),CLR,ECH,CYH);CLR<=NOT KEY(0);SC<=STA TE(1) AND STA TE(0);ADJ<=SEC AND (NOT SC)AND KEY(1);ECS<=(SEC AND SC)OR(ADJ AND NOT STA TE(1)AND STA TE(0));ECM<=(CYS AND SC)OR(ADJ AND NOT STA TE(1) AND STA TE(0));ECH<=(CYM AND SC)OR(ADJ AND NOT STA TE(1) AND NOT STA TE(0));SELOUT<=SEL;GEN:FOR I IN 0 TO 6 GENERA TESEGOUT(I)<=SEG(I)AND(SC OR (GLITTER OR NOT MA TCH));END GENERA TE;SEGOUT(7)<='0';END BLOCK CONNECTION;FREE_COUNTER:BLOCKSIGNAL Q :STD_LOGIC_VECTOR(13 DOWNTO 0);SIGNAL DLY,SDLY:STD_LOGIC;BEGINPROCESS(CP)BEGINIF CP'EVENT AND CP='1'THENDLY<=Q(10);SDLY<=Q(3);Q<=Q+1;END IF;END PROCESS;GLITTER<=Q(10);SEC<=Q(10)AND NOT DLY;S<=Q(4 DOWNTO 2);SAMPLE<=Q(3)AND NOT SDLY;SEL<="000"WHEN S=0 ELSE"001"WHEN S=1 ELSE"010"WHEN S=2 ELSE"011"WHEN S=3 ELSE"100"WHEN S=4 ELSE"101"WHEN S=5 ELSE"110"WHEN S=6 ELSE"111"WHEN S=7 ELSE"000";ENB<="001"WHEN(S=0 OR S=1)ELSE"010"WHEN(S=3 OR S=4)ELSE"100"WHEN(S=6 OR S=7)ELSE"000";BIN<=DBS WHEN ENB="001"ELSEDBM WHEN ENB="010"ELSEDBH WHEN ENB="100"ELSE"000000";MA TCH<='1' WHEN ((S=0 OR S=1)AND STA TE="10")ELSE '1' WHEN ((S=3 OR S=4)AND STA TE="01")ELSE'1' WHEN ((S=6 OR S=7)AND STA TE="00")ELSE'0';END BLOCK FREE_COUNTER;BINARY_BCD:BLOCKBEGINBCD<="00000000" WHEN BIN =0 ELSE"00000001" WHEN BIN =1 ELSE"00000010" WHEN BIN =2 ELSE"00000011" WHEN BIN =3 ELSE"00000100" WHEN BIN =4 ELSE"00000101" WHEN BIN =5 ELSE"00000110" WHEN BIN =6 ELSE"00000111" WHEN BIN =7 ELSE"00001000" WHEN BIN =8 ELSE"00001001" WHEN BIN =9 ELSE"00010000" WHEN BIN =10 ELSE"00010001" WHEN BIN =11 ELSE"00010010" WHEN BIN =12 ELSE"00010011" WHEN BIN =13 ELSE"00010100" WHEN BIN =14 ELSE"00010110" WHEN BIN =16 ELSE "00010111" WHEN BIN =17 ELSE "00011000" WHEN BIN =18 ELSE "00011001" WHEN BIN =19 ELSE "00100000" WHEN BIN =20 ELSE "00100001" WHEN BIN =21 ELSE "00100010" WHEN BIN =22 ELSE "00100011" WHEN BIN =23 ELSE "00100100" WHEN BIN =24 ELSE "00100101" WHEN BIN =25 ELSE "00100110" WHEN BIN =26 ELSE "00100111" WHEN BIN =27 ELSE "00101000" WHEN BIN =28 ELSE "00101001" WHEN BIN =29 ELSE "00110000" WHEN BIN =30 ELSE "00110001" WHEN BIN =31 ELSE "00110010" WHEN BIN =32 ELSE "00110011" WHEN BIN =33 ELSE "00110100" WHEN BIN =34 ELSE "00110101" WHEN BIN =35 ELSE "00110110" WHEN BIN =36 ELSE "00110111" WHEN BIN =37 ELSE "00111000" WHEN BIN =38 ELSE "00111001" WHEN BIN =39 ELSE "01000000" WHEN BIN =40 ELSE "01000001" WHEN BIN =41 ELSE "01000010" WHEN BIN =42 ELSE "01000011" WHEN BIN =43 ELSE "01000100" WHEN BIN =44 ELSE "01000101" WHEN BIN =45 ELSE "01000110" WHEN BIN =46 ELSE "01000111" WHEN BIN =47 ELSE "01001000" WHEN BIN =48 ELSE "01001001" WHEN BIN =49 ELSE "01010000" WHEN BIN =50 ELSE "01010001" WHEN BIN =51 ELSE "01010010" WHEN BIN =52 ELSE "01010011" WHEN BIN =53 ELSE "01010100" WHEN BIN =54 ELSE "01010101" WHEN BIN =55 ELSE "01010110" WHEN BIN =56 ELSE "01010111" WHEN BIN =57 ELSE "01011000" WHEN BIN =58 ELSE"00000000";END BLOCK BINARY_BCD;SELECT_BCD:BLOCKBEGINNUM<=BCD(3 DOWNTO 0) WHEN (S=0 OR S=3 OR S=6) ELSE BCD(7 DOWNTO 4) WHEN (S=1 OR S=4 OR S=7) ELSE"1010";END BLOCK SELECT_BCD;SEVEN_SEGMENT:BLOCKBEGINSEG<="0111111" WHEN NUM=0 ELSE"0000110" WHEN NUM=1 ELSE"1011011" WHEN NUM=2 ELSE"1001111" WHEN NUM=3 ELSE"1100110" WHEN NUM=4 ELSE"1101101" WHEN NUM=5 ELSE"1111101" WHEN NUM=6 ELSE"0000111" WHEN NUM=7 ELSE"1111111" WHEN NUM=8 ELSE"1101111" WHEN NUM=9 ELSE"1000000" WHEN NUM=10 ELSE"0000000";END BLOCK SEVEN_SEGMENT;DEBOUNCE:BLOCKSIGNAL D0,D1,S,R,DLY,NDLY:STD_LOGIC;BEGINPROCESS(CP)BEGINIF CP'EVENT AND CP='1' THENIF SAMPLE='1' THEND1<=D0;D0<=KEY(2);S<=D0 AND D1;R<=NOT D0 AND NOT D1;END IF;END IF;END PROCESS;DLY<=R NOR NDLY;NDLY<=S NOR DLY;DLY_OUT<=DLY;END BLOCK DEBOUNCE;DIFFERENTIAL:BLOCKSIGNAL D1,D0:STD_LOGIC;BEGINPROCESS(CP)BEGINIF CP'EVENT AND CP='1' THEND1<=D0;D0<=DLY_OUT;END IF;END PROCESS;DIFF<=D0 AND NOT D1;END BLOCK DIFFERENTIAL;TIMERSET:BLOCKSIGNAL Q:STD_LOGIC_VECTOR (2 DOWNTO 0);SIGNAL SET,EC:STD_LOGIC;BEGINPROCESS(CP)BEGINIF SET='1' THENQ<="011";ELSIF CP'EVENT AND CP='1' THENIF EC='1' THENQ<=Q-1;END IF;END IF;END PROCESS;SET<='1' WHEN Q=7 ELSE'0';EC<=DIFF AND KEY(2);STA TE<=Q(1 DOWNTO 0);END BLOCK TIMERSET;END A;子程序2个:LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;--********************************ENTITY COUNTER24 ISPORT(CP :IN STD_LOGIC;BIN :OUT STD_LOGIC_VECTOR(5 DOWNTO 0);S :IN STD_LOGIC;CLR :IN STD_LOGIC;EC :IN STD_LOGIC;CY24:OUT STD_LOGIC );END COUNTER24;--********************************ARCHITECTURE A OF COUNTER24 ISSIGNAL Q :STD_LOGIC_VECTOR(4 DOWNTO 0);SIGNAL RST,DLY:STD_LOGIC;BEGINPROCESS(CP,RST)BEGINIF RST='1'THENQ<="00000";ELSIF CP'EVENT AND CP='1'THENDLY<=Q(4);IF EC='1'THENQ<=Q+1;END IF;END IF;END PROCESS;CY24<=NOT Q(4) AND DLY;RST<='1'WHEN Q=24 OR CLR='1' ELSE '0';BIN<=('0'&Q)WHEN S='1' ELSE "000000";END A;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;--**************************************************************ENTITY COUNTER60 ISPORT( CP :IN STD_LOGIC;BIN :OUT STD_LOGIC_VECTOR(5 DOWNTO 0);S :IN STD_LOGIC;CLR :IN STD_LOGIC;EC :IN STD_LOGIC;CY60:OUT STD_LOGIC);END COUNTER60;--**************************************************************ARCHITECTURE A OF COUNTER60 ISSIGNAL Q:STD_LOGIC_VECTOR(5 DOWNTO 0);SIGNAL RST,DLY:STD_LOGIC;BEGINPROCESS(CP,RST)BEGINIF RST='1'THENQ<="000000";ELSIF CP'EVENT AND CP='1'THENDLY<=Q(5);IF EC='1'THENQ<=Q+1;END IF;END IF;END PROCESS;CY60<=NOT Q(5) AND DLY;RST<='1' WHEN Q=60 OR CLR='1' ELSE '0';BIN<=Q WHEN S='1' ELSE "000000";END A;。