LCK4011-DB中文资料

Product Brief, Revision 1May 3, 2005 LCK4011 Programmable Clock GeneratorFeaturesFlexible programming allows for output frequencies from 3.13 MHz to400 MHz.Twenty-one programmable output clocks at various volt-age levels, including: 1.2 V, 1.5 V, 2.5 V, and 3.3 V.High-speed differential clocks with divide-by-24 framing pulse.Limited support for 1.5 V differential outputs.I2C slave interface to allow for programmability.Low-power sleep mode:—Clocks are individually programmed to stop or supply the reference clock.—Unused clock output buffers need not be powered.—Sleep mode power as low as 0.45 mW.Programmable delay matching to compensate for system signal skew.10 MHz to 40 MHz input reference clock or crystal range.50 ps max skew between any two differential clocks.Period jitter performance:—200ps max at 300 MHz VCO frequency.Package and processing:—100-pin FSBGA package, 10 mm x 10 mm,0.8 mm pitch.—0.14 µm process.ApplicationsPC motherboard clock source.Hand-held device, PDA.PC peripherals.Printers, copiers, faxes, etc.SAN (storage area network).Storage media devices.HBA (host bus adapter).OverviewAgere Systems’LCK4011is a programmable timing system that provides up to 21 programmable output clocks and three programmable frame-synchronizing pulses generated from a single external clock reference source.There are three 1.5V differential output clocks (HCLK_0, 1, 2) and one 1.5V differential output clock (VCLK), each pro-grammable up to400 MHz. Complementing these output clocks are three divide-by-24 frame sync outputs (HSYNC_0, 1 and NBSYNC), each with a single-ended 1.2V level. In addition, the three HCLK clocks and the three frame syncs support individual programmable delays rang-ing from tens of pico seconds to 7 ns in 128 steps.There are two 3.3V (GPCLK33_0, 1) and two 2.5V (GPCLK25_0, 1) single-ended output clocks that can be op-tioned to accept up to four preprogrammed frequency refer-ences. Two 1.2 V (HTBEN_0, 1) single-ended, programmable output clocks have an added feature that en-ables them to be stopped high as well as low. There are five 3.3V (PCLK33_0, 1, 2, 3, 4) output clocks, two 2.5V (PCLK25_0, 1) output clocks, one 1.5V (PCLK15) output clock, and one 1.2V (PCLK12) output clock; all can be op-tioned to accept either of two preprogrammed frequency ref-erences.There are two dedicated 2.5V (REFCLK_0, 1) single-ended output clocks that are optioned to distribute the external crystal frequency reference. This reference may be distrib-uted to other frequency generation systems on the same cir-cuit board.The device features four cascaded PLL synthesizers that can be programmed to create a variety of output frequen-cies and phases. One of the PLL synthesizers uses an ex-ternal crystal reference to establish a system timing reference that is distributed to the other three PLLs. Subse-quently, each of these PLL synthesizers manipulate this system timing reference through feed-forward and feed-back dividers, controlled via user programmable registers. The LCK4011is programmable via a standard two-wire I2C interface. The fast mode (up to 400 kHz) of the I2C bus specification 2.1 is supported. The slave address of the de-vice is selectable to allow for two devices on the same I2C bus.Product Brief, Revision 1LCK4011 Programmable Clock GeneratorMay 3, 2005Figure 1. LCK4011 Functional Block Diagram÷1 to 8÷10 to 64 evenPLL4200 MHz—400 MHzXTAL/REFCLKSDATA I 2C InterfacePower ManagerControl &Status RegistersADDSEL SCLKRESET_NPDREFCLK_0REFCLK_1HTBEN_0HTBEN_1GPCLK25_1PCLK12PCLK33_1PCLK33_2PCLK33_4PCLK25_0VCLK HCLK_0HCLK_1HCLK_2HSYNC_0HSYNC_1NBSYNCERROR_NGPCLK33_1T o all PLLsT o all Prog Div and Delay T o all Output MUX Arrays÷5 to 130PLL1360 MHz—720 MHz VCO÷2 to 257PLL3200 MHz—400 MHz÷5 to 130PLL2200 MHz—400 MHzVCO÷5 to 130PCLK15PCLK33_0÷10 to 64 even ÷10 to 64 even÷10 to 64 even ÷10 to 64 even÷10 to 64 even ÷10 to 64 even÷10 to 64 evenPCLK33_3GPCLK33_0GPCLK25_0PCLK25_1Oscillator ÷10 to 64 even÷1 to 8÷9 or 6 to 20 even÷9 or 6 to 20 even÷5 to 130÷5 to 130÷1PDVCOPD÷1PD÷1PDVCO10 to 40 MHz ÷5 to 130÷1Programmable DelayProduct Brief, Revision 1May 3, 2005LCK4011 Programmable Clock Generator Functional DescriptionThe LCK4011 has four individually programmable clock multiplier/clock divider PLLs. Numerous output frequency combina-tions are attainable. There are six primary functions required for full functionality of the LCK4011 as follows:I2C Interface:—Provides access to the control/status registers where the parameters that control the PLLs are stored.PLLs:—Four VCO-based PLLs generate all of the required output clock signals from a single crystal input: PLL1 synthesizes output clocks and is the reference clock to the other three PLLs.PLL2 synthesizes single-ended and differential output clocks and has phase delay capability.PLL3 synthesizes output clocks.PLL4 synthesizes a single differential output clock.Power manager (PowMan):—Ensures that the LCK4011 is powered up and down gracefully. It also performs the operation of entering the LCK4011 into low-power mode by shutting down all output clocks and stopping the PLLs. PowMan also ensures that the LCK4011 wakes up from this low power mode without any glitches on the output clocks.Output multiplexer:—Provides flexibility in routing the divided PLL outputs to the output buffers. And the outputs may be reconfigured on-the-fly.Output buffers:—Include both single-ended and differential output formats. The outputs support 3.3V, 2.5V, 1.5V, and 1.2V for single-ended outputs, and 1.5V for differential outputs.—Power pins associated with unused clock buffers can be left unconnected and floating in order to minimize power dis-sipation.Control/status registers:—The LCK4011 supports flexible modes of operation through the use of individual control/status registers. These regis-ters control all operational aspects of the device.Custom BuffersThe LCK4011 contains two custom buffers that were designed to meet the I2C bus electrical characteristics for the SCLK and SDATA pins. These buffers are bidirectional open drain buffers with hysteresis in order to meet the standard and the fast mode specifications. External pull-up resistors should be connected to the same VDD (3.3 V or 2.5 V) used to supply voltage to the I/O buffers.A complete detailed description of the I2C interface and transfer is described in the I2C -Bus Specification, Version 2.1, Jan-uary 2000. (See website: /markets/mms/protocols/I2c/)Special FeaturesDifferential clocking:—The LCK4011 provides four differential output clocks. Three of these outputs are generated by PLL2 and the fourth is generated by PLL4. These differential clocks allow for clock frequencies of up to 400 MHz. Each output clock can be individually enabled, three of the output clocks generated from PLL2 have programmable delay elements to allow for skew matching in various system topologies.Synchronization framing pulses:—Synchronization framing pulses are associated with the three differential clocks from PLL2. Each synchronization pulse is one clock cycle wide and occurs on every 24th clock cycle. These framing pulses also have individual pro-grammable delay elements to allow for skew matching with the high-speed differential clocks in various system topol-ogies.Programmable delay:—The phase of all outputs from PLL2 may individually be delayed with respect to the other PLL outputs. Individual pro-grammable delays range from tens of pico seconds to 7 ns in 128 steps.Copyright © 2005 Agere Systems Inc.All Rights ReservedProduct Brief, Revision 1LCK4011 Programmable Clock GeneratorMay 3, 2005Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere, Agere Systems, and the Agere logo are registered trademarks of Agere Systems Inc.For additional information, contact your Agere Systems Account Manager or the following:INTERNET:Home: Sales: /sales E-MAIL:docmaster@N. AMERICA:Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-91381-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)ASIA:CHINA: (86) 21-54614688 (Shanghai), (86) 755-25881122 (Shenzhen)JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6741-9855, TAIWAN: (886) 2-2725-5858 (Taipei)EUROPE:Tel. (44) 1344 296 400Ordering InformationTable 1. Ordering InformationDevice Package Type Comcode LCK4011-DB 100-Pin FSBGA Package700074644L-LCK4011-DB700081371。