PROKNETAnIPATMprocessor

2. On the next clock cycle, a second packet comes in, the CU will write it in to the FIFO, and at the same time it will read the first byte
3. Steps 1 and 2 are repeated until CU_Done_Trailer is asserted, which indicates to start sending the CRC
Module architecture/functionality
TLL module ALU module Trailer module CRC module SAR module CU module
Achievements Limitations / Future work Summary
4. When the counter is done, a Done_Trailer signal is sent to CU
CRC Module Architecture
Figure 4
CRC Module Functionality
2nd Packet
4 bytes of valid CRC
provided on a connection basis rather than on a cell basis, which reduces the required processing power
What is IP/ATM?
Combination allows for networks around the world to present a service that is as reliable and dedicated as ATM, while utilizing IP’s greater transmission capability and reduced overheads IP over ATM requires one to be able to segment the variable IP-packets into 48-byte cells at the transmitter (our focus)
2. On the next clock cycle, the byte that was written in step 1, gets read and at the same time another byte is written into the FIFO
3. Steps 1 and 2 are repeated until the CU_EOP (End of Packet) signal is asserted by the CU, which indicates to start sending the trailer
Total length of packet is variable, ranging from 20 bytes to 64k bytes;
Each packet is treated independently; No error control or reliability mechanisms; Routing of every single packet is required which
Trailer Module Architecture
Figure 3
Trailer Module Functionality
8 byte Trailer
8 byte FIFO
Incoming byte
A byte is written and another is read simultaneously.
TL CPI
UU
1
0
CU_C_EOP is low.
1st Packet
4 bytes of valid CRC
Sequence 4
CRC Module
1. The Trailer module sends the first byte of packet, thus the CU writes it to the 4-byte FIFO
Figure 7
SAR Module Functionality
PAD
SEGMENTATION
Trailer
Message
Sequence 5
Each is 48 bytes.
Control Unit Module
Microprocessor chosen was an 8-bit one
All instruction opcodes were limited to 8 bits, while memory was addressed with a 12-bit address bus
ALU Module
16-bit adder-subtractor unit Aids in the instruction execution, by residing on the datapath of the main processor and feeds the accumulator Designed using combinatorial ALU design techniques
48 byte cells
Adding Padding bits
TLL
TRAILER
CRC
SAR
2nd IP Packet 8 bytes Trailer Appended
UU CPI Total Length
0000 CRC
A complete Padded IP Packet
with valid CRC
consumes greater processing power
What is Aቤተ መጻሕፍቲ ባይዱM?
A communication protocol that
Utilizes connection-based cells that are guided using a pre-planned path between nodes;
What is IP?
A communication protocol that
Utilizes connectionless-based datagrams that are routed using hop-by-hop routing algorithms to transfer them;
module; Control Unit (CU) module
System Breakdown (2)
Figure 1
System Operation
Figure 2
A complete Padded IP Packet with valid CRC 1st IP Packet
Memory
Project introduction
Proknet = processor + network Capable of receiving incoming variablesized Internet Protocol (IP) packets, and outputting fixed-sized ATM cells Design is outlined, architecture is overviewed and final results are presented
CU_EOP switches high which means it’s time to output the Trailer.
1
0
CU_EOP is low.
Sequence 3
Trailer Module
1. When a byte of a packet is received from the TLL module, the control unit wries into the 8-byte FIFO memory
Project objectives
Main goal: “To provide an IP over ATM segmentation entity” Design goals:
Forum compliance; Efficient implementation; Digital design adherence; Speed of execution and Network processor functionality
Total length of cell is fixed at 53 bytes; Each cell traverses the dedicated route for the
entire length of the data transmission; Error control and reliability mechanisms are
Extractor
TLR 11
Pad Algorithm
Sequence 2
Outputs the Number of Pad bits Needed to make the packet divisible by 48.
TLL Module Functionality
Extract the total length field from the IP packet Perform preliminary setups for the downstream modules in the pipeline Calculate the number of padding bits needed and store that value in a register
CRC32 Algorithm
4 byte FIFO
A byte is written and another is read simultaneously.
CU_C_EOP switches high which means it’s time to output the 4 bytes of valid CRC.
4. Once all 4 bytes are placed on the pipeline, Done_Crc is sent to the CU
Initial IP Packet Structure
Figure 5
Post-trailer Packet Structure
Figure 6
In-memory Packet Structure
PROKNETAnIPATMpro cessor
Presentation Outline (1)
Introduction Objectives Self-imposed Q&A’s
IP ATM IP over ATM
System breakdown System operation
Presentation Outline (2)
System Breakdown (1)
Proknet is made up of the following
Total Length Logic (TLL) module; Arithmetic Logic Unit (ALU) module; Trailer module; Cyclic Redundancy Check (CRC) module; Segmentation and Reassembly (SAR)
48 byte cells
Sequence 1
TLL(Total Length Logic)
TL
Incoming Packets
(2/2)
4th
3rd 2nd 1st
byte byte byte byte
11
Counter 1
TL (1/2)
1
TRAILER Module
Extractor extracts the 8 byte Total Length from the packet and stores it into TLR register.