A63L73361中文资料
L7386A中文资料
18
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索诺泰克超声刀可切割的材料示例说明书
FB-0131-6LFB -3186-4L FB -0231-6L ---FB -3236-6L FB -3234FB -3136-6L4FB -3136-5H FB -3126-3L FB -3134FB -4136-1WSH-3510SF-3441SF-3400ⅡSF-30SF-0102SF-653 TechnologyWe own a patent for the blade holding system.Notations used in this leaflet :The ultrasonic cutter is a safe and clean processing machine that does not discharge cutting chips, polluted water, noise or smoke. The cutting blade performs expansion and contraction movements at an ultrafast speed of 20,000 times or over per second with the amplitude of up to 70 microns.As a result, it can cut the materials that are usually hard to cut easily and beautifully.The SONOFILE ultrasonic cutter, utilizing ultrasonic vibrations of a specialized processing machine manufacturer SONOTEC features excellent durability and smooth operability as well by employing our own blade holding system.We will test-cut free of charge if a work sample is provided.We will choose thecombination of the oscillator and the transducer, which are optimum for the intended material and the cuttingconditions.With our knowledge and experience accumulated for a long period, we will propose the ultrasonic cutters that bestfit the customer.Check the sharpness of our cutter through the test cutting.For use with automated equipment M echanism that the cord and the air tube rotate Detachable cord( For details, see Page 5. )For use with manual equipment Product conforming to CEFeaturesFeaturesHigh-power Ultrasonic Cutter featuring Maximum Output of 500 W◎ Cutter with a maximum power output of 500 W capable of handling materials requiring high-power cutting.◎ Tools including carbide blades and long blades can be used.◎ Mountable on automated machinery, industrial robots and plotters.◎ Various types of prepregs (boron, Kevlar, polyethylene fibers, etc.)◎ Rubber (vulcanized latex, non-vulcanized latex, sheetingmaterials, sealing materials and tubes) and leather (natural and artificial)◎ Thermoplastics (boards, sheeting materials, films, laminated materials, flooring materials)◎ Fabric materials, nonwoven fabrics and paper (specially-treated paper and coated paper)The oscillator with a maximum power output of 500 W enabled powerful cutting of difficult-to-cut and extra-tough work pieces. Abrasion resistant carbide blade with 1 mm thickness can be used. Exchanging signals for on/off, emergency stop, change of output level, and other features with automated machinery or industrial robots is, of course, possible.◎ Cutter with a maximum power output of 500 Wcapable of handling materials requiring high-power cutting.◎ Tools including carbide blades and long blades can beused.◎ Mountable on automated machinery, industrial robotsand plotters.Features◎ Powerful ultrasonic cutter with a maximum poweroutput of 300 W.◎ Mountable on automated machinery, industrial robotsand plotters.FeaturesSH -3510SF -3441Standard Model for Use with Automated MachineryThis ultrasonic oscillator is capable of exchanging signals with the main units of automated machinery, industrial robots, plotters, etc., for operations, such as turning on/off, emergency stop and switching the output level.Frequency adjustment Automatic tracking type Maximum output 500 WOutput adjustment Step-less continuously-variable type Power requirement Single phase 200 VAC, 50/60 Hz Power consumption 1000VAOuter dimensions300 (W) x 400 (D) x 200 (H) (mm)Weight 10.2kgFunctionDetection of error causeExternal deviceconnection functionOscillation ON/OFF, Adjustment of ultrasonic output, Warning of error stop, Recovery from errorFrequency adjustmentAutomatic tracking type Maximum output 300 WOutput adjustment Step-less continuously-variable type Power requirement Single phase 200 VAC, 50/60 Hz Power consumption 500 VAOuter dimensions 232 (W) x 340 (D) x 170 (H) (mm)Weight6.5 kgExternal deviceconnection functionOscillation ON/OFF, Adjustment of ultrasonic output, Warning of error stopSpecificationsSpecificationsfor 3510for SH -3510SF -3441-8701SF -3110-8500RRThis is a large amplitude type where theblade vibration amplitude is made larger than conventional models. With a 42 mm diameter cylindrical shape, the model is easy to be mounted on automated machinery, industrial robots and plotters. It is best suited forcutting and punching processing of 3D parts by mounting on industrial robots, in addition to processing of sheets and punching.The transducer generates powerful and stable vibrations even for cutting that requires high power, and the profile is designed to endure long-term use.The main body of the transducer is a cylindrical duralumin case that is easy for mounting on automated machinery. The blade width can be selected according to applications, which enables to design the blade that fits the profile of the article to be machined. Particularly, the transducer is best fit to up-and-down push cutting (guillotine system) and punching.The transducer features compact size, but powerful performance thanks to the high frequency drive, thereby ensuring sharp cutting. The user-friendly design of shape enables to fully utilize the robot’s operation area. A forced air-cooling system andextended continuous use have been realized by featuring the air inlet.-81108541RRThe transducer is suitable for gate cutting of molded articles containing glass or carbon fibers, which are hard to cut or machine in the past.＊The total length varies depending on the tool on which the transducer is mounted.＊We can make varioustypes of custom-order punching tools.Punching SampleFrequency24 kHz Cord length Up to 10 mHousing material SUS303 / Resin (Duracon)Outer dimensions φ12 / φ23 / φ55 x 221L (mm)Weight 1,160 g Blade thickness1.0 mmFrequency20 kHz Cord length Up to 10 m Housing material SUS303Outer dimensions φ42 / φ55 x 269L (mm)Weight 1,600 g (excluding the cord)Blade thicknessThe thickness depends on the specifications.Frequency20 kHz Cord length Up to 10 m Housing material Aluminum alloyOuter dimensions φ16 / φ46 x 168.5 L (mm)Weight 600 g (excluding the cord)Blade thicknessThe thickness depends on the specifications.FB -4221-9FB -0231-6L FB -0131-6LStandard ToolsOptional ToolStandard ToolsFB -3136-6L4FB -3296-1SpecificationsSpecificationsSpecificationsFrequency22 kHz Cord length Up to 10 m Housing material SUS 303Outer dimensions Hexagonal 11 / φ42 x 175L (mm)Weight650 gBlade thicknessThe thickness depends on the specifications of holder (0.4 to 1.0 mm)SpecificationsStandard ToolsFB -3136-5HFrequency40 kHz Cord length Up to 10 m Housing material SUS 303Outer dimensionsφ10 / φ26 / φ42 x 175 L (mm)Weight 650 g Blade thickness0.6 mmSpecifications220.81106743.8φ55φ23( Unit : mm )( Unit : mm )1751162237φ42( Unit : mm )( Unit : mm )( Unit : mm )φ12Angle type49271758822382710φ26φ4211094269φ55φ42137.5168.531306FB-3234FB-3294-2◎ Stable vibrations with a maximum amplitude of 30microns ensure remarkable cutting performance.◎ Our unique technologies suppress the heat generationof transducers, thus enabling extended continuoususe.◎ Adoption of the exclusive square-head screws and thescrewdriver ensures easy and robust mounting of tools.Features◎ An ultrasonic cutter featuring the size convenient forcarrying around.◎ The transducer is provided with a hand switch and theactivation of operation is notified with illuminationand sound◎ The cutter can also be used as a versatile machine forcutting various materials.FeaturesThis is a manual type ultrasonic cutter, which daringly pursued niceuser-friendliness. It is provided with a portable handle and storagerack for use at various jobsites. It is best fitted for a wide range ofapplications including carbon prepregs, resins, rubber, and fabrics. Forsafety measures, the activation of ultrasonic vibration is reported withillumination and sound. The product complies with the CE Standard.This is a high-frequency cutter featuring the 40 kHz (40,000 vibrationsper second) vibration frequency of tool with the amplitude of 30 microns.It maximizes the effect of ultrasonic high-speed micro vibrations. A widerange of materials, including newly developed composite materials,rubber and leather, can be cut at will with low processing pressure, sharpcutting surface and little cutting chips. The power control circuit speciallydeveloped by us and the cooling air inlet suppress the heat generation oftransducer even for large amplitude, thus enabling extended continuoususe. (For a long-time operation without air cooling, contact us.)◎ Rubber (vulcanized latex, non-vulcanized latex, sheetingmaterials, sealing materials and tubes) and leather(natural and artificial)◎ Thermoplastics (boards, sheeting materials, films,laminated materials, flooring materials)◎ Fabric materials, nonwoven fabrics, and paper (specially-treated paper and coated paper)Specifications: Oscillator653TransducerFrequency40KHzCord length Up to 10 mHousing material SUS 303Outer dimensionsφ10/φ30×139.5L（mm）Weight300 g (excluding the cord)Blade thicknessThe thickness depends on the specifications ofthe holder. ( 0.4 mm / 0.5 mm / 0.6 mm )Frequency22 kHzCord length 3 mHousing material Resin (Duracon)Outer dimensions Hexagonal 11 / φ40 x 155L (mm)Weight350 gBlade thickness0.4 mmFrequency adjustment Automatic tracking typeMaximum output /Output adjustment100 W / Step-less continuously-variable typePower requirement Single phase 200 VAC, 50/60 HzPower consumption300 VAOuter dimensions230 (W) x 232 (D) x 144 (H) (mm)Weight 4.6 kgExternal deviceconnection functionOscillation ON/OFF, Detectionof high load, Warning of errorstop, Recovery from errorSpecifications: OscillatorFrequency adjustment Automatic tracking typeMaximum output /Output adjustment100 W / Step-less continuously-variable typePower requirement Single phase 200 VAC, 50/60 HzPower consumption300 VAOuter dimensions230 (W) x 232 (D) x 144 (H) (mm)(194 (H) including the handle)Weight 4.8 kg ( 5.7 kg including the storage rack)External deviceconnection functionOscillation from transducer ON/OFFWhile oscillation is activated, the lampon the transducer illuminates andsound is generated from the oscillator.Specifications: Oscillator◎ Carbon prepregs with thickness up to t10◎ Thermoplastics◎ Rubber◎FabricsApplicableMaterialsApplicableMaterials＊Manufacturing of the 200 V type is also possible.-TransducerSF-653Oscillator SF-0102OscillatorFB-3136-5HStandard ToolsStandard Tool139.511524.513615537φ40φ30φ10Hand Switch( Unit : mm )This is a highly versatile hand tool compatible with small and large blades depending on the applications.This is a manual-operation type transducer that allows the use of large tools, such as of the chisel typeand knife type to assist high power manual operations, including stripping exterior building walls and rustremoval.This is a high-frequency cutter featuring the 40 kHz (40,000 vibrationsper second) vibration frequency of tools with an amplitude of 30 microns.It maximizes the effect of ultrasonic high-speed micro vibrations. A widerange of materials, including newly developed composite materials,rubber, and leather, can be cut at will with low processing pressure,sharp cutting surfaces, and little cutting chips.This is a high-power ultrasonic cutter featuring the ultrasonic poweroutput of 220 W. The tool’s ultrasonic vibrations at a frequency of 22 kHz(22,000 vibrations per second) drastically reduce the cutting resistance.Varieties of materials can be cut even more rapidly and cleanly with alower processing pressure. A function to enable constant monitoring ofloads during cutting was added anew, thereby ensuring added safety anduser friendliness.FB-3136-6L4FB-3134FB-3294-2◎ The output adjustment can be done in step-lessand continuous manner from the minimum to themaximum levels.◎ The constant amplitude circuit always keeps vibrationsat stable amplitude.◎ The overload protection circuit is featured.◎ Force air cooling is possible by installing the air inlet(SF-3140).Features◎ Stable vibrations with a maximum amplitude of 30microns ensure remarkable cutting performance.◎ Light in weight and easy-to-hold transducer (150 g)where much greater importance is attached to itsoperating performance.◎ Adoption of the exclusive square-head screws andthe screwdriver ensures easy and robust mounting oftools.FeaturesHigh-output cutter for manual operation: Assisting manual operations with clear cutting The effect of ultrasonic high-speed micro vibrations realized cutting of materials at will.Frequency adjustment Automatic tracking typeMaximum output220 WOutput adjustment Step-less continuously-variable typePower requirement Single phase 100 VAC, 50/60 HzPower consumption500 VAOuter dimensions142 (W) x 294 (D) x 210 (H) (mm)(260 (H) including the handle)Weight 4.5kgSpecifications: OscillatorSpecifications: TransducerFrequency40 kHzCord length 4 mHousing material Resin (Duracon)Outer dimensionsφ10 / φ18.5 / φ28 x 150.6 L (mm)Weight150 g (excluding the cord)Blade thickness Dedicated for use with a 0.4 mm bladeHP-660TransducerSF-7400TransducerSF-3140SF-3400ⅡOscillatorSF-30OscillatorFrequency adjustment Automatic tracking typeMaximum output / Outputadjustment45 W / Two-step continuously-variable typePower requirement Single phase 100 VAC, 50/60 HzPower consumption100 VAOuter dimensions Approx. 170 (W) x 180 (D) x 78 (H) (mm)Weight Approx. 1.5 kgSpecifications: Oscillator Welding Tool ScraperSpecifications: Transducer SF-3140Specifications: Transducer SF-7400Frequency22 kHzCord length(Up to 10 m)Housing material Resin (Duracon)Outer dimensionsφ16 / φ40 x 154L (mm)Weight340 g (excluding the cord)Hand switch Pushbutton typeFrequency22 kHzCord length Up to 10 mHousing material Aluminum alloyOuter dimensions Hexagonal 12 / φ27/ φ40 x 260L (mm)Weight600 g (excluding the cord)Blade thickness0.6 mmStandard ToolsOptional ToolStandard Tools◎ Plastics (boards, sheets, films, laminated materials)◎ Various types of prepregs (single sheet cutting,overlapped cutting)◎ Leather (natural and artificial)◎ Rubber (vulcanized latex, non-vulcanized latex)◎ Fabric materials, nonwoven fabrics◎ Paper and cardboards◎ Rubber (vulcanized latex, non-vulcanized latex,sheeting materials, sealing materials and tubes)and leather (natural and artificial)◎ Thermoplastics (boards, sheeting materials, films,laminated materials, flooring materials)◎ Fabric materials, nonwoven fabrics and paper(specially treated paper and coated paper)ApplicableMaterials対象材料ApplicableMaterials1051053515φ27φ40φ1226086.352.811.5φ18.5φ28150.6Hand Switchwith Lamp14212154φ40φ16( Unit : mm )( Unit : mm )( Unit : mm )。
L6997资料
PIN CONNECTION (Top View)
NOSKIP GNDSENSE INT VSENSE VCC GND VREF VFB OSC SS
1 2 3 4 5 6 7 8 9 10
TSSOP20
20 19 18 17 16 15 14 13 12 11
BOOT HGATE PHASE VDR LGATE PGND PGOOD OVP SHDN ILIM
SHUTDOWN SECTION SHDN Device On Device Off ISHVDR ISHVCC Drivers shutdown current Devices shutdown current 1.2
SOFT START SECTION ISS Soft Start current Active Soft start and voltage CURRENT LIMIT AND ZERO CURRENT COMPARATOR ILIM input bias current Zero Crossing Comparator offset Phase-gnd DKILIM Current limit factor RILIM = 2KΩ to 200KΩ 4.6 -2 1.6 1.8 5 5.4 2 2 VSS = 0.4V 4 300 400 6 500
ELECTRICAL CHARACTERISTICS (VCC = VDR = 3.3V; Tamb = 0°C to 85°C unless otherwise specified)
Symbol SUPPLY SECTION Vin VCC, VDR VCC Turn-onvoltage Turn-off voltage Hysteresis IqVDR IqVcc Quiescent Current Drivers Device Quiescent current VFB > VREF VFB > VREF Input voltage range Vout=Vref Fsw=110Khz Iout=1A 1 3 2.86 2.75 90 7 400 20 600 28 5.5 2.97 2.9 V V V V mV µA µA V 0.6 SHDN to GND SHDN to GND 1 5 15 V µA µA µA mV µA mV µA Parameter Test Condition Min. Typ. Max. Unit
FLZ3V6A中文资料
FLZ2V2 - FLZ39V Zener DiodesMarch 2006FLZ2V2 - FLZ39VZener DiodesAbsolute Maximum Ratings T a= 25°C unless otherwise noted* These ratings are limiting values above which the serviceability of the diode may be impaired.Thermal Characteristics* Device mounted on FR-4 PCB with 3’’ × 4.5” X 0.06 with only signal traceElectrical Characteritics Tamb = 25°C unless otherwise specifiedPackage Marking and Ordering InformationSymbolParameterValueUnitsP D Power Dissipation500mW T STG Storage Temperature Range -65 to +175°C T J Maximum Junction Temperature 175°C I ZMMaximum Regulator CurrentP D /V ZmASymbolParameterValueUnitR θJAThermal Resistance, Junction to Ambient300°C/WSymbolParameter/ Test conditionMin.Typ.Max.UnitV FForward Voltage / I F =200mA----1.2VDevice MarkingDevicePackageReel SizeTape WidthQuantityColor Band Marking Per ToleranceRefer to Product table listSOD-807”8mm2,500SOD-80 Glass caseColor Band Denotes CathodeColor Band MarkingTolerance 1st Band 2nd Band A Blue Red B Blue Green C Blue Black D Blue GrayFLZ3V0B 3.02 3.12 3.2135204501351 FLZ3V3FLZ3V3A 3.17 3.27 3.3635204501141 FLZ3V3B 3.33 3.43 3.5235204501141 FLZ3V6FLZ3V6A 3.48 3.57 3.6648208501 2.81 FLZ3V6B 3.64 3.73 3.8148208501 2.81 FLZ3V9FLZ3V9A 3.78 3.88 3.9740208501 1.41 FLZ3V9B 3.93 4.03 4.1240208501 1.41 FLZ4V3FLZ4V3A 4.07 4.15 4.23322085010.471 FLZ4V3B 4.22 4.30 4.38322085010.471FLZ4V3C 4.35 4.44 4.52322085010.471 FLZ4V7FLZ4V7A 4.48 4.56 4.64212077010.191 FLZ4V7B 4.60 4.68 4.75212077010.191FLZ4V7C 4.73 4.81 4.89212077010.191 FLZ5V1FLZ5V1A 4.86 4.94 5.021********.19 1.5 FLZ5V1B 4.99 5.08 5.16172068510.19 1.5FLZ5V1C 5.13 5.23 5.33172068510.19 1.5 FLZ5V6FLZ5V6A 5.31 5.41 5.5010.52042510.75 2.5 FLZ5V6B 5.48 5.58 5.6810.52042510.75 2.5FLZ5V6C 5.66 5.76 5.8610.52042510.75 2.5 FLZ6V2FLZ6V2A 5.83 5.94 6.048.5202551 3.33 FLZ6V2B 6.01 6.12 6.228.5202551 3.33FLZ6V2C 6.18 6.28 6.388.5202551 3.33 FLZ6V8FLZ6V8A 6.33 6.45 6.57 6.6201230.5 1.1 3.5 FLZ6V8B 6.54 6.66 6.77 6.6201230.5 1.1 3.5FLZ6V8C 6.72 6.83 6.93 6.6201230.5 1.1 3.5 FLZ7V5FLZ7V5A 6.907.047.17 6.620950.50.3 4.0 FLZ7V5B7.137.267.39 6.620950.50.3 4.0FLZ7V5C7.357.497.62 6.620950.50.3 4.0 FLZ8V2FLZ8V2A7.587.737.88 6.620950.50.35 FLZ8V2B7.847.998.13 6.620950.50.35FLZ8V2C8.098.248.39 6.620950.50.35 FLZ9V1FLZ9V1A8.348.518.68 6.620950.50.36 FLZ9V1B8.638.808.97 6.620950.50.36FLZ9V1C8.919.099.27 6.620950.50.36FLZ12VB11.5311.7111.899.510950.50.1339FLZ12VC11.8312.0512.279.510950.50.1339 FLZ13V FLZ13VA12.2112.4512.6811.410950.50.13310 FLZ13VB12.6212.8713.1211.410950.50.13310FLZ13VC13.0713.3315.3811.410950.50.13310 FLZ15V FLZ15VA13.5213.7914.0513.310950.50.13311 FLZ15VB13.9914.2614.5213.310950.50.13311FLZ15VC14.4514.7214.9913.310950.50.13311 FLZ16V FLZ16VA14.9015.1915.4715.2101320.50.13312 FLZ16VB15.3615.6515.9315.2101320.50.13312FLZ16VC15.8316.1416.4515.2101320.50.13312 FLZ18V FLZ18VA16.3816.7017.0219.4101230.50.13313 FLZ18VB16.9617.2917.6119.4101230.50.13313FLZ18VC17.5617.9018.2419.4101230.50.13313 FLZ20V FLZ20VA18.1718.5218.8623.5101700.50.13315 FLZ20VB18.7819.1319.4823.5101700.50.13315FLZ20VC19.4219.8020.1823.5101700.50.13315FLZ20VD19.9320.3020.6723.5101700.50.13315 FLZ22V FLZ22VA20.2820.6621.0325.651700.50.13317 FLZ22VB20.8221.2121.5925.651700.50.13317FLZ22VC21.2921.6622.0225.651700.50.13317FLZ22VD21.7522.1522.5425.651700.50.13317 FLZ24V FLZ24VA22.3222.6923.0629.051700.50.13319 FLZ24VB22.8123.2423.6729.051700.50.13319FLZ24VC23.3523.7824.2129.051700.50.13319FLZ24VD23.8724.3124.7529.051700.50.13319 FLZ27V FLZ27VA24.3324.8925.453852100.50.133 21 FLZ27VB25.0425.6226.193852100.50.133 21FLZ27VC25.6926.2926.883852100.50.133 21FLZ27VD26.3626.9727.573852100.50.133 21 FLZ30V FLZ30VA27.0727.6928.314652100.50.133 23 FLZ30VB27.7728.4129.054652100.50.133 23FLZ30VC28.4429.0929.744652100.50.133 23FLZ30VD29.1029.7730.434652100.50.133 23FLZ36VD34.1934.8935.596352100.50.13327 FLZ39V FLZ39VA34.8635.5736.287252100.50.13330 FLZ39VB35.5336.2636.997252100.50.13330FLZ39VC36.1836.9237.667252100.50.13330FLZ39VD36.8237.5838.337252100.50.13330Note :1. Zener Voltage(V z)The zener voltage is measured with the device junction in the thermal equilibrium at the lead temperature (TL) at at 30°C ± 1°C and 3/8” lead length.Dimensions in MillimetersFAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR As used herein:2. A critical component is any component of a life support device Formative or In This datasheet contains the design specifications for This datasheet contains preliminary data, andThis datasheet contains final specifications. Fairchild This datasheet contains specifications on a product Across the board. Around the world.™DISCLAIMERPRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.LIFE SUPPORT POLICYSYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.PRODUCT STATUS DEFINITIONS Definition of TermsDatasheet Identification Product Status DefinitionAdvance InformationDesign product development. Specifications may change in any manner without notice.PreliminaryFirst Productionsupplementary data will be published at a later date.Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.No Identification Needed Full ProductionSemiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Productionthat has been discontinued by Fairchild semiconductor.The datasheet is printed for reference information only.PACMAN™POP™Power247™PowerEdge™SPM™Stealth™SuperFET™SuperSOT™-3The Power Franchise ®Programmable Active Droop™Rev. I18。
LS7366中文资料
GENERAL FEATURES:• Operating voltage: 3.0V to 5.5V (V DD - V SS )• 5V count frequency: 40MHz • 3V count frequency: 20MHz • 32-bit counter (CNTR).• 32-bit data register (DTR) and comparator.• 32-bit output register (OTR).• Two 8-bit mode registers (MDR0, MDR1) for programmable functional modes.• 8-bit instruction register (IR).• 8-bit status register (STR).• Latched Interrupt output on Carry or Borrow or Compare or Index.• Index driven counter load, output register load or counter reset.• Internal quadrature clock decoder and filter.• x1, x2 or x4 mode of quadrature counting.• Non-quadrature up/down counting.• Modulo-N, Non-recycle, Range-limit or Free-running modes of counting• 8-bit, 16-bit, 24-bit and 32-bit programmable configuration synchronous (SPI) serial interface• LS7366 (DIP); LS7366-S (SOIC); LS7366-TS (TSSOP) - See Figure 1-SPI/MICROWIRE (Serial Peripheral Interface):• Standard 4-wire connection: MOSI, MISO, SS/ and SCK. • Slave mode only.GENERAL DESCRIPTION:LS7366 is a 32-bit CMOS counter, with direct interface for quadra-ture clocks from incremental encoders. It also interfaces with the index signals from incremental encoders to perform variety of marker functions.For communications with microprocessors or microcontrollers, it provides a 4-wire SPI/MICROWIRE bus.The four standard bus I/Os are SS/, SCK, MISO and MOSI. The data transfer between a micro-controller and a slave LS7366 is synchronous. The synchronization is done by the SCK clocks supplied by the microcontroller.Each transmission is organized in blocks of 1 to 5 bytes of data. A transmission cycle is intitiated by a high to low transition of the SS/ input. The first byte received in a transmission cycle is always an instruction byte, whereas the second through the fifth bytes are always interpreted as data bytes. A transmission cycle is terminated with the low to high transition of the SS/ input. Received bytes are shifted in at the MOSI input, MSB first, with the leading edges (high transition) of the SCK clocks. Output data are shifted out on the MISO output, MSB first, with the trailing edges (low transition) of the SCK clocks.32-BIT QUADRATURE COUNTER WITH SERIAL INTERFACE1234567891011121314Vss V DD B A INDEX LFLAG/SS/SCK LS7366MISO MOSIf CKi f CKO PIN ASSIGNMENT TOP VIEWCNT_EN DFLAG/FIGURE 1LSI/CSILSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405LS7366U L®A3800January 2005Read and write commands cannot be combined.For example, when the device is shifting out read data on MISO output, it ignores the MOSI input,even though the SS/ input is active. SS/ must be terminated and reasserted before the device will accept a new command.The counter can be configured to operate as a 1, 2, 3 or 4-byte counter. When configured as a n-byte counter, the CNTR, DTR and OTR are all configured as n-byte registers, where n = 1, 2, 3 or 4. The content of the instruction/data identity is automatically adjusted to match the n-byte configu-ration. For example, if the counter is configured as a 2-byte counter, the instruction “write to DTR”expects 2 data bytes following the instruction byte.If the counter is configured as a 3-byte counter, the same instruction will expect 3 bytes of data follow-ing the instruction byte.Following the transfer of the appropriate number of bytes any further attempt of data transfer is ignored until a new instruction cycle is started by switching the SS/ input to high and then low.The counter can be programmed to operate in a number of different modes, with the operating characteristics being written into the two mode registers MDR0 and MDR1. Hardware I/Os are provided for event driven operations, such as processor interrupt and index related functions.I/O Pins:Following is a description of all the input/output pins.A (Pin 12)B (Pin 11)Inputs. A and B quadrature clock outputs from incremental encoders are directly applied to the A and B inputs of the LS7366. These clocks are ideally 90 degrees out-of-phase signals. A and B inputs are validated by on-chip digital filters and then decoded for up/down direction and count clocks.In non-quadrature mode, A serves as the count input andB serves as the direction input (B = high enables up count, B = low enables down count). In non-quadrature mode,the A and B inputs are not filtered internally, and are instantaneous in nature.INDEX (Pin 10)Input. The INDEX is a programmable input that canbe driven directly by the Index output of an incremental encoder. It can be programmed via the MDR to functionas one of the following:LCNTR (load CNTR with data from DTR), RCNTR(reset CNTR), or LOTR (load OTR with data from CNTR). Alternatively, the INDEX input can be masked out for"no functionality".In quadrature mode, the INDEX input is validated with the filter clock in order to synchronize with the quadrature inputs A and B. To be valid, the INDEX signal in quadrature mode must overlap the condition in which both A and B are low or both A and B are high. In non-quadrature mode, however, the INDEX input is instantaneous in nature and totally independent of A and B.f CK i (Pin 2), f CK0 (Pin 1)Input, Output. A crystal connected between these 2 pins generates the basic clock for filtering the A, B and INDEX inputs in the quadrature count mode. Instead of a crystal the f CKi input may also be driven by an external clock.The frequency at the f CKi input is either divided by 2(if MDR0 <B7> = 1) or divided by 1 (if MDR0 <B7> = 0)for the filter circuit. For proper filtering of the A, B andthe Index inputs the following condition must be satisfied:f f≥ 4f QAWhere f f is the internal filter clock frequency derived from the fCKi in accordance with the status of MDR0 <B7> and f QA is the maximum frequency of Clock A in quadrature mode.In non-quadrature count mode, f CKi is not used and should be tied off to any stable logic state.SS/ (Pin 4)A high to low transition at the SS/ (Slave Select) input selects the LS7366 for serial bi-directional data transfer;a low to high transition disables serial data transferand brings the MISO output to high impedance state.This allows for the accommodation of multiple slave units on the serial I/O.CNT_EN (Pin 12)Input. Counting is enabled when CNT_EN input is high; counting is disabled when this input is low.There is an internal pull-up resistor on this input.LFLAG/ (Pin 8), DFLAG/ (Pin 9)Outputs. LFLAG/ and DFLAG/ are programmable outputs to flag the occurences of Carry (counter overflow), Borrow (counter underflow), Compare (CNTR = DTR) and INDEX. The LFLAG/ is an open drain latched output. In contrast, the DFLAG/ is a push-pull instantaneous output. The LFLAG/ can be wired in multi-slave configuration, forming a single processor interrupt line. When active LFLAG/ switches to logic 0 and can be restored to the high impedence state only by clearing the status register, STR. In contrast, the DFLAG/ dynamically switches low with occurences of Carry, Borrow, Compare and INDEX conditions. The configuration of LFLAG/ and DFLAG/ are made through the control register MDR1. In free-running count mode LFLAG/ and DFLAG/ output the same status information in latched and dynamic form, respectively. In single-cycle mode the DFLAG/ outputs CY and BW signals independent of the MDR1 configura-tion. In range-limit and modulo-n modes, DFLAG/ outputs CMP signal in count-up direction (at CNTR = DTR) and BW signal when CNTR underflows independent of the MDR1 configuration. In effect, DFLAG/ generates mode-relevant marker signals in all modes, excepting the free-running count mode wherein MDR1 configures the output signal selection.MOSI (RXD) (Pin 7)Input. Serial output data from the host processor is shifted into the LS7366 at this input.MISO (TXD) (Pin 6)Output. Serial output data from the LS7366 is shifted out on the MISO (Master In Slave Out) pin. The MISO output goes into high impedance state when SS/ input is at logic high, providing multiple slave-unit serial outputs to be wire-ORed.SCK (Pin 5)Input. The SCK input serves as the shift clock input for transmit-ting data in and out of LS7366 on the MOSI and the MISO pins, respectively. Since the LS7366 can operate only in the slave mode, the SCK signal is provided by the host processor as a means for synchronizing the serial transmission between itself and the slave LS7366.REGISTERS:The following is a list of LS7366 internal registers:Upon power-up the registers DTR, CNTR, STR, MDR0 and MDR1 are reset to zero.DTR. The DTR is a software configurable 8, 16, 24 or 32-bit input data register which can be written into directly from MOSI, the serial input. The DTR data can be transferred into the 32-bit counter (CNTR) under program control or by hardware index signal. The DTR can be cleared to zero by software control.In certain count modes, such as modulo-n and range-limit,DTR holds the data for "n" and the count range, respectively.In compare operations, whereby compare flag is set, the DTR is compared with the CNTR.STR. The STR is an 8-bit status register which stores count related status information.CY BW CMP IDX CEN PLS U/D S 7 6 5 4 3 2 1 0CY: Carry (CNTR overflow) latchBW: Borrow (CNTR underflow) latch CMP: Compare (CNTR = DTR) latch IDX: Index latchCEN: Count enable status: 0: counting disabled, 1: counting enabled7366-012405-3IR . The IR is an 8-bit register that fetches instruction bytes from the received data stream and executes them to perform such functions as setting up the operating mode for the chip (load the MDR) and data transfer among the various registers.B7 B6 B5 B4 B3 B2 B1 B0B2 B1 B0 = XXX (Don’t care)B5 B4 B3 = 000: Select none= 001: Select MDR0 = 010: Select MDR1= 011: Select DTR = 100: Select CNTR = 101: Select OTR = 110: Select STR = 111: Select noneB7 B6 = 00: CLR register= 01: RD register = 10: WR register = 11: LOAD register The actions of the four functions, CLR, RD, WR and LOAD are elaborated in Table 1.TABLE 1Number of Bytes OP Code Register OperationMDR0Clear MDR0 to zero MRD1Clear MDR1 to zero1 CLR DTR NoneCNTR Clear CNTR to zero OTR None STR Clear STR to zero MDR0Output MDR0 serially on TXD (MISO)MDR1Output MDR1 serially on TXD (MISO)2 to 5 RD DTR NoneCNTR Transfer CNTR to OTR, then output OTR seriallyon TXD (MISO)OTR Output OTR serially on TXD (MISO)STR Output STR serially on TXD (MISO)MDR0Write serial data at RXD (MOSI) into MDR0MDR1Write serial data at RXD (MOSI) into MDR12 to 5 WR DTR Write serial data at RXD (MOSI) into DTRCNTR None OTR None STR None MDR0None MDR1None1 LOAD DTR NoneCNTR Transfer DTR to CNTR in “parallel”OTR Transfer CNTR to OTR in “parallel”CNTR. The CNTR is a software configurable 8, 16, 24 or 32-bit up/down counter which counts the up/down pulses resulting from the quadrature clocks applied at the A and B inputs, or alternatively, in non-quadrature mode, pulses applied at the A input. By means of IR intructions the CNTR can be cleared, loaded from the DTR or in turn, can be transferred into the OTR. The “clear CNTR”and the “load CNTR” commands in the ”range-limit” mode, however have limitations. In this mode when the CNTR is frozen in up count direction at CNTR = DTR, a “clear CNTR” command will only function if the count direction is reversed from up to down. Similarly, in the down direction at CNTR = 0, a “load CNTR” command will only function if the direction is reversed from down to up.OTR. The OTR is a software configuration 8, 16, 24 or 32-bit register which can be read back on the MISO output. Since instantaneous CNTR value is often needed to be read while the CNTR continues to count, the OTR serves as a convenient dump site for instantaneous CNTR data which can then be read without interfering with the counting process.PLS: Power loss indicator latch; set upon power upU/D: Count direction indicator: 0: count down, 1: count up S: Sign bit. 1: negative, 2: positiveA “CLR STR” command to IR resets all status bits except CEN and U/D. In quadrature mode, if the quadrature clocks have been halted, the status bits CY, BW and CMP are not affected by a “CLR STR” command under the following conditions: CY: If CNTR = FFFFFFFF with status bit U/D = 1 BW: If CNTR = 0 with status bit U/D = 0 CMP: If CNTR = DTRIn non-quadrature mode the same rules apply if input A is held at logic low.7366-112204-4ABSOLUTE MAXIMUM RATINGS: (All voltages referenced to Vss)Parameter Symbol Values Unit DC Supply Voltage V DD +7.0V Voltage V IN Vss - 0.3 to V DD + 0.3 VOperating Temperature T A -25 to +85o C Storage Temperature T STG -65 to +150o C MDR1. The MDR1 (Mode Register 1) is an 8-bit read/write register which is appended to MDR0 for additional modes. Upon power-up MDR1 is cleared to zero.B7 B6 B5 B4 B3 B2 B1 B0B1 B0 = 00: 4-byte counter mode = 01: 3-byte counter mode = 10: 2-byte counter mode. = 11: 1-byte counter mode B2 = 0: Enable counting = 1: Disable counting B3 = : not used B4 = 0: NOP= 1: FLAG on IDX (B4 of STR) B5 = 0: NOP= 1: FLAG on CMP (B5 of STR) B6 = 0: NOP= 1: FLAG on BW (B6 of STR) B7 = 0: NOP= 1: FLAG on CY (B7 of STR)MDR0. The MDR0 (Mode Register 0) is an 8-bit read/write register that sets up the operating mode for the LS7366. The MDR0 is written into by executing the "write-to-MDR0" instruction via the instruction register. Upon power up MDR0 is cleared to zero. The following is a breakdown of the MDR bits:B7 B6 B5 B4 B3 B2 B1 B0B1 B0 = 00: non-quadrature count mode. (A = clock, B = direction). = 01: x1 quadrature count mode (one count per quadrature cycle). = 10: x2 quadrature count mode (two counts per quadrature cycle). = 11: x4 quadrature count mode (four counts per quadrature cycle).B3 B2 = 00: free-running count mode.= 01: single-cycle count mode (counter disabled with carry or borrow, re-enabled with reset or load). = 10: range-limit count mode (up and down count-ranges are limited between DTR and zero, respectively; counting freezes at these limits but resumes when direction reverses). = 11: modulo-n count mode (input count clock frequency is divided by a factor of (n+1), where n = DTR, in both up and down directions).B5 B4 = 00: disable index.= 01: configure index as the "load CNTR" input (transfers DTR to CNTR). = 10: configure index as the "reset CNTR" input (clears CNTR to 0). = 11: configure index as the "load OTR" input (transfers CNTR to OTR). B6 = 0: Negative index input = 1: Positive index inputB7 = 0: Filter clock division factor = 1 = 1: Filter clock division factor = 2NOTE: Applicable to both LFLAG/ and DFLAG/DC Electrical Characteristics. (T A = -25˚C to +85°C)Parameter Symbol Min. TYP Max. Unit RemarksSupply Voltage V DD 3.0- 5.5V-Supply Current I DD300400450µA V DD = 3.0VI DD700800950µA V DD = 5.0VInput Voltagesf CK i, Logic high V CH- 2.1 2.3V V DD = 3.0VV CH- 3.5 3.7V V DD = 5.0Vf CKi, Logic Low V CL0.70.9-V V DD = 3.0VV CL 1.3 1.5-V V DD = 5.0VAll other inputs, Logic High V AH- 1.9 2.1V V DD = 3.0VV AH- 3.2 3.5V V DD = 5.0VAll other inputs, Logic Low V AL0.50.7-V V DD = 3.0VV AL 1.0 1.2-V V DD = 5.0VInput Currents:CNT_EN Low I IEL- 3.0 5.0µA V AL = 0.7V, V DD = 3.0VI IEL-10.015.0µA V AL = 1.2V, V DD = 5.0V CNT_EN High I IEH- 1.0 3.0µA V AH = 1.9V, V DD = 3.0VI IEH- 4.0 6.0µA V AH = 3.2V, V DD = 5.0V All other inputs, High or Low--00µA-Output Currents:FLAG Sink I OFL-1.3-2.0-mA V OUT = 0.5V, V DD = 3.0VI OFL-3.2-4.0-mA V OUT = 0.5V, V DD = 5.0V FLAG Source- 0 0-mA Open Drain Outputf CKO Sink I OCL-1.3-2.0-mA V OUT = 0.5V, V DD = 3.0VI OCL-3.2-4.0-mA V OUT = 0.5V, V DD = 5.0V f CKO Source I OCH 1.3 2.0-mA V OUT = 2.5V, V DD = 3.0VI OCH 3.2 4.0-mA V OUT = 4.5V, V DD = 5.0V TXD/MISO:Sink I OML-1.5-2.4-mA V OUT = 0.5V, V DD = 3.0VI OML-3.8-4.8-mA V OUT = 0.5V, V DD = 5.0V Source I OMH 1.5 2.4-mA V OUT = 0.5V, V DD = 3.0VI OMH 3.8 4.8-mA V OUT = 0.5V, V DD = 5.0V Transient Characteristics. (T A = -25˚C to +85˚C, V DD = 5V ± 10%)Parameter Symbol Min. Value Max.Value Unit Remarks(See Fig. 2 & 3)SCK High Pulse Width t CH100-ns-SCK Low Pulse Width t CL100-ns-SS/ Set Up Time t CSL100-ns-SS/ Hold Time t CSH100-ns-Quadrature Mode(See Fig. 4, 6 & 7)f CKI High Pulse Width t112-ns-f CKI Pulse Width t212-ns-f CKI Frequency f FCK-40MHz-Effective Filter Clock fF Period t325-ns t3 = t1+t2, MDR0 <7> = 0t350-ns t3 = 2(t1+t2), MDR0 <7> = 1 Effective Filter Clock f F frequency f F-40MHz f F = 1/ t3Quadrature Separation t426-ns t4 > t3Quadrature Clock Pulse Width t552-ns t5≥ 2t3Quadrature Clock frequency f QA, f QB-9.6MHz f QA = f QB < 1/4t3 Quadrature Clock to Count Delay t Q14t35t3--x1 / x2 / x4 Count Clock Pulse Width t Q212-ns t Q2 = (t3)/2Index Input Pulse Width ti d32-ns t id > t4Index Set Up Time ti s-5ns-Index Hold Time ti h-5ns-Quadrature clock to t fl 4.5t3 5.5t3ns-DFLAG/ or LFLAG/ delayDFLAG/ output width t fw26-ns t fw = t4Parameter Symbol Min. Value Max.Value Unit RemarksNon-Quadrature Mode(See Fig. 5 & 8)Clock A - High Pulse Width t612-ns-Clock A - Low Pulse Width t712-ns-Direction Input B Set-up Time t8S12-ns-Direction Input B Hold Time t8H10-ns-Clock Frequency (non-Mod-N)f A-40MHz f A = (1/(t6 + t7))Clock to DFLAG/ or t920-ns-LFLAG/ delayDFLAG/ output width t1012-ns t10 = t7Transient Characteristics. (T A = -25˚C to +85˚C, V DD = 3.3V ± 10%)Parameter Symbol Min. Value Max.Value Unit Remarks(See Fig. 2 & 3)SCK High Pulse Width t CH120-ns-SCK Low Pulse Width t CL120-ns-SS/ Set Up Time t CSL120-ns-SS/ Hold Time t CSH120-ns-Quadrature Mode(See Fig. 4, 6 & 7)f CKI High Pulse Width t124-ns-f CKI Pulse Width t224-ns-f CKI Frequency f FCK-20MHz-Effective Filter Clock fF Period t350-ns t3 = t1+t2, MDR0 <7> = 0t3100-ns t3 = 2(t1+t2), MDR0 <7> = 1 Effective Filter Clock f F frequency f F-20MHz f F = 1/t3Quadrature Separation t452-ns t4 > t3Quadrature Clock Pulse Width t5105-ns t5≥ 2t3Quadrature Clock frequency f QA, f QB- 4.5MHz f QA = f QB < 1/4t3 Quadrature Clock to Count Delay t Q14t35t3--x1/x2/x4 Count Clock Pulse Width t Q225-ns t Q2 = (t3)/2Index Input Pulse Width t id60-ns t id > t4Index Set Up Time t is-10ns-Index Hold Time t ih-10ns-Quadrature clock to t fl 4.5t3 5.5t3ns-DFLAG/ or LFLAG/ delayDFLAG/ output width t fw52-ns t fw = t4Non-Quadrature Mode(See Fig. 5 & 8)Clock A - High Pulse Width t624-ns-Clock A - Low Pulse Width t724-ns-Direction Input B Set-up Time t8S24-ns-Direction Input B Hold Time t8H24-ns-Clock Frequency (non-Mod-N)f A-40MHz f A = (1/(t6 + t7))Clock to DFLAG/or t940-ns-LFLAG/ delayDFLAG/ output width t1024-ns t10 = t7。
LOA676中文资料
LS A676, LA A676, LO A676, LY A676Hyper SIDELED ®Hyper-Bright LED2002-09-181Besondere Merkmale•Geh äusetyp: wei ßes SMT Geh äuse•Besonderheit des Bauteils: Abstrahlung parallel zur Platine, deshalb ideal zur Einkopplung in Lichtleiter•Wellenl änge: 633 nm (super-rot), 615nm (amber), 606 nm (orange), 587nm (gelb)•Abstrahlwinkel: Lambertscher Strahler (120°)•Technologie: InGaAlP•optischer Wirkungsgrad: 11 lm/W (gelb, orange, amber), 7 lm/W (super-rot)•Gruppierungsparameter: Lichtst ärke, Wellenl änge•Verarbeitungsmethode: f ür alle SMT-Best ücktechniken geeignet •L ötmethode: IR Reflow L öten und Wellenl öten (TTW)•Vorbehandlung: nach JEDEC Level 2•Gurtung: 12 mm Gurt mit 2000/Rolle, ø330mm Anwendungen•optischer Indikator•Einkopplung in Lichtleiter•Hinterleuchtung (LCD, Schalter, Tasten, Displays, Werbebeleuchtung, Allgemeinbeleuchtung)•Innenbeleuchtung im Automobilbereich (z.B. Instrumentenbeleuchtung, u.ä.)•Markierungsbeleuchtung (z.B. Stufen, Fluchtwege, u.ä.)•Signal- und SymbolleuchtenFeatures•package: white SMT package•feature of the device: radiation directionparallel to PCB, so an ideal LED for coupling in light guides•wavelength: 633 nm (super-red), 615 (amber), 606 nm (orange), 587 nm (yellow)•viewing angle: Lambertian Emitter (120°)•technology: InGaAlP•optical efficiency: 11 lm/W (yellow, orange, amber), 7 lm/W (super-red)•grouping parameter: luminous intensity, wavelength•assembly methods: suitable for all SMT assembly methods•soldering methods: IR reflow soldering and TTW soldering•preconditioning: acc. to JEDEC Level 2•taping: 12 mm tape with 2000/reel, ø330mmApplications•optical indicators•coupling into light guides•backlighting (LCD, switches, keys, displays, illuminated advertising, general lighting)•interior automotive lighting. (e.g. dashboard backlighting, etc.)•marker lights (e.g. steps, exit ways, etc.)•signal and symbol luminaire2002-09-182Anm.:-1 gesamter Farbbereich (siehe Seite 4)-24 gesamter Farbbereich, Lieferung in Einzelgruppen (siehe Seite 5)-26 gesamter Farbbereich, Lieferung in Einzelgruppen (siehe Seite 5)Die Standardlieferform von Serientypen beinhaltet eine untere bzw. eine obere Familiengruppe,die aus nur 3bzw.4 Halbgruppen besteht. Einzelne Halbgruppen sind nicht erhältlich.In einer Verpackungseinheit /Gurt ist immer nur eine Halbgruppe enthalten.Note:-1 Total color tolerance range (please see page 4)-24 Total color tolerance range, delivery in single groups (please see page 5)-26 Total color tolerance range, delivery in single groups (please see page 5)The standard shipping format for serial types includes a lower or upper family group of 3or 4individual groups. Individual half groups are not available.No packing unit /tape ever contains more than one luminous intensity half group.TypTypeEmissions-farbe Color of EmissionFarbe derLichtaustritts-fl ächeColor of the Light Emitting AreaLichtst ärkeLuminous Intensity I F = 20mA I V (mcd)LichtstromLuminous FluxI F = 20mA ΦV (mlm)BestellnummerOrdering CodeLS A676-N2P2-1LS A676-P2R1-1super-red colorless clear 35.5 ...71.056.0 ...140.0150 (typ.)280 (typ.)Q62703Q5074Q62703Q5075LA A676-Q1R1-1LA A676-R1S2-1amber colorless clear 71.0 ...140.0112.0 ...280.0310 (typ.)560 (typ.)Q62703Q4972Q62703Q4973LO A676-Q1R1-24LO A676-R1S2-24orange colorless clear 71.0 ...140.0112.0 ...280.0310 (typ.)560 (typ.)Q62702Q5032Q62702Q5033LY A676-P2Q2-26LY A676-Q2S1-26yellowcolorless clear56.0 ...112.090.0 ...224.0240 (typ.)440 (typ.)Q62703Q5111Q62703Q5112Grenzwerte Maximum RatingsBezeichnung Parameter SymbolSymbolWerteValuesEinheitUnitLS, LO, LA LYBetriebstemperatur Operating temperature range Top– 55 … + 100°CLagertemperaturStorage temperature range Tstg– 55 … + 100°CSperrschichttemperatur Junction temperature Tj+ 100°CDurchlassstrom Forward current IF30mAStoßstromSurge currentt≤ 10 µs, D = 0.005IFM10.2ASperrspannung1) Reverse voltage VR12VLeistungsaufnahme Power consumption Ptot80mWWärmewiderstand Thermal resistanceSperrschicht/UmgebungJunction/ambientSperrschicht/LötpadJunction/solder pointMontage auf PC-Board FR 4 (Padgröße ≥ 16mm2) mounted on PC board FR 4 (pad size ≥ 16 mm 2)Rth JARth JS530300K/WK/W1)für kurzzeitigen Betrieb geeignet / suitable for short term application2002-09-1832002-09-184Kennwerte (T A = 25 °C)Characteristics Bezeichnung ParameterSymbol SymbolWerte Values Einheit UnitLSLA LO LY Wellenl änge des emittierten Lichtes (typ.)Wavelength at peak emission I F = 20mAλpeak645622610591nmDominantwellenl änge 1)(typ.)Dominant wavelength 1)I F = 20mAλdom633± 6615± 6606–6/+3587–7/+8nmSpektrale Bandbreite bei 50 % I rel max (typ.)Spectral bandwidth at 50 % I rel max I F = 20mA∆λ16161615nmAbstrahlwinkel bei 50 % I V (Vollwinkel)(typ.)Viewing angle at 50 % I V 2ϕ120120120120Grad deg.Durchlassspannung 2)(typ.)Forward voltage 2)(max.)I F = 20mA V F V F 2.02.4 2.02.4 2.02.4 2.02.4V VSperrstrom(typ.)Reverse current (max.)V R = 12 VI R I R 0.01100.01100.01100.0110µA µATemperaturkoeffizient von λpeak (typ.)Temperature coefficient of λpeak I F = 20mA; –10°C ≤ T ≤ 100°C TC λpeak0.140.130.130.13nm/KTemperaturkoeffizient von λdom (typ.)Temperature coefficient of λdom I F = 20mA; –10°C ≤ T ≤ 100°C TC λdom0.050.060.070.10nm/KTemperaturkoeffizient von V F (typ.)Temperature coefficient of V F I F = 20mA; –10°C ≤ T ≤ 100°C TC V– 2.0– 1.8– 1.7– 2.5mV/KOptischer Wirkungsgrad (typ.)Optical efficiency I F = 20mAηopt7111111lm/W1)Wellenl ängen werden mit einer Stromeinpr ägedauer von 25ms und einer Genauigkeit von ±1nm ermittelt.Wavelengths are tested at a current pulse duration of 25ms and a tolerance of ±1nm.2)Spannungswerte werden mit einer Stromeinpr ägedauer von 1ms und einer Genauigkeit von ±0,1V ermittelt.Voltages are tested at a current pulse duration of 1ms and a tolerance of ±0.1V.2002-09-185Helligkeitswerte werden mit einer Stromeinpr ägedauer von 25ms und einer Genauigkeit von ±11% ermittelt.Luminous intensity is tested at a current pulse duration of 25ms and a tolerance of ±11%.1)Wellenl ängengruppen / Wavelength groupsGruppe Group yellow orange Einheit Unit min.max.min.max.2580583600603nm 3583586603606nm 4586589606609nm 5589592nm 6592595nmHelligkeits-GruppierungsschemaLuminous Intensity Groups LichtgruppeLuminous Intensity Group Lichtst ärkeLuminous Intensity I V (mcd)Lichtstrom Luminous Flux ΦV (mlm)N2P1P2Q1Q2R1R2S1S235.5 ...45.045.0 ...56.056.0 ...71.071.0 ...90.090.0 ...112.0112.0 ...140.0140.0 ...180.0180.0 ...224.0224.0 ...280.0120 (typ.)150 (typ.)190 (typ.)240 (typ.)300 (typ.)380 (typ.)480 (typ.)600 (typ.)760 (typ.)Gruppenbezeichnung auf Etikett Group Name on Label Beispiel: P2-3Example: P2-3LichtgruppeLuminous Intensity Group Halbgruppe Half Group Wellenl änge Wavelength P23Relative spektrale Emission I rel = f (λ), T A = 25 °C, I F = 20mA Relative Spectral EmissionV(λ) = spektrale AugenempfindlichkeitStandard eye response curveAbstrahlcharakteristik I rel = f (ϕ)2002-09-186Durchlassstrom I F = f (V F)Forward CurrentMaximal zulässiger Durchlassstrom I F = f (T) Max. Permissible Forward Current Relative Lichtstärke I V/I V(20mA) = f (I F) Relative Luminous IntensityV V(25 °C)ARelative Luminous Intensity2002-09-187Zulässige Impulsbelastbarkeit I F = f (t p) Permissible Pulse Handling Capability Duty cycle D = parameter, T A = 25 °CF p Permissible Pulse Handling Capability Duty cycle D = parameter, T A = 85 °CZulässige Impulsbelastbarkeit I F = f (t p) Permissible Pulse Handling Capability Duty cycle D = parameter, T A = 25 °CF p Permissible Pulse Handling Capability Duty cycle D = parameter, T A = 85 °C2002-09-188MaßzeichnungPackage OutlinesMaße werden wie folgt angegeben: mm (inch) / Dimensions are specified as follows: mm (inch). Kathodenkennung:abgeschrägte EckeCathode mark:bevelled edgeGewicht / Approx. weight:40 mg2002-09-189Lötbedingungen Vorbehandlung nach JEDEC Level 2 Soldering Conditions Preconditioning acc. to JEDEC Level 2 IR-Reflow Lötprofil(nach IPC 9501)IR Reflow Soldering Profile(acc. to IPC 9501)2002-09-1810Wellenlöten (TTW)(nach CECC 00802)TTW Soldering(acc. to CECC 00802)2002-09-1811Empfohlenes Lötpaddesign Wellenlöten (TTW)Recommended Solder Pad TTW SolderingMaße werden wie folgt angegeben: mm (inch) / Dimensions are specified as follows: mm (inch) 2002-09-1812Empfohlenes Lötpaddesign IR Reflow LötenRecommended Solder Pad IR Reflow SolderingMaße werden wie folgt angegeben: mm (inch) / Dimensions are specified as follows: mm (inch). Gurtung / Polarität und Lage Verpackungseinheit2000/Rolle, ø330 mm Method of Taping / Polarity and Orientation Packing unit2000/reel, ø330 mmMaße werden wie folgt angegeben: mm (inch) / Dimensions are specified as follows: mm (inch)2002-09-18132002-09-1814Published by OSRAM Opto Semiconductors GmbH Wernerwerkstrasse 2, D-93049 Regensburg © All Rights Reserved.Attention please!The information describes the type of component and shall not be considered as assured characteristics.All typical data and graphs are basing on representative samples, but don ’t represent the production range. If requested, e.g. because of technical improvements, these typ. data will be changed without any further notice.Terms of delivery and rights to change design reserved. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact our Sales Organization.If printed or downloaded, please find the latest version in the Internet.PackingPlease use the recycling operators known to you. We can also help you – get in touch with your nearest sales office.By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred.Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components 1 may only be used in life-support devices or systems 2 with the express written approval of OSRAM OS.1A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or the effectiveness of that device or system.2Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.Revision History:2002-09-18Date of changePrevious Version:2002-08-19Page Subjects (major changes since last revision)12recommended solder pad (TTW soldering)4value (wavelength amber/yellow 5wavelength groups2wavelength grouping for yellow and orange 14annotations2002-07-254value (TC λdom from 0.04 to 0.05nm/K)2002-07-2513recommended solder pad (IR reflow soldering)2002-08-013, 4value (reverse voltage from 3V to 12V)2002-09-18。
AU6366中文资料
AU6366USB2.0 Single LUNMultiple Flash Card Reader Controller Technical Reference ManualAU6366USB2.0 Single LUN Multiple Flash Card Reader ControllerC o p y r i g h tCopyright © 1997 - 2007. Alcor Micro, Corp. All Rights Reserved. No part of this data sheet may be reproduced, transmitted, transcribed, stored in a retrieval system or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise, without prior written permission from Alcor Micro, Corp.T r a d e m a r k A c k n o w l e d g e m e n t sThe company and product names mentioned in this document may be the trademarks or registered trademarks of their manufacturers.D i s c l a i m e rAlcor Micro, Corp. reserves the right to change this product without prior notice. Alcor Micro, Corp. makes no warranty for the use of its products and bears no responsibility for any error that appear in this document. Specifications are subject to change without prior notice.R e v i s i o n H i s t o r yDate Revision DescriptionJan 2006 1.00W Official ReleaseAug 2006 1.01W Update new address of Los Angeles OfficeNov 2006 1.02W Modify “1.2 Features”July 2007 1.03W Modify “5.6 Power Switch Feature”C o n t a c t I n f o r m a t i o n:Web site: /Taiwan China ShenZhen OfficeAlcor Micro, Corp. Rm.2407-08, Industrial Bank Building 4F, No 200 Kang Chien Rd., Nei Hu, No.4013, Shennan Road,Taipei, Taiwan, R.O.C. ShenZhen,China. 518026Phone: 886-2-8751-1984 Phone: (0755) 8366-9039Fax: 886-2-2659-7723 Fax: (0755) 8366-9101Santa Clara Office Los Angeles Office2901 Tasman Drive, Suite 206 9070 Rancho Park CourtSanta Clara, CA 95054 Rancho Cucamonga, CA 91730USA USA Phone: (408) 845-9300 Phone: (909) 483-9900Fax: (408) 845-9086 Fax: (909) 944-0464<Memo>Table of Contents1. Introduction (1)1.1 Description (1)1.2 Features (1)2. Application Block Diagram (2)3. Pin Assignment (3)4. System Architecture and Reference Design (6)4.1 AU6366 Block Diagram (6)5. Electrical Characteristics (7)5.1 Absolute Maximum Ratings (7)5.2 Recommended Operating Conditions (7)5.3 General DC Characteristics (7)5.4 DC Electrical Characteristics of 3.3V I/O Cells (8)5.5 USB Transceiver Characteristics (8)5.6 Power Switch Feature (12)6. Mechanical Information (13)7. Abbreviations (14)iList of FiguresFigure 2.1 Block Diagram (2)Figure 3.1 Pin Assignment Diagram (3)Figure 4.1 AU6366 Block Diagram (6)Figure 5.1 Built-in card power switch I-V curve (12)Figure 5.2 Card Detect Power-on Timing (12)Figure 6.1 Mechanical Information Diagram (13)List of TablesTable 3.1 Pin Descriptions (4)Table 5.1 Absolute Maximum Ratings (7)Table 5.2 Recommended Operating Conditions (7)Table 5.3 General DC Characteristics (7)Table 5.4 DC Electrical Characteristics of 3.3V I/O Cells (8)Table 5.5 Electrical characteristics (8)Table 5.6 Static characteristic：Digital pin (9)Table 5.7 Static characteristic：Analog I/O pins（DP/DM） (9)Table 5.8 Dynamic characteristic：Analog I/O pins（DP/DM） (10)ii1. Introduction1.1D e s c r i p t i o nThe AU6366 is a single chip integrated USB 2.0 multimedia card reader controller that enables PC/DVD/Printer to read/write various type of flash media cards. Flash media cards such as CF, SMC, XD, SD, MMC, Memory Stick are widely used in digital camera, cell phone, PDA and MP3 player to store digital photos and compressed music.Performance of AU6366 is maximized by implementing the latest and fastest card specification available form the industry.The AU6366 is designed in shared pin architecture to meet cost and space regulate for Notebook end reunite.1.2F e a t u r e sSupport USB V2.0 specification and USB Device Class Definition for Mass Storage, Bulk-Transport V1.0Support CF/MD/SD/MMC/MS/MS_Pro/MS_Duo/xD/SMC compatible flash cardSupport the latest flash card specification: CF 3.0 (16-bit IDE mode), SD1.1 (HS-SD), MMC4.0 (8-bit), MSPro parallel mode (4-bit), xD 1.2 Hardware DMA engine integrated for performance enhancementWork with default driver from Windows ME/2000/XP and Mac OS X; Windows 98/2000(SP1/SP2) and Mac OS 9 are supported by vendor driver fromAlcor.Ping-pong FIFO implementation for concurrent bus operationSupport multiple sectors transfer optimize performanceSupport slot-to-slot read/write operationSupport Dynamic Icon UtilitySupport LED for bus operating indicationPower switch integrated to reduce production BOM cost30MHz 8051 CPUBuilt in 3.3V to 2.5V regulatorRun at 12MHz crystalAvailable in 48-pin LQFP packageAU6366 USB 2.0 Single LUN Multiple Flash Card Reader Controller V1.03W 12. Application Block DiagramThe following application drawing demonstrates a typical card reader block diagram using AU6366. By connecting one card reader to a desktop or notebook PC through USB bus, the AU6366 becomes a bus-powered, high speed USB card reader, which can be used as a bridge for data transfer between Desktop PC and Notebook PC.Figure 2.1 Block DiagramSMC/SD/MMCAU6366AU6366 USB 2.0 Single LUN Multiple Flash Card Reader Controller V1.03W 2AU6366 USB 2.0 Single LUN Multiple Flash Card Reader Controller V1.03W33. Pin AssignmentThe AU6366 is delivered in 48pin LQFP form factor. Documented below is a figure shows signal names of each pin and a table in the following page describes each pin in more details.Figure 3.1 Pin Assignment DiagramCARDDATA15CFWTN CLEDCHIPRESETN GNDAVDDARPUAVDD DPDMAVSS RREFXDCDNCONTROLOUT5CONTROLOUT4CONTROLOUT3CONTROLOUT2CONTROLOUT1CONTROLOUT0VDDCARDDATA1CARDDATA2GNDCARDDATA0SDCDNVSSHCPWR_V33SMCDNCFCDNMSINSVDD25VPVSSPVDDXOVDDHXICARDDATA3CARDDATA4CARDDATA5CARDDATA6CARDDATA7CARDDATA8CARDDATA9CARDDATA10CARDDATA11CARDDATA12CARDDATA14CARDDATA13AU6366 USB 2.0 Single LUN Multiple Flash Card Reader Controller V1.03W4Table 3.1 Pin DescriptionsPin #Pin NameI/ODescription1 CARDDATA15 I/O CF Data15/xD Data72 CFWTN I CF WAITN3 CLED O Card Operating LED4 CHIPRESETNI Chip Reset, Pull up with RC 5 GNDA PLL Ground 6 VDDA I PLL VDD 2.5V7 RPU I Connected with an 1.5k pull up resistor to 3.3 VDD 8 AVDD I Analog Power 3.3V 9 DP I/O DP 10 DM I/O DM11 AVSS Analog Ground12 RREF I Connected an 1k resistor to GND for impedance match13 PVDD I OSC Power 3.3V 14 XI I 12 MHz crystal input. 15 XO O 12 MHz crystal output. 16 PVSS OSC Ground 17 VDD25V O Core Power 2.5V 18 VDDH I 3.3V for IO pad 19 CPWR_V33 O Card Power 3.3V 20 VSSH Power Ground 21 MSINS I MS INS22 SMCDN I SMC Card Detect 23 CFCDN I CF Card Detect 24 SDCDN I SD Card Detect 25 XDCDN I xD Card Detect26 CONTROLOUT5 O CFRESETN and SMWRN/XDWRN 27 CONTROLOUT4 O CFWRN and SMRDN/XDRDN 28 CONTROLOUT3 O CFRDN and XDCEN/SMCEN 29CONTROLOUT2OCFAD2 and SMALE/XDALEAU6366 USB 2.0 Single LUN Multiple Flash Card Reader Controller V1.03W5Pin #Pin NameI/ODescription30 CONTROLOUT1 O CFAD1, MSCLK and SMCLE/XDCLE 31 CONTROLOUT0O CFAD0, SDCLK and MSBS 32 VDD I Core power 2.5V 33 GND Core Ground34 CARDDATA0 I/O CFDATA0, MSDATA0,and SDCMD 35 CARDDATA1 I/O CFDATA1,MSDATA1,XDWPN,and SMWPN 36 CARDDATA2 I/O CFDATA2,MSDATA2,and SDWP37 CARDDATA3 I/O CFDATA3,MSDATA3,SMRBN,and XDRBN 38 CARDDATA4 I/O CFDATA4 and SDDATA0 39 CARDDATA5 I/O CFDATA5 and SDDATA1 40 CARDDATA6 I/O CFDATA6 and SDDATA2 41 CARDDATA7 I/O CFDATA7 and SDDATA342 CARDDATA8 I/O CFDATA8,XDDATA0, and SDDATA4 43 CARDDATA9 I/O CFDATA9,XDDATA1, and SDDATA5 44 CARDDATA10 I/O CFDATA10,XDDATA2, and SDDATA6 45 CARDDATA11 I/O CFDATA11,XDDATA3, and SDDATA7 46 CARDDATA12 I/O CFDATA12 and XDDATA4 47 CARDDATA13 I/O CFDADA13 and XDDATA5 48CARDDATA14I/OCFDATA14 and XDDATA64. System Architecture and Reference Design4.1 A U 6366 B l o c k D i a g r a mFigure 4.1 AU6366 Block DiagramCF MD SMC SD MMC MS xDUSB Upstream PortAU6366 USB 2.0 Single LUN Multiple Flash Card Reader Controller V1.03W65. Electrical Characteristics5.1A b s o l u t e M a x i m u m R a t i n g sTable 5.1 Absolute Maximum RatingsSYMBOL PARAMETER RATING UNITS V DDH Power Supply -0.3 to V DDH +0.3 VV IN Input Signal Voltage -0.3 to 3.6 VV OUT Output Signal Voltage-0.3 to V DDH +0.3 VT STG Storage Temperature-40 to 150 O C5.2 Recommended Operating ConditionsTable 5.2 Recommended Operating ConditionsSYMBOL PARAMETER MIN TYP MAX UNITS V DDH Power Supply 3.0 3.3 3.6 V V DD Digital Supply 2.25 2.5 2.75 V V IN Input Signal Voltage 0 3.3 3.6 V T OPR Operating Temperature 0 70 O C 5.3G e n e r a l D C C h a r a c t e r i s t i c sTable 5.3 General DC CharacteristicsSYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSI IN Input current No pull-up orpull-down-10 ±1 10 µAI OZ Tri-state leakage current-10 ±1 10 µA C IN Input capacitance Pad Limit 2.8 ρF C OUT Output capacitance Pad Limit 2.8 ρFC BID Bi-directional buffercapacitancePad Limit 2.8 ρFAU6366 USB 2.0 Single LUN Multiple Flash Card Reader Controller V1.03W 75.4D C E l e c t r i c a l C h a r a c t e r i s t i c s o f3.3V I/O C e l l sTable 5.4 DC Electrical Characteristics of 3.3V I/O CellsLimitsSYMBOL PARAMETER CONDITIONSMIN TYP MAXUNIT V DDH Power supply 3.3V I/O 3.0 3.3 3.6 V V il Input low voltage 0.8 VV ih Input high voltage LVTTL2.0 VV ol Output low voltage ∣I ol∣=2~16mA 0.4 V V oh Output high voltage ∣I oh∣=2~16mA 2.4 V R pu Input pull-up resistance PU=high, PD=low55 75 190 KΩR pd Input pull-down resistance PU=low, PD=high40 75 190 KΩI in Input leakage current V in= V DDH or 0 -10 ±1 10 μAI oz Tri-state output leakagecurrent-10 ±1 10 μA5.5U S B T r a n s c e i v e r C h a r a c t e r i s t i c sTable 5.5 Electrical characteristicsSymbol Parameter Conditions Min.Typ. Max.Unit VD33 Analog supply Voltage 3.0 3.3 3.6 V VDDUVDDADigital supply Voltage 2.25 2.5 2.75 VI CC Operating supply current High speed operatingat 480 MHz73mAI CC (susp)Suspend supply currentIn suspend mode,current with 1.5kΩpull-up resistor on pinRPU disconnected120µAAU6366 USB 2.0 Single LUN Multiple Flash Card Reader Controller V1.03W 8Table 5.6 Static characteristic：Digital pinSymbol Parameter Conditions Min. Typ. Max. UnitInput levelsV IL Low-level input voltage 0.8 V V IH High-level input voltage 2.0 VOutput levelsV OL Low-level output voltage 0.2 V V OH High-level output voltage VDDH-0.2V Table 5.7 Static characteristic：Analog I/O pins（DP/DM）Symbol Parameter Conditions Min.Typ. Max. UnitUSB2.0 Transceiver（HS）Input Levels（differential receiver）V HSDIFF High speed differentialinput sensitivity∣V I（DP）-V I（DM）∣measured at theconnection asapplication circuit300 mVV HSCM High speed data signalingcommon mode voltagerange-50 500mVSquelch detected 100 mVV HSSQ High speed squelchdetection threshold No squelch detected150 mVDisconnectiondetected625 mVV HSDSC High speed disconnectiondetection threshold Disconnection notdetected525mVOutput LevelsV HSOIHigh speed idle leveloutput voltage(differential)-10 10mVV HSOLHigh speed low leveloutput voltage(differential)-10 10mVV HSOHHigh speed high leveloutput voltage(differential)-360 400mVV CHIRPJ Chirp-J output voltage（differential）700 1100mVV CHIRPK Chirp-K output voltage（differential）-900 -500mVResistanceR DRV Driver output impedance Equivalent resistanceused as internal chiponly3 6 9 ΩAU6366 USB 2.0 Single LUN Multiple Flash Card Reader Controller V1.03W 9Overallresistanceincluding externalresistor40.5 45 49.5 TerminationV TERM Termination voltage forpull-up resistor on pinRPU3.0 3.6V USB1.1 Transceiver（FS/LS）Input Levels（differential receiver）V DI Differential inputsensitivity∣V I（DP）-V I（DM）∣0.2 VV CM Differential commonmode voltage0.8 2.5V Input Levels（single-ended receivers）V SE Single ended receiverthreshold0.8 2.0VOutput levelsV OL Low-level output voltage0 0.3 V V OH High-level output voltage 2.8 3.6 VTable 5.8 Dynamic characteristic：Analog I/O pins（DP/DM）Symbol Parameter Conditions Min.Typ. Max. UnitDriver CharacteristicsHigh-Speed Modet HSR High-speed differentialrise time500 pst HSF High-speed differential falltime500 psFull-Speed Modet FR Rise time CL=50pF；10 to 90﹪of∣V OH-V OL∣；4 20nst FF Fall time CL=50pF；90 to 10﹪of∣V OH-V OL∣；4 20nst FRMA Differential rise/fall timematching（t FR / t FF）Excluding the firsttransition from idlemode90 110 ％V CRS Output signal crossovervoltageExcluding the firsttransition from idlemode1.32.0 VLow-Speed Modet LR Rise time CL=200pF-600pF；10 to 90﹪of∣V OH-V OL∣；75 300nsAU6366 USB 2.0 Single LUN Multiple Flash Card Reader Controller V1.03W 10t LFFall timeCL=200pF-600pF ；90 to 10﹪of ∣V OH -V OL ∣； 75 300 nst LRMA Differential rise/fall timematching （t LR / t LF ）Excluding the firsttransition from idlemode80 125 ％ V CRS Output signal crossovervoltageExcluding the firsttransition from idlemode 1.3 2.0 V V OHHigh-level output voltage2.83.6VAU6366 USB 2.0 Single LUN Multiple Flash Card Reader Controller V1.03W115.6 P o w e r S w i t c h F e a t u r eFigure 5.1 Built-in card power switch I-V curve3.3V+/- 0.3V1ms to 10ms ( Depend Load Capacitor )CARD_POWERCARD_DETECT100ms + System Polling timingFigure 5.2 Card Detect Power-on TimingAU6366 USB 2.0 Single LUN Multiple Flash Card Reader Controller V1.03W126. Mechanical InformationFigure 6.1 Mechanical Information DiagramGAUGE PLANE SEATING PLANE1.60.15 1.45 0.16 BSC BSC BSC BSC BSC 0.270.75 REF1.JEDEC OUTLINE: MS-026 BBC2. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.ALLOWABLE PROTRUSION IS 0.25mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS IMCLUDING MOLD MISMATCH.3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08mmAU6366 USB 2.0 Single LUN Multiple Flash Card Reader Controller V1.03W137. AbbreviationsIn this chapter some of the terms and abbreviations used throughout the technical reference manual are listed as follows.SIE Serial Interface EngineCF Compact FlashMD Micro DriveSMC SmartMedia CardMS Memory StickSD Secure DigitalMMC Multimedia CardUTMI USB Transceiver Macrocell InterfaceAbout Alcor Micro, Corp.Alcor Micro, Corp. designs, develops and markets highly integrated and advanced peripheral semiconductor, and software driver solutions for the personal computer and consumer electronics markets worldwide. We specialize in USB solutions and focus on emerging technology such as USB and IEEE 1394. The company offers a range of semiconductors including controllers for USB hub, integrated keyboard/USB hub and USB Flash memory card reader…etc. Alcor Micro, Corp. is based in Taipei, Taiwan, with sales offices in Taipei, Japan, Korea and California. Alcor Micro is distinguished by its ability to provide innovative solutions for spec-driven products. Innovations like single chip solutions for traditional multiple chip products and on-board voltage regulators enable the company to provide cost-efficiency solutions for the computer peripheral device OEM customers worldwide.AU6366 USB 2.0 Single LUN Multiple Flash Card Reader Controller V1.03W 14。
ISL6336资料
ISL6336, ISL6336A
Ordering Information
PART NUMBER
PART MARKING
TEMP. RANGE (°C)
PACKAGE (Pb-Free)
PKG. DWG. #
ISL6336CRZ*
ISL6336 CRZ0 来自o +7048 Ld 7x7 QFN
L48.7x7
Microprocessor loads can generate load transients with extremely fast edge rates and require high efficiency over the full load range. The ISL6336, ISL6336A utilizes Intersil’s proprietary Active Pulse Positioning (APP) and Adaptive Phase Alignment (APA) modulation scheme and a proprietary active phase dropping/adding and diode emulation scheme to achieve extremely fast transient response with fewer output capacitors and high efficiency from light load to full load.
• Precision Multiphase Core Voltage Regulation - Differential Remote Voltage Sensing - ±0.5% System Accuracy Over Life, Load, Line and Temperature - Bi-directional Adjustable Reference-Voltage Offset
OB6663L Datasheet
FEATURES
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©On-Bright Electronics
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Integrated Transition Mode (TM) PFC Controller and Quasi-Resonant (QR) PWM Controller Built-in Dual Output PFC Control Multi-Mode Operation for QR Stage Separated AGND and PGND Provide Better Noise Immunity Analog Multiplier with Built-in THD Optimizer for PFC Stage Line Feed-forward Compensation for PFC Stage Enhanced Dynamic Response for PFC Stage Less than 200mW Standby Power Consumption Minimum QR Short Circuit Power Consumption Audio Noise Free Operation External Latch Triggering for Both Converters Minimum OFF time for Ringing Suppression Maximum ON Time Limit for QR Converter Built-in 4ms Soft Start for QR Converter Internal Leading Edge Blanking for Both Converters
BATT-3V6;EL-USB-3;中文规格书,Datasheet资料
Martel Electronics Corporation T el: 800-821-0023PO Box 770Email: sales@ Londonderry, NH 03053 USAWeb: © Copyright 2005 Martel Eectronics CorporationAll trademarks are the property of their respective owners.P/N 000000000 Rev. xFEATURESORDERING INFORMATIONStock Number Standard Data LoggerEL-USB-3(Data Logger,Measurement Leads,Software on CD and Battery)Replacement BatteryBAT 3V6•0-30V d.c.Measurement Range •Logging Rates between 1s and 12hr •Stores 32,510readings•Connection via two screw terminals•USB Interface for Set-up and Data Download •User-Programmable Alarm Thresholds •Red and Green LED Status Indication •Replaceable Internal Lithium BatteryEL-USB-3Voltage USB Data LoggerThis data logger measures and stores up to 32,510voltage readings over a 0-30V d.c.measurement range.The user can easily set up the logging rate and start time,and download the stored data by plugging the module straight into a PC's USB port and running the purpose designed software under Windows 98,2000or XP .The data can then be graphed,printed and exported to other applications.The data logger is supplied complete with a long-life lithium battery.Correct functioning of the unit is indicated by flashing red and green LED.The data logger features a pair of screw terminals and is is supplied complete with a set of measurement leads terminating in crocodile clips.WINDOWS CONTROL SOFTWAREEasy to install and use,the control software runs under Windows 98,2000and XP (Home and ProfessionalEditions).It allows the user to set up and download any EL-USB-3.The latest version of the control software may be downloaded from . DATA LOGGER SET-UPS•Logger Name•Logging Rate (1s,10s,1m,5m,30m,1hr,6hr,12hr)•High and Low Alarms •Start Date and Start Time*depending on ambient temperature,logging rate and use of alarm LED./2Martel Electronics Corporation DT -EL -USB3EL-USB-3Voltage USB Data LoggerLED FLASHING MODESEL-USB-3features a red and a green LED.The LEDs on an EL-USB-3will flash in one of the following ways,assuming alarm latching is turned off (exact timings to be confirmed).By default latching is disabled,so the red LED will continue to flash,even after the logged voltage has returned to normal.The red LED will effectively have latched into its alarm condition.This feature ensures that the user is notified that an alarm level has been exceeded,without the need to download the data from the logger.Latching can be turned on via the control software.The red LED will then no longer continue to flash after the logged voltage has returned to normal.Instead,the green LED will then flash.-Green single flash,Logger primed and ready to start.every 30seconds-Green single flash,Logging in progress,last stored value OKevery 10seconds -Red single flash,Logging in progress,the last stored reading is equal to or the low alarm level every 10seconds (If latching is turned on,then a stored value is equal to or exceeds the low alarm level)-Red double flash Logging in progress,the last stored reading is equal to or exceeds the high alarm level every 10seconds(If latching is turned on,then a stored value is equal to or exceeds the high alarm level)-Green single flash,Low battery,logging in progress,the last stored value OKevery 20seconds -Red single flash,Low battery,logging in progress,the last stored value is equal to or exceeds the low alarm levelevery 20seconds -Red double flash,Low battery,logging in progress,the last stored value is equal to or exceeds the high alarm levelevery 20seconds-Green double flash,Logger is full,last stored value OKevery 20seconds -Red/Green single flash,Logger is full,last stored value is equal to or exceeds the low or high alarm levelevery 20seconds,alarm latching turned on -No LEDs flashLEDs disabled during configuration to save battery power and increase logging duration.orBattery dead.exceeds /DT -EL -USB3Martel Electronics Corporation 3EL-USB-3Voltage USB Data Loggerbattery voltage /分销商库存信息:MARTEL-ELECTRONICSBATT-3V6EL-USB-3。
61113中文资料
61113 GENERAL PURPOSE (NPN) TRANSISTOR SURFACE MOUNT PACKAGE(2N2369AUB)Mii OPTOELECTRONIC PRODUCTSDIVISIONFeatures:• Hermeticallysealed •Hermetically sealed 3 pin LCC •MIL-PRF-19500 screening available A pplications:• AnalogSwitches• SignalConditioning •Small Signal Amplifiers • HighDensityPackagingDESCRIPTIONThe 61113 is a N-P-N, general-purpose switching and amplifier transistor in a 3 pin leadless chip carrier package. All packages are hermetically sealed for high reliability and harsh environments. This device is available custom binned to customer specifications in commercial or screened to MIL-PRF-19500 up to JANS level.ABSOLUTE MAXIMUM RATINGSCollector-Base Voltage - V CBO.................................................................................................................................................40Vdc Collector-Emitter Voltage - V CEO..............................................................................................................................................15Vdc Collector-Emitter Voltage - V CES..............................................................................................................................................40Vdc Emitter-Base Voltage - V EBO...................................................................................................................................................4.5Vdc Collector Current – I C(Peak).......................................................................................................................................................500mA Continuous Collector Current ................................................................................................................................................200mA Maximum Junction Temperature...........................................................................................................................................+200°C Operating Temperature (See part selection guide for actual operating temperature)............................................-65°C to +125°C61113 SURFACE MOUNT NPN GENERAL PURPOSE TRANSISTOR (TYPE 2N2369AUB) ELECTRICAL CHARACTERISTICST A = 25°C unless otherwise specified.PARAMETER SYMBOL MIN MAX UNITS TEST CONDITIONS NOTE Collector-Base Breakdown Voltage BV CBO40V dc I C = 10µA, I E= 0Collector-Emitter Breakdown Voltage BV CEO40V dc I C= 10µA , I B= 0µACollector-Emitter Sustaining Voltage BV CES15V dc I C= 10m A , I B= 0µAEmitter-Base Breakdown Voltage BV EBO 4.5V dc I C= 0, I E= 10µACollector-Base Cutoff Current I CBO0.4µA V CB = 20V, I E = 030µA V CB = 20V, I E= 0, T A = 150°CCollector-Emitter Cutoff Current I CES0.4µA V CE = 20VForward-Current Transfer Ratio h fe-120-V CE = 1V, I C = 10mAh fe20-V CE = 1V, I C = 100mAh fe20-V CE = 2V, I C = 100mAh fe420-V CE = 1V, I C = 10mA @ -55ºC1h fe630-V CE= 0.35V, I C = 10mA @ -55ºCCollector-Emitter Saturation Voltage V CE (SAT)0.20V I C = 10mA, I B= 1mA1V CE (SAT)0.30V I C = 10mA, I B= 1mA @ +125ºCV CE (SAT)0.25V I C = 30mA, I B= 3mAV CE (SAT)0.50V I C = 100mA, I B= 10mA1 Base-Emitter Saturation Voltage V BE (SAT)0.70.85V I C = 10mA, I B= 1mA1V BE (SAT)0.59-V I C = 10mA, I B= 1mA @ +125ºCV BE (SAT) 1.02V I C = 10mA, I B= 1mA @ -55ºC1.15V I C = 30mA, I B= 3mAV BE (SAT) 1.60V I C = 100mA, I E= 10mA1SMALL-SIGNAL CHARACTERISTICSCurrent-Gain – Bandwidth Product f r500MHz V CB = 10V, 100kHz, < f < 1 MHzC IBO25pF V EB = 0.5 V, 100kHz, < f < 1 MHzInput Capacitance(Output Open Capacitance)Turn-On Time t on35nS V CC= 30V, I C = 150mA,I B1 = 15mATurn-Off Time t off300nS V CC = 30V, I C = 150mA,I B1 = I B2 = 15mANOTES:1. Pulse width < 300µs, duty cycle <2.0%.SELECTION GUIDEPART NUMBER PART DESCRIPTION61113-0012N2369AUB PNP transistor, commercial version61113-0022N2369AUB PNP transistor, JAN level screening61113-0032N2369AUB PNP transistor, JANTX level screening61113-0042N2369AUB PNP transistor, JANTXV level screening61113-0052N2369AUB PNP transistor, JANS level screeningNOTE: Also available in dual and quad configurations upon request. Can also be supplied in gull wing surface mount versions.。
A67L7336E-4.5中文资料
NC NC NC VCCQ VSSQ NC NC I/Ob0 I/Ob1 VSSQ VCCQ I/Ob2 I/Ob3 VCC VCC VCC VSS I/Ob4 I/Ob5 VCCQ VSSQ I/Ob6 I/Ob7 I/Ob8/NC NC VSSQ VCCQ NC NC NC
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PRELIMINARY
(December, 1999, Version 0.1)
1
AMIC Technology, Inc.
DBA and Direct Bus Alternation are trademarks of AMIC Technology, Inc
元器件交易网
Block Diagram (128K X 32/36)
ZZ MODE
MODE LOGIC
ADV/LD
CEN CLK
CLK LOGIC
BURST LOGIC ADDRESS COUNTER CLR
A0-A16
ADDRESS REGISTERS
WRITE ADDRESS REGISTER
WRITE ADDRESS REGISTER
8/9
BYTEa WRITE DRIVER BYTEb WRITE DRIVER BYTEc WRITE DRIVER BYTEd WRITE DRIVER
8/9
8/9 ADV/LD R/W BWE BW1 BW2 BW3 BW4 WRITE REGISTRY & CONTROL LOGIC
UPA672T-T1-A;中文规格书,Datasheet资料
To our customers,Old Company Name in Catalogs and Other DocumentsOn April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding.Renesas Electronics website: April 1st, 2010Renesas Electronics CorporationIssued by: Renesas Electronics Corporation ()Send any inquiries to /inquiry.Notice1. All information included in this document is current as of the date this document is issued. Such information, however, issubject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rightsof third parties by or arising from the use of Renesas Electronics products or technical information described in this document.No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation ofsemiconductor products and application examples. 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The quality grade of each Renesas Electronics product is “Standard” unless otherwiseexpressly specified in a Renesas Electronics data sheets or data books, etc.“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots.“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically designed for life support.“Specific”: Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcareintervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.8. 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Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of aRenesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you.10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmentalcompatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of RenesasElectronics.12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in thisdocument or Renesas Electronics products, or if you have any other inquiries.(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.Document No. G11259EJ1V0DS00 (1st edition) Date Published June 1996 P2ELECTRICAL CHARACTERISTICS (T A = 25 ˚C)PARAMETERSYMBOL TEST CONDITIONSMIN.TYP.MAX.UNITDrain Cut-off Current I DSS V DS = 50 V, V GS = 010µA Gate Leakage Current I GSS V GS = ±7.0 V, V DS = 0±5.0µA Gate Cut-off Voltage V GS(off)V DS = 3.0 V, I D = 1.0 µA 0.7 1.01.5V Forward Transfer Admittance |y fs |V DS = 3.0 V, I D = 10 mA 20mS Drain to Source On-State Resistance R DS(on)1V GS = 2.5 V, I D = 10 mA 2040ΩDrain to Source On-State Resistance R DS(on)2V GS = 4.0 V, I D = 10 mA1520ΩInput Capacitance C iss V DS = 3.0 V, V GS = 0, f = 1.0 MHz6pF Output CapacitanceCoss 8pF Reverse Transfer Capacitance C rss 1.2pF Turn-On Delay Time t d(on)V DD = 3 V, I D = 20 mA, V GS(on) = 3 V,9ns Rise Timet r R G = 10 Ω, R L = 120 Ω50ns Turn-Off Delay Time t d(off)20ns Fall Timet f40nsSWITCHING TIME MEASUREMENT CIRCUIT AND CONDITIONSV µτ = 1 s Duty Cycle ≤ 1 %µPA672T3TYPICAL CHARACTERISTICS (T A = 25 ˚C)TOTAL POWER DISSIPATION vs. AMBIENT TEMPERATUREP T - T o t a l P o w e r D i s s i p a t i o n - m WT A - Ambient Temperature - ˚CDRAIN CURRENT vs.DRAIN TO SOURCE VOLTAGEI D - D r a i n C u r r e n t - m AV DS - Drain to Source Voltage - V TRANSFER CHARACTERISTICSI D - D r a i n C u r r e n t - m AV GS - Gate to Source Voltage - V FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT|y f s | - F o r w a r d T r a n s f e r A d m i t t a n c e - m SI D - Drain Current - mADRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT R D S (o n ) - D r a i n t o S o u r c e O n -S t a t e R e s i s t a n c e - ΩI D - Drain Current - mADRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT R D S (o n ) - D r a i n t o S o u r c e O n -S t a t e R e s i s t a n c e - ΩI D - Drain Current - mA2530050751502502001501005010012511008060402023451001010.10.010.001123100502011000251020501005020102511001251020501005020102511001251020504DRAIN TO SOURCE ON-STAGE RESISTANCE vs. GATE TO SOURCE VOLTAGE R D S (o n ) - D r a i n t o S o u r c e O n -S t a t e R e s i s t a n c e - ΩV GS - Gate to Source Voltage - VCAPACITANCE vs. DRAIN TO SOURCE VOLTAGEC i s s , C o s s , C r s s , - C a p a c i t a n c e - p FV DS - Drain to Source Voltage - V t d (o n ), t r , t d (o f f ), t r - S w i t c h i n g T i m e - n sI D - Drain Current - mAI S D - S o u r c e t o D r a i n C u r r e n t - m AV SD - Source to Drain Voltage - VSWITCHING CHARACTERISTICSSOURCE TO DRAIN DIODE FORWARD VOLTAGE30201071234561021002510.50.20.1151020501002010002050105211501002005001001.00.610100.20.40.8REFERENCEDocument Name Document No.NEC semiconductor device reliability/quality control system TEI-1202Quality grade on NEC semiconductor devices IEI-1209 Semiconductor device mounting technology manual C10535EGuide to quality assurance for semiconductor devices MEI-1202 Semiconductor selection guide X10679E5No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others.While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features.NEC devices are classified into the following three quality grades:“Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based ona customer designated “quality assurance program“ for a specific application. The recommended applicationsof a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application.Standard:Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronicequipment and industrial robotsSpecial:Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designedfor life support)Specific:Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc.The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books.If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance.Anti-radioactive design is not implemented in this product.M4 94.11分销商库存信息: RENESASUPA672T-T1-A。
A43L2616AV-6中文资料
Preliminary 1M X 16 Bit X 4 Banks Synchronous DRAMDocument Title1M X 16 Bit X 4 Banks Synchronous DRAMRevision HistoryDate Remark Rev. No. History Issue issue November 30, 2004 Preliminary0.0 InitialA43L2616APreliminary1M X 16 Bit X 4 Banks Synchronous DRAMFeatureJEDEC standard 3.3V power supplyLVTTL compatible with multiplexed address Four banks / Pulse RAS MRS cycle with address key programs - CAS Latency (2,3)- Burst Length (1,2,4,8 & full page) - Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Clock Frequency: 166MHz @ CL=3 143MHz @ CL=3Burst Read Single-bit Write operationDQM for masking Auto & self refresh 64ms refresh period (4K cycle) Commercial Temperature Operation : 0°C~70°C Industrial Temperature Operation : -40°C~85°C for –U grade 54 Pin TSOP (II) and 54 Balls CSP (8mm x 8mm)General DescriptionThe A43L2616A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 X 1,048,576 words by 16 bits, fabricated with AMIC’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock.I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.Pin ConfigurationTSOP (II)V S SD Q 15V S S QD Q 14D Q 13V D D QD Q 12D Q 11V S S QD Q 10D Q 9V D D QD Q 8V S SU D Q MC KC K EN CA 9A 8A 7A 6A 5A 4V S SV D DD Q 0V D D QD Q 1D Q 2V S S QD Q 3D Q 4V D D QD Q 5D Q 6V S S QD Q 7V D DL D Q MW EC A SR A SC SA 10/A PB S 1B S 0A 0A 1A 2A 3V D DA 11N CPin Configuration (continued)54 Balls CSP (8 mm x 8 mm)Top ViewBlock DiagramCLKADDDQiPin DescriptionsAbsolute Maximum Ratings*Voltage on any pin relative to VSS (Vin, Vout ) . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +4.6V Voltage on VDD supply relative to VSS (VDD, VDDQ ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to +4.6V Storage Temperature (T STG ) . . . . . . . . . . -55°C to +150°C Soldering Temperature X Time (T SLODER ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec Power Dissipation (P D ) . . . . . . . . . . . . . . . . . . . . . . . . .1W Short Circuit Current (Ios) . . . . . . . . . . . . . . . . . . . . 50mA *CommentsPermanent device damage may occur if “Absolute Maximum Ratings” are exceeded.Functional operation should be restricted to recommended operating condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.Capacitance (T A =25°C, f=1MHz)DC Electrical CharacteristicsRecommend operating conditions (Voltage referenced to VSS = 0V, T A = 0ºC to +70ºC or T A = -40ºC to +85ºC)Parameter Symbol Min Typ Max Unit NoteSupply Voltage VDD,VDDQ 3.0 3.3 3.6 VInput High Voltage V IH 2.0 3.0 VDD+0.3 VInput Low Voltage V IL -0.3 0 0.8 V Note 1 Output High Voltage V OH 2.4 --V I OH = -2mAOutput Low Voltage V OL - - 0.4 V I OL = 2mA Input Leakage Current I IL -5 - 5 µA Note 2 Output Leakage Current I OL -5 - 5 µANote 3Output Loading ConditionSee Figure 1Note: 1. V IL (min) = -1.5V AC (pulse width ≤ 5ns).2. Any input 0V ≤ VIN ≤ VDD + 0.3V, all other pins are not under test = 0V3. Dout is disabled, 0V ≤ Vout ≤ VDDDecoupling Capacitance Guide LineRecommended decoupling capacitance added to power line at board.Parameter Symbol Value UnitDecoupling Capacitance between VDD and VSS C DC1 0.1 + 0.01 µF Decoupling Capacitance between VDDQ and VSSQC DC20.1 + 0.01µFNote: 1. VDD and VDDQ pins are separated each other.All VDD pins are connected in chip. All VDDQ pins are connected in chip. 2. VSS and VSSQ pins are separated each otherAll VSS pins are connected in chip. All VSSQ pins are connected in chip.DC Electrical Characteristics(Recommended operating condition unless otherwise noted, T A = 0°C to 70°C T A = -40ºC to +85ºC) Note: 1. Measured with outputs open. Addresses are changed only one time during t CC (min).2. Refresh period is 64ms. Addresses are changed only one time during t CC (min).3. I CC6 normal version: A43L2616AV-6, A43L2616AV-7.4. I CC6 low self refresh current version: A43L2616AV-6V, A43L2616AV-7V.AC Operating Test Conditions(VDD = 3.3V ±0.3V, T A = 0°C to +70°C or T A = -40ºC to +85ºC)Parameter ValueAC input levelsV IH /V IL = 2.4V/0.4V Input timing measurement reference level 1.4VInput rise and all time (See note3)tr/tf = 1ns/1ns Output timing measurement reference level 1.4V Output load conditionSee Fig.2Output(Fig. 1) DC Output Load Circuit ΩTT =1.4V (Fig. 2) AC Output Load CircuitAC Characteristics(AC operating conditions unless otherwise noted)-6 -7Symbol Parameter CAS Latency Min Max Min MaxUnit Notet CC CLK cycle time 6 1000 7 1000 ns 1t SACCLK to valid Output delay- 5 - 5.4 ns 1,2 t OH Output data hold time 2.5-2.7-ns2t CH CLK high pulse width 32.5 - 2.5 - ns 3 t CL CLK low pulse width 2.5 - 2.5 - ns 3 t SS Input setup time 2 - 2 - ns 3 t SH Input hold time 1 - 1 - ns 3 t SLZ CLK to output in Low-Z 1-1-ns2t SHZCLK to output In Hi-Z3- 5.5 - 6 ns*All AC parameters are measured from half to half.Note : 1. Parameters depend on programmed CAS latency.2. If clock rising time is longer than 1ns, (tr/2-0.5) ns should be added to the parameter.3. Assumed input rise and fall time (tr & tf) = 1ns.If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.Operating AC Parameter(AC operating conditions unless otherwise noted)Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer.2. Minimum delay is required to complete write.Simplified Truth Table(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low) Note : 1. OP Code: Operand CodeA0~A11, BS0, BS1: Program keys. (@MRS)2. MRS can be issued only at both banks precharge state.A new command can be issued after 2 clock cycle of MRS.3. Auto refresh functions as same as CBR refresh of DRAM.The automatical precharge without Row precharge command is meant by “Auto”.Auto/Self refresh can be issued only at both precharge state.4. BS0, BS1 : Bank select address.If both BS1 and BS0 are “Low” at read, write, row active and precharge, bank A is selected.If both BS1 is “Low” and BS0 is “High” at read, write, row active and precharge, bank B is selected.If both BS1 is “High” and BS0 is “Low” at read, write, row active and precharge, bank C is selected.If both BS1 and BS0 are “High” at read, write, row active and precharge, bank D is selected.If A10/AP is “High” at row precharge, BS1 and BS0 is ignored and all banks are selected.5. During burst read or write with auto precharge, new read write command cannot be issued.Another bank read write command can be issued at every burst length.6. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0) butmasks the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)Mode Register Filed Table to Program ModesRegister Programmed with MRS AddressBS0, BS1A11, A10A9A8A7A6A5A4A3A2A1A0FunctionRFURFU W.B.L TM CAS Latency BT Burst Length(Note 1)(Note 2)Test ModeCAS LatencyBurst TypeBurst LengthA8 A7TypeA6 A5 A4Latency A3TypeA2A1 A0 BT=0BT=10 0 Mode Register Set0 0 0Reserved0Sequential 00 0 1 1 0 1 0 0 1- 1Interleave 00 1 2 2 1 0 0 1 0 2 0 1 0 4 4 1 1Vendor Use Only0 1 1 3 0 1 188 Write Burst Length 1 0 0Reserved 10 0 Reserved Reserved A9 Length 1 0 1Reserved10 1 ReservedReserved0 Burst 1 1 0Reserved 1 1 0 Reserved Reserved 1 Single Bit 1 1 1Reserved11 1 256(Full)ReservedPower Up Sequence1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.2. Maintain stable power, stable clock and NOP input condition for a minimum of 200µs.3. Issue precharge commands for all banks of the devices.4. Issue 2 or more auto-refresh commands.5. Issue a mode register set command to initialize the mode register. cf.) Sequence of 4 & 5 may be changed.The device is now ready for normal operation.Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.Burst Sequence (Burst Length = 4)Initial addressSequential Interleave A1 A00 0 0 1 2 3 0 1 2 30 1 1 2 3 0 1 0 3 21 023 0 1 2 3 0 11 1 3 0 123 2 1 0Burst Sequence (Burst Length = 8)Initial addressSequential Interleave A2 A1 A00 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 70 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 60 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 50 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 41 0 0 4 5 6 7 0 1234567 0 1 2 31 0 1 5 6 7 0 12345 4 76 1 0 3 21 1 0 6 7 0 1234567 4 5 2 3 0 11 1 1 7 0 1234567 6 5 4 3 2 1 0Device OperationsClock (CLK)The clock input is used as the reference for all SDRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between V IL and V IH. During operation with CKE high all inputs are assumed to be in valid state (low or high) for the duration of set up and hold time around positive edge of the clock for proper functionality and ICC specifications.Clock Enable (CLK)The clock enable (CKE) gates the clock onto SDRAM. If CKE goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock is suspended form the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When both banks are in the idle state and CKE goes low synchronously with clock, the SDRAM enters the power down mode form the next clock cycle. The SDRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least “t SS + 1 CLOCK” before the high going edge of the clock, then the SDRAM becomes active from the same clock edge accepting all the input commands.Bank Select (BS0, BS1)This SDRAM is organized as 4 independent banks of 1,048,576 words X 16 bits memory arrays. The BS0, BS1 inputs is latched at the time of assertion of RAS and CASto select the bank to be used for the operation. The bank select BS0, BS1 is latched at bank activate, read, write mode register set and precharge operations.Address Input (A0 ~ A11)The 20 address bits required to decode the 262,144 word locations are multiplexed into 12 address input pins (A0~A11). The 12 bit row address is latched along with RAS, BS0 and BS1 during bank activate command. The 8 bit column address is latched along with CAS, WE, BS0 and BS1during read or write command.NOP and Device DeselectWhen , CAS and WE are high, the SDRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock like bank activate, burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS, CAS and WE, and all the address inputs are ignored.Power-UpThe following sequence is recommended for POWER UP 1. Power must be applied to either CKE and DQM inputs topull them high and other pins are NOP condition at the inputs before or along with VDD (and VDDQ) supply.The clock signal must also be asserted at the same time.2. After VDD reaches the desired voltage, a minimumpause of 200 microseconds is required with inputs in NOP condition.3. Both banks must be precharged now.4. Perform a minimum of 2 Auto refresh cycles to stabilizethe internal circuitry.5. Perform a MODE REGISTER SET cycle to program theCAS latency, burst length and burst type as the default value of mode register is undefined.At the end of one clock cycle from the mode register set cycle, the device is ready for operation.When the above sequence is used for Power-up, all the out-puts will be in high impedance state. The high impedance of outputs is not guaranteed in any other power-up sequence.cf.) Sequence of 4 & 5 may be changed.Mode Register Set (MRS)The mode register stores the data for controlling the various operation modes of SDRAM. It programs the CAS latency, addressing mode, burst length, test mode and various vendor specific options to make SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SDRAM. The mode register is written by asserting low on CS,RAS, CAS,(The SDRAM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0~A11, BS0 and BS1 in the same cycle as CS,,CAS,WE going low is the data written in the mode register. One clock cycle is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as both banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length field uses A0~A2, burst type uses A3, addressing mode uses A4~A6, A7~A8, A11, BS0 and BS1 are used for vendor specific options or test mode. And the write burst length is programmed using A9. A7~A8, A11, BS0 and BS1 must be set to low for normal SDRAM operation.Refer to table for specific codes for various burst length, addressing modes and CAS latencies.Device Operations (continued)Bank ActivateThe bank activate command is used to select a random row in an idle bank. By asserting low on RAS and CS with desired row and bank addresses, a row access is initiated. The read or write operation can occur after a time delay of t RCD(min) from the time of bank activation. t RCD(min) is an internal timing parameter of SDRAM, therefore it is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing t RCD(min) with cycle time of the clock and then rounding off the result to the next higher integer. The SDRAM has two internal banks on the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of both banks immediately. Also the noise generated during sensing of each bank of SDRAM is high requiring some time for power supplies recover before the other bank can be sensed reliably. t RRD(min) specifies the minimum time required between activating different banks. The number of clock cycles required between different bank activation must be calculated similar to t RCD specification. The minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by t RAS(min) specification before a precharge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by t RAS(max). The number of cycles for both t RAS(min) and t RAS(max) can be calculated similar to t RCD specification.Burst ReadThe burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The burst read command is issued by asserting low on CS and CAS with WE being high on the positive edge of the clock. The bank must be active for at least t RCD(min) before the burst read command is issued. The first output appears CAS latency number of clock cycles after the issue of burst read command. The burst length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in the mode register. The output goes into high-impedance at the end of the burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. The burst stop command is valid at every page burst length. Burst WriteThe burst write command is similar to burst read command, and is used to write data into the SDRAM consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. By asserting low on CS,CAS and WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even though the internal writing may not have been completed yet. The writing can not complete to burst length. The burst write can be terminated by issuing a burst read and DQM for blocking data inputs or burst write in the same or the other active bank. The burst stop command is valid only at full page burst length where the writing continues at the end of burst and the burst is wrap around. The write burst can also be terminated by using DQM for blocking data and precharging the bank “t RDL” after the last data input to be written into the active row. See DQM OPERATION also.DQM OperationThe DQM is used to mask input and output operation. It works similar to OE during read operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in the read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock, therefore the masking occurs for a complete cycle. The DQM signal is important during burst interrupts of write with read or precharge in the SDRAM. Due to asynchronous nature of the internal write, the DQM operation is critical to avoid unwanted or incomplete writes when the complete burst write is not required.PrechargeThe precharge operation is performed on an active bank by asserting low on CS,RAS,WE and A10/AP with valid BA of the bank to be precharged. The precharge command can be asserted anytime after t RAS(min) is satisfied from the bank activate command in the desired bank. “t RP” is defined as the minimum time required to precharge a bank. The minimum number of clock cycles required to complete row precharge is calculated by dividing “t RP” with clock cycle time and rounding up to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can be active is specified by t RAS(max). Therefore, each bank has to be precharged within t RAS(max) from the bank activate command. At the end of precharge, the bank enters the idle state and is ready to be activated again.Entry to Power Down, Auto refresh, Self refresh and Mode register Set etc, is possible only when both banks are in idle state.Device Operations (continued)Auto PrechargeThe precharge operation can also be performed by usingauto precharge. The SDRAM internally generates thetiming to satisfy t RAS(min) and “t RP” for the programmedburst length and CAS latency. The auto prechargecommand is issued at the same time as burst read or burstwrite by asserting high on A10/AP. If burst read or burstwrite command is issued with low on A10/AP, the bank isleft active until a new command is asserted. Once autoprecharge command is given, no new commands arepossible to that particular bank until the bank achieves idlestate.Four Banks PrechargeBoth banks can be precharged at the same time by using Precharge all command. Asserting low on CS,RAS and WE with high on A10/AP after both banks have satisfied t RAS(min) requirement, performs precharge on both banks.At the end of tRP after performing precharge all, bothbanks are in idle state.Auto RefreshThe storage cells of SDRAM need to be refreshed every64ms to maintain data. An auto refresh cycle accomplishesrefresh of a single row of storage cells. The internalcounter increments automatically on every auto refreshcycle to refresh all the rows. An auto refresh command is issued by asserting low on CS,RAS and CAS with high on CKE and WE. The auto refresh command can only be asserted with both banks being in idle state and the deviceis not in power down mode (CKE is high in the previouscycle). The time required to complete the auto refresh operation is specified by “t RC(min)”. The minimum number of clock cycles required can be calculated by driving “t RC” with clock cycle time and then rounding up to the next higher integer. The auto refresh command must be followed by NOP’s until the auto refresh operation is completed. Both banks will be in the idle state at the end of auto refresh operation. The auto refresh is the preferred refresh mode when the SDRAM is being used for normal data transactions. The auto refresh cycle can be performed once in 15.6us or a burst of 4096 auto refresh cycles once in 64ms.Self RefreshThe self refresh is another refresh mode available in the SDRAM. The self refresh is the preferred refresh mode for data retention and low power operation of SDRAM. In self refresh mode, the SDRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing is internally generated to reduce power consumption.The self refresh mode is entered from all banks idle state by asserting low on CS,RAS,CAS and CKE with high on WE. Once the self refresh mode is entered, only CKE state being low matters, all the other inputs including clock are ignored to remain in the self refresh.The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP’s for a minimum time of “t RC” before the SDRAM reaches idle state to begin normal operation. If the system uses burst auto refresh during normal operation, it is recommended to used burst 4096 auto refresh cycles immediately after exiting self refresh.Basic feature And Function Descriptions1. CLOCK SuspendNote: CLK to CLK disable/enable=1 clock2. DQM Operation* Note : 1. DQM makes data out Hi-Z after 2 clocks which should masked by CKE “L”.2. DQM masks both data-in and data-out.3. CAS Interrupt (I)Note : 1. By “Interrupt”, It is possible to stop burst read/write by external command before the end of burst.By “CAS Interrupt”, to stop burst read/write by CAS access; read, write and block write.2. t CCD : CAS to CAS delay. (=1CLK)3. t CDL : Last data in to new column address delay. (= 1CLK).4. CAS Interrupt (II) : Read Interrupted Write & DQM* Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.2. To prevent bus contention, DQM should be issued which makes a least one gap between data in and data out.5. Write Interrupted by Precharge & DQMNote : 1. To inhibit invalid write, DQM should be issued.2. This precharge command and burst write command should be of the same bank, otherwise it is not prechargeinterrupt but only another bank precharge of dual banks operation.6. Precharge7. Auto Precharge* Note : 1. The row active command of the precharge bank can be issued after t RP from this point.The new read/write command of other active bank can be issued from this point.At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.8. Burst Stop & Interrupted by Precharge9. MRSNote : 1. t RDL : 1CLK 2. t BDL : 1CLK; Last data in to burst stop delay.Read or write burst stop command is valid at every burst length.3. Number of valid output data after row precharge or burst stop: 1,2 for CAS latency = 2, 3 respectively.4. PRE: All banks precharge if necessary.MRS can be issued only when all banks are in precharged state.10. Clock Suspend Exit & Power Down Exit11. Auto Refresh & Self Refresh* Note : 1. Active power down : one or more bank active state.2. Precharge power down : both bank precharge state.3. The auto refresh is the same as CBR refresh of conventional DRAM.No precharge commands are required after Auto Refresh command.During t RC from auto refresh command, any other command can not be accepted.4. Before executing auto/self refresh command, both banks must be idle state.5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.6. During self refresh mode, refresh interval and refresh operation are performed internally.After self refresh entry, self refresh mode is kept while CKE is LOW.During self refresh mode, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.During t RC from self refresh exit command, any other command can not be accepted.Before/After self refresh mode, burst auto refresh cycle (4K cycles ) is recommended.12. About Burst Type ControlSequential counting At MRS A3=”0”. See the BURST SEQUENCE TABE.(BL=4,8) BL=1,2,4,8 and full page wrap around.BasicMODEInterleave counting At MRS A3=” 1”. See the BURST SEQUENCE TABE.(BL=4,8) BL=4,8 At BL=1,2 Interleave Counting = Sequential CountingRandom MODE Random column Accesst CCD = 1 CLKEvery cycle Read/Write Command with random column address can realizeRandom Column Access.That is similar to Extended Data Out (EDO) Operation of convention DRAM.13. About Burst Length ControlPower On Sequence & Auto RefreshCKECSRASCASADDRBS0, BS1A10/APWEDQMDQ(A-Bank)Single Bit Read-Write-Read Cycles (Same Page) @CAS Latency=3, Burst Length=1CLOCKCKECSRASCASADDRBS0, BS1A10/APWEDQMDQ* Note : 1. All inputs can be don’t care when CS is high at the CLK high going edge.2. Bank active & read/write are controlled by BS0, BS1.BS1 BS0 Active & Read/WriteA0 0 BankB0 1 BankC1 0 BankD1 1 Bank3. Enable and disable auto precharge function are controlled by A10/AP in read/write command.A10/AP BS1 BS0Operation0 0 Disable auto precharge, leave bank A active at end of burst.0 1 Disable auto precharge, leave bank B active at end of burst.1 0 Disable auto precharge, leave bank C active at end of burst.1 1 Disable auto precharge, leave bank D active at end of burst.0 0 Enable auto precharge, precharge bank A at end of burst.0 1 Enable auto precharge, precharge bank B at end of burst.11 0 Enable auto precharge, precharge bank C at end of burst.1 1 Enable auto precharge, precharge bank D at end of burst.4. A10/AP and BS0, BS1 control bank precharge when precharge command is asserted.A10/AP BS1 BS0 PrechargeA0 0 0 BankB0 0 1 BankC0 1 0 BankD0 1 1 BankBanks1 X X All。
DL5223B-T1中文资料
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元器件交易网
SENSITRON SEMICONDUCTOR
Data Sheet 2596, Rev. -
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元器件交易网 SENSITRON SEMICONDUCTOR
TECHNICAL DATA
DISCLAIMER: 1- The information given herein, including the specifications and dimensions, is subject to change without prior notice to improve product characteristics. Before ordering, purchasers are advised to contact the Sensitron Semiconductor sales department for the latest version of the datasheet(s). 2- In cases where extremely high reliability is required (such as use in nuclear power control, aerospace and aviation, traffic equipment, medical equipment, and safety equipment), safety should be ensured by using semiconductor devices that feature assured safety or by means of users’ fail-safe precautions or other arrangement. 3- In no event shall Sensitron Semiconductor be liable for any damages that may result from an accident or any other cause during operation of the user’s units according to the datasheet(s). Sensitron Semiconductor assumes no responsibility for any intellectual property claims or any other problems that may result from applications of information, products or circuits described in the datasheets. 4- In no event shall Sensitron Semiconductor be liable for any failure in a semiconductor device or any secondary damage resulting from use at a value exceeding the absolute maximum rating. 5- No license is granted by the datasheet(s) under any patents or other rights of any third party or Sensitron Semiconductor. 6- The datasheet(s) may not be reproduced or duplicated, in any form, in whole or part, without the expressed written permission of Sensitron Semiconductor. 7- The products (technologies) described in the datasheet(s) are not to be provided to any party whose purpose in their application will hinder maintenance of international peace and safety nor are they to be applied to that purpose by their direct purchasers or any third party. When exporting these products (technologies), the necessary procedures are to be taken in accordance with related laws and regulations.
A1323LUA-T中文资料
A1323LUA-T中文资料A1321, A1322, and A1323recoverability after temperature cycling. Having the Hallelement and an amplifier on a single chip minimizes many problems normallyassociated with low-level analog signals.Output precision is obtained by internal gain and offset trim adjustments made at end-of-line during the manufacturing process.The A132X family is provided in a 3-pin single in-line package (UA) and a 3-pin surface mount package (LH). Each package isavailable in a lead (Pb) free version (suffix, –T) , with a 100% mattetin plated leadframe.Description (continued)Ratiometric Linear Hall Effect Sensorfor High-T emperature OperationA1321, A1322, and A1323Selection GuidePart Number Pb-free 1Packing 2Mounting Ambient, T A(oC)Sensitivity, Typ. (mV/G)A1321ELHLT-T Yes 7-in. reel, 3000 pieces/reel Surface Mount –40 to 855.000A1321EUA-T Yes Bulk, 500 pieces/bag SIP through hole A1321LLHLT-T Yes 7-in. reel, 3000 pieces/reel Surface Mount –40 to 150A1321LUA-T Yes Bulk, 500 pieces/bag SIP through hole A1322ELHLT-T Yes 7-in. reel, 3000 pieces/reel Surface Mount –40 to 853.125A1322EUA-T Yes Bulk, 500 pieces/bag SIP through hole A1322LLHLT-T Yes 7-in. reel, 3000 pieces/reel Surface Mount –40to 150A1322LUA-T Yes Bulk, 500 pieces/bag SIP through hole A1323ELHLT-T Yes 7-in. reel, 3000 pieces/reel Surface Mount –40 to 852.500A1323EUA-T Yes Bulk, 500 pieces/bag SIP through hole A1323LLHLT-T Yes 7-in. reel, 3000 pieces/reel Surface Mount –40 to 150A1323LUA-TYesBulk, 500 pieces/bagSIP through hole1Pb-based variants are being phased out of the product line.a. Certain variants cited in this footnote are in production but have been determined to be LAST TIME BUY . This classification indicates that sale of this device is currently restricted to existing customer applications. The device should not be purchased for new design applications because obsolescence in the near future is probable. Samples are no longer available. Status change: October 31, 2006. Deadlilne for receipt of LAST TIME BUY ORDERS: April 27, 2007. These variants include: A1322ELHLT, A1322EUA, and A1323LLHLT.b. Certain variants cited in this footnote are in production but have been determined to be NOT FOR NEW DESIGN. This classification indicates that sale of this device is currently restricted to existing customer applications. The device should not be purchased for new design applications because obsolescence in the near future is probable. Samples are no longer available. Status change: May 1, 2006. These variants include: A1321ELHLT, A1321EUA, A1321LLHLT, A1321LUA, A1322LLHLT, A1322LUA, A1323ELHLT, A1323EUA, and A1323LUA.2Contact Allegro for additional packing options.Absolute Maximum RatingsCharacteristicSymbol NotesRating Units Supply Voltage V CC *Additional current draw may be observed atvoltages above the minimum supply Zener clamp voltage, V Z(min), due to the Zener diode turning on.8V Output VoltageV OUT 8V Reverse Supply Voltage V RCC –0.1V Reverse Supply Voltage V RCC –0.1V Output Sink CurrentI OUT 10mA Operating Ambient Temperature T A Range E –40 to 85oC Range L–40 to 150oC Maximum Junction T emperature T J (max)165oC Storage TemperatureT stg–65 to 170oCRatiometric Linear Hall Effect Sensorfor High-T emperature OperationA1321, A1322, and A1323DEVICE CHARACTERISTICS 1 over operating temperature (T A ) range, unless otherwise notedCharacteristic Symbol Test Conditions Min.Typ.2Max.Units Electrical Characteristics; V CC = 5 V, unless otherwise noted Supply Voltage V cc(op)Operating; Tj < 165°C4.55.0 5.5V Supply Current I cc B = 0, I out = 0–5.68mA Quiescent Voltage V out(q) B = 0, T A = 25oC, I out = 1 mA 2.4252.5 2.575V Output Voltage 3V out(H) B = +X , I out = –1 mA –4.7–V V out(L)B = –X , I out = 1 mA –0.2–V Output Source Current Limit 3I out(LM) B = –X , V out → 0–1.0–1.5–mA Supply Zener Clamp Voltage V Z I cc = 11 mA = I cc(max) + 368.3–V Output Bandwidth BW –30–kHz Clock Frequency fC –150–kHz Output Characteristics; over V CC range, unless otherwise notedNoise, Peak-to-Peak 4V N A1321; C bypass = 0.1 μF, no load ––40mV A1322; C bypass = 0.1 μF, no load ––25mV A1323; C bypass = 0.1 μF, no load ––20mV Output Resistance R out I out ≤ ±1 mA –1.53ΩOutput Load Resistance R L I out ≤ ±1 mA, VOUT to GND 4.7––k ΩOutput Load Capacitance C LVOUT to GND ––10nF1 Negative current is de ? ned as conventional current coming out of (sourced from) the speci ? ed device terminal.2 Typical data is at T A= 25°C. They are for initial design estimations only, and assume optimum manufacturing and applicationconditions. Performance may vary for individual units, within the speci ? ed maximum and minimum limits.3 In these tests, the vector X is intended to represent positiveand negative ? elds suf ? cient to swing the output driver between fully OFF and saturated (ON), respectively. It is NOT intended to indicate a range of linear operation.4 Noise speci ? cation includes both digital and analog noise.Ratiometric Linear Hall Effect Sensorfor High-T emperature OperationA1321, A1322, and A1323MAGNETIC CHARACTERISTICS 1,2 over operating temperature range, T A ; V CC = 5 V, I out = –1 mA; unless otherwise notedCharacteristics Symbol Test Condition Min Typ 3Max Units 4Sensitivity 5Sens A1321; T A = 25oC 4.750 5.000 5.250mV/GA1322; T A = 25oC2.9693.125 3.281mV/G A1323; T A = 25oC2.375 2.500 2.625mV/G Delta V out(q) as a func-tion of temperatureV out(q)(ΔT)De ? ned in terms of magnetic ? ux density, B ––±10GRatiometry, V out(q)V out(q)(ΔV)––±1.5%Ratiometry, Sens ΔSens (ΔV)––±1.5%Positive Linearity Lin+––±1.5%Negative Linearity Lin–––±1.5%Symmetry Sym ––±1.5%UA PackageDelta Sens at T A = max 5ΔSens (TAmax)From hot to room temperature –2.5 –7.5%Delta Sens at T A = min 5ΔSen s (TAmin)From cold to room temperature –6 –4%Sensitivity Drift 6Sens Drift T A = 25°C; after temperature cycling and over time –12%LH PackageDelta Sens at T A = max 5ΔSens (TAmax)From hot to room temperature –5 –5%Delta Sens at T A = min 5ΔSens (TAmin)F rom cold to room temperature –3.5 –8.5%Sensitivity Drift 6Sens Drift T A = 25°C; after temperature cycling and over time –0.3282%1 Additional information on chracteristics is provided in the section Characteristics De ? nitions, on the next page.2 Negative current is de ? ned as conventional current coming out of (sourced from) the speci ? ed device terminal.3 Typical data is at T A= 25°C, except for ΔSens, and at x.x Sens. Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the speci ? ed maximum and minimum limits. In addition, the typical values vary with gain.4 10G = 1 millitesla.5 After 150oC pre-bake and factory programming.6 Sensitivity drift is the amount of recovery with time.Ratiometric Linear Hall Effect Sensorfor High-T emperature OperationA1321, A1322, and A1323Quiescent Voltage Output. In the quiescent state (nomagnetic ? eld), the output equals one half of the supply voltage over the operating voltage range and the operating temperature range. Due to internal component tolerances and thermal con-siderations, there is a tolerance on the quiescent voltage output both as a function of supply voltage and as a function of ambient temperature. For purposes of speci ? cation, the quiescent voltage output as a function of temperature is de ? ned in terms of mag-netic ? ux density, B, as:This calculation yields the device’s equivalent accuracy,over the operating temperature range, in gauss (G).Sensitivity. The presence of a south-pole magnetic ? eld per-pendicular to the package face (the branded surface) increases the output voltage from its quiescent value toward the supply voltage rail by an amount proportional to the magnetic ? eld applied. Conversely, the application of a north pole will decrease the output voltage from its quiescent value. This proportionality is speci ? ed as the sensitivity of the device and is de ? ned as:The stability of sensitivity as a function of temperature is de ? ned as:Characteristic De ? nitionsRatiometric. The A132X family features a ratiometric output.The quiescent voltage output and sensitivity are proportional to the supply voltage (ratiometric).The percent ratiometric change in the quiescent voltage output is de ? ned as:and the percent ratiometric change in sensitivity isde ? ned as:Linearity and Symmetry. The on-chip output stageis designed to provide a linear output with a supply voltage of 5 V . Although application of very high magnetic ? elds will not damage these devices, it will force the output into a non-linear region. Linearity in percent is measured and de ? ned as: and output symmetry as:ΔV out(q)(ΔΤ)V out(q)(ΤΑ)V out(q)(25oC )Sens (25oC )–=(1)2BV out(–B)V out(+B )Sens –=ΔSens (ΔΤ)Sens (ΤΑ) Sens (25oC )Sens (25oC )–=× 100%(2)(3)V out(q)(V CC )V out(q)(5V)ΔV out(q)(ΔV)=× 100%V CC 5V(4)V CC 5V=× 100%ΔSens (ΔV )Sens (V CC )Sens (5V )(5)–=× 100%Lin+V out(+B)2(V out(+B /2)–V out(q))V out(q)(6) –=× 100%Lin–V out(–B)2(V out(–B /2)–V out(q))V out(q)(7)–=× 100%Sym V out(+B)V out(q)–V out(–B)V out(q)(8)Ratiometric Linear Hall Effect Sensor for High-T emperature OperationA1321, A1322, and A1323Typical Characteristics(30 pieces, 3 fabrication lots)Continued on the next page... Ratiometric Linear Hall Effect Sensor for High-T emperature OperationA1321, A1322, and A1323Typical Characteristics, continued (30 pieces, 3 fabrication lots)Ratiometric Linear Hall Effect Sensorfor High-T emperature OperationA1321, A1322, and A1323THERMAL CHARACTERISTICS may require derating at maximum conditions, see application informationCharacteristicSymbolTest Conditions*Value Units Package Thermal ResistanceR θJAPackage LH, 1-layer PCB with copper limited to solder pads 228oC/W Package LH, 2-layer PCB with 0.463 in.2 of copper area each side connected by thermal vias110oC/W Package UA, 1-layer PCB with copper limited to solder pads165oC/W*Additional thermal information available on Allegro website.654321Temperature (oC)M a x i m u m A l l o w a b l e V C C (V ) Power Derating CurveV CC(min)V CC(max)1002003004005006007008009001000110012001300140015 00160017001800190020406080100120140160180Temperature (°C)P o w e r D i s s i p a t i o n , P D (m W )Power Dissipation versus Ambient TemperatureRatiometric Linear Hall Effect Sensorfor High-T emperature OperationA1321, A1322, and A1323Power DeratingThe device must be operated below the maximum junction temperature of the device, T J(max). Under certain combinations of peak conditions, reliable operation may require derating sup-plied power or improving the heat dissipation properties of the application. This section presents a procedure for correlating factors affecting operating T J . (Thermal data is also available on the Allegro MicroSystems Web site.)The Package Thermal Resistance, R θJA , is a ? gure of merit sum-marizing the ability of the application and the device to dissipate heat from the junction (die), through all paths to the ambient air. Its primary component is the Effective Thermal Conductivity, K, of the printed circuit board, including adjacent devices and traces. Radiation from the die through the device case, R θJC , is relatively small component of R θJA . Ambient air temperature, T A , and air motion are signi ? cant external factors, damped by overmolding.The effect of varying power levels (Power Dissipation, P D ), can be estimated. The following formulas represent the fundamental relationships used to estimate T J , at P D . P D = V IN × I IN (1)ΔT = P D × R θJA (2)T J = T A + ΔT(3)For example, given common conditions such as: T A = 25°C,V CC = 12 V, I CC = 4 mA, and R θJA = 140 °C/W, then: P D = V CC × I CC = 12 V × 4 mA = 48 mW ΔT = P D × R θJA = 48 mW × 140 °C/W = 7°CT J = T A + ΔT = 25°C + 7°C = 32°CA worst-case estimate, P D(max), represents the maximum allow-able power level (V CC(max), I CC(max)), without exceeding T J(max), at a selected R θJA and T A .Example : Reliability for V C C at T A = 150°C, package UA, using minimum-K PCB.Observe the worst-case ratings for the device, speci ? cally: R θJA = 165°C/W, T J(max) = 165°C, V CC(max) = 5.5 V , and I CC(max) = 8 mA.Calculate the maximum allowable power level, P D(max). First, invert equation 3:ΔT max = T J(max) –T A = 165 °C –150 °C = 15 °CThis provides the allowable increase to T J resulting from internal power dissipation. Then, invert equation 2:P D(max) = ΔT max ÷ R θJA = 15°C ÷ 165 °C/W = 91 mW Finally, invert equation 1 with respect to voltage: V CC(est) = P D(max) ÷ I CC(max) = 91 mW ÷ 8 mA = 11.4 V The result indicates that, at T A , the application and device can dissipate adequate amounts o f heat at voltages ≤V CC(est).Compare V CC(est) to V CC(max). If V CC(est) ≤ V CC(max), then reli-able operation between V CC(est) and V CC(max) requires enhanced R θJA . If V CC(est) ≥ V CC(max), then operation between V CC(est) and V CC(max) is reliable under these conditions.Ratiometric Linear Hall Effect Sensorfor High-T emperature OperationA1321, A1322, and A1323Package LH, 3-Pin; (SOT-23W)Terminal ListSymbol NumberDescriptionPackage LH Package UAVCC 11Connects power supply to chip VOUT 23Output from circuit GND32GroundPackage LHPackage UAPin-out Drawings213Ratiometric Linear Hall Effect Sensor for High-T emperature OperationA1321, A1322, and A1323The products described herein are manufactured under one or more of the following U.S. patents: 5,045,920; 5,264,783;5,442,283; 5,389,889; 5,581,179; 5,517,112; 5,619,137; 5,621,319; 5,650,719; 5,686,894; 5,694,038; 5,729,130; 5,917,320; and other patents pending.Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de p ar t ures from the detail spec i ? c a t ions as may be required to permit improvements in the per f or m ance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current.Allegro products are not authorized for use as critical components in life-support devices or sys t ems without express written approval. The in f or m a t ion in c lud e d herein is believed to be ac c u r ate and reliable. How e v e r, Allegro MicroSystems, Inc. assumes no re s pon s i b il i t y for its use; nor for any in f ringe m ent of patents or other rights of third parties which may result from its use.Copyright ? 2004, 2006, Allegro MicroSystems, Inc.Package UA, 3-Pin SIP。
ATtiny11-6SI资料
1Features•Utilizes the AVR ® RISC Architecture•High-performance and Low-power 8-bit RISC Architecture–90 Powerful Instructions – Most Single Clock Cycle Execution –32 x 8 General Purpose Working Registers –Up to 8 MIPS Throughput at 8 MHz •Nonvolatile Program and Data Memory –1K Byte of Flash Program MemoryIn-System Programmable (ATtiny12)Endurance: 1,000 Write/Erase Cycles (ATtiny11/12)–64 Bytes of In-System Programmable EEPROM Data Memory for ATtiny12Endurance: 100,000 Write/Erase Cycles–Programming Lock for Flash Program and EEPROM Data Security •Peripheral Features–Interrupt and Wake-up on Pin Change–One 8-bit Timer/Counter with Separate Prescaler –On-chip Analog Comparator–Programmable Watchdog Timer with On-chip Oscillator •Special Microcontroller Features–Low-power Idle and Power-down Modes –External and Internal Interrupt Sources–In-System Programmable via SPI Port (ATtiny12)–Enhanced Power-on Reset Circuit (ATtiny12)–Internal Calibrated RC Oscillator (ATtiny12)•Specification–Low-power, High-speed CMOS Process Technology –Fully Static Operation•Power Consumption at 4 MHz, 3V , 25°C –Active: 2.2 mA –Idle Mode: 0.5 mA–Power-down Mode: <1 µA •Packages–8-pin PDIP and SOIC •Operating Voltages–1.8 - 5.5V for ATtiny12V-1–2.7 - 5.5V for ATtiny11L-2 and ATtiny12L-4–4.0 - 5.5V for ATtiny11-6 and ATtiny12-8•Speed Grades–0 - 1.2 MHz (ATtiny12V-1)–0 - 2 MHz (ATtiny11L-2)–0 - 4 MHz (ATtiny12L-4)–0 - 6 MHz (ATtiny11-6)–0 - 8 MHz (ATtiny12-8)Pin Configuration8-bit Microcontroller with 1K Byte2ATtiny11/121006D–AVR–07/03DescriptionThe ATtiny11/12 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny11/12achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed.The AVR core combines a rich instruction set with 32 general-purpose working regis-ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.ATtiny11 Block DiagramThe ATtiny11 provides the following features: 1K bytes of Flash, up to five general-pur-pose I/O lines, one input line, 32general-purpose working registers, an 8-bit timer/counter, internal and external interrupts, programmable Watchdog Timer with internal oscillator, and two software-selectable power-saving modes. The Idle Mode stops the CPU while allowing the timer/counters and interrupt system to continue func-tioning. The Power-down Mode saves the register contents but freezes the oscillator,disabling all other chip functions until the next interrupt or hardware reset. The wake-up or interrupt on pin change features enable the ATtiny11 to be highly responsive to exter-nal events, still featuring the lowest power consumption while in the power-down modes.The device is manufactured using Atmel’s high-density nonvolatile memory technology.By combining an RISC 8-bit CPU with Flash on a monolithic chip, the Atmel ATtiny11 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications.The ATtiny11 AVR is supported with a full suite of program and system development tools including: macro assemblers, program debugger/simulators, in-circuit emulators,and evaluation kits.3ATtiny11/121006D–AVR–07/03Figure 1. The ATtiny11 Block Diagram4ATtiny11/121006D–AVR–07/03ATtiny12 Block DiagramFigure 2. The ATtiny12 Block DiagramThe ATtiny12 provides the following features: 1K bytes of Flash, 64 bytes EEPROM, up to six general-purpose I/O lines, 32general-purpose working registers, an 8-bit timer/counter, internal and external interrupts, programmable Watchdog Timer with internal oscillator, and two software-selectable power-saving modes. The Idle Mode stops the CPU while allowing the timer/counters and interrupt system to continue func-tioning. The Power-down Mode saves the register contents but freezes the oscillator,disabling all other chip functions until the next interrupt or hardware reset. The wake-up or interrupt on pin change features enable the ATtiny12 to be highly responsive to exter-nal events, still featuring the lowest power consumption while in the power-down modes.The device is manufactured using Atmel’s high-density nonvolatile memory technology.By combining an RISC 8-bit CPU with Flash on a monolithic chip, the Atmel ATtiny12 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications.5ATtiny11/121006D–AVR–07/03The ATtiny12 AVR is supported with a full suite of program and system development tools including: macro assemblers, program debugger/simulators, in-circuit emulators,and evaluation kits.Pin DescriptionsVCC Supply voltage pin.GNDGround pin.Port B (PB5..PB0)Port B is a 6-bit I/O port. PB4..0 are I/O pins that can provide internal pull-ups (selected for each bit). On ATtiny11, PB5 is input only. On ATtiny12, PB5 is input or open-drain output. The port pins are tri-stated when a reset condition becomes active, even if the clock is not running. The use of pins PB5..3 as input or I/O pins is limited, depending on reset and clock settings, as shown below.Notes:1.“Used” means the pin is used for reset or clock purposes.2.“-” means the pin function is unaffected by the option.3.Input means the pin is a port input pin.4.On A Ttiny11, PB5 is input only. On A Ttiny12, PB5 is input or open-drain output.5.I/O means the pin is a port input/output pin.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.Clock OptionsThe device has the following clock source options, selectable by Flash fuse bits as shown:Table 2. PB5..PB3 Functionality vs. Device Clocking OptionsDevice Clocking Option PB5PB4PB3External Reset Enabled Used (1)-(2)-External Reset Disabled Input (3)/I/O (4)--External Crystal-Used Used External Low-frequency Crystal -Used Used External Ceramic Resonator -Used Used External RC Oscillator -I/O (5)Used External Clock -I/O Used Internal RC Oscillator -I/OI/OTable 3. Device Clocking Options SelectDevice Clocking OptionATtiny11 CKSEL2..0ATtiny12 CKSEL3..0External Crystal/Ceramic Resonator 1111111 - 1010External Low-frequency Crystal 1101001 - 1000External RC Oscillator1010111 - 01016ATtiny11/121006D–AVR–07/03The various choices for each clocking option give different start-up times as shown in Table 7 on page 18 and Table 9 on page 20.Internal RC OscillatorThe internal RC oscillator option is an on-chip oscillator running at a fixed frequency of 1MHz in ATtiny11 and 1.2 MHz in ATtiny12. If selected, the device can operate with no external components. The device is shipped with this option selected. On ATtiny11, the Watchdog Oscillator is used as a clock, while ATtiny12 uses a separate calibrated oscillator.Crystal OscillatorXTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 3. Either a quartz crystal or a ceramic resonator may be used. Maximum frequency for crystal and resona-tors is 4 MHz. Minimum voltage for running on a low-frequency crystal is 2.5V.Figure 3. Oscillator ConnectionsNote:When using the MCU Oscillator as a clock for an external device, an HC buffer should be connected as indicated in the figure.External ClockTo drive the device from an external clock source, XTAL1 should be driven as shown in Figure 4.Figure 4. External Clock Drive ConfigurationInternal RC Oscillator 1000100 - 0010External Clock0000001 - 0000Reserved Other Options -Table 3. Device Clocking Options Select (Continued)Device Clocking Option ATtiny11 CKSEL2..0ATtiny12 CKSEL3..07ATtiny11/121006D–AVR–07/03External RC OscillatorFor timing insensitive applications, the external RC configuration shown in Figure 5 can be used. For details on how to choose R and C, see Table 29 on page 59. The external RC oscillator is sensitive to noise from neighboring pins, and to avoid problems, PB5put pin.Figure 5. External RC Configuration8ATtiny11/121006D–AVR–07/03Architectural OverviewThe fast-access register file concept contains 32 x 8-bit general-purpose working regis-ters with a single-clock-cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the reg-ister file – in one clock cycle.Two of the 32 registers can be used as a 16-bit pointer for indirect memory access. This pointer is called the Z-pointer, and can address the register file and the Flash program memory.The ALU supports arithmetic and logic functions between registers or between a con-stant and a register. Single-register operations are also executed in the ALU. Figure 2shows the ATtiny11/12 AVR RISC microcontroller architecture. The AVR uses a Har-vard architecture concept with separate memories and buses for program and data memories. The program memory is accessed with a two-stage pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program mem-ory. This concept enables instructions to be executed in every clock cycle. The program memory is reprogrammable Flash memory.With the relative jump and relative call instructions, the whole 512 address space is directly accessed. All AVR instructions have a single 16-bit word format, meaning that every program memory address contains a single 16-bit instruction.During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is a 3-level-deep hardware stack dedicated for subrou-tines and interrupts.The I/O memory space contains 64 addresses for CPU peripheral functions as control registers, timer/counters, and other I/O functions. The memory spaces in the AVR archi-tecture are all linear and regular memory maps.9ATtiny11/121006D–AVR–07/03Figure 6. The ATtiny11/12 AVR RISC ArchitectureA flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All the different interrupts have a sepa-rate interrupt vector in the interrupt vector table at the beginning of the program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority.General-purpose Register FileFigure 7 shows the structure of the 32 general-purpose registers in the CPU.Figure 7. AVR CPU General-purpose Working RegistersAll the register operating instructions in the instruction set have direct- and single-cycle access to all registers. The only exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, and ORI between a constant and a register and the LDI instruction for load-immediate constant data. These instructions apply to the second half of the registers in the register file – R16..R31. The general SBC, SUB, CP, AND,7R0 R1R2General-…purpose …Working R28RegistersR29R30 (Z-register low byte)R31 (Z-register high byte)10ATtiny11/121006D–AVR–07/03OR and all other operations between two registers or on a single register apply to the entire register file.Registers 30 and 31 form a 16-bit pointer (the Z-pointer) which is used for indirect Flash memory and register file access. When the register file is accessed, the contents of R31are discarded by the CPU.ALU – Arithmetic Logic UnitThe high-performance AVR ALU operates in direct connection with all the 32 general-purpose working registers. Within a single clock cycle, ALU operations between regis-ters in the register file are executed. The ALU operations are divided into three main categories – arithmetic, logic and bit-functions. Some microcontrollers in the AVR prod-uct family feature a hardware multiplier in the arithmetic part of the ALU.Flash Program MemoryThe ATtiny11/12 contains 1K bytes on-chip Flash memory for program storage. Since all instructions are single 16-bit words, the Flash is organized as 512 x 16 words. The Flash memory has an endurance of at least 1000 write/erase cycles.The ATtiny11/12 Program Counter is 9 bits wide, thus addressing the 512 words Flash program memory.See page 46 for a detailed description on Flash memory programming.Program and Data Addressing ModesThe ATtiny11/12 AVR RISC Microcontroller supports powerful and efficient addressing modes. This section describes the different addressing modes supported in the ATtiny11/12. In the figures, OP means the operation code part of the instruction word.To simplify, not all figures show the exact location of the addressing bits.Register Direct, Single Register RdFigure 8. Direct Single-register AddressingThe operand is contained in register d (Rd).11ATtiny11/121006D–AVR–07/03Register IndirectFigure 9. Indirect Register AddressingThe register accessed is the one pointed to by the Z-register (R31, R30).Register Direct, Two Registers Rd and RrFigure 10. Direct Register Addressing, Two Registers Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).I/O DirectFigure 11. I/O Direct AddressingOperand address is contained in 6 bits of the instruction word. n is the destination or source register address.12ATtiny11/121006D–AVR–07/03Relative Program Addressing, RJMP and RCALLFigure 12. Relative Program Memory Addressing Program execution continues at address PC + k + 1. The relative address k is -2048 to 2047.Constant Addressing Using the LPM InstructionFigure 13. Code Memory Constant AddressingConstant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 511), the LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB =1).Subroutine and Interrupt Hardware StackThe ATtiny11/12 uses a 3-level-deep hardware stack for subroutines and interrupts. Thehardware stack is 9 bits wide and stores the program counter (PC) return address while subroutines and interrupts are executed.RCALL instructions and interrupts push the PC return address onto stack level 0, and the data in the other stack levels 1-2 are pushed one level deeper in the stack. When a RET or RETI instruction is executed the returning PC is fetched from stack level 0, and the data in the other stack levels 1-2 are popped one level in the stack.If more than three subsequent subroutine calls or interrupts are executed, the first val-ues written to the stack are overwritten. Pushing four return addresses A1, A2, A3, and A4, followed by four subroutine or interrupt returns, will pop A4, A3, A2, and once moreA2 from the hardware stack.13ATtiny11/121006D–AVR–07/03EEPROM Data MemoryThe ATtiny12 contains 64 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endur-ance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on page 38, specifying the EEPROM Address Register, the EEPROM Data Register, and the EEPROM Control Register.For SPI data downloading, see “Memory Programming” on page 46 for a detailed description.Memory Access and Instruction Execution TimingThis section describes the general access timing concepts for instruction execution and internal memory access.The AVR CPU is driven by the System Clock Ø, directly generated from the external clock crystal for the chip. No internal clock division is used.Figure 14 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access register file concept. This is the basic pipe-lining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.Figure 14. The Parallel Instruction Fetches and Instruction ExecutionsFigure 15 shows the internal timing concept for the register file. In a single clock cycle,an ALU operation using two register operands is executed and the result is stored back to the destination register.Figure 15. Single-cycle ALU Operation14ATtiny11/121006D–AVR–07/03I/O MemoryThe I/O space definition of the ATtiny11/12 is shown in the following table:All the different ATtiny11/12 I/O and peripherals are placed in the I/O space. The differ-ent I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general-purpose working registers and the I/O space. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions.In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the Instruction Set Summary for more details.For compatibility with future devices, reserved bits should be written to zero if accessed.Reserved I/O memory addressed should never be written.The different I/O and peripherals control registers are explained in the following sections.Status Register – SREGThe AVR status register (SREG) at I/O space location $3F is defined as:•Bit 7 - I: Global Interrupt EnableThe global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If theBit 76543210$3F I T H S V N Z C SREGRead/Write R/W R/W R/W R/W R/W R/W R/W R/W InitialValue15ATtiny11/121006D–AVR–07/03global interrupt enable register is cleared (zero), none of the interrupts are enabled inde-pendent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.•Bit 6 - T: Bit Copy StorageThe bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.•Bit 5 - H: Half Carry FlagThe half carry flag H indicates a half-carry in some arithmetic operations. See the Instruction Set description for detailed information.•Bit 4 - S: Sign Bit, S = N ⊕ VThe S-bit is always an exclusive or between the negative flag N and the two’s comple-ment overflow flag V. See the Instruction Set description for detailed information.•Bit 3 - V: Two’s Complement Overflow FlagThe two’s complement overflow flag V supports two’s complement arithmetic. See the Instruction Set description for detailed information.•Bit 2 - N: Negative FlagThe negative flag N indicates a negative result from an arithmetical or logical operation.See the Instruction Set description for detailed information.•Bit 1 - Z: Zero FlagThe zero flag Z indicates a zero result from an arithmetical or logical operation. See the Instruction Set description for detailed information.•Bit 0 - C: Carry FlagThe carry flag C indicates a carry in an arithmetical or logical operation. See the Instruc-tion Set description for detailed information.Note that the status register is not automatically stored when entering an interrupt rou-tine and restored when returning from an interrupt routine. This must be handled by software.Reset and Interrupt HandlingThe ATtiny11 provides four different interrupt sources and the ATtiny12 provides five.These interrupts and the separate reset vector each have a separate program vector in the program memory space. All the interrupts are assigned individual enable bits which must be set (one) together with the I-bit in the status register in order to enable the interrupt.The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors. The complete list of vectors is shown in Table 5. The list also determines the priority levels of the different interrupts. The lower the address, the higher the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0, etc.16ATtiny11/121006D–AVR–07/03The most typical and general program setup for the reset and interrupt vector addresses for the ATtiny11 are:Address LabelsCode Comments$000rjmp RESET ; Reset handler $001rjmp EXT_INT0; IRQ0 handler $002rjmp PIN_CHANGE ;Pin change handler $003rjmp TIM0_OVF ; Timer0 overflow handler $004rjmpANA_COMP; Analog Comparator handler;$005MAIN:<instr> xxx ; Main program start……… …The most typical and general program setup for the reset and interrupt vector addresses for the ATtiny12 are:Address LabelsCode Comments$000rjmp RESET ; Reset handler $001rjmp EXT_INT0; IRQ0 handler $002rjmp PIN_CHANGE ;Pin change handler $003rjmp TIM0_OVF ; Timer0 overflow handler $004rjmp EE_RDY ; EEPROM Ready handler $005rjmpANA_COMP; Analog Comparator handler;$006MAIN:<instr> xxx ; Main program start……… …17ATtiny11/121006D–AVR–07/03Reset SourcesThe ATtiny11/12 provides three or four sources of reset:•Power-on Reset. The MCU is reset when the supply voltage is below the power-on reset threshold (V POT ).•more than 50 ns.•Watchdog Reset. The MCU is reset when the Watchdog timer period expires and the Watchdog is enabled.•Brown-out Reset. The MCU is reset when the supply voltage V CC falls below a certain voltage (A Ttiny12 only).During reset, all I/O registers are then set to their initial values, and the program starts execution from address $000. The instruction placed in address $000 must be an RJMP – relative jump – instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 16 shows the reset logic for the ATtiny11. Figure 17 shows the reset logic for the ATtiny12. Table 6 defines the electrical parameters of the reset circuitry for ATtiny11. Table 8 shows the parameters of the reset circuitry for ATtiny12.Figure 16. Reset Logic for the ATtiny11POT(falling).18ATtiny11/121006D–AVR–07/03Power-on Reset for the ATtiny11A Power-on Reset (POR) circuit ensures that the device is reset from power-on. As shown in Figure 16, an internal timer is clocked from the watchdog timer. This timer pre-vents the MCU from starting a certain period after V CC has reached the Power-on Threshold Voltage – V POT . See Figure 18. The total reset period is the Delay Time-out period – t TOUT . The FSTRT fuse bit in the Flash can be programmed to give a shorter start-up time.The start-up times for the different clock options are shown in the following table. The Watchdog Oscillator is used for timing the start-up time, and this oscillator is voltage dependent as shown in the section “ATtiny11 Typical Characteristics” on page 60.If the built-in start-up delay is sufficient, RESET can be connected to V CC directly or via an external pull-up resistor. By holding the RESET pin low for a period after V CC has been applied, the Power-on Reset period can be extended. Refer to Figure 19 for a tim-ing example on this.19ATtiny11/121006D–AVR–07/03Figure 17. Reset Logic for the ATtiny12Note:1.The Power-on Reset will not work unless the supply voltage has been below V POT(falling).Table 8. Reset Characteristics for the A Ttiny1220ATtiny11/121006D–AVR–07/03Note:1.Due to the limited number of clock cycles in the start-up period, it is recommendedthat Ceramic Resonator be used.This table shows the start-up times from reset. From sleep, only the clock counting part of the start-up time is used. The Watchdog oscillator is used for timing the real-time part of the start-up time. The number of WDT oscillator cycles used for each time-out is shown in Table 10.The frequency of the watchdog oscillator is voltage dependent as shown in the section “ATtiny11 Typical Characteristics” on page 60.Note that the BODLEVEL fuse can be used to select start-up times even if the Brown-out Detection is disabled (by leaving the BODEN fuse unprogrammed).The device is shipped with CKSEL3..0 = 0010.Table 10. Number of Watchdog Oscillator CyclesATtiny11/12Power-on Reset for the ATtiny12A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detec-tion level is nominally 1.4V. The POR is activated whenever V CC is below the detection level. The POR circuit can be used to trigger the start-up reset, as well as detect a fail-ure in supply voltage.The Power-on Reset (POR) circuit ensures that the device is reset from power-on.Reaching the Power-on Reset threshold voltage invokes a delay counter, which deter-mines the delay for which the device is kept in Reset after V CC rise. The time-out period of the delay counter can be defined by the user through the CKSEL fuses. The different selections for the delay period are presented in Table 9. The Reset signal is activated again, without any delay, when the V CC decreases below detection level.CC directly or via after V CC has been applied, the Power-on Reset period can be extended. Refer to Fig-ure 19 for a timing example on this.Figure 18. CC .Figure 19. MCU Start-up, RESET Extended ExternallyExternal ResetAn external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – V RST – on its positive edge, the delay timer starts the MCU after the Time-out period (t TOUT ) has expired.Figure 20. External Reset during OperationBrown-out Detection (ATtiny12)ATtiny12 has an on-chip brown-out detection (BOD) circuit for monitoring the V CC level during the operation. The BOD circuit can be enabled/disabled by the fuse BODEN. When BODEN is enabled (BODEN programmed), and V CC decreases below the trigger level, the brown-out reset is immediately activated. When V CC increases above the trig-ger level, the brown-out reset is deactivated after a delay. The delay is defined by the user in the same way as the delay of POR signal, in Table 5. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 1.8V (BODLEVEL unprogrammed), or 2.7V (BODLEVEL programmed). The trigger level has a hysteresis of 50 mV to ensure spike-free brown-out detection.The BOD circuit will only detect a drop in V CC if the voltage stays below the trigger level for longer than 7 µs for trigger level 2.7V, 24 µs for trigger level 1.8V (typical values). Figure 21. Brown-out Reset during Operation (ATtiny12)Note:The hysteresis on V BOT: V BOT + = V BOT + 25 mV, V BOT- = V BOT - 25 mV.。
A63P73361E-8F资料
128K X 36 Bit Synchronous High Speed SRAM with Preliminary Burst Counter and Flow-through Data OutputDocument Title128K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data OutputRevision HistoryDate Remark Rev. No. History Issue0.0 Initial issue July 7, 2005 Preliminary128K X 36 Bit Synchronous High Speed SRAM with Preliminary Burst Counter and Flow-through Data Output FeaturesFast access times: 6.5/7.5/8.0 ns(153/133/117 MHz)Single 2.5V±5% power supplySynchronous burst functionIndividual Byte Write control and Global WriteThree separate chip enables allow wide range of options for CE control, address pipelining Selectable BURST modeSLEEP mode (ZZ pin) providedAvailable in 100-pin LQFP packageIndustrial operating temperature range: -45°C to +125°C for -I seriesGeneral DescriptionThe A63P73361 is a high-speed SRAM containing 4.5M bits of bit synchronous memory, organized as 128K words by 36 bits.The A63P73361 combines advanced synchronous peripheral circuitry, 2-bit burst control, input registers, output buffer and a 128K X 36 SRAM core to provide a wide range of data RAM applications.The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. Synchronous inputs include all addresses (A0 - A16), all data inputs (I/O1 - I/O36), active LOW chip enable (CE), two additional chip enables (CE2, CE2), burst control inputs (ADSC, ADSP, ADV), byte write enables (BWE, BW1, BW2, BW3, BW4) and Global Write (GW). Asynchronous inputs include output enable (OE), clock (CLK), BURST mode (MODE) and SLEEP mode (ZZ). Burst operations can be initiated with either the address status processor (ADSP) or address status controller (ADSC) input pin. Subsequent burst sequence burst addresses can be internally generated by the A63P73361 and controlled by the burst advance (ADV) pin. Write cycles are internally self-timed and synchronous with the rising edge of the clock (CLK).This feature simplifies the write interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/O1 - I/O9, BW2 controls I/O10 - I/O18, BW3 controls I/O19 - I/O27, and BW4 controls I/O28 - I/O36, all on the condition that BWE is LOW. GW LOW causes all bytes to be written.Pin ConfigurationI/O 20I/O 21VCCQ GNDQ I/O 22I/O 23I/O 24I/O 25GNDQ I/O 26I/O 27VCCQ VCC NC I/O 34GND I/O 28I/O 29VCCQ GNDQ I/O 30I/O 31I/O 32I/O 33GNDQ VCCQ I/O 35I/O 17I/O 16VCCQ GNDQ I/O 15I/O 14I/O 13I/O 12GNDQ VCCQ I/O 11I/O 10GND NC VCC ZZ I/O 8I/O 7VCCQ GNDQ I/O 6I/O 5I/O 4I/O 3GNDQ VCCQ I/O 2I/O 1A 15A 14A 13A 12A 11A 10N CV C CG N DN CA 0A 1A 2A 3A 4A 5M O D EC E 2A 7A 6C L KG N DV C CA 9A 8NC A D VA D S PA D S CO EB W EG WC E 2B W 1B W 2B W 3B W 4C EA 16I/O 9I/O 18I/O 19I/O 36N CN CBlock DiagramCLKPin DescriptionSynchronous Truth Table (See Notes 1 Through 5)Notes: 1. X = "Disregard", H = Logic High, L = Logic Low.WRITE = L means:2.BWx (BW1,BW2,BW3, or BW4) and BWE are low or1)AnyGW is low.2)3. All inputs except OE must be synchronized with setup and hold times around the rising edge (L-H) of CLK.4. For write cycles that follow read cycles, OE must be HIGH before the input data request setup time and heldHIGH throughout the input data hold time.ADSP LOW always initiates an internal Read at the L-H edge of CLK. A Write is performed by setting one or 5.more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. Refer to the Write timing diagram for clarification.Write Truth TableLinear Burst Address Table (MODE = LOW)First Address (External) Second Address (Internal)Third Address (Internal) Fourth Address (Internal) X . . . X00 X . . . X01 X . . . X10 X . . . X11X . . . X01 X . . . X10 X . . . X11 X . . . X00X . . . X10 X . . . X11 X . . . X00 X . . . X01X . . . X11 X . . . X00 X . . . X01 X . . . X10 Interleaved Burst Address Table (MODE = HIGH or NC)First Address (External) Second Address (Internal)Third Address (Internal) Fourth Address (Internal) X . . . X00 X . . . X01 X . . . X10 X . . . X11X . . . X01 X . . . X00 X . . . X11 X . . . X10X . . . X10 X . . . X11 X . . . X00 X . . . X01X . . . X11 X . . . X10 X . . . X01 X . . . X00Absolute Maximum Ratings*Power Supply Voltage (VCC) . . . . . . . . . . -0.5V to +3.6V Voltage Relative to GND for any Pin Except VCC (Vin, Vout) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V Power Dissipation (P D) . . . . . . . . . . . . . . . . . . . . . . . . 2W Storage Temperature (Tbias) . . . . . . . . . . -65°C to 150 °C Storage Temperature (Tstg) . . . . . . . . . . . -55°C to 125°C Operating RangesAmbient TemperatureCommercial (C) Devices . . . . . . . . . . . . . . . 0°C to +70°C Industrial (I) Devices . . . . . . . . . . . . . . . -45°C to +125°C V CC & V CCQ Supply VoltagesV CC for all devices . . ….. . . . . . . . . . . . . . . . . . . . +2.5VV CCQ for all devices . . ….. . . . . . . . . . . . . . . . . . . +2.5V Operating ranges define those limits between which the functionally of the device is guaranteed.*CommentsStresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.Recommended DC Operating Conditions(0°C ≤ T A≤ 70°C, VCC, VCCQ = 2.5V+5% or 2.5V-5%, unless otherwise noted)Symbol Parameter Min.Typ.Max.UnitNote VCC Supply Voltage (Operating Voltage Range) 2.375 2.5 2.625 VVCCQ Isolated Input Buffer Supply 2.375 2.5 2.625 VGND Supply Voltage to GND 0.0 - 0.0 VV IH Input High Voltage 1.7 - VCC+0.3 V 1, 2V IHQ Input High Voltage (I/O Pins) 1.7 - VCC+0.3 VV IL Input Low Voltage -0.3 - 0.7 V 1, 2DC Electrical Characteristics(0°C ≤ T A≤ 70°C, VCC, VCCQ = 2.5V+5% or 2.5V-5%, unless otherwise noted)CapacitanceConditions Symbol Parameter Typ.Max.UnitC IN InputCapacitance 3 4 pFT A = 25 C; f = 1MHzVCC = 2.5VCapacitance 4 5 pFC I/O Input/Output* These parameters are sampled and not 100% tested.AC Characteristics (0°C ≤ T A≤ 70°C, VCC = 2.5V+5% or 2.5V-5%)Notes:1. All voltages refer to GND.2. Overshoot: V IH≤ +2V for t ≤ t KC/2.Undershoot:V IL≥ -0.7V for t ≤ t KC/2.Power-up: V IH≤ +2 and VCC ≤ 1.7Vtfor≤ 200ms3. I CC1 is given with no output current. I CC1 increases with greater output loading and faster cycle times.4. Test conditions assume the output loading shown in Figure 1, unless otherwise specified.5. For output loading, C L = 5pF, as shown in Figure 2. Transition is measured ±150mV from steady state voltage.6. At any given temperature and voltage condition, t KQHZ is less than t KQLZ and t OEHZ is less than t QELZ.7. A WRITE cycle is defined by at least one Byte Write enable LOW and ADSP HIGH for the required setup and holdtimes. A READ cycle is defined by all byte write enables HIGH and (ADSC or ADV LOW) or ADSP LOW for the required setup and hold times.8. OE has no effect when a Byte Write enable is sampled LOW.9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLKADSP or ADSC is LOW and the chip is enabled. All other synchronous inputs must meet the setup and eitherwhenhold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP or ADSC is LOW to remain enabled.10. The load used for V OH, V OL testing is shown in Figure 2. AC load current is higher than the given DC values.AC I/O curves are available upon request.11. "Device Deselected" means device is in POWER-DOWN mode, as defined in the truth table. "Device Selected" meansdevice is active (not in POWER-DOWN mode).12. MODE pin has an internal pulled-up, and ZZ pin has an internal pulled-down. All of then exhibit an input leakagecurrent of 10µA.13. Snooze (ZZ) input is recommended that users plan for four clock cycles to go into SLEEP mode and four clocks toemerge from SLEEP mode to ensure no data is lost.Timing WaveformsRead TimingNotes: 1. QA(2) refers to output from address A2. Q(A2+1) refers to output from the next internal burst address following A2.2.CE and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE does not cause Q to be driven until after the following clock rising edge.CLKADSCADDRESSGW,BWE CE (NOTE 2)ADVOEDOUTDon't Care UndefinedTiming Waveforms (continued)CLKADSPADSCADDRESSOEDIN GWCE(NOTE 2)DOUT(NOTE 5)Don't Care UndefinedWrite TimingNotes: 1. D(A2) refers to output from address A2. D(A2+1) refers to output from the internal burst address immediately following A2.2. Timing forCE2 and CE2 is identical to that for CE. As shown in the above diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.3.OE must be HIGH before the input data setup, and held HIGH throughout the data hold period. This prevents input/output data contention for the period prior to the time Byte Write enable inputs are sampled.4.ADV must be HIGH to permit a Write to the loaded address. 5. Byte Write enables are decided by means of a Write truth table.Timing Waveforms (continued)Read/Write TimingNotes: 1. Q(A4) refers to output from address A4. Q(A4+1) refers to output from the next internal burst address following A4.2.CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE is LOW and CE2 is HIGH, When CE is HIGH, CE2 is HIGH and CE2 is LOW.3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP ,ADSC , or ADV cycle isperformed.4. Byte Write enables are decided by means of a Write truth table.5. Back-to-back READs may be controlled by either ADSP or ADSCCLKADSPADSCADDRESSCE (NOTE 2)ADVOEDINGW,BWE,BW1-BW4(NOTE 3)DOUTBack-to-Back READs Single WRITEWRITEsDon't Care UndefinedAC Test ConditionsInput Pulse Levels GND to 3VInput Rise and Fall Times 1 nsInput Timing Reference Levels 1.5VOutput Reference Levels VccQ/2Output Load See Figures 1 and 2Figure 1. Output Load Equivalent FigureQL=50ΩT2. Output Load EquivalentQOrdering InformationPart No. Access Times (ns) Frequency (MHz) Package A63P73361E-6.5 6.5 153 100LLQFP A63P73361E-6.5F 6.5 153 100L Pb-Free LQFPA63P73361E-7.5 7.5 133 100LLQFP A63P73361E-7.5F 7.5 133 100L Pb-Free LQFPA63P73361E-8 8 117 100LLQFP A63P73361E-8F 8 117 100L Pb-Free LQFPPackage InformationLQFP 100L Outline Dimensions unit: inches/mmNotes:1. Dimensions D and E do not include mold protrusion.2. Dimensions b does not include dambar protrusion.Total in excess of the b dimension at maximum material condition.Dambar cannot be located on the lower radius of the foot.。
A67L9336E-3.8资料
Preliminary1M X 18, 512K X 36 LVTTL, Pipelined ZeBL TM SRAMDocument Title1M X 18, 512K X 36 LVTTL, Pipelined ZeBL TM SRAMRevision HistoryDate Remark Rev. No. History Issue0.0 Initial issue August, 20, 2005 PreliminaryPreliminary1M X 18, 512K X 36 LVTTL, Pipelined ZeBL TM SRAMFeaturesFast access time:2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilizationSignal +3.3V ± 5% power supplyIndividual Byte Write control capabilityClock enable (CEN) pin to enable clock and suspend operations Clock-controlled and registered address, data and control signalsRegistered output for pipelined applicationsThree separate chip enables allow wide range of options for CE control, address pipeliningInternally self-timed write cycleSelectable BURST mode (Linear or Interleaved)SLEEP mode (ZZ pin) providedAvailable in 100 pin LQFP packageGeneral DescriptionThe AMIC Zero Bus Latency (ZeBL TM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.The A67L0618, A67L9336 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. The synchronous inputs include all address, all data inputs, active low chip enable (CE), two additional chip enables for easy depth expansion (CE2, CE2), cycle start input (ADV/), synchronous clock enable (CEN), byte write enables (,,BW3,) and read/write (R/W). Asynchronous inputs include the output enable (OE), clock (CLK), SLEEP mode (ZZ, tied LOW if unused) and burst mode (MODE). Burst Mode can provide either interleaved or linear operation, burst operation can be initiated by synchronous address Advance/Load (ADV/) pin in Low state. Subsequent burst address can be internally generated by the chip and controlled by the same input pin ADV/ in High state. Write cycles are internally self-time and synchronous with the rising edge of the clock input and when R/W is Low. The feature simplified the write interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/Oa pins; BW2controls I/Ob pins; BW3controls I/Oc pins; and BW4controls I/Od pins. Cycle types can only be defined when an address is loaded.The SRAM operates from a +3.3V power supply, and all inputs and outputs are LVTTL-compatible. The device is ideally suited for high bandwidth utilization systems.Pin ConfigurationBlock Diagram (512K X 36)Block Diagram (1M X 18)Pin DescriptionPin Description (continued)Truth Table (Notes 5 - 7)Notes:1. Continue Burst cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ orWRITE) is chosen in the initial Begin Burst cycle. A Continue Deselect cycle can only be entered if a Deselect cycle is executed first.2. Dummy READ and WRITE Abort cycles can be considered NOPs because the device performs no operation. A WRITEAbort means a WRITE command is given, but no operation is performed.3. OE may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off theoutput drivers during a WRITE cycle. Some users may use OE when the bus turn-on and turn-off times do not meet their requirements.4. If an Ignore Clock Edge command occurs during a READ operation, the I/O bus will remain active (Low-Z). If it occursduring a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the Ignored Clock Edge cycle.5. X means “Don’t Care.” H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BW1,BW2,BW3and BW4) are HIGH. BWx = L means one or more byte write signals are LOW.6. BW1enables WRITEs to Byte “a” (I/Oa pins); BW2enables WRITEs to Byte “b” (I/Ob pins); BW3enables WRITEs toByte “c” (I/Oc pins); BW4 enables WRITEs to Byte “d” (I/Od pins).7. The address counter is incremented for all Continue Burst cycles.Partial Truth Table for READ/WRITE Commands (X18)Note : Using and BYTE WRITE(s), any one or more bytes may be written.Partial Truth Table for READ/WRITE Commands (X36)Note : Using R/W and BYTE WRITE(s), any one or more bytes may be written.Linear Burst Address Table (MODE = LOW)(Internal)AddressAddressFirst Address (External) Second(Internal)Third Address (Internal) Fourth X . . . X00 X . . . X01 X . . . X10 X . . . X11X . . . X01 X . . . X10 X . . . X11 X . . . X00X . . . X10 X . . . X11 X . . . X00 X . . . X01X . . . X11 X . . . X00 X . . . X01 X . . . X10 Interleaved Burst Address Table (MODE = HIGH or NC)Address(Internal)(Internal)Third Address (Internal) Fourth First Address (External) SecondAddressX . . . X00 X . . . X01 X . . . X10 X . . . X11X . . . X01 X . . . X00 X . . . X11 X . . . X10X . . . X10 X . . . X11 X . . . X00 X . . . X01X . . . X11 X . . . X10 X . . . X01 X . . . X00Absolute Maximum Ratings*Power Supply Voltage (VCC) . . . . . . . . . . -0.3V to +4.6V Voltage Relative to GND for any Pin Except VCC (Vin, Vout) . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V Operating Temperature (Topr) . . . . . . . . . . . 0°C to 70°C Storage Temperature (Tbias) . . . . . . . . . . -10°C to 85 °C Storage Temperature (Tstg) . . . . . . . . . . -55°C to 125°C*CommentsStresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.DC Electrical Characteristics and Operating Conditions(0°C ≤ T A ≤ 70°C, VCC, VCCQ = +3.3V ± 5% unless otherwise noted) Symbol ParameterConditions Min. Max. Unit NoteV IH Input High Voltage 1.7 VCC+0.3 V 1,2 V IL Input Low Voltage-0.3 0.8 V1,2IL I Input Leakage Current 0V ≤ V IH ≤ VCC -2.0TBDµAIL OOutput Leakage CurrentOutput(s) disabled, 0V ≤ V IN ≤ VCC-2.0 TBD µAV OH Output High Voltage I OH = -1.0mA 2.0 V 1,3 V OLOutput Low VoltageI OL = 1.0mA0.4V 1,3 VCC Supply Voltage 3.135 3.465 V 1 VCCQ Isolated Output Buffer Supply3.135VCCV1,4CapacitanceSymbol ParameterConditions Typ. Max. Unit NoteC I Control Input Capacitance 3 4 pF 6 C OInput/Output Capacitance (I/O)45pF6C A Address Capacitance T A = 25°C; f = 1MHz VCC = 3.3V3 3.5 pF 6Note : 1. All voltages referenced to VSS (GND).2. Overshoot : V IH ≤ +4.6V for t ≤ t KHKH /2 for I ≤ 20mA Undershoot : V IL ≥ -0.7V for t ≤ t KHKH /2 for I ≤ 20mAPower-up : V IH ≤ +3.465V and VCC ≤ 3.135V for t ≤ 200ms3. The load used for V OH , V OL testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O curves are available upon request.4. VCC and VCCQ can be externally wired together to the same power supply.5. This parameter is sampled.I CC Operating Condition and Maximum LimitsMax.Symbol Parameter-2.6 -2.8-3.2-3.5-3.8-4.2Unit ConditionsI CC Power SupplyCurrent : Operating460 440410*********mADevice selected; All inputs ≤V ILor ≥V IH; Cycle time ≥t KC(MIN);VCC = MAX; Outputs openI SB Standby TBD TBD TBD TBD TBD TBD mA Device deselected; VCC = MAX; All inputs ≤ VSS+0.2 or ≥ VCC-0.2; Cycle time ≥ t KC (MIN)I SB1Standby TBD TBD TBD TBD TBD TBD mA Device deselected; VCC = MAX; All inputs ≤VSS+0.2 or ≥ VCC-0.2; All inputs static; CLK frequency=0ZZ ≤ 0.2VI SB2 Standby TBD TBD TBD TBD TBD TBD mA Device deselected; VCC = MAX; All inputs ≤ V IL; or ≥ V IH; All inputs static;CLK frequency=MAXZZ ≥ VCC-0.2VI SB2Z SLEEPMode TBD TBD TBD TBD TBD TBD mA ZZ≥ V IHAC Characteristics (Note 4)(0°C ≤ T A≤ 70°C, VCC = +3.3V± 5%)Notes: 1. This parameter is sampled.2. Output loading is specified with C1=5pF as in Figure 2.3. Transition is measured ±200mV from steady state voltage.4. OE can be considered a “Don’t Care” during WRITE; however, controlling OE can help fine-tune a system forturnaround timing.5. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges ofCLK when ADV/LD is LOW and chip enabled. All other synchronous inputs meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK (when ADV/LD is LOW) to remain enabled.AC Test ConditionsInput Pulse Levels GND to 3.0V Input Rise and Fall Times 1.0nsInput Timing Reference Levels 1.25V Output Reference Levels 1.25V Output Load See Figures 1 and 2Figure 1Output Load EquivalentFigure 2Output Load EquivalentSLEEP ModeSLEEP Mode is a low current “Power-down” mode in which the device is deselected and current is reduced to I SB2Z . This duration of SLEEP Mode is dictated by the length of time the ZZ is in a HIGH state. After entering SLEEP Mode, all inputs except ZZ become disabled and all outputs go to High-Z.The ZZ pin is asynchronous, active high input that causes the device to enter SLEEP Mode. When the ZZ pin becomes logic HIGH, ISB2Z is guaranteed after the time t ZZI is met. Any operation pending when entering SLEEP Mode is not guaranteed to successfully complete. Therefore, SLEEP Mode (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting SLEEP Mode during t RZZ , only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SLEEP Mode.SLEEP Mode Electrical Characteristics(VCC, VCCQ = +3.3V ±5%)Symbol ParameterConditions Min. Max. Unit NoteI SB2Z Current during SLEEP Mode ZZ ≥ V IH - 60 mAt ZZ ZZ active to input ignored 0 2(t KHKH ) ns 1 t RZZ ZZ inactive to input sampled 02(t KHKH ) ns 1t ZZI ZZ active to snooze current - 2(t KHKH ) ns 1 t RZZIZZ inactive to exit snooze currentns1Note : 1. This parameter is sampled.SLEEP Mode Waveform: Don't CareREAD/WRITE TimingNote : 1. For this waveform, ZZ is tied LOW.2. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BRST operations are optional.3. CE represents three signals. When CE = 0, it represents CE = 0, CE2 = 0, CE2 = 1.4. Data coherency is provided for all possible operations. If a READ is initiated the most current data is used. The most recent data may be from the input data register.WRITE D(A1)WRITE D(A2)BURST WRITE D(A2+1)READ Q(A3)READ Q(A4)BURST READ Q(A4+1)WRITE D(A5)READ Q(A6)WRITE D(A7)DESELECT: Don't Care: UndefinedNOP, STALL and Deselect CyclesNote : 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CEN being used to create a “pause.” A WRITE isnot performed during this cycle.2. For this waveform, ZZ and OE are tied LOW.3. CE represents three signals. When CE = 0, it represents CE = 0, 2CE = 0, CE2 = 1.4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data may be from the input data register.: Don't Care: Undefined12345678910CLK CEN CE ADV/LD R/W BWx I/OOrdering InformationPart No.ConfigureCycle Time / Access TimePackageA67L0618E-4.2 7.5ns / 4.2ns 100L LQFP A67L0618E-4.2F 7.5ns / 4.2ns 100L Pb-Free LQFPA67L0618E-3.8 6.7ns / 3.8ns 100L LQFP A67L0618E-3.8F 6.7ns / 3.8ns 100L Pb-Free LQFPA67L0618E-3.5 6.0ns / 3.5ns 100L LQFP A67L0618E-3.5F6.0ns / 3.5ns 100L Pb-Free LQFPA67L0618E-3.2 5.0ns / 3.2ns 100L LQFP A67L0618E-3.2F 5.0ns / 3.2ns 100L Pb-Free LQFPA67L0618E-2.8 4.4ns / 2.8ns 100L LQFP A67L0618E-2.8F 4.4ns / 2.8ns 100L Pb-Free LQFPA67L0618E-2.6 4.0ns / 2.6ns 100L LQFP A67L0618E-2.6F 1M X 184.0ns / 2.6ns 100L Pb-Free LQFPA67L9336E-4.2 7.5ns / 4.2ns 100L LQFP A67L9336E-4.2F 7.5ns / 4.2ns 100L Pb-Free LQFPA67L9336E-3.8 6.7ns / 3.8ns 100L LQFP A67L9336E-3.8F 6.7ns / 3.8ns 100L Pb-Free LQFPA67L9336E-3.5 6.0ns / 3.5ns 100L LQFP A67L9336E-3.5F6.0ns / 3.5ns 100L Pb-Free LQFPA67L9336E-3.2 5.0ns / 3.2ns 100L LQFP A67L9336E-3.2F 5.0ns / 3.2ns 100L Pb-Free LQFPA67L9336E-2.8 4.4ns / 2.8ns 100L LQFP A67L9336E-2.8F 4.4ns / 2.8ns 100L Pb-Free LQFPA67L9336E-2.6 4.0ns / 2.6ns 100L LQFP A67L9336E-2.6F512K X 364.0ns / 2.6ns100L Pb-Free LQFPPackage InformationLQFP 100L Outline Dimensions unit: inches/mmNotes:1. Dimensions D and E do not include mold protrusion.2. Dimensions b does not include dambar protrusion.Total in excess of the b dimension at maximum material condition.Dambar cannot be located on the lower radius of the foot.。
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128K X 36 Bit Synchronous High Speed SRAM with Preliminary Burst Counter and Flow-through Data OutputDocument Title128K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data OutputRevision HistoryDate Remark Rev. No. History Issue0.0 Initial issue July 7, 2005 Preliminary128K X 36 Bit Synchronous High Speed SRAM with Preliminary Burst Counter and Flow-through Data Output FeaturesFast access times: 6.5/7.5/8.0 ns(153/133/117 MHz)Single 3.3V±5% power supplySynchronous burst functionIndividual Byte Write control and Global WriteThree separate chip enables allow wide range of options for CE control, address pipelining Selectable BURST modeSLEEP mode (ZZ pin) providedAvailable in 100-pin LQFP packageIndustrial operating temperature range: -45°C to +125°C for -I seriesGeneral DescriptionThe A63L73361 is a high-speed SRAM containing 4.5M bits of bit synchronous memory, organized as 128K words by 36 bits.The A63L73361 combines advanced synchronous peripheral circuitry, 2-bit burst control, input registers, output buffer and a 128K X 36 SRAM core to provide a wide range of data RAM applications.The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. Synchronous inputs include all addresses (A0 - A17), all data inputs (I/O1 - I/O36 ), active LOW chip enable (CE), two additional chip enables (CE2, CE2), burst control inputs (ADSC, ADSP, ADV), byte write enables (BWE, BW1, BW2, BW3, BW4) and Global Write (GW). Asynchronous inputs include output enable (OE), clock (CLK), BURST mode (MODE) and SLEEP mode (ZZ). Burst operations can be initiated with either the address status processor (ADSP) or address status controller (ADSC) input pin. Subsequent burst sequence burst addresses can be internally generated by the A63L73361 and controlled by the burst advance (ADV) pin. Write cycles are internally self-timed and synchronous with the rising edge of the clock (CLK).This feature simplifies the write interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/O1 - I/O9, BW2 controls I/O10 - I/O18, BW3 controls I/O19 - I/O27, and BW4 controls I/O28 - I/O36, all on the condition that BWE is LOW. GW LOW causes all bytes to be written.Pin ConfigurationI/O 20I/O 21VCCQ GNDQ I/O 22I/O 23I/O 24I/O 25GNDQ I/O 26I/O 27VCCQ VCC NC I/O 34GND I/O 28I/O 29VCCQ GNDQ I/O 30I/O 31I/O 32I/O 33GNDQ VCCQ I/O 35I/O 17I/O 16VCCQ GNDQ I/O 15I/O 14I/O 13I/O 12GNDQ VCCQ I/O 11I/O 10GND NC VCC ZZ I/O 8I/O 7VCCQ GNDQ I/O 6I/O 5I/O 4I/O 3GNDQ VCCQ I/O 2I/O 1A 15A 14A 13A 12A 11A 10N CV C CG N DN CA 0A 1A 2A 3A 4A 5M O D EC E 2A 7A 6C L KG N DV C CA 9A 8NC A D VA D S PA D S CO EB W EG WC E 2B W 1B W 2B W 3B W 4C EA 16I/O 9I/O 18I/O 19I/O 36N CN CBlock DiagramCLKPin DescriptionSynchronous Truth Table (See Notes 1 Through 5)Notes: 1. X = "Disregard", H = Logic High, L = Logic Low.WRITE = L means:2.BWx (BW1,BW2,BW3, or BW4) and BWE are low or1)AnyGW is low.2)3. All inputs except OE must be synchronized with setup and hold times around the rising edge (L-H) of CLK.4. For write cycles that follow read cycles, OE must be HIGH before the input data request setup time and heldHIGH throughout the input data hold time.ADSP LOW always initiates an internal Read at the L-H edge of CLK. A Write is performed by setting one or 5.more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. Refer to the Write timing diagram for clarification.Write Truth TableLinear Burst Address Table (MODE = LOW)First Address (External) Second Address (Internal)Third Address (Internal) Fourth Address (Internal) X . . . X00 X . . . X01 X . . . X10 X . . . X11X . . . X01 X . . . X10 X . . . X11 X . . . X00X . . . X10 X . . . X11 X . . . X00 X . . . X01X . . . X11 X . . . X00 X . . . X01 X . . . X10 Interleaved Burst Address Table (MODE = HIGH or NC)First Address (External) Second Address (Internal)Third Address (Internal) Fourth Address (Internal) X . . . X00 X . . . X01 X . . . X10 X . . . X11X . . . X01 X . . . X00 X . . . X11 X . . . X10X . . . X10 X . . . X11 X . . . X00 X . . . X01X . . . X11 X . . . X10 X . . . X01 X . . . X00Absolute Maximum Ratings*Power Supply Voltage (VCC) . . . . . . . . . . -0.5V to +4.6V Voltage Relative to GND for any Pin Except VCC (Vin, Vout) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V Power Dissipation (P D) . . . . . . . . . . . . . . . . . . . . . . . . 2W Storage Temperature (Tbias) . . . . . . . . . . -65°C to 150 °C Storage Temperature (Tstg) . . . . . . . . . . . -55°C to 125°C Operating RangesAmbient TemperatureCommercial (C) Devices . . . . . . . . . . . . . . . 0°C to +70°C Industrial (I) Devices . . . . . . . . . . . . . . . -45°C to +125°C V CC & V CCQ Supply VoltagesV CC for all devices . . ….. . . . . . . . . . . . . . . . . . . . +3.3VV CCQ for all devices . . ….. . . . . . . . . . . . . . . . . . . +3.3V Operating ranges define those limits between which the functionally of the device is guaranteed.*CommentsStresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.Recommended DC Operating Conditions(0°C ≤ T A≤ 70°C, VCC, VCCQ = 3.3V+5% or 3.3V-5%, unless otherwise noted)Symbol Parameter Min.Typ.Max.UnitNote VCC Supply Voltage (Operating Voltage Range) 3.135 3.3 3.465 VVCCQ Isolated Input Buffer Supply 3.135 3.3 3.465 VGND Supply Voltage to GND 0.0 - 0.0 VV IH Input High Voltage 2 - VCC+0.3 V 1, 2V IHQ Input High Voltage (I/O Pins) 2 - VCC+0.3 VV IL Input Low Voltage -0.3 - 0.8 V 1, 2DC Electrical Characteristics(0°C ≤ T A≤ 70°C, VCC, VCCQ = 3.3V+5% or 3.3V-5%, unless otherwise noted)CapacitanceConditions Symbol Parameter Typ.Max.UnitC IN InputCapacitance 3 4 pFT A = 25 C; f = 1MHzVCC = 3.3VCapacitance 4 5 pFC I/O Input/Output* These parameters are sampled and not 100% tested.AC Characteristics (0°C ≤ T A≤ 70°C, VCC = 3.3V+5% or 3.3V-5%)Notes:1. All voltages refer to GND.2. Overshoot: V IH≤ +2V for t ≤ t KC/2.Undershoot:V IL≥ -0.7V for t ≤ t KC/2.Power-up: V IH≤ +2 and VCC ≤ 1.7Vtfor≤ 200ms3. I CC1 is given with no output current. I CC1 increases with greater output loading and faster cycle times.4. Test conditions assume the output loading shown in Figure 1, unless otherwise specified.5. For output loading, C L = 5pF, as shown in Figure 2. Transition is measured ±150mV from steady state voltage.6. At any given temperature and voltage condition, t KQHZ is less than t KQLZ and t OEHZ is less than t QELZ.7. A WRITE cycle is defined by at least one Byte Write enable LOW and ADSP HIGH for the required setup and holdtimes. A READ cycle is defined by all byte write enables HIGH and (ADSC or ADV LOW) or ADSP LOW for the required setup and hold times.8. OE has no effect when a Byte Write enable is sampled LOW.9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLKADSP or ADSC is LOW and the chip is enabled. All other synchronous inputs must meet the setup and eitherwhenhold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP or ADSC is LOW to remain enabled.10. The load used for V OH, V OL testing is shown in Figure 2. AC load current is higher than the given DC values.AC I/O curves are available upon request.11. "Device Deselected" means device is in POWER-DOWN mode, as defined in the truth table. "Device Selected" meansdevice is active (not in POWER-DOWN mode).12. MODE pin has an internal pulled-up, and ZZ pin has an internal pulled-down. All of then exhibit an input leakagecurrent of 10µA.13. Snooze (ZZ) input is recommended that users plan for four clock cycles to go into SLEEP mode and four clocks toemerge from SLEEP mode to ensure no data is lost.Timing WaveformsRead TimingNotes: 1. QA(2) refers to output from address A2. Q(A2+1) refers to output from the next internal burst address following A2.2.CE and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE does not cause Q to be driven until after the following clock rising edge.CLKADSCADDRESSGW,BWE CE (NOTE 2)ADVOEDOUTDon't Care UndefinedTiming Waveforms (continued)CLKADSPADSCADDRESSOEDIN GWCE(NOTE 2)DOUT(NOTE 5)Don't Care UndefinedWrite TimingNotes: 1. D(A2) refers to output from address A2. D(A2+1) refers to output from the internal burst address immediately following A2.2. Timing forCE2 and CE2 is identical to that for CE. As shown in the above diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.3.OE must be HIGH before the input data setup, and held HIGH throughout the data hold period. This prevents input/output data contention for the period prior to the time Byte Write enable inputs are sampled.4.ADV must be HIGH to permit a Write to the loaded address. 5. Byte Write enables are decided by means of a Write truth table.Timing Waveforms (continued)Read/Write TimingNotes: 1. Q(A4) refers to output from address A4. Q(A4+1) refers to output from the next internal burst address following A4.2.CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE is LOW and CE2 is HIGH, When CE is HIGH, CE2 is HIGH and CE2 is LOW.3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP ,ADSC , or ADV cycle isperformed.4. Byte Write enables are decided by means of a Write truth table.5. Back-to-back READs may be controlled by either ADSP or ADSCCLKADSPADSCADDRESSCE (NOTE 2)ADVOEDINGW,BWE,BW1-BW4(NOTE 3)DOUTBack-to-Back READs Single WRITEWRITEsDon't Care UndefinedAC Test ConditionsInput Pulse Levels GND to 3VInput Rise and Fall Times 1 nsInput Timing Reference Levels 1.5VOutput Reference Levels VccQ/2Output Load See Figures 1 and 2Figure 1. Output Load Equivalent FigureQL=50ΩT2. Output Load EquivalentQOrdering InformationPart No. Access Times (ns) Frequency (MHz) Package A63L73361E-6.5 6.5 153 100LLQFP A63L73361E-6.5F 6.5 153 100L Pb-Free LQFPA63L73361E-7.5 7.5 133 100LLQFP A63L73361E-7.5F 7.5 133 100L Pb-Free LQFPA63L73361E-8 8 117 100LLQFP A63L73361E-8F 8 117 100L Pb-Free LQFPPackage InformationLQFP 100L Outline Dimensions unit: inches/mmNotes:1. Dimensions D and E do not include mold protrusion.2. Dimensions b does not include dambar protrusion.Total in excess of the b dimension at maximum material condition.Dambar cannot be located on the lower radius of the foot.。