HD74SSTV16858T资料

VREF+310 mV — VREF+150 mV —
VREF–310 mV V VREF–150 mV V
(Common mode range) VCMR
High level output current Low level output current Operating temperature
Note: The RESET input of the device must be held at VDDQ or GND to ensure proper device operation. The differential inputs must not be floating, unless RESET is low.
Rev.2, June. 2001, page ห้องสมุดไป่ตู้ of 13
HD74SSTV16858
Electrical Characteristics
Item Input diode voltage Output voltage
Symbol VCC (V)
Min — 1.95 0 — — — —
Typ — — — — — — — —
HD74SSTV16858
Pin Arrangement
Q10A 1 Q09A 2 GND 3 Q08A 4 Q07A 5 VDDQ 6 GND 7 Q06A 8 Q05A 9 Q04A 10 GND 11 Q03A 12 Q02A 13 Q01A 14 GND 15 Q00A 16 Q10B 17 VDDQ 18 Q09B 19 Q08B 20 Q07B 21 GND 22 Q06B 23 Q05B 24 Q04B 25 GND 26 VDDQ 27 Q03B 28 Q02B 29 GND 30 Q01B 31 Q00B 32
VI < 0 or VI > VCC VO < 0 or VO > VDDQ VO = 0 to VDDQ TSSOP
ICC, IDDQ or IGND ±100
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This current will flow only when the output is in the high state and VO > VDDQ.
(Top view)
Rev.2, June. 2001, page 2 of 13
HD74SSTV16858
Absolute Maximum Ratings
Item Supply voltage Input voltage
*1 *1, 2
Symbol VCC or VDDQ VI VO IIK IOK IO PT Tstg
64 VDDQ 63 GND 62 D10 61 D9 60 VCC 59 VDDQ 58 GND 57 D8 56 D7 55 VDDQ 54 GND 53 D6 52 D5 51 RESET 50 GND 49 CLK 48 CLK 47 VDDQ 46 VCC 45 VREF 44 D4 43 GND 42 VDDQ 41 D3 40 D2 39 GND 38 VDDQ 37 VCC 36 D1 35 D0 34 GND 33 VDDQ
HD74SSTV16858
1:2 11-bit SSTL_2 Registered Buffer
ADE-205-351B (Z) Rev.2 June 2001 Description
The HD74SSTV16858 is a 1:2 11-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input. Data flow from D to QA, QB is controlled by differential clock pins (CLK, CLK) and the RESET. Data is triggered on the positive edge of the positive clock (CLK), and the negative clock (CLK) must be used to maintain noise margins. When RESET is low, all registers are reset and all outputs are low. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up.
Features
• Supports LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input • Differential SSTL_2 (Stub series terminated logic) CLK signal • Flow through architecture optimizes PCB layout
Max –1.2 — VDDQ 0.2 0.35 ±5 45 10 90
Unit Test Conditions V V IIN = –18 mA IOH = –100 µA IOH = –16 mA IOL = 100 µA IOL = 16 mA µA mA µA VIN = 2.7 V or 0 VIN = VIH(AC) or VIL(AC), IO = 0 RESET = GND
peak input)
Symbol Min VCC VDDQ VREF VTT VI VIH VIL VIH VIL VIH VIL VPP IOH IOL Ta VDDQ 2.3 1.15 VREF–40 mV 0 — — 1.7 –0.3 0.97 360 — — 0
Typ 2.5 2.5 1.25 VREF — — — — — — — — — —
Function Table
Inputs RESET L H H H H: L: X: ↑: ↓: Note: CLK X ↓ ↓ L or H CLK X ↑ ↑ H or L D X H L X Outputs QA L H L Q0
*1
QB L H L Q0
*1
High level Low level Immaterial Low to high transition High to low transition 1. Output level before the indicated steady state input conditions were established.
VIK VOH VOL
2.3 2.3 2.3
2.3 to 2.7 VCC–0.2 — 2.3 to 2.7 — 2.7
Input current
(All inputs)
IIN ICC
*2
Quiescent supply current Standby current Dynamic operating clock only
Ratings –0.5 to 3.6 –0.5 to VDDQ+0.5 –0.5 to VDDQ+0.5 ±50 ±50 ±50 1 –65 to +150
Unit V V V mA mA mA mA W °C
Conditions
Output voltage
Input clamp current Output clamp current Continuous output current VCC, VDDQ or GND current / pin Maximum power dissipation at Ta = 55°C (in still air) Storage temperature Notes:
*3
rOH rOL rO(∆) Data inputs CIN
CLK and CLK
2.3 to 2.7 7 2.3 to 2.7 7 2.5 2.5
*1
— — — — — 3.0
Rev.2, June. 2001, page 3 of 13
HD74SSTV16858
Recommended Operating Conditions
Item Supply voltage Output supply voltage Reference voltage Termination voltage Input voltage AC high level input voltage AC low level input voltage DC high level input voltage DC low level input voltage High level input voltage Low level input voltage Differential input voltage (Minimum peak to
Rev.2, June. 2001, page 4 of 13
HD74SSTV16858
Logic Diagram
*1
RESET CLK CLK D0
51 48 49 35
VREF
45
1D C1 R
16 32
Q00A Q00B
To ten other channels
Note:
1.
RESET input gate is connected to VDDQ.
2.7
ICC (stdy) 2.7 ICCD
*2
2.7
µA/ RESET = VCC, clock VI = VIH(AC) or VIL(AC), MHz CLK and CLK switching 50% duty cycle µA/ clock MHz/ data input
*4 *4
Dynamic operating per each ICCD data input
Max 2.7 2.7 1.35 VREF+40 mV VCC — — VDDQ+0.3 0.7 1.53 — –20 20 70
Unit Conditions V V V V V V V V V V mV mA mA °C D D D D RESET RESET CLK, CLK CLK, CLK VREF = 0.5 × VDDQ
*2
2.7
—
—
20
RESET = VCC, VI = VIH(AC) or VIL(AC),
CLK and CLK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle.
Output high Output low