ADC0802中文资料
常用芯片
MAX232 5V电源多通道RS232驱动器/接收器
MC1403 2.5V精密电压基准电路
MC1404 5.0v/6.25v/10v 基准电压
MC1413/MC1416 七路达林顿驱动器
MC145026/MC145027/MC145028 编码器/译码器
74347 TTL BCD—7段译码器/驱动器
74352 TTL 双4选1数据选择器/复工器
74353 TTL 三态输出双4选1数据选择器/复工器
74365 TTL 门使能输入三态输出六同相线驱动器
74366 TTL 门使能输入三态输出六反相线驱动器
74367 TTL 4/2线使能输入三态六同相线驱动器
74132 TTL 2输入端四与非施密特触发器
74133 TTL 13输入端与非门
74136 TTL 四异或门
74138 TTL 3-8线译码器/复工器
74139 TTL 双2-4线译码器/复工器
7414 TTL 六反相施密特触发器
74145 TTL BCD—十进制译码/驱动器
7415 TTL 开路输出3输入端三与门
74368 TTL 4/2线使能输入三态六反相线驱动器
7437 TTL 开路输出2输入端四与非缓冲器
74373 TTL 三态同相八D锁存器
74374 TTL 三态反相八D锁存器
74375 TTL 4位双稳态锁存器
74377 TTL 单边输出公共使能八D锁存器
74378 TTL 单边输出公共使能六D锁存器
ICM7226 带BCD输出10MHz通用计数器
ISO2-CMOS MT8880C DTMF 收发器
ADC12DC080资料
ADVANCE INFORMATIONSeptember 2007 ADC12DC080/ADC12DC105Dual 12-Bit, 80/105 MSPS A/D Converter with CMOS OutputsGeneral DescriptionNOTE: This is Advance Information for products current-ly in development. ALL specifications are design targets and are subject to change.The ADC12DC080 and ADC12DC105 are high-performance CMOS analog-to-digital converters capable of converting two analog input signals into 12-bit digital words at rates up to 80/105 Mega Samples Per Second (MSPS) respectively. These converters use a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external com-ponent count, while providing excellent dynamic perfor-mance. A unique sample-and-hold stage yields a full-power bandwidth of 1 GHz. The ADC12DC080/105 may be operated from a single +3.3V power supply. A power-down feature re-duces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs provide a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the AD-C12DC080/105 can be operated with an external 1.2V refer-ence. Output data format (offset binary versus 2's comple-ment) and duty cycle stabilizer are pin-selectable. The duty cycle stabilizer maintains performance over a wide range of clock duty cycles.The ADC12DC080/105 is available in a 60-lead LLP package and operates over the industrial temperature range of −40°C to +85°C.Features■ 1 GHz Full Power Bandwidth■Internal sample-and-hold circuit and precision reference ■Low power consumption■Clock Duty Cycle Stabilizer■Single +3.3V supply operation■Power-down mode■Offset binary or 2's complement output data format■60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch) Key Specifications■For ADC12DC105■Resolution12 Bits ■Conversion Rate105 MSPS ■SNR (f IN = 240 MHz)67 dBFS (typ)■SFDR (f IN = 240 MHz)83 dBFS (typ)■Full Power Bandwidth 1 GHz (typ)■Power Consumption800 mW (typ) Applications■High IF Sampling Receivers■Wireless Base Station Receivers■Test and Measurement Equipment■Communications Instrumentation■Portable InstrumentationConnection Diagram30015401© 2007 National Semiconductor ADC12DC080/ADC12DC105 Dual 12-Bit, 80/105 MSPS A/D Converter with CMOS OutputsBlock Diagram30015402Ordering InformationIndustrial (−40°C ≤ T A ≤ +85°C)Package ADC12DC080CISQ 60 Pin LLP ADC12DC105CISQ60 Pin LLP 2A D C 12D C 080/A D C 12D C 105Pin Descriptions and Equivalent CircuitsPin No.SymbolEquivalent CircuitDescriptionANALOG I/O313V IN A+V IN B+Differential analog input pins. The differential full-scale input signal level is 2V P-P with each input pin signal centered on a common mode voltage, V CM .214V IN A-V IN B-511V RP A V RP B These pins should each be bypassed to AGND with a low ESL (equivalent series inductance) 0.1 µF capacitor placed very close to the pin to minimize stray inductance. An 0201 size 0.1 µFcapacitor should be placed between V RP and V RN as close to the pins as possible, and a 1 µF capacitor should be placed in parallel.V RP and V RN should not be loaded. V CMO may be loaded to 1mA for use as a temperature stable 1.5V reference.It is recommended to use V CMO to provide the common mode voltage, V CM , for the differential analog inputs.79V CMO A V CMO B 610V RN A V RN B59V REFReference Voltage. This device provides an internally developed 1.2V reference. When using the internal reference, V REF should be decoupled to AGND with a 0.1 µF and a 1µF, low equivalent series inductance (ESL) capacitor.This pin may be driven with an external 1.2V reference voltage.This pin should not be used to source or sink current.DIGITAL I/O19OF/DCSThis is a four-state pin controlling the input clock mode and output data format.OF/DCS = V A , output data format is 2's complement without duty cycle stabilization applied to the input clockOF/DCS = AGND, output data format is offset binary, without duty cycle stabilization applied to the input clock.OF/DCS = (2/3)*V A , output data is 2's complement with duty cycle stabilization applied to the input clockOF/DCS = (1/3)*V A , output data is offset binary with duty cycle stabilization applied to the input clock.18CLKThe clock input pin.The analog inputs are sampled on the rising edge of the clock input.5720PD_A PD_BThis is a two-state input controlling Power Down.PD = V A , Power Down is enabled and power dissipation is reduced.PD = AGND, Normal operation.ADC12DC080/ADC12DC105Pin No.Symbol Equivalent CircuitDescription42-49,52-55DA0-DA7,DA8-DA11Digital data output pins that make up the 12-bit conversion result for Channel A. DA0 (pin 42) is the LSB, while DA11 (pin 55) is the MSB of the output word. Output levels are CMOS compatible.23-24,27-36DB0-DB1,DB3-DB11Digital data output pins that make up the 12-bit conversion result for Channel B. DB0 (pin 23) is the LSB, while DB11 (pin 36) is the MSB of the output word. Output levels are CMOS compatible.39DRDYData Ready Strobe. The data output transition is synchronized with the falling edge of this signal. This signal switches at the same frequency as the CLK input.ANALOG POWER 8, 16, 17, 58,60V APositive analog supply pins. These pins should be connected to a quiet source and be bypassed to AGND with 0.1 µF capacitors located close to the power pins.1, 4, 12, 15,Exposed Pad AGNDThe ground return for the analog supply.DIGITAL POWER 26, 38,50V DRPositive driver supply pin for the output drivers. This pin should be connected to a quiet voltage source and be bypassed to DRGND with a 0.1 µF capacitor located close to the power pin.25, 37, 51DRGNDThe ground return for the digital output driver supply. This pins should be connected to the system digital ground, but not be connected in close proximity to the ADC's AGND pins. 4A D C 12D C 080/A D C 12D C 105Absolute Maximum Ratings (Notes 1, 3)If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.Supply Voltage (V A , V DR )−0.3V to 4.2V Voltage on Any Pin (Not to exceed 4.2V)−0.3V to (V A +0.3V)Input Current at Any Pin other than Supply Pins (Note 4)±5 mA Package Input Current (Note 4)±50 mA Max Junction Temp (T J )+150°C Thermal Resistance (θJA )30°C/WESD Rating Human Body Model (Note 6)2500V Machine Model (Note 6)250V Storage Temperature −65°C to +150°C Soldering process must comply with National Semiconductor's Reflow Temperature Profilespecifications. Refer to /packaging.(Note 7)Operating Ratings(Notes 1, 3)Operating Temperature −40°C ≤ T A ≤ +85°CSupply Voltage (V A )+2.7V to +3.6V Output Driver Supply (V DR )+2.4V to V AClock Duty Cycle(DCS Enabled)30/70 %(DCS disabled)45/55 %V CM1.4V to 1.6V|AGND-DRGND|≤100mVADC12DC080 Converter Electrical CharacteristicsThis product is currently under development. As such, the parameters specified are DESIGN TARGETS. The specifica-tions cannot be guaranteed until device characterization has taken place.Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V A = +3.0V, V DR = +2.5V, Internal V REF =+1.2V, f CLK = 80 MHz, V CM = V CMO , C L = 5 pF/pin. Typical values are for T A = 25°C. Boldface limits apply for T MIN ≤ T A ≤T MAX . All other limits apply for T A = 25°C (Notes 8, 9)SymbolParameterConditionsTypical (Note 10)LimitsUnits (Limits)STATIC CONVERTER CHARACTERISTICSResolution with No Missing Codes 12Bits (min)INL Integral Non Linearity (Note 11) ±0.5LSB (max)LSB (min)DNL Differential Non Linearity ±0.4LSB (max)LSB (min)Under Range Output Code 00Over Range Output Code40954095 REFERENCE AND ANALOG INPUT CHARACTERISTICS V CMO Common Mode Output Voltage 1.5 1.451.55V (min)V (max)V CM Analog Input Common Mode Voltage1.5 1.41.6V (min)V (max)C IN V IN Input Capacitance (each pin to GND) (Note 12)V IN = 1.5 Vdc ± 0.5 V (CLK LOW)8.5 pF (CLK HIGH)3.5 pF V REFExternal Reference Voltage1.201.1761.224V (min)V (max)ADC12DC080/ADC12DC105ADC12DC080 Dynamic Converter Electrical CharacteristicsUnless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V A = +3.0V, V DR = +2.5V, Internal V REF =+1.2V, f CLK = 80 MHz, V CM = V CMO , C L = 5 pF/pin, . Typical values are for T A = 25°C. Boldface limits apply for T MIN ≤ T A ≤T MAX . All other limits apply for T A = 25°C (Notes 8, 9)SymbolParameterConditionsTypical(Note 10)LimitsUnits (Limits)(Note 2)DYNAMIC CONVERTER CHARACTERISTICS, A IN = -1dBFS FPBW Full Power Bandwidth -1 dBFS Input, −3 dB Corner1.0 GHz SNRSignal-to-Noise Ratiof IN = 10 MHz 71.2dBFS f IN = 70 MHz 70dBFSf IN = 170 MHz 68 dBFS SFDRSpurious Free Dynamic Rangef IN = 10 MHz90 dBFS f IN = 70 MHz 88dBFS f IN = 170 MHz 83 dBFS ENOBEffective Number of Bitsf IN = 10 MHz11.5 Bits f IN = 70 MHz 11.3Bits f IN = 170 MHz 11 Bits THDTotal Harmonic Disortionf IN = 10 MHz−88 dBFS f IN = 70 MHz −85dBFS f IN = 170 MHz −80 dBFS H2Second Harmonic Distortionf IN = 10 MHz−100 dBFS f IN = 70 MHz −95dBFS f IN = 170 MHz −85 dBFS H3Third Harmonic Distortionf IN = 10 MHz−90 dBFS f IN = 70 MHz −88dBFS f IN = 170 MHz −83 dBFS SINADSignal-to-Noise and Distortion Ratiof IN = 10 MHz71.1 dBFS f IN = 70 MHz 69.8dBFS f IN = 170 MHz67.7dBFSADC12DC080 Logic and Power Supply Electrical CharacteristicsUnless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V A = +3.0V, V DR = +2.5V, Internal V REF =+1.2V, f CLK = 80 MHz, V CM = V CMO , C L = 5 pF/pin. Typical values are for T A = 25°C. Boldface limits apply for T MIN ≤ T A ≤T MAX . All other limits apply for T A = 25°C (Notes 8, 9)SymbolParameterConditionsTypical (Note 10)LimitsUnits (Limits)DIGITAL INPUT CHARACTERISTICS (CLK, PD_A,PD_B)V IN(1)Logical “1” Input Voltage V D = 3.6V 2.0V (min)V IN(0)Logical “0” Input Voltage V D = 3.0V 0.8V (max)I IN(1)Logical “1” Input Current V IN = 3.3V 10 µA I IN(0)Logical “0” Input Current V IN = 0V −10 µA C IN Digital Input Capacitance5 pF DIGITAL OUTPUT CHARACTERISTICS (DA0-DA11,DB0-DB11,DRDY)V OUT(1)Logical “1” Output Voltage I OUT = −0.5 mA , V DR = 2.4V 1.2V (min)V OUT(0)Logical “0” Output VoltageI OUT = 1.6 mA, V DR = 2.4V 0.4V (max)+I SC Output Short Circuit Source Current V OUT = 0V −10 mA −I SC Output Short Circuit Sink Current V OUT = V DR 10 mA C OUTDigital Output Capacitance5pFPOWER SUPPLY CHARACTERISTICS 6A D C 12D C 080/A D C 12D C 105Symbol Parameter ConditionsTypical(Note 10)LimitsUnits(Limits)IAAnalog Supply Current Full Operation200mA (max)IDRDigital Output Supply Current Full Operation (Note 13)26mAPower Consumption Excludes I DR (Note 13)600mW (max) Power Down Power Consumption PD_A=PD_B=V A30mW ADC12DC080 Timing and AC CharacteristicsUnless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.0V, VDR= +2.5V, Internal VREF=+1.2V, fCLK = 80 MHz, VCM= VCMO, CL= 5 pF/pin. Typical values are for TA= 25°C. Timing measurements are taken at 50% ofthe signal amplitude. Boldface limits apply for TMIN ≤ TA≤ TMAX. All other limits apply for TA= 25°C (Notes 8, 9)Symb Parameter ConditionsTypical(Note 10)LimitsUnits(Limits)Maximum Clock Frequency80MHz (max) Minimum Clock Frequency20MHz (min) tCHClock High Time6nstCLClock Low Time6nstCONVConversion Latency7Clock Cyclest OD Output Delay of CLK to DATA Relative to rising edge of CLK426ns (min)ns (max)tSUData Output Setup Time Relative to DRDY5ns (min)tHData Output Hold Time Relative to DRDY5ns (min)tADAperture Delay0.6nstAJAperture Jitter0.1ps rmsADC12DC080/ADC12DC105ADC12DC105 Converter Electrical CharacteristicsThis product is currently under development. As such, the parameters specified are DESIGN TARGETS. The specifica-tions cannot be guaranteed until device characterization has taken place.Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V A = +3.3V, V DR = +2.5V, Internal V REF =+1.2V, f CLK = 105 MHz, V CM = V CMO , C L = 5 pF/pin. Typical values are for T A = 25°C. Boldface limits apply for T MIN ≤ T A ≤T MAX . All other limits apply for T A = 25°C (Notes 8, 9)SymbolParameterConditionsTypical(Note 10)LimitsUnits (Limits)STATIC CONVERTER CHARACTERISTICSResolution with No Missing Codes 12Bits (min)INL Integral Non Linearity (Note 11) ±0.5LSB (max)LSB (min)DNL Differential Non Linearity ±0.4LSB (max)LSB (min)Under Range Output Code 00Over Range Output Code40954095 REFERENCE AND ANALOG INPUT CHARACTERISTICS V CMO Common Mode Output Voltage 1.5 1.451.55V (min)V (max)V CM Analog Input Common Mode Voltage1.5 1.41.6V (min)V (max)C IN V IN Input Capacitance (each pin to GND)(Note 12)V IN = 1.5 Vdc ± 0.5 V (CLK LOW)8.5 pF (CLK HIGH)3.5 pF V REFExternal Reference Voltage1.201.1761.224V (min)V (max)ADC12DC105 Dynamic Converter Electrical CharacteristicsUnless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V A = +3.3V, V DR = +2.5V, Internal V REF =+1.2V, f CLK = 105 MHz, V CM = V CMO , C L = 5 pF/pin, . Typical values are for T A = 25°C. Boldface limits apply for T MIN ≤ T A ≤T MAX . All other limits apply for T A = 25°C (Notes 8, 9)SymbolParameterConditionsTypical(Note 10)LimitsUnits (Limits)(Note 2)DYNAMIC CONVERTER CHARACTERISTICS, A IN = -1dBFS FPBW Full Power Bandwidth -1 dBFS Input, −3 dB Corner1.0 GHz SNRSignal-to-Noise Ratiof IN = 10 MHz 70.1dBFS f IN = 70 MHz 69.1dBFSf IN = 240 MHz 67 dBFS SFDRSpurious Free Dynamic Rangef IN = 10 MHz88 dBFS f IN = 70 MHz 85dBFS f IN = 240 MHz 83 dBFS ENOBEffective Number of Bitsf IN = 10 MHz11.3 Bits f IN = 70 MHz 11.2Bits f IN = 240 MHz 10.8 Bits THDTotal Harmonic Disortionf IN = 10 MHz−86 dBFS f IN = 70 MHz −85dBFS f IN = 240 MHz −80 dBFS H2Second Harmonic Distortionf IN = 10 MHz−95 dBFS f IN = 70 MHz −90dBFS f IN = 240 MHz−85dBFS 8A D C 12D C 080/A D C 12D C 105Symbol Parameter ConditionsTypical(Note 10)LimitsUnits(Limits)(Note 2)H3Third Harmonic DistortionfIN= 10 MHz−88dBFSfIN= 70 MHz−85dBFSfIN= 240 MHz−83dBFSSINAD Signal-to-Noise and Distortion RatiofIN= 10 MHz70dBFSfIN= 70 MHz69dBFSfIN= 240 MHz66.8dBFSADC12DC105 Logic and Power Supply Electrical CharacteristicsUnless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR= +2.5V, Internal VREF=+1.2V, fCLK = 105 MHz, VCM= VCMO, CL= 5 pF/pin. Typical values are for TA= 25°C. Boldface limits apply for TMIN≤ TA≤T MAX . All other limits apply for TA= 25°C (Notes 8, 9)Symbol Parameter ConditionsTypical(Note 10)LimitsUnits(Limits)DIGITAL INPUT CHARACTERISTICS (CLK, PD_A,PD_B)VIN(1)Logical “1” Input Voltage V D = 3.6V 2.0V (min)VIN(0)Logical “0” Input Voltage V D = 3.0V0.8V (max)IIN(1)Logical “1” Input Current V IN = 3.3V10µAIIN(0)Logical “0” Input Current VIN= 0V−10µACINDigital Input Capacitance5pFDIGITAL OUTPUT CHARACTERISTICS (DA0-DA11,DB0-DB11,DRDY)VOUT(1)Logical “1” Output Voltage I OUT = −0.5 mA , V DR = 2.4V 1.2V (min)VOUT(0)Logical “0” Output Voltage I OUT = 1.6 mA, V DR = 2.4V0.4V (max)+ISC Output Short Circuit Source Current VOUT= 0V−10mA−ISCOutput Short Circuit Sink Current V OUT = V DR10mACOUTDigital Output Capacitance5pF POWER SUPPLY CHARACTERISTICSIAAnalog Supply Current Full Operation242mA (max)IDRDigital Output Supply Current Full Operation (Note 13)32mAPower Consumption Excludes I DR (Note 13)800mW (max) Power Down Power Consumption PD_A=PD_B=V A33mW ADC12DC105 Timing and AC CharacteristicsUnless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR= +2.5V, Internal VREF=+1.2V, fCLK = 105 MHz, VCM= VCMO, CL= 5 pF/pin. Typical values are for TA= 25°C. Timing measurements are taken at 50% ofthe signal amplitude. Boldface limits apply for TMIN ≤ TA≤ TMAX. All other limits apply for TA= 25°C (Notes 8, 9)Symb Parameter ConditionsTypical(Note 10)LimitsUnits(Limits)Maximum Clock Frequency105MHz (max) Minimum Clock Frequency20MHz (min) tCHClock High Time4nstCLClock Low Time4nstCONVConversion Latency7Clock Cyclest OD Output Delay of CLK to DATA Relative to rising edge of CLK426ns (min)ns (max)tSUData Output Setup Time Relative to DRDY3ns (min)tHData Output Hold Time Relative to DRDY3ns (min)tADAperture Delay0.6nstAJAperture Jitter0.1ps rmsADC12DC080/ADC12DC105Note 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is guaranteed to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.Note 2:This parameter is specified in units of dBFS - indicating the value that would be attained with a full-scale input signal.Note 3:All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified.Note 4:When the input voltage at any pin exceeds the power supplies (that is, V IN < AGND, or V IN > V A ), the current at that pin should be limited to ±5 mA. The ±50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of ±5 mA to 10.Note 5:The maximum allowable power dissipation is dictated by T J,max , the junction-to-ambient thermal resistance, (θJA ), and the ambient temperature, (T A ), and can be calculated using the formula P D,max = (T J,max - T A )/θJA . The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided.Note 6:Human Body Model is 100 pF discharged through a 1.5 k Ω resistor. Machine Model is 220 pF discharged through 0 ΩNote 7:Reflow temperature profiles are different for lead-free and non-lead-free packages.Note 8:The inputs are protected as shown below. Input voltage magnitudes above V A or below GND will not damage this device, provided current is limited per (Note 4). However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described in the Operating Ratings section.30015411Note 9:With a full scale differential input of 2V P-P , the 12-bit LSB is 488 µV.Note 10:Typical figures are at T A = 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are not guaranteed.Note 11:Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative full-scale.Note 12:The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance.Note 13:I DR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage,V DR , and the rate at which the outputs are switching (which is signal dependent). I DR =V DR (C 0 x f 0 + C 1 x f 1 +....C 11 x f 11) where V DR is the output driver power supply voltage, C n is total capacitance on the output pin, and f n is the average frequency at which that pin is toggling.Note 14:This parameter is guaranteed by design and/or characterization and is not tested in production. 10A D C 12D C 080/A D C 12D C 105Specification DefinitionsAPERTURE DELAY is the time after the falling edge of the clock to when the input signal is acquired or held for conver-sion.APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output.CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the total time of one period. The specification here refers to the ADC clock input signal.COMMON MODE VOLTAGE (V CM ) is the common DC volt-age applied to both input terminals of the ADC.CONVERSION LATENCY is the number of clock cycles be-tween initiation of conversion and when that data is presented to the output driver stage. Data for any given sample is avail-able at the output pins the Pipeline Delay plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the conversion by the pipeline delay.CROSSTALK is coupling of energy from one channel into the other channel.DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB.EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion Ratio or SINAD. ENOB is defined as (SINAD -1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits.FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input.GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as:Gain Error = Positive Full Scale Error − Negative Full ScaleError It can also be expressed as Positive Gain Error and Negative Gain Error, which are calculated as:PGE = Positive Full Scale Error - Offset Error NGE = Offset Error - Negative Full Scale ErrorINTEGRAL NON LINEARITY (INL) is a measure of the de-viation of each individual code from a best fit straight line. The deviation of any given code from this straight line is measured from the center of that code value.INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time.It is defined as the ratio of the power in the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dBFS.LSB (LEAST SIGNIFICANT BIT) is the bit that has the small-est value or weight of all bits. This value is V FS /2n , where “V FS ” is the full scale input voltage and “n” is the ADC reso-lution in bits.MISSING CODES are those output codes that will never ap-pear at the ADC outputs. The ADC is guaranteed not to have any missing codes.MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.NEGATIVE FULL SCALE ERROR is the difference between the actual first code transition and its ideal value of ½ LSB above negative full scale.OFFSET ERROR is the difference between the two input voltages [(V IN +) – (V IN -)] required to cause a transition from code 2047 to 2048.OUTPUT DELAY is the time delay after the falling edge of the clock before the data update is presented at the output pins.PIPELINE DELAY (LATENCY) See CONVERSION LATEN-CY.POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of 1½ LSB below positive full scale.POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power supply voltage. PSRR is the ratio of the Full-Scale output of the ADC with the supply at the minimum DC supply limit to the Full-Scale output of the ADC with the supply at the maximum DC supply limit, expressed in dB.SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sam-pling frequency, not including harmonics or DC.SIGNAL TO NOISE PL US DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral com-ponents below half the clock frequency, including harmonics but excluding d.c.SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-ence, expressed in dB, between the rms values of the input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input.TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-pressed in dB, of the rms total of the first nine harmonic levels at the output to the level of the fundamental at the output. THD is calculated aswhere f 1 is the RMS power of the fundamental (output) fre-quency and f 2 through f 10 are the RMS power of the first 9harmonic frequencies in the output spectrum.SECOND HARMONIC DISTORTION (2ND HARM) is the dif-ference expressed in dB, between the RMS power in the input frequency at the output and the power in its 2nd harmonic level at the output.THIRD HARMONIC DISTORTION (3RD HARM) is the dif-ference, expressed in dB, between the RMS power in the input frequency at the output and the power in its 3rd harmonic level at the output.ADC12DC080/ADC12DC105Timing Diagrams30015409FIGURE 1. Output TimingTransfer Characteristic30015410FIGURE 2. Transfer Characteristic 12A D C 12D C 080/A D C 12D C 105Physical Dimensions inches (millimeters) unless otherwise notedTOP View...............................SIDE View...............................BOTTOM View60-Lead LLP PackageOrdering Numbers:ADC12DC080CISQ / ADC12DC105CISQNS Package Number SQA60A ADC12DC080/ADC12DC105NotesA D C 12D C 080/A D C 12D C 105 D u a l 12-B i t , 80/105 M S P S A /DC o n v e r t e r w i t h C M O S O u t p u t sTHE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIG HT TO MAKE CHANG ES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. 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常用ic名称
74系列TTL电路检索7400 TTL 2输入端四与非门7401 TTL 集电极开路2输入端四与非门7402 TTL 2输入端四或非门7403 TTL 集电极开路2输入端四与非门7404 TTL 六反相器7405 TTL 集电极开路六反相器7406 TTL 集电极开路六反相高压驱动器7407 TTL 集电极开路六正相高压驱动器7408 TTL 2输入端四与门7409 TTL 集电极开路2输入端四与门7410 TTL 3输入端3与非门74107 TTL 带清除主从双J-K触发器74109 TTL 带预置清除正触发双J-K触发器7411 TTL 3输入端3与门74112 TTL 带预置清除负触发双J-K触发器7412 TTL 开路输出3输入端三与非门74121 TTL 单稳态多谐振荡器74122 TTL 可再触发单稳态多谐振荡器74123 TTL 双可再触发单稳态多谐振荡器74125 TTL 三态输出高有效四总线缓冲门74126 TTL 三态输出低有效四总线缓冲门7413 TTL 4输入端双与非施密特触发器74132 TTL 2输入端四与非施密特触发器74133 TTL 13输入端与非门74136 TTL 四异或门74138 TTL 3-8线译码器/复工器74139 TTL 双2-4线译码器/复工器7414 TTL 六反相施密特触发器74145 TTL BCD—十进制译码/驱动器7415 TTL 开路输出3输入端三与门74150 TTL 16选1数据选择/多路开关74151 TTL 8选1数据选择器74153 TTL 双4选1数据选择器74154 TTL 4线—16线译码器74155 TTL 图腾柱输出译码器/分配器74156 TTL 开路输出译码器/分配器74157 TTL 同相输出四2选1数据选择器74158 TTL 反相输出四2选1数据选择器7416 TTL 开路输出六反相缓冲/驱动器74160 TTL 可预置BCD异步清除计数器74161 TTL 可予制四位二进制异步清除计数器74162 TTL 可预置BCD同步清除计数器74163 TTL 可予制四位二进制同步清除计数器74164 TTL 八位串行入/并行输出移位寄存器74165 TTL 八位并行入/串行输出移位寄存器74166 TTL 八位并入/串出移位寄存器74169 TTL 二进制四位加/减同步计数器7417 TTL 开路输出六同相缓冲/驱动器74170 TTL 开路输出4×4寄存器堆74173 TTL 三态输出四位D型寄存器74174 TTL 带公共时钟和复位六D触发器74175 TTL 带公共时钟和复位四D触发器74180 TTL 9位奇数/偶数发生器/校验器74181 TTL 算术逻辑单元/函数发生器74185 TTL 二进制—BCD代码转换器74190 TTL BCD同步加/减计数器74191 TTL 二进制同步可逆计数器74192 TTL 可预置BCD双时钟可逆计数器74193 TTL 可预置四位二进制双时钟可逆计数器74194 TTL 四位双向通用移位寄存器74195 TTL 四位并行通道移位寄存器74196 TTL 十进制/二-十进制可预置计数锁存器74197 TTL 二进制可预置锁存器/计数器7420 TTL 4输入端双与非门7421 TTL 4输入端双与门7422 TTL 开路输出4输入端双与非门74221 TTL 双/单稳态多谐振荡器74240 TTL 八反相三态缓冲器/线驱动器74241 TTL 八同相三态缓冲器/线驱动器74243 TTL 四同相三态总线收发器74244 TTL 八同相三态缓冲器/线驱动器74245 TTL 八同相三态总线收发器74247 TTL BCD—7段15V输出译码/驱动器74248 TTL BCD—7段译码/升压输出驱动器74249 TTL BCD—7段译码/开路输出驱动器74251 TTL 三态输出8选1数据选择器/复工器74253 TTL 三态输出双4选1数据选择器/复工器74256 TTL 双四位可寻址锁存器74257 TTL 三态原码四2选1数据选择器/复工器74258 TTL 三态反码四2选1数据选择器/复工器74259 TTL 八位可寻址锁存器/3-8线译码器7426 TTL 2输入端高压接口四与非门74260 TTL 5输入端双或非门74266 TTL 2输入端四异或非门7427 TTL 3输入端三或非门74273 TTL 带公共时钟复位八D触发器74279 TTL 四图腾柱输出S-R锁存器7428 TTL 2输入端四或非门缓冲器74283 TTL 4位二进制全加器74290 TTL 二/五分频十进制计数器74293 TTL 二/八分频四位二进制计数器74295 TTL 四位双向通用移位寄存器74298 TTL 四2输入多路带存贮开关74299 TTL 三态输出八位通用移位寄存器7430 TTL 8输入端与非门7432 TTL 2输入端四或门74322 TTL 带符号扩展端八位移位寄存器74323 TTL 三态输出八位双向移位/存贮寄存器7433 TTL 开路输出2输入端四或非缓冲器74347 TTL BCD—7段译码器/驱动器74352 TTL 双4选1数据选择器/复工器74353 TTL 三态输出双4选1数据选择器/复工器74365 TTL 门使能输入三态输出六同相线驱动器74366 TTL 门使能输入三态输出六反相线驱动器74367 TTL 4/2线使能输入三态六同相线驱动器74368 TTL 4/2线使能输入三态六反相线驱动器7437 TTL 开路输出2输入端四与非缓冲器74373 TTL 三态同相八D锁存器74374 TTL 三态反相八D锁存器74375 TTL 4位双稳态锁存器74377 TTL 单边输出公共使能八D锁存器74378 TTL 单边输出公共使能六D锁存器74379 TTL 双边输出公共使能四D锁存器7438 TTL 开路输出2输入端四与非缓冲器74380 TTL 多功能八进制寄存器7439 TTL 开路输出2输入端四与非缓冲器74390 TTL 双十进制计数器74393 TTL 双四位二进制计数器7440 TTL 4输入端双与非缓冲器7442 TTL BCD—十进制代码转换器74447 TTL BCD—7段译码器/驱动器7445 TTL BCD—十进制代码转换/驱动器74450 TTL 16:1多路转接复用器多工器74451 TTL 双8:1多路转接复用器多工器74453 TTL 四4:1多路转接复用器多工器7446 TTL BCD—7段低有效译码/驱动器74460 TTL 十位比较器74461 TTL 八进制计数器74465 TTL 三态同相2与使能端八总线缓冲器74466 TTL 三态反相2与使能八总线缓冲器74467 TTL 三态同相2使能端八总线缓冲器74468 TTL 三态反相2使能端八总线缓冲器74469 TTL 八位双向计数器7447 TTL BCD—7段高有效译码/驱动器7448 TTL BCD—7段译码器/内部上拉输出驱动74490 TTL 双十进制计数器74491 TTL 十位计数器74498 TTL 八进制移位寄存器7450 TTL 2-3/2-2输入端双与或非门74502 TTL 八位逐次逼近寄存器74503 TTL 八位逐次逼近寄存器7451 TTL 2-3/2-2输入端双与或非门74533 TTL 三态反相八D锁存器74534 TTL 三态反相八D锁存器7454 TTL 四路输入与或非门74540 TTL 八位三态反相输出总线缓冲器7455 TTL 4输入端二路输入与或非门74563 TTL 八位三态反相输出触发器74564 TTL 八位三态反相输出D触发器74573 TTL 八位三态输出触发器74574 TTL 八位三态输出D触发器74645 TTL 三态输出八同相总线传送接收器74670 TTL 三态输出4×4寄存器堆7473 TTL 带清除负触发双J-K触发器7474 TTL 带置位复位正触发双D触发器7476 TTL 带预置清除双J-K触发器7483 TTL 四位二进制快速进位全加器7485 TTL 四位数字比较器7486 TTL 2输入端四异或门7490 TTL 可二/五分频十进制计数器7493 TTL 可二/八分频二进制计数器7495 TTL 四位并行输入\输出移位寄存器7497 TTL 6位同步二进制乘法器ICL7106,ICL7107 3位半A/D转换器DAC0830/DAC0832 8位D/A转换器ADC0831/ADC0832/ADC0834/ADC0838 8位A/D转换器ADC0808/ADC0809 8位A/D转换器ADC0802/ADC0803/ADC0804 8位A/D转换器AD7520/AD7521/AD7530/AD7521 D/A转换器4N35/4N36/4N37 光电耦合器ICL7116,ICL7117 3位半A/D转换器ICL7650 载波稳零运算放大器ICL7660/MAX1044 CMOS电源电压变换器ICL8038 单片函数发生器ICM7216 10MHz通用计数器ICM7226 带BCD输出10MHz通用计数器ISO2-CMOS MT8880C DTMF 收发器LF351 JFET输入运算放大器LF353 JFET输入宽带高速双运算放大器LM117/LM317A/LM317 三端可调电源LM124/LM124/LM324 低功耗四运算放大器LM137/LM337 三端可调负电压调整器LM139/LM239/LM339 低功耗四电压比较器LM158/LM258/LM358 低功耗双运算放大器LM193/LM293/LM393 低功耗双电压比较器LM201/LM301 通用运算放大器[中文资料]LM231/LM331 精密电压—频率转换器LM285/LM385 微功耗基准电压二极管[中文资料]LM308A 精密运算放大器LM386 低压音频小功率放大器LM399 带温度稳定器精密电压基准电路LM431 可调电压基准电路LM567/LM567C 锁相环音频译码器LM741 运算放大器LM831 双低噪声音频功率放大器LM833 双低噪声音频放大器LM8365 双定时LED电子钟电路MAX038 0.1Hz-20MHz 单片函数发生器MAX232 5V电源多通道RS232驱动器/接收器MC1403 2.5V精密电压基准电路MC1404 5.0v/6.25v/10v 基准电压MC1413/MC1416 七路达林顿驱动器MC145026/MC145027/MC145028 编码器/译码器MC145403-5/8 RS232驱动器/接收器MC145406 RS232驱动器/接收器MC145407 RS232驱动器/接收器MC145583 RS232驱动器/接收器MC145740 DTMF 接收器MC1488 二输入与非四线路驱动器MC1489 四施密特可控线路驱动器MC2833 低功率调频发射系统MC3362 低功率调频窄频带接收器MC4558 双运算放大器MC7800系列1.0A三端正电压稳压器MC78L00系列0.1A三端正电压稳压器[中文资料]MC78M00系列0.5A三端正电压稳压器MC78T00系列3.0A正电压稳压器[中文资料]MC7900系列1.0A三端负电压稳压器[中文资料]MC79L00系列0.1A三端负电压稳压器[中文资料]MC79M00系列0.5A三端负电压稳压器[中文资料]Microchip PIC系列单片机RS232通讯应用MM5369 3.579545MHz-60Hz 17级分频振荡器MOC3009/MOC3012 双向可控硅输出光电耦合器MOC3020/MOC3023 双向可控硅输出光电耦合器MOC3081/MOC3082/MOC3083 过零双向可控硅输出光电耦合器MOC8050 无基极达林顿晶体管输出光电耦合器MOC8111 无基极晶体管输出光电耦合器MT8870 DTMF双音频接收器MT8888C DTMF 收发器NE5532/NE5532A 双低噪声运算放大器NE5534/SE5534 低噪声运算放大器NE555/SA555 单时基电路NE556/SA556/SE556 双时基电路NE570/NE571/SA571 音频压缩扩展器OP07 低电压飘移运算放大器OP27 低噪音精密运算放大器OP37 低噪音高速精密运算放大器OP77 低电压飘移运算放大器OP90 精密低电压微功耗运算放大器PC817/PC827/PC847 高效光电耦合器PT2262 无线遥控发射编码器芯片PT2272 无线遥控接收解码器芯片SG2524/SG3524 脉宽调制PWMST7537 电力线调制解调器电路TDA1521 2×12W Hi-Fi 音频功率放大器TDA2030 14W Hi-Fi 音频放大器TDA7000T FM 单片调频接收电路TDA7010T FM 单片调频接收电路TDA7021T FM MTS 单片调频接收电路TDA7040T 低电压锁相环立体声解码器TDA7050 低电压单/双声道功率放大器TL062/TL064 低功耗JFET输入运算放大器TL071/TL072/TL074 低噪声JFET输入运算放大器TL082/TL084 JFET 宽带高速运算放大器TL494 脉宽调制PWMTL594 精密开关模式脉宽调制控制TLP521/1-4 光电耦合器TOP100-4 TOPSwitch 三端PWM开关电源电路TOP221-7 TOPSwitch-Ⅱ三端PWM开关电源电路TOP232-4 TOPSwitch-FX 五端柔韧设计开关电源电路TOP412/TOP414 TOPSwitch 三端PWM DC-DC 开关电源ULN2068 1.5A/50V 4路达林顿驱动电路ULN2803 500mA/50V 8路达林顿驱动电路ULN2803/ULN2804 线性八外围驱动器阵列[中文资料] VFC32 电压—频率/频率—电压转换器添加评论40系列CMOS电路检索4000 CMOS 3输入双或非门1反相器4001 CMOS 四2输入或非门4002 CMOS 双4输入或非门4006 CMOS 18级静态移位寄存器4007 CMOS 双互补对加反相器4008 CMOS 4位二进制并行进位全加器4009 CMOS 六缓冲器/转换器（反相）4010 CMOS 六缓冲器/转换器（同相）40100 CMOS 32位双向静态移位寄存器40101 CMOS 9位奇偶发生器/校验器40102 CMOS 8位BCD可预置同步减法计数器40103 CMOS 8位二进制可预置同步减法计数器40104 CMOS 4位三态输出双向通用移位寄存器40105 CMOS 先进先出寄存器40106 CMOS 六施密特触发器40107 CMOS 2输入双与非缓冲/驱动器40108 CMOS 4×4多端寄存40109 CMOS 四三态输出低到高电平移位器4011 CMOS 四2输入与非门40110 CMOS 十进制加减计数/译码/锁存/驱动40117 CMOS 10线—4线BCD优先编码器4012 CMOS 双4输入与非门4013 CMOS 带置位/复位的双D触发器4014 CMOS 8级同步并入串入/串出移位寄存器40147 CMOS 10线—4线BCD优先编码器4015 CMOS 双4位串入/并出移位寄存器4016 CMOS 四双向开关40160 CMOS 非同步复位可预置BCD计数器40161 CMOS 非同步复位可预置二进制计数器40162 CMOS 同步复位可预置BCD计数器40163 CMOS 同步复位可预置二进制计数器4017 CMOS 十进制计数器/分频器40174 CMOS 六D触发器40175 CMOS 四D触发器4018 CMOS 可预置1/N 计数器40181 CMOS 4位算术逻辑单元40182 CMOS 超前进位发生器4019 CMOS 四与或选译门40192 CMOS 可预制四位BCD计数器40193 CMOS 可预制四位二进制计数器40194 CMOS 4位双向并行存取通用移位寄存器4020 CMOS 14级二进制串行计数/分频器40208 CMOS 4×4多端寄存器4021 CMOS 异步8位并入同步串入/串出寄存器4022 CMOS 八进制计数器/分频器4023 CMOS 三3输入与非门4024 CMOS 7级二进制计数器4025 CMOS 三3输入或非门40257 CMOS 四2线-1线数据选择器/多路传输4026 CMOS 7段显示十进制计数/分频器4027 CMOS 带置位复位双J-K主从触发器4028 CMOS BCD- 十进制译码器4029 CMOS 可预制加/减（十/二进制）计数器4030 CMOS 四异或门4031 CMOS 64级静态移位寄存器4032 CMOS 3位正逻辑串行加法器4033 CMOS 十进制计数器/消隐7段显示4034 CMOS 8位双向并、串入/并出寄存器4035 CMOS 4位并入/并出移位寄存器4038 CMOS 3位串行负逻辑加法器4040 CMOS 12级二进制计数/分频器4041 CMOS 四原码/补码缓冲器4042 CMOS 四时钟控制D 锁存器4043 CMOS 四三态或非R/S 锁存器4044 CMOS 四三态与非R/S 锁存器4045 CMOS 21位计数器4046 CMOS PLL 锁相环电路4047 CMOS 单稳态、无稳态多谐振荡器4048 CMOS 8输入端多功能可扩展三态门4049 CMOS 六反相缓冲器/转换器4050 CMOS 六同相缓冲器/转换器4051 CMOS 8选1双向模拟开关4052 CMOS 双4选1双向模拟开关4053 CMOS 三2选1双向模拟开关4054 CMOS 四位液晶显示驱动器4055 CMOS BCD—7段译码/液晶显示驱动器4056 CMOS BCD—7段译码/驱动器4059 CMOS 可编程1/N 计数器4060 CMOS 14级二进制计数/分频/振荡器4063 CMOS 四位数字比较器4066 CMOS 四双向模拟开关4067 CMOS 单16通道模拟开关4068 CMOS 8输入端与非门4069 CMOS 六反相器4070 CMOS 四异或门4071 CMOS 四2输入端或门4072 CMOS 4输入端双或门4073 CMOS 3输入端三与门4075 CMOS 3输入端三或门4076 CMOS 4位三态输出D寄存器4077 CMOS 四异或非门4078 CMOS 8输入端或非门4081 CMOS 四2输入端与门4082 CMOS 4输入端双与门4085 CMOS 双2×2与或非门4086 CMOS 2输入端可扩展四与或非门4089 CMOS 二进制系数乘法器4093 CMOS 四2输入端施密特触发器4094 CMOS 8级移位存储总线寄存器4095 CMOS 选通J-K同相输入主从触发器4096 CMOS 选通J-K反相输入主从触发器4097 CMOS 双8通道模拟开关4098 CMOS 双单稳态多谐振荡器4099 CMOS 八位可寻址锁存器4500 CMOS 工业控制一位微处理器4501 CMOS 三组门电路4502 CMOS 可选通六反相缓冲器4503 CMOS 六三态同相缓冲器4504 CMOS 六TTL-CMOS电平移位器4506 CMOS 双二组2输入可扩展与或非门4508 CMOS 双三态输出四位锁存器4510 CMOS BCD可预置可逆计数器4511 CMOS BCD-7段锁存/译码/LED驱动4512 CMOS 8通道数据选择器4513 CMOS BCD-7段译码/锁存/驱动器4514 CMOS 四位锁存/4-16高有效译码器4515 CMOS 四位锁存/4-16低有效译码器4516 CMOS 二进制四位可预置可逆计数器4517 CMOS 双64位静态移位寄存器4518 CMOS 双BCD加法计数器4519 CMOS 四位与或选择器4520 CMOS 双二进制加法计数器4522 CMOS 可预置BCD 1/N 计数器4526 CMOS 可预置二进制1/N 计数器4527 CMOS BCD系数乘法器4528 CMOS 双单稳态多谐振荡器4529 CMOS 双四路或单八路模拟开关4530 CMOS 双5输入优势逻辑门4531 CMOS 12位奇偶校验电路4532 CMOS 8输入优先权译码器4534 CMOS 时分制5位十进制计数器4536 CMOS 可编程定时器4538 CMOS 双精密单稳多谐振荡器4539 CMOS 双四路数据选择器/多路开关4541 CMOS 可编程振荡器/计时器4543 CMOS BCD-7段译码/锁存/液晶驱动器4544 CMOS BCD-7段译码/消隐/驱动器4547 CMOS BCD-7段译码/大电流驱动器4549 CMOS 逐级近似寄存器4551 CMOS 4×2通道模拟开关4553 CMOS 3位数BCD计数器4554 CMOS 2×2并行二进制乘法器4555 CMOS 双4选1高选中译码器4556 CMOS 双4选1低选中译码器4557 CMOS 1-64位可变字长移位寄存器4558 CMOS BCD-7段译码器4559 CMOS 逐级近似寄存器4560 CMOS BCD全加器4561 CMOS “9”补码电路4562 CMOS 128位静态移位寄存器4566 CMOS 工业时基发生器4568 CMOS 相位比较器/可编辑计数器4569 CMOS 双可预置BCD/二进制计数器4572 CMOS 六门电路4580 CMOS 4×4多端寄存器4581 CMOS 4位算术逻辑单元4582 CMOS 超前进位发生器4583 CMOS 双多能施密特触发器4584 CMOS 六施密特触发器4585 CMOS 4位数字比较器4597 CMOS 8位总线相容计数/锁存器4598 CMOS 8位总线相容可寻址锁存器4599 CMOS 8位可寻址双向锁存器。
ADC0802
File Number 3094.1
Functional Diagram
ADC0802, ADC0803, ADC0804
2 RD
1 CS 3 WR
READ
“1” = RESET SHIFT REGISTER
SET
Q “0” = BUSY AND RESET STATE
RESET
CLK R 19
20 Ld PDIP
-40 to 85
20 Ld CERDIP
-40 to 85
20 Ld SOIC
PKG. NO E20.3 F20.3 F20.3 E20.3 F20.3 M20.3 F20.3 E20.3 F20.3 M20.3
Pinout
Typical Application Schematic
The ADC0802 family are CMOS 8-Bit, successive-approximation A/D converters which use a modified potentiometric ladder and are designed to operate with the 8080A control bus via three-state outputs. These converters appear to the processor as memory locations or I/O ports, and hence no interfacing logic is required.
The differential analog voltage input has good commonmode-rejection and permits offsetting the analog zero-inputvoltage value. In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution.
ADC0832中文资料及汇编程序
;拉低 CLK 端,形成下降沿 3
R7,#8 C,ADDO ACC.0,C A ADCLK
;准备送下后 8 个时钟脉冲 ;接收数据 ;左移一次
ADCLK
;形成一次时钟脉冲
R7,AD_1 C,ADDO ACC.0,C B,A R7,#8 C,ADDO ACC.0,C
;循环 8 次 ;接收数据
;接收数据
作为单通道模拟信号输入时 ADC0832 的输入电压是 0~5V 且 8 位分辨率时的电压精度 为 19.53mV。如果作为由 IN+与 IN-输入的输入时，可是将电压值设定在某一个较大范围之 内，从而提高转换的宽度。但值得注意的是，在进行 IN+与 IN-的输入时，如果 IN-的电压 大于 IN+的电压则转换后的数据结果始终为 00H。 ADC0832 芯片接口程序的编写： 为了高速有效的实现通信，我们采用汇编语言编写接口程序。由于 ADC0832 的数据转 换时间仅为 32μS，所以 A/D 转换的数据采样频率可以很快，从而也保证的某些场合对 A/D 转换数据实时性的要求。数据读取程序以子程序调用的形式出现，方便了程序的移植。 程 序占用资源有累加器 A，工作寄存器 R7,通用寄存器 B 和特殊寄存器 CY。通道功能寄 存器和转换值共用寄存器 B。在使用转换子程序之前必须确定通道功能寄存器 B 的值，其 赋值语句为“MOV B,#data”（00H~03H） 。运行转换子程序后的转换数据值被放入 B 中。 子程序退出后即可以对 B 中数据处理。 ADC0832 芯片接口程序[汇编]: ;以下接口定义根据硬件连线更改 ADCS BIT P3.5 ;使能接口 ADCLK BIT P3.4 ;时钟接口 ADDO BIT P3.3 ;数据输出接口（复用） ADDI BIT P3.3 ;数据输入接口 ;以下语句在调用转换程序前设定 MOV B,#00H ;装入通道功能选择数据值 ;以下为 ADC0832 读取数据子程序 ;==== ADC0832 读数据子程序==== ADCONV: SETB ADDI ;初始化通道选择 NOP NOP CLR ADCS ;拉低/CS 端 NOP NOP
(完整word版)adc0808中文资料
11.2.4 典型的集成ADC芯片为了满足多种需要，目前国内外各半导体器件生产厂家设计并生产出了多种多样的ADC芯片。
仅美国AD公司的ADC产品就有几十个系列、近百种型号之多。
从性能上讲，它们有的精度高、速度快，有的则价格低廉。
从功能上讲，有的不仅具有A/D转换的基本功能，还包括内部放大器和三态输出锁存器；有的甚至还包括多路开关、采样保持器等，已发展为一个单片的小型数据采集系统。
尽管ADC芯片的品种、型号很多，其内部功能强弱、转换速度快慢、转换精度高低有很大差别，但从用户最关心的外特性看，无论哪种芯片，都必不可少地要包括以下四种基本信号引脚端：模拟信号输入端(单极性或双极性)；数字量输出端(并行或串行)；转换启动信号输入端；转换结束信号输出端。
除此之外，各种不同型号的芯片可能还会有一些其他各不相同的控制信号端。
选用ADC芯片时，除了必须考虑各种技术要求外，通常还需了解芯片以下两方面的特性。
（1）数字输出的方式是否有可控三态输出。
有可控三态输出的ADC芯片允许输出线与微机系统的数据总线直接相连，并在转换结束后利用读数信号RD选通三态门，将转换结果送上总线。
没有可控三态输出(包括内部根本没有输出三态门和虽有三态门、但外部不可控两种情况)的ADC芯片则不允许数据输出线与系统的数据总线直接相连，而必须通过I/O接口与MPU交换信息。
（2）启动转换的控制方式是脉冲控制式还是电平控制式。
对脉冲启动转换的ADC芯片，只要在其启动转换引脚上施加一个宽度符合芯片要求的脉冲信号，就能启动转换并自动完成。
一般能和MPU配套使用的芯片，MPU的I/O写脉冲都能满足ADC芯片对启动脉冲的要求。
对电平启动转换的ADC芯片，在转换过程中启动信号必须保持规定的电平不变，否则，如中途撤消规定的电平，就会停止转换而可能得到错误的结果。
为此，必须用D 触发器或可编程并行I/O 接口芯片的某一位来锁存这个电平，或用单稳等电路来对启动信号进行定时变换。
ADC0820中文翻译资料
双线封装 （陶瓷） 表面贴片封装 蒸汽（60s） 红外线照射
300℃ 215℃ 220℃
操作实验参数
TMIN TA TMAX 温度范围 ADC0820CCJ － 40℃ TA ＋ 85℃ 封装功率逸散（25℃时） 875mW ADC0820CIWM －40℃ TA ＋85℃ 所有端口的当前输入（说明 5） 1mA ADC0820BCN,ADC0820CCN 封装的当前输入（说明 5） 4mA 0℃ TA 70℃ 静电放电磁化率 （说明 9） 1200V ADC0820BCV 0℃ TA 70℃ 焊接温度（焊接时 10s 内） ADC0820BCWM,ADC0820CCWM 双线封装 （塑料） 260℃ 0℃ TA 70℃ 转换特性： 下面的说明适用于 RD 模式 （pin VCC 范围 4.5V～8V 7=0） ， Vcc=5V, VREF ( ) 5V ,且 VREF ( ) GND ,除非有特殊说明， 黑体的限制参数是适用于 TMIN 到 TMAX 所有其他限制 TA T j 25 ℃
WR
/RDY
WR : 当 CS 为低电平，转换从 WR 的下降
沿开始。 大约 800ns （预置的内部输出时间，
INT 会变为低电平。 INT 会被 RD 或 CS 的
上升沿重置（见图 3，4） 。 10 11 GND 地线
t I ）之后的 WR 上升沿，转换结果将会选通
到输出锁存， 如果 RD 没有先于这个输出时 间被触发（见图 3，4） 。 WR-RD 模式 RDY:这是一个开漏输出（无内部上拉设 备） ，RDY 会在 CS 之后变为低电平；当转 换结果选通到输出锁存时，RDY 将会变为 三态。这被用来简化微处理器的显示界面 （见图 2） 。 模式 模式：模式选择输入—通过一个 50µA 的电 流源将其内部与 GND 连接起来 RD 模式：当模式为低电平时。 WR-RD 模式：当模式为高电平时。
ADC0832CCN
±1 ±1
± 1⁄2 ±1 ± 1⁄2 ±1
Molded (N) Molded (N) SO(M) PCC (V) PCC (V) Molded (N) C0831/ADC0832/ADC0834/ADC0838
Absolute Maximum Ratings
+
15 mA 6.5V
Operating Ratings (Notes 1, 2)
Supply Voltage, VCC Temperature Range ADC0832/8CIWM ADC0834BCN, ADC0838BCV, ADC0831/2/4/8CCN, ADC0838CCV, ADC0831/2/4/8CCWM 0˚C to +70˚C 4.5 VDC to 6.3 VDC TMIN≤TA≤TMAX −40˚C to +85˚C
2)
(Notes 1,
Dual-In-Line Package (Plastic) Molded Chip Carrier Package Vapor Phase (60 sec.) Infrared (15 sec.) ESD Susceptibility (Note 5)
260˚C 215˚C 220˚C 2000V
Key Specifications
n n n n n Resolution Total Unadjusted Error Single Supply Low Power Conversion Time 8 Bits
± 1⁄2 LSB and ± 1 LSB
5 VDC 15 mW 32 µs
Features
General Description
The ADC0831 series are 8-bit successive approximation A/D converters with a serial I/O and configurable input multiplexers with up to 8 channels. The serial I/O is configured to comply with the NSC MICROWIRE™ serial data exchange standard for easy interface to the COPS™ family of processors, and can interface with standard shift registers or µPs. The 2-, 4- or 8-channel multiplexers are software configured for single-ended or differential inputs as well as channel assignment. The differential analog voltage input allows increasing the common-mode rejection and offsetting the analog zero input voltage value. In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution. n n n n n n n n n n Operates ratiometrically or with 5 VDC voltage reference No zero or full-scale adjust required 2-, 4- or 8-channel multiplexer options with address logic Shunt regulator allows operation with high voltage supplies 0V to 5V input range with single 5V power supply Remote operation with serial digital data link TTL/MOS input/output compatible 0.3" standard width, 8-, 14- or 20-pin DIP package 20 Pin Molded Chip Carrier Package (ADC0838 only) Surface-Mount Package
ADC08032中文资料
ADC08031/ADC08032/ADC08034/ADC080388-Bit High-Speed Serial I/O A/D Converters withMultiplexer Options,Voltage Reference,and Track/Hold FunctionGeneral DescriptionThe ADC08031/ADC08032/ADC08034/ADC08038are 8-bit successive approximation A/D converters with serial I/O and configurable input multiplexers with up to 8channels.The serial I/O is configured to comply with the NSC MICROW-IRE ™serial data exchange standard for easy interface to the COPS ™family of controllers,and can easily interface with standard shift registers or microprocessors.The ADC08034and ADC08038provide a 2.6V band-gap de-rived reference.For devices offering guaranteed voltage ref-erence performance over temperature see ADC08131,ADC08134and ADC08138.A track/hold function allows the analog voltage at the positive input to vary during the actual A/D conversion.The analog inputs can be configured to operate in various combinations of single-ended,differential,or pseudo-differential modes.In addition,input voltage spans as small as 1V can be accommodated.Applicationsn Digitizing automotive sensors n Process control monitoringn Remote sensing in noisy environments nInstrumentationn Test systemsn Embedded diagnosticsFeaturesn Serial digital data link requires few I/O pins n Analog input track/hold functionn 2-,4-,or 8-channel input multiplexer options with address logicn 0V to 5V analog input range with single 5V power supplyn No zero or full scale adjustment required n TTL/CMOS input/output compatible n On chip 2.6V band-gap referencen 0.3"standard width 8-,14-,or 20-pin DIP package n 14-,20-pin small-outline packagesKey Specificationsn Resolution:8bitsn Conversion time (f C =1MHz):8µs (max)n Power dissipation:20mW (max)n Single supply:5V DC (±5%)n Total unadjusted error:±1⁄2LSB and ±1LSB nNo missing codes over temperatureOrdering InformationIndustrial (−40˚C ≤T A ≤+85˚C)Package ADC08031CIN*N08E ADC08038CIN*N20A ADC08031CIWM,ADC08032CIWM,M14B ADC08034CIWM ADC08038CIWMM20B*Not recomended for new designs.COPS ™microcontrollers and MICROWIRE ™are trademarks of National Semiconductor Corporation.June 2000ADC08031/ADC08032/ADC08034/ADC080388-Bit High-Speed Serial I/O A/D Converters with Multiplexer Options,Voltage Reference,and Track/Hold Function©2000National Semiconductor Corporation Connection DiagramsADC08038DS010555-2ADC08034DS010555-3ADC08031Dual-In-Line PackageDS010555-5ADC08032Small Outline PackageDS010555-30ADC08031Small Outline PackageDS010555-31A D C 08031/A D C 08032/A D C 08034/A D C 08038 2Absolute Maximum Ratings(Notes1,3) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Supply Voltage(V CC) 6.5V Voltage at Inputs and Outputs−0.3V to V CC+0.3V Input Current at Any Pin(Note4)±5mA Package Input Current(Note4)±20mA Power Dissipation at T A=25˚C(Note5)800mW ESD Susceptibility(Note6)1500VSoldering InformationN Package(10sec.)SO Package:Vapor Phase(60sec.)Infrared(15sec.)(Note7)235˚C215˚C220˚CStorage Temperature−65˚C to+150˚COperating Ratings(Notes2,3)Temperature Range T MIN≤T A≤T MAXADC08031BIN,ADC08031CIN,−40˚C≤T A≤+85˚CADC08032BIN,ADC08032CIN,ADC08034BIN,ADC08034CIN,ADC08038BIN,ADC08038CIN,ADC08031BIWM,ADC08032BIWM,ADC08034BIWM,ADC08038BIWMADC08031CIWM,ADC08032CIWM,ADC08034CIWM,ADC08038CIWMSupply Voltage(V CC) 4.5V DC to6.3V DCElectrical CharacteristicsThe following specifications apply for V CC=V REF=+5V DC,and f CLK=1MHz unless otherwise specified.Boldface limitsapply for T A=T J=T MIN to T MAX;all other limits T A=T J=25˚C.Symbol Parameter Conditions Typical Limits Units(Note8)(Note9)(Limits) CONVERTER AND MULTIPLEXER CHARACTERISTICSTotal Unadjusted Error(Note10)BIN,BIWM±1⁄2LSB(max)CIN,CIWM±1LSB(max)Differential8Bits(min)LinearityR REF Reference Input Resistance(Note11) 3.5kΩ1.3kΩ(min)6.0kΩ(max)V IN Analog Input Voltage(Note12)(V CC+0.05)V(max)(GND−0.05)V(min) DC Common-Mode Error±1⁄4LSB(max)Power Supply Sensitivity V CC=5V±5%,±1⁄4LSB(max)V REF=4.75VOn Channel Leakage On Channel=5V,0.2µA(max)Current(Note13)Off Channel=0V1On Channel=0V,−0.2µA(max)Off Channel=5V−1Off Channel Leakage On Channel=5V,−0.2µA(max)Current(Note13)Off Channel=0V−1On Channel=0V,0.2µA(max)Off Channel=5V1DIGITAL AND DC CHARACTERISTICSV IN(1)Logical“1”Input Voltage V CC=5.25V 2.0V(min)V IN(0)Logical“0”Input Voltage V CC=4.75V0.8V(max)I IN(1)Logical“1”Input Current V IN=5.0V1µA(max)I IN(0)Logical“0”Input Current V IN=0V−1µA(max)V OUT(1)Logical“1”Output Voltage V CC=4.75V:I OUT=−360µA 2.4V(min)I OUT=−10µA 4.5V(min)V OUT(0)Logical“0”Output Voltage V CC=4.75V0.4V(max)I OUT=1.6mAADC08031/ADC08032/ADC08034/ADC080383Electrical Characteristics(Continued)The following specifications apply for V CC =V REF =+5V DC ,and f CLK =1MHz unless otherwise specified.Boldface limits apply for T A =T J =T MIN to T MAX ;all other limits T A =T J =25˚C.SymbolParameterConditionsTypical Limits Units (Note 8)(Note 9)(Limits)DIGITAL AND DC CHARACTERISTICS I OUT TRI-STATE ®Output Current V OUT =0V −3.0µA (max)V OUT =5V 3.0µA (max)I SOURCE Output Source Current V OUT =0V −6.5mA (min)I SINK Output Sink Current V OUT =V CC8.0mA (min)I CCSupply CurrentADC08031,ADC08034,CS =HIGH3.0mA (max)and ADC08038ADC08032(Note 16)7.0mA (max)REFERENCE CHARACTERISTICS V REF OUTNominal Reference OutputV REF OUT Option Available Only on 2.6VADC08034and ADC08038Electrical CharacteristicsThe following specifications apply for V CC =V REF =+5V DC ,and t r =t f =20ns unless otherwise specified.Boldface limits apply for T A =T J =T MIN to T MAX ;all other limits T A =T J =25˚C.Symbol ParameterConditionsTypical Limits Units (Note 8)(Note 9)(Limits)f CLKClock Frequency 10kHz (min)1MHz (max)Clock Duty Cycle 40%(min)(Note 14)60%(max)T C Conversion Time (Not Including f CLK =1MHz81/f CLK (max)MUX Addressing Time)8µs (max)t CA Acquisition Time1⁄21/f CLK (max)t SELECT CLK High while CS is High 50ns t SET-UP CS Falling Edge or Data Input 25ns (min)Valid to CLK Rising Edge t HOLD Data Input Valid after CLK 20ns (min)Rising Edget pd1,t pd0CLK Falling Edge to Output C L =100pF:Data Valid (Note 15)Data MSB First 250ns (max)Data LSB First200ns (max)t 1H ,t 0HTRI-STATE Delay from Rising Edge C L =10pF,R L =10k Ω50nsof CS to Data Output and SARS Hi-Z(see TRI-STATE Test Circuits)C L =100pF,R L =2k Ω180ns (max)C IN Capacitance of Logic Inputs 5pF C OUTCapacitance of Logic Outputs5pFNote 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.Note 2:Operating Ratings indicate conditions for which the device is functional.These ratings do not guarantee specific performance limits.For guaranteed speci-fications and test conditions,see the Electrical Characteristics.The guaranteed specifications apply only for the test conditions listed.Some performance character-istics may degrade when the device is not operated under the listed test conditions.Note 3:All voltages are measured with respect to AGND =DGND =0V DC ,unless otherwise specified.Note 4:When the input voltage V IN at any pin exceeds the power supplies (V IN <(AGND or DGND)or V IN >V CC )the current at that pin should be limited to 5mA.The 20mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5mA to four pins.Note 5:The maximum power dissipation must be derated at elevated temperatures and is dictated by T JMAX ,θJA and the ambient temperature,T A .The maximum allowable power dissipation at any temperature is P D =(T JMAX −T A )/θJA or the number given in the Absolute Maximum Ratings,whichever is lower.For these de-A D C 08031/A D C 08032/A D C 08034/A D C 08038 4Electrical Characteristics(Continued)vices,T JMAX =125˚C.The typical thermal resistances (θJA )of these parts when board mounted follow:ADC08031and ADC08032with BIN and CIN suffixes 120˚C/W,ADC08038with CIN suffix 80˚C/W.ADC08031with CIWM suffix 140˚C/W,ADC08032140˚C/W,ADC08034140˚C/W,ADC08038with CIWM suffix 91˚C/W.Note 6:Human body model,100pF capacitor discharged through a 1.5k Ωresistor.Note 7:See AN450“Surface Mounting Methods and Their Effect on Product Reliability”or Linear Data Book section “Surface Mount”for other methods of soldering surface mount devices.Note 8:Typicals are at T J =25˚C and represent the most likely parametric norm.Note 9:Guaranteed to National’s AOQL (Average Outgoing Quality Level).Note 10:Total unadjusted error includes offset,full-scale,linearity,multiplexer.Note 11:Cannot be tested for the ADC08032.Note 12:For V IN(−)≥V IN(+)the digital code will be 00000000.Two on-chip diodes are tied to each analog input (see Block Diagram)which will forward-conduct for analog input voltages one diode drop below ground or one diode drop greater than V CC supply.During testing at low V CC levels (e.g.,4.5V),high level analog inputs (e.g.,5V)can cause an input diode to conduct,especially at elevated temperatures,which will cause errors for analog inputs near full-scale.The spec allows 50mV forward bias of either diode;this means that as long as the analog V IN does not exceed the supply voltage by more than 50mV,the output code will be correct.Ex-ceeding this range on an unselected channel will corrupt the reading of a selected channel.Achievement of an absolute 0V DC to 5V DC input voltage range will there-fore require a minimum supply voltage of 4.950V DC over temperature variations,initial tolerance and loading.Note 13:Channel leakage current is measured after a single-ended channel is selected and the clock is turned off.For off channel leakage current the following two cases are considered:one,with the selected channel tied high (5V DC )and the remaining seven off channels tied low (0V DC ),total current flow through the off chan-nels is measured;two,with the selected channel tied low and the off channels tied high,total current flow through the off channels is again measured.The two cases considered for determining on channel leakage current are the same except total current flow through the selected channel is measured.Note 14:A 40%to 60%duty cycle range insures proper operation at all clock frequencies.In the case that an available clock has a duty cycle outside of these limits the minimum time the clock is high or low must be at least 450ns.The maximum time the clock can be high or low is 100µs.Note 15:Since data,MSB first,is the output of the comparator used in the successive approximation loop,an additional delay is built in (see Block Diagram)to allow for comparator response time.Note 16:For the ADC08032V REF IN is internally tied to V CC ,therefore,for the ADC08032reference current is included in the supply current.Typical Performance CharacteristicsLinearity Error vs Reference VoltageDS010555-32Linearity Error vs TemperatureDS010555-33Linearity Error vs Clock FrequencyDS010555-34Power Supply Current vs Temperature (ADC08038,ADC08034,ADC08031)DS010555-35Note:For ADC08032add I REFOutput Current vs TemperatureDS010555-36Power Supply Current vs Clock FrequencyDS010555-37ADC08031/ADC08032/ADC08034/ADC080385Leakage Current Test CircuitTRI-STATE Test Circuits and WaveformsTiming DiagramsDS010555-7t 1HDS010555-38DS010555-39t 0HDS010555-40DS010555-41Data Input TimingDS010555-10*To reset these devices,CLK and CS must be simultaneously high for a period of t SELECT or greater.Otherwise these devices are compatible with industry standards ADC0831/2/4/8.A D C 08031/A D C 08032/A D C 08034/A D C 08038 6Timing Diagrams(Continued)Data Output TimingDS010555-11ADC08031Start Conversion TimingDS010555-12ADC08031TimingDS010555-13*LSB first output not available on ADC08031.LSB information is maintained for remainder of clock periods until CS goes high.ADC08032TimingDS010555-14ADC08031/ADC08032/ADC08034/ADC080387Timing Diagrams(Continued)ADC08034TimingDS010555-15A D C 08031/A D C 08032/A D C 08034/A D C 08038 8Timing Diagrams(Continued)A D C 08038T i m i n gD S 010555-16*M a k e s u r e c l o c k e d g e #18c l o c k s i n t h e L S B b e f o r e S E i s t a k e n l o wADC08031/ADC08032/ADC08034/ADC080389元器件交易网ADC08038Functional Block DiagramFunctional Description1.0MULTIPLEXER ADDRESSINGThe design of these converters utilizes a comparator struc-ture with built-in sample-and-hold which provides for a differ-ential analog input to be converted by a successive-approximation routine.The actual voltage converted is always the difference be-tween an assigned “+”input terminal and a “−”input terminal.The polarity of each input terminal of the pair indicates which line the converter expects to be the most positive.If the as-signed “+”input voltage is less than the “−”input voltage the converter responds with an all zeros output code.A unique input multiplexing scheme has been utilized to pro-vide multiple analog channels with software-configurable single-ended,differential,or pseudo-differential (which will convert the difference between the voltage at any analog in-put and a common terminal)operation.The analog signal conditioning required in transducer-based data acquisition systems is significantly simplified with this type of input flex-ibility.One converter package can now handle ground refer-enced inputs and true differential inputs as well as signals with some arbitrary reference voltage.A particular input configuration is assigned during the MUX addressing sequence,prior to the start of a conversion.The MUX address selects which of the analog inputs are to beD S 010555-17*S o m e o f t h e s e f u n c t i o n s /p i n s a r e n o t a v a i l a b l e w i t h o t h e r o p t i o n s .F o r t h e A D C 08034,t h e “S E L 1”F l i p -F l o p i s b y p a s s e d ,f o r t h e A D C 08032,b o t h “S E L 0”a n d “S E L 1”F l i p -F l o p s a r e b y p a s s e d .A D C 08031/A D C 08032/A D C 08034/A D C 0803810元器件交易网Functional Description(Continued) enabled and whether this input is single-ended or differential. Differential inputs are restricted to adjacent channel pairs. For example,channel0and channel1may be selected as a differential pair but channel0or1cannot act differentially with any other channel.In addition to selecting differential mode the polarity may also be selected.Channel0may be selected as the positive input and channel1as the negative input or vice versa.This programmability is best illustrated by the MUX addressing codes shown in the following tables for the various product options.The MUX address is shifted into the converter via the DI line. Because the ADC08031contains only one differential input channel with a fixed polarity assignment,it does not require addressing.The common input line(COM)on the ADC08038can be used as a pseudo-differential input.In this mode the voltage on this pin is treated as the“−”input for any of the other input channels.This voltage does not have to be analog ground;it can be any reference potential which is common to all of the inputs.This feature is most useful in single-supply applica-tions where the analog circuity may be biased up to a poten-tial other than ground and the output signals are all referred to this potential.TABLE1.Multiplexer/Package OptionsPartNumberNumber of AnalogChannelsNumber ofPackagePinsSingle-Ended DifferentialADC08031118ADC08032218ADC080344214ADC080388420TABLE2.MUX Addressing:ADC08038Single-Ended MUX ModeMUX Address Analog Single-Ended Channel#START SGL/ODD/SELECT01234567COM DIF SIGN1011000+−11001+−11010+−11011+−11100+−11101+−11110+−11111+−TABLE3.MUX Addressing:ADC08038Differential MUX ModeMUX Address Analog Differential Channel-Pair#START SGL/ODD/SELECT0123 DIF SIGN1001234567 10000+−10001+−10010+−10011+−10100−+10101−+10110−+10111−+ADC08031/ADC08032/ADC08034/ADC08038Functional Description(Continued)TABLE 4.MUX Addressing:ADC08034Single-Ended MUX ModeMUX AddressChannel #START SGL/ODD/SELECT123DIF SIGN 11100+1101+1110+1111+COM is internally tied to AGNDMUX Addressing:ADC08032Single-Ended MUX ModeMUX Address Channel #START SGL/ODD/01DIF SIGN 110+111+COM is internally tied to AGNDDifferential MUX ModeMUX AddressChannel #START SGL/ODD/SELECT123DIF SIGN 11000+−1001+−1010−+111−+Differential MUX ModeMUX Address Channel #START SGL/ODD/01DIF SIGN 100+−11−+Since the input configuration is under software control,it can be modified as required before each conversion.A channel can be treated as a single-ended,ground referenced input for one conversion;then it can be reconfigured as part of a differential channel for another conversion.Figure 1illus-trates the input flexibility which can be achieved.The analog input voltages for each channel can range from 50mV below ground to 50mV above V CC (typically 5V)with-out degrading conversion accuracy.2.0THE DIGITAL INTERFACEA most important characteristic of these converters is their serial data link with the controlling ing a serial communication format offers two very significant system im-provements;it allows many functions to be included in a small package and it can eliminate the transmission of lowlevel analog signals by locating the converter right at the analog sensor;transmitting highly noise immune digital data back to the host processor.To understand the operation of these converters it is best to refer to the Timing Diagrams and Functional Block Diagram and to follow a complete conversion sequence.For clarity a separate timing diagram is shown for each device.1.A conversion is initiated by pulling the CS (chip select)line low.This line must be held low for the entire conver-sion.The converter is now waiting for a start bit and its MUX assignment word.2.On each rising edge of the clock the status of the data in(DI)line is clocked into the MUX address shift register.The start bit is the first logic “1”that appears on this line (all leading zeros are ignored).Following the start bit the converter expects the next 2to 4bits to be the MUX as-signment word.A D C 08031/A D C 08032/A D C 08034/A D C 08038Functional Description(Continued)3.When the start bit has been shifted into the start locationof the MUX register,the input channel has been as-signed and a conversion is about to begin.An interval of 1⁄2clock period(where nothing happens)is automatically inserted to allow the selected MUX channel to settle.The SARS line goes high at this time to signal that a con-version is now in progress and the DI line is disabled(it no longer accepts data).4.The data out(DO)line now comes out of TRI-STATEand provides a leading zero for this one clock period of MUX settling time.5.During the conversion the output of the SAR comparatorindicates whether the analog input is greater than(high) or less than(low)a series of successive voltages gener-ated internally from a ratioed capacitor array(first5bits) and a resistor ladder(last3bits).After each comparison the comparator’s output is shipped to the DO line on the falling edge of CLK.This data is the result of the conver-sion being shifted out(with the MSB first)and can be read by the processor immediately.6.After8clock periods the conversion is completed.TheSARS line returns low to indicate this1⁄2clock cycle later.7.The stored data in the successive approximation registeris loaded into an internal shift register.If the programmer prefers the data can be provided in an LSB first format [this makes use of the shift enable(SE)control line].On the ADC08038the SE line is brought out and if held high the value of the LSB remains valid on the DO line.When SE is forced low the data is clocked out LSB first.On de-vices which do not include the SE control line,the data, LSB first,is automatically shifted out the DO line after the MSB first data stream.The DO line then goes low and stays low until CS is returned high.The ADC08031 is an exception in that its data is only output in MSB first format.8.All internal registers are cleared when the CS line is highand the t SELECT requirement is met.See Data Input Tim-ing under Timing Diagrams.If another conversion is de-sired CS must make a high to low transition followed by address information.The DI and DO lines can be tied together and controlled through a bidirectional processor I/O bit with one wire.This is possible because the DI input is only“looked-at”during the MUX addressing interval while the DO line is still in a high impedance state.8Single-EndedDS010555-488Pseudo-DifferentialDS010555-49 4DifferentialDS010555-50Mixed ModeDS010555-51 FIGURE1.Analog Input Multiplexer Options for the ADC08038ADC08031/ADC08032/ADC08034/ADC08038Functional Description(Continued)3.0REFERENCE CONSIDERATIONSThe voltage applied to the reference input on these convert-ers,V REF IN,defines the voltage span of the analog input (the difference between V IN(MAX)and V IN(MIN)over which the 256possible output codes apply.The devices can be used either in ratiometric applications or in systems requiring ab-solute accuracy.The reference pin must be connected to a voltage source capable of driving the reference input resis-tance which can be as low as 1.3k Ω.This pin is the top of a resistor divider string and capacitor array used for the suc-cessive approximation conversion.In a ratiometric system the analog input voltage is propor-tional to the voltage used for the A/D reference.This voltage is typically the system power supply,so the V REF IN pin can be tied to V CC (done internally on the ADC08032).This tech-nique relaxes the stability requirements of the system refer-ence as the analog input and A/D reference move together maintaining the same output code for a given input condition.For absolute accuracy,where the analog input varies be-tween very specific voltage limits,the reference pin can be biased with a time and temperature stable voltage source.For the ADC08034and the ADC08038a band-gap derived reference voltage of 2.6V (Note 8)is tied to V REF OUT.This can be tied back to V REF IN.Bypassing V REF OUT with a 100µF capacitor is recommended.The LM385and LM336reference diodes are good low current devices to use with these converters.The maximum value of the reference is limited to the V CC supply voltage.The minimum value,however,can be quite small (see Typical Performance Characteristics)to allow di-rect conversions of transducer outputs providing less than a 5V output span.Particular care must be taken with regard to noise pickup,circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1LSB equals V REF/256).4.0THE ANALOG INPUTSThe most important feature of these converters is that they can be located right at the analog signal source and through just a few wires can communicate with a controlling proces-sor with a highly noise immune serial bit stream.This in itself greatly minimizes circuitry to maintain analog signal accu-racy which otherwise is most susceptible to noise pickup.However,a few words are in order with regard to the analog inputs should the input be noisy to begin with or possibly riding on a large common-mode voltage.The differential input of these converters actually reduces the effects of common-mode input noise,a signal common to both selected “+”and “−”inputs for a conversion (60Hz is most typical).The time interval between sampling the “+”in-put and then the “−”input is 1⁄2of a clock period.The change in the common-mode voltage during this short time interval can cause conversion errors.For a sinusoidal common-mode signal this error is:where f CM is the frequency of the common-mode signal,V PEAK is its peak voltage value and f CLK is the A/D clock frequency.For a 60Hz common-mode signal to generate a 1⁄4LSB error (≈5mV)with the converter running at 250kHz,its peak value would have to be 6.63V which would be larger than allowed as it exceeds the maximum analog input limits.Source resistance limitation is important with regard to the DC leakage currents of the input multiplexer.Bypass capaci-tors should not be used if the source resistance is greater than 1k Ω.The worst-case leakage current of ±1µA over tem-perature will create a 1mV input error with a 1k Ωsource re-sistance.An op amp RC active low pass filter can provide both impedance buffering and noise filtering should a high impedance signal source be required.5.0OPTIONAL ADJUSTMENTS5.1Zero ErrorThe zero of the A/D does not require adjustment.If the mini-mum analog input voltage value,V IN(MIN),is not ground a zero offset can be done.The converter can be made to out-DS010555-52a)RatiometricDS010555-53b)Absolute with a Reduced SpanFIGURE 2.Reference ExamplesA D C 08031/A D C 08032/A D C 08034/A D C 08038Functional Description(Continued)put00000000digital code for this minimum input voltage by biasing any V IN(−)input at this V IN(MIN)value.This utilizes the differential mode operation of the A/D.The zero error of the A/D converter relates to the location of the first riser of the transfer function and can be measured by grounding the V IN(−)input and applying a small magnitude positive voltage to the V IN(+)input.Zero error is the differ-ence between the actual DC input voltage which is neces-sary to just cause an output digital code transition from0000 0000to00000001and the ideal1⁄2LSB value(1⁄2LSB= 9.8mV for V REF=5.000V DC).5.2Full ScaleThe full-scale adjustment can be made by applying a differ-ential input voltage which is11⁄2LSB down from the desired analog full-scale voltage range and then adjusting the mag-nitude of the V REF IN input(or V CC for the ADC08032)for a digital output code which is just changing from11111110to 11111111.5.3Adjusting for an Arbitrary Analog InputVoltage RangeIf the analog zero voltage of the A/D is shifted away from ground(for example,to accommodate an analog input signal which does not go to ground),this new zero reference should be properly adjusted first.A V IN(+)voltage whichequals this desired zero reference plus1⁄2LSB(where theLSB is calculated for the desired analog span,using1LSB=analog span/256)is applied to selected“+”input and thezero reference voltage at the corresponding“−”input shouldthen be adjusted to just obtain the00HEX to01HEX code tran-sition.The full-scale adjustment should be made[with the properV IN(−)voltage applied]by forcing a voltage to the V IN(+)in-put which is given by:where:V MAX=the high end of the analog input rangeandV MIN=the low end(the offset zero)of the analog range.(Both are ground referenced.)The V REF IN(or V CC)voltage is then adjusted to provide acode change from FE HEX to FF HEX.This completes the ad-justment procedure.ADC08031/ADC08032/ADC08034/ADC08038。
ADC0803中文资料
元器件交易网IMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinueany product or service without notice, and advise customers to obtain the latest version of relevant informationto verify, before placing orders, that information being relied on is current and complete. All products are soldsubject to the terms and conditions of sale supplied at the time of order acknowledgement, including thosepertaining to warranty, patent infringement, and limitation of liability.TI warrants performance of its semiconductor products to the specifications applicable at the time of sale inaccordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extentTI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarilyperformed, except those mandated by government requirements.CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OFDEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICALAPPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, ORWARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHERCRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TOBE FULLY AT THE CUSTOMER’S RISK.In order to minimize risks associated with the customer’s applications, adequate design and operatingsafeguards must be provided by the customer to minimize inherent or procedural hazards.TI assumes no liability for applications assistance or customer product design. TI does not warrant or representthat any license, either express or implied, is granted under any patent right, copyright, mask work right, or otherintellectual property right of TI covering or relating to any combination, machine, or process in which suchsemiconductor products or services might be or are used. TI’s publication of information regarding any thirdparty’s products or services does not constitute TI’s approval, warranty or endorsement thereof.Copyright © 1998, Texas Instruments Incorporated。
ADC0804中文资料_数据手册_参数
adc0808中文资料
11.2.4 典型的集成ADC芯片为了满足多种需要，目前国内外各半导体器件生产厂家设计并生产出了多种多样的ADC芯片。
仅美国AD公司的ADC产品就有几十个系列、近百种型号之多。
从性能上讲，它们有的精度高、速度快，有的则价格低廉。
从功能上讲，有的不仅具有A/D转换的基本功能，还包括内部放大器和三态输出锁存器；有的甚至还包括多路开关、采样保持器等，已发展为一个单片的小型数据采集系统。
尽管ADC芯片的品种、型号很多，其内部功能强弱、转换速度快慢、转换精度高低有很大差别，但从用户最关心的外特性看，无论哪种芯片，都必不可少地要包括以下四种基本信号引脚端：模拟信号输入端(单极性或双极性)；数字量输出端(并行或串行)；转换启动信号输入端；转换结束信号输出端。
除此之外，各种不同型号的芯片可能还会有一些其他各不相同的控制信号端。
选用ADC芯片时，除了必须考虑各种技术要求外，通常还需了解芯片以下两方面的特性。
（1）数字输出的方式是否有可控三态输出。
有可控三态输出的ADC芯片允许输出线与微机系统的数据总线直接相连，并在转换结束后利用读数信号RD选通三态门，将转换结果送上总线。
没有可控三态输出(包括内部根本没有输出三态门和虽有三态门、但外部不可控两种情况)的ADC芯片则不允许数据输出线与系统的数据总线直接相连，而必须通过I/O接口与MPU交换信息。
（2）启动转换的控制方式是脉冲控制式还是电平控制式。
对脉冲启动转换的ADC芯片，只要在其启动转换引脚上施加一个宽度符合芯片要求的脉冲信号，就能启动转换并自动完成。
一般能和MPU配套使用的芯片，MPU的I/O写脉冲都能满足ADC芯片对启动脉冲的要求。
对电平启动转换的ADC芯片，在转换过程中启动信号必须保持规定的电平不变，否则，如中途撤消规定的电平，就会停止转换而可能得到错误的结果。
为此，必须用D 触发器或可编程并行I/O 接口芯片的某一位来锁存这个电平，或用单稳等电路来对启动信号进行定时变换。
ADC08200 200MHz高速模数转换芯片
ADC082008-Bit,20MSPS to 200MSPS,1.05mW/MSPS A/D ConverterGeneral DescriptionThe ADC08200is a low-power,8-bit,monolithic analog-to-digital converter with an on-chip track-and-hold circuit.Opti-mized for low cost,low power,small size and ease of use,this product operates at conversion rates up to 230MSPS while consuming just 1.05mW per MHz of clock frequency,or 210mW at 200MSPS.Raising the PD pin puts the ADC08200into a Power Down mode where it consumes 1mW.The unique architecture achieves 7.3Effective Bits with 50MHz input frequency.The ADC08200is resistant to latch-up and the outputs are short-circuit proof.The top and bottom of the ADC08200’s reference ladder are available for connections,enabling a wide range of input possibilities.The digital outputs are TTL/CMOS compatible with a separate output power supply pin to support interfacing with 3V or 2.5V logic.The digital inputs (CLK and PD)are TTL/CMOS compatible.The ADC08200is offered in a 24-lead plastic package (TSSOP)and is specified over the industrial temperature range of −40˚C to +85˚C.Featuresn Single-ended inputn Internal sample-and-hold function n Low voltage (single +3V)operation n Small packagenPower-down featureKey Specificationsj Resolution:8bitsj Maximum sampling frequency:200MSPS (min)j DNL:±0.4LSB (typ)j ENOB (f IN =50MHz):7.3bits (typ)j THD (f IN =50MHz):−61dB (typ)j No missing codes Guaranteedj Power ConsumptionOperating 1.05mW/MSPS (typ)Power down1mW (typ)Applicationsn Flat panel displays n Projection systems n Set-top boxesn Battery-powered instruments n Communicationsn Medical scan converters n X-ray imagingn High speed viterbi decoders nAstronomyPin Configuration20017901May 2002ADC082008-Bit,20MSPS to 200MSPS,1.05mW/MSPS A/D Converter©2002National Semiconductor Corporation Ordering InformationADC08200CIMT TSSOPADC08200CIMTX TSSOP(tape and reel)Block Diagram20017902 Pin Descriptions and Equivalent CircuitsPin No.Symbol Equivalent Circuit Description6V IN2Pin Descriptions and Equivalent Circuits(Continued)Pin No.Symbol Equivalent Circuit Description23PD3Absolute Maximum Ratings(Notes 1,2)If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.Supply Voltage (V A )3.8VVoltage on Any Input or Output Pin −0.3V to V A Reference Voltage (V RT ,V RB )V A to AGND CLK,PD Voltage Range −0.05V to (V A +0.05V)Input Current at Any Pin (Note 3)±25mA Package Input Current (Note 3)±50mAPower Dissipation at T A =25˚C See (Note 4)ESD Susceptibility (Note 5)Human Body Model Machine Model2500V 200VSoldering Temperature,Infrared,10seconds (Note 6)235˚CStorage Temperature−65˚C to +150˚COperating Ratings (Notes 1,2)Operating Temperature Range −40˚C ≤T A ≤+85˚C Supply Voltage (V A )+2.7V to +3.6V Ground Difference |GND -DR GND|0V to 300mV Upper Reference Voltage (V RT )0.5V to (V A −0.3V)Lower Reference Voltage (V RB )0V to (V RT −0.5V)V IN Voltage RangeV RB to V RTConverter Electrical CharacteristicsThe following specifications apply for V A =V DR =+3.0V DC ,V RT =+1.9V,V RB =0.3V,C L =5pF,f CLK =200MHz at 50%duty cycle.Boldface limits apply for T A =T MIN to T MAX :all other limits T A =25˚C (Notes 7,8)Symbol ParameterConditionsTypical (Note 9)Limits (Note 9)Units (Limits)DC ACCURACY INL Integral Non-Linearity +1.0−0.3+1.9−1.2LSB (max)LSB (min)DNL Differential Non-Linearity ±0.4±0.95LSB (max)Missing Codes 0(max)FSE Full Scale Error 3650mV (max)V OFFZero Scale Offset4660mV (max)ANALOG INPUT AND REFERENCE CHARACTERISTICS V IN Input Voltage 1.6V RB V (min)V RTV (max)C IN V IN Input Capacitance V IN =0.75V +0.5Vrms(CLK LOW)3pF (CLK HIGH)4pF R IN R IN Input Resistance >1M ΩBW Full Power Bandwidth 500MHzV RT Top Reference Voltage 1.9V A V (max)0.5V (min)V RB Bottom Reference Voltage 0.3V RT −0.5V (max)0V (min)R REFReference Ladder ResistanceV RT to V RB160120Ω(min)200Ω(max)CLK,PD DIGITAL INPUT CHARACTERISTICS V IH Logical High Input Voltage V DR =V A =3.6V 2.0V (min)V IL Logical Low Input Voltage V DR =V A =2.7V 0.8V (max)I IH Logical High Input Current V IH =V DR =V A =3.6V 10nA I IL Logical Low Input Current V IL =0V,V DR =V A =2.7V−50nA C IN Logic Input Capacitance 3pF DIGITAL OUTPUT CHARACTERISTICSV OH High Level Output Voltage V A =V DR =2.7V,I OH =−400µA 2.6 2.4V (min)V OLLow Level Output VoltageV A =V DR =2.7V,I OL =1.0mA0.40.5V (max)DYNAMIC PERFORMANCEA D C 082004Converter Electrical Characteristics(Continued)The following specifications apply for V A=V DR=+3.0V DC,V RT=+1.9V,V RB=0.3V,C L=5pF,f CLK=200MHz at50%duty cycle.Boldface limits apply for T A=T MIN to T MAX:all other limits T A=25˚C(Notes7,8)Symbol Parameter Conditions Typical(Note9)Limits(Note9)Units(Limits)ENOB Effective Number of Bits f IN=4MHz,V IN=FS−0.25dB7.5Bitsf IN=20MHz,V IN=FS−0.25dB7.4Bitsf IN=50MHz,V IN=FS−0.25dB7.3 6.9Bits(min) f IN=70MHz,V IN=FS−0.25dB7.2Bitsf IN=100MHz,V IN=FS−0.25dB7.0BitsSINAD Signal-to-Noise&Distortion f IN=4MHz,V IN=FS−0.25dB47dBf IN=20MHz,V IN=FS−0.25dB46dBf IN=50MHz,V IN=FS−0.25dB4643.3dB(min) f IN=70MHz,V IN=FS−0.25dB45dBf IN=100MHz,V IN=FS−0.25dB44dBSNR Signal-to-Noise Ratio f IN=4MHz,V IN=FS−0.25dB47dBf IN=20MHz,V IN=FS−0.25dB46dBf IN=50MHz,V IN=FS−0.25dB4643.4dB(min) f IN=70MHz,V IN=FS−0.25dB45dBf IN=100MHz,V IN=FS−0.25dB44dBSFDR Spurious Free Dynamic Range f IN=4MHz,V IN=FS−0.25dB60dBc f IN=20MHz,V IN=FS−0.25dB58dBc f IN=50MHz,V IN=FS−0.25dB60dBc f IN=70MHz,V IN=FS−0.25dB57dBc f IN=100MHz,V IN=FS−0.25dB54dBcTHD Total Harmonic Distortion f IN=4MHz,V IN=FS−0.25dB−60dBc f IN=20MHz,V IN=FS−0.25dB−58dBc f IN=50MHz,V IN=FS−0.25dB−60dBc f IN=70MHz,V IN=FS−0.25dB-56dBc f IN=100MHz,V IN=FS−0.25dB−53dBcHD22nd Harmonic Distortion f IN=4MHz,V IN=FS−0.25dB−66dBc f IN=20MHz,V IN=FS−0.25dB-68dBc f IN=50MHz,V IN=FS−0.25dB−66dBc f IN=70MHz,V IN=FS−0.25dB-60dBc f IN=100MHz,V IN=FS−0.25dB−55dBcHD33rd Harmonic Distortion f IN=4MHz,V IN=FS−0.25dB−72dBc f IN=20MHz,V IN=FS−0.25dB−58dBc f IN=50MHz,V IN=FS−0.25dB−72dBc f IN=70MHz,V IN=FS−0.25dB-58dBc f IN=100MHz,V IN=FS−0.25dB−60dBcIMD Intermodulation Distortion f1=11MHz,V IN=FS−6.25dBf2=12MHz,V IN=FS−6.25dB-55dBcPOWER SUPPLY CHARACTERISTICSI A Analog Supply Current DC Input69.7586mA(max) f IN=10MHz,V IN=FS−3dB69.75mA(max)I DR Output Driver Supply Current DC Input,PD=Low0.250.6mA(max)I A+I DR Total Operating Current DC Input,PD=Low7086.6mA(max) CLK Low,PD=Hi0.3mAPC Power Consumption DC Input,Excluding Reference210260mW(max)PSRR1Power Supply Rejection Ratio FSE change with2.7V to3.3V changein V A54dBADC08200 5Converter Electrical Characteristics(Continued)The following specifications apply for V A=V DR=+3.0V DC,V RT=+1.9V,V RB=0.3V,C L=5pF,f CLK=200MHz at50%duty cycle.Boldface limits apply for T A=T MIN to T MAX:all other limits T A=25˚C(Notes7,8)Symbol Parameter Conditions Typical(Note9)Limits(Note9)Units(Limits)AC ELECTRICAL CHARACTERISTICSf C1Maximum Conversion Rate230200MHz(min) f C2Minimum Conversion Rate10MHzt CL Minimum Clock Low Time0.87 1.0ns(min) t CH Minimum Clock High Time0.650.75ns(min) t OH Output Hold Time CLK to Data Invalid 2.1nst OD Output Delay CLK to Data Transition 3.52.5ns(min) 5ns(max)Pipeline Delay(Latency)6Clock Cycles t AD Sampling(Aperture)Delay CLK Rise to Acquisition of Data 2.6nst AJ Aperture Jitter2ps rms Note1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.Operating Ratings indicate conditions for which the device is functional,but do not guarantee specific performance limits.For guaranteed specifications and test conditions,see the Electrical Characteristics.The guaranteed specifications apply only for the test conditions listed.Some performance characteristics may degrade when the device is not operated under the listed test conditions.Note2:All voltages are measured with respect to GND=AGND=DR GND=0V,unless otherwise specified.Note3:When the input voltage at any pin exceeds the power supplies(that is,less than AGND or DR GND,or greater than V A or V DR),the current at that pin should be limited to25mA.The50mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25mA to two.Note4:The absolute maximum junction temperature(T J max)for this device is150˚C.The maximum allowable power dissipation is dictated by T J max,the junction-to-ambient thermal resistance(θJA),and the ambient temperature(T A),and can be calculated using the formula P D MAX=(T J max−T A)/θJA.In the24-pin TSSOP,θJA is92˚C/W,so P D MAX=1,358mW at25˚C and435mW at the maximum operating ambient temperature of85˚C.Note that the power consumption of this device under normal operation will typically be about245mW(205mW quiescent power+16mW reference ladder power+24mW to drive the output bus capacitance).The values for maximum power dissipation listed above will be reached only when the ADC08200is operated in a severe fault condition(e.g.,when input or output pins are driven beyond the power supply voltages,or the power supply polarity is reversed).Obviously,such conditions should always be avoided.Note5:Human body model is100pF capacitor discharged through a1.5kΩresistor.Machine model is220pF discharged through ZERO Ohms.Note6:See AN-450,“Surface Mounting Methods and Their Effect on Product Reliability”.Note7:The analog inputs are protected as shown below.Input voltage magnitudes up to V A+300mV or to300mV below GND will not damage this device.However,errors in the A/D conversion can occur if the input goes above V DR or below GND by more than100mV.For example,if V A is2.7V DC the full-scale input voltage must be≤2.8V DC to ensure accurate conversions.6Specification DefinitionsAPERTURE(SAMPLING)DELAY is that time required after the rise of the clock input for the sampling switch to open. The Sample/Hold circuit effectively stops capturing the input signal and goes into the“hold”mode t AD after the clock goes high.APERTURE JITTER is the variation in aperture delay from sample to sample.Aperture jitter shows up as input noise. CLOCK DUTY CYCLE is the ratio of the time that the clock wave form is at a logic high to the total time of one clock period.DIFFERENTIAL NON-LINEARITY(DNL)is the measure of the maximum deviation from the ideal step size of1LSB. Measured at200MSPS with a ramp input.EFFECTIVE NUMBER OF BITS(ENOB,or EFFECTIVE BITS)is another method of specifying Signal-to-Noise and Distortion Ratio,or SINAD.ENOB is defined as(SINAD–1.76)/6.02and says that the converter is equivalent to a perfect ADC of this(ENOB)number of bits.FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops3dB below its low frequency value for a full scale input.FULL-SCALE ERROR is a measure of how far the last code transition is from the ideal11⁄2LSB below V REF and is defined as:V max+1.5LSB–V REFwhere V max is the voltage at which the transition to the maximum(full scale)code occurs.INTEGRAL NON-LINEARITY(INL)is a measure of the deviation of each individual code from a line drawn from zero scale(1⁄2LSB below the first code transition)through positive full scale(1⁄2LSB above the last code transition).The devia-tion of any given code from this straight line is measured from the center of that code value.The end point test method is used.Measured at200MSPS with a ramp input. INTERMODULATION DISTORTION(IMD)is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. it is defined as the ratio of the power in the second and thrid order intermodulation products to the power in one of the original frequencies.IMD is usually expressed in dBFS. MISSING CODES are those output codes that are skipped and will never appear at the ADC outputs.These codes cannot be reached with any input value.OUTPUT DELAY is the time delay after the rising edge of the input clock before the data update is present at the output pins.OUTPUT HOLD TIME is the length of time that the outputdata is valid after the rise of the input clock.PIPELINE DELAY(LATENCY)is the number of clock cyclesbetween initiation of conversion and when that data is pre-sented to the output driver stage.New data is available atevery clock cycle,but the data lags the conversion by thePipeline Delay plus the Output Delay.POWER SUPPLY REJECTION RATIO(PSRR)is a mea-sure of how well the ADC rejects a change in the powersupply voltage.For the ADC08200,PSRR1is the ratio of thechange in Full-Scale Error that results from a change in thedc power supply voltage,expressed in dB.PSRR2is ameasure of how well an a.c.signal riding upon the powersupply is rejected from the output.SIGNAL TO NOISE RATIO(SNR)is the ratio,expressed indB,of the rms value of the input signal at the output to therms value of the sum of all other spectral components belowone-half the sampling frequency,not including harmonics ordc.SIGNAL TO NOISE PLUS DISTORTION(S/(N+D)orSINAD)is the ratio,expressed in dB,of the rms value of theinput signal at the output to the rms value of all of the otherspectral components below half the clock frequency,includ-ing harmonics but excluding dc.SPURIOUS FREE DYNAMIC RANGE(SFDR)is the differ-ence,expressed in dB,between the rms values of the inputsignal at the output and the peak spurious signal,where aspurious signal is any signal present in the output spectrumthat is not present at the input.TOTAL HARMONIC DISTORTION(THD)is the ratio ex-pressed in dB,of the rms total of the first nine harmoniclevels at the output to the level of the fundamental at theoutput.THD is calculated as 7Timing DiagramTypical Performance Characteristics V=V DR=3V,f CLK=200MHz,f IN=50MHz,unless other-Awise statedINL INL vs Temperature2001790820017914 INL vs Supply Voltage INL vs Sample Rate20017915200179108Typical Performance Characteristics V A =V DR =3V,f CLK =200MHz,f IN =50MHz,unlessotherwise stated (Continued)DNLDNL vs Temperature2001790920017917DNL vs Supply Voltage DNL vs Sample Rate2001791820017911SNR vs Temperature SNR vs Supply Voltage2001792020017921ADC082009Typical Performance Characteristics V A =V DR =3V,f CLK =200MHz,f IN =50MHz,unlessotherwise stated (Continued)SNR vs Sample RateSNR vs Input Frequency2001791220017923SNR vs Clock Duty Cycle Distortion vs Temperature2001792420017925Distortion vs Supply Voltage Distortion vs Sample Rate2001792620017913A D C 08200 10Typical Performance Characteristics V A =V DR =3V,f CLK =200MHz,f IN =50MHz,unlessotherwise stated (Continued)Distortion vs Input FrequencyDistortion vs Clock Duty Cycle2001792820017929SINAD/ENOB vs Temperature SINAD/ENOB vs Supply Voltage2001793020017938SINAD/ENOB vs Sample Rate SINAD/ENOB vs Input Frequency2001791620017939ADC0820011Typical Performance Characteristics V A =V DR =3V,f CLK =200MHz,f IN =50MHz,unlessotherwise stated (Continued)SINAD/ENOB vs Clock Duty CyclePower Consumption vs Sample Rate2001794020017919Spectral Response @f IN =50MHz Spectral Response @f IN =76MHz2001794620017947Spectral Response @f IN =99MHzIntermodulation Distortion2001794820017943A D C 08200 12Functional DescriptionThe ADC08200uses a new,unique architecture that achieves over7effective bits at input frequencies up to and beyond100MHz.The analog input signal that is within the voltage range set by V RT and V RB is digitized to eight bits.Input voltages below V RB will cause the output word to consist of all zeroes.Input voltages above V RT will cause the output word to consist of all ones.Incorporating a switched capacitor bandgap,the ADC08200 exhibits a power consumption that is proportional to fre-quency,limiting power consumption to what is needed at the clock rate that is used.This and its excellent performance over a wide range of clock frequencies makes it an ideal choice as a single ADC for many8-bit needs.Data is acquired at the rising edge of the clock and the digital equivalent of that data is available at the digital outputs6 clock cycles plus t OD later.The ADC08200will convert as long as the clock signal is present.The device is in the active state when the Power Down pin(PD)is low.When the PD pin is high,the device is in the power down mode,where the output pins hold the last conversion before the PD pin went high and the device consumes just1mW. Applications Information1.0REFERENCE INPUTSThe reference inputs V RT and V RB are the top and bottom of the reference ladder,respectively.Input signals between these two voltages will be digitized to8bits.External volt-ages applied to the reference input pins should be within the range specified in the Operating Ratings table(0.5V to(V A−0.3V)for V RT and−100mV to(V RT−0.5V)for V RB).Any device used to drive the reference pins should be able to source sufficient current into the V RT pin and sink sufficient current from the V RB pin.The reference bias circuit of Figure2is very simple and the performance is adequate for many applications.However, circuit tolerances will lead to a wide referance voltage range. Better reference stability can be achieved by driving the reference pins with low impedance sources.The circuit of Figure3will allow a more accurate setting of the reference voltages.The lower amplifier must have bipo-lar supplies as its output voltage must go negative to force V RB to any voltage below the V BE of the PNP transistor.Of course,the divider resistors at the amplifier input could be changed to suit your reference voltage needs,or the divider can be replaced with potentiometers for precise settings.The bottom of the ladder(V RB)may simply be returned to ground if the minimum input signal excursion is0V.Be sure that the driving source can source sufficient current into the V RT pin and sink enough current from the V RB pin to keep these pins stable.The LMC662amplifier shown was chosen for its low offset voltage and low cost.V RT should always be at least0.5V more positive than V RB to minimize noise.The V RM pin is the center of the reference ladder and should be bypassed to a quiet point in the analog ground plane with a0.1µF capacitor.DO NOT allow this pin to float.20017932FIGURE2.Simple,low component count reference biasing.Because of the ladder and external resistor tolerances,the reference voltage can vary too much for some applications.ADC0820013Applications Information(Continued)2.0THE ANALOG INPUTThe analog input of the ADC08200is a switch followed by an integrator.The input capacitance changes with the clock level,appearing as 3pF when the clock is low,and 4pF when the clock is high.Since a dynamic capacitance is more difficult to drive than is a fixed capacitance,choose an amplifier that can drive this type of load.Figure 4shows an example of an input circuit using the CLC409.Any input amplifier should incorporate some gain as operational amplifiers exhibit better phase margin and transient response with gains above 2or 3than with unity gain.If an overall gain of less than 3is required,attenuate the input and operate the amplifier at a higher gain,as shown in Figure 4.The RC at the amplifier output filters the clock rate energy that comes out of the analog input due to the input sampling circuit.The optimum time constant for this circuit depends not only upon the amplifier and ADC,but also on the circuit layout and board material.A resistor value should be chosen between 18Ωand 47Ωand the capacitor value chose ac-cording to the formulaThis will provide optimum SNR performance.Best THD per-formance is realized when the capacitor and resistor values are both zero.To optimize SINAD,reduce the capacitor value until SINAD performance is optimized.That is,until SNR =−THD.This value will usually be in the range of 20%to 65%of the value calculated with the above formula.An accurate calculation is not possible because of the board material and layout dependence.The circuit of Figure 4has both gain and offset adjustments.If you eliminate these adjustments normal circuit tolerances may result in signal clipping unless care is exercised in the worst case analysis of component tolerances and the input signal excursion is appropriately limited to account for the worst case conditions.20017933FIGURE 3.Driving the reference to force desired values requires driving with a low impedance source.A D C 08200 14Applications Information(Continued)3.0POWER SUPPLY CONSIDERATIONSA/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed.A 10µF tantalum or aluminum electrolytic capacitor should be placed within an inch(2.5cm)of the A/D power pins,with a 0.1µF ceramic chip capacitor placed within one centimeter of the converter’s power supply pins.Leadless chip capaci-tors are preferred because they have low lead inductance. While a single voltage source is recommended for the V A and V DR supplies of the ADC08200,these supply pins should be well isolated from each other to prevent any digital noise from being coupled into the analog portions of the ADC.A choke or27Ωresistor is recommended between these supply lines with adequate bypass capacitors close to the supply pins.As is the case with all high speed converters,the ADC08200 should be assumed to have little power supply rejection. None of the supplies for the converter should be the supply that is used for other digital circuitry in any system with a lot of digital power being consumed.The ADC supplies should be the same supply used for other analog circuitry.No pin should ever have a voltage on it that is in excess of the supply voltage or below ground by more than300mV, not even on a transient basis.This can be a problem upon application of power and power shut-down.Be sure that the supplies to circuits driving any of the input pins,analog or digital,do not come up any faster than does the voltage at the ADC08200power pins.4.0THE DIGITAL INPUT PINSThe ADC08200has two digital input pins:The PD pin and the Clock pin.4.1The PD PinThe Power Down(PD)pin,when high,puts the ADC08200 into a low power mode where power consumption is reduced to1mW.Once the clock is restored,there is a time of6clock cycles plus t OD before the output data is valid.The digital output pins retain the last conversion output code when either the clock is stopped or the PD pin is high.4.2The ADC08200ClockAlthough the ADC08200is tested and its performance is guaranteed with a200MHz clock,it typically will function well with clock frequencies from10MHz to230MHz.The low and high times of the clock signal can affect the performance of any A/D Converter.Because achieving a precise duty cycle is difficult,the ADC08200is designed to maintain performance over a range of duty cycles.While it is specified and performance is quaranteed with a50%clock duty cycle and200Msps,ADC08200performance is typi-cally maintained with clock high and low times of0.65ns and 0.87ns,respectively,corresponding to a clock duty cycle range of13%to82.5%with a200MHz clock.The CLOCK line should be series terminated at the clock source in the characteristic impedance of that line.If the clock line is longer than20017934FIGURE4.The input amplifier should incorporate some gain for best performance(see text).ADC0820015Applications Information(Continued)where t r is the clock rise time and t prop is the propagation rate of the signal along the trace,the CLOCK pin should be a.c.terminated with a series RC to ground such that the resisitor value is equal to the characteristic impedance of the clock line and the capacitor value iswhere ’l’is the line length in inches and Z o is the character-istic impedance of the clock line.This termination should be located as close as possible to,but within one centimeter of,the ADC08200clock pin.5.0LAYOUT AND GROUNDINGProper grounding and proper routing of all signals are es-sential to ensure accurate conversion.A combined analog and digital ground plane should be used.Since digital switching transients are composed largely of high frequency components,total ground plane copper weight will have little effect upon the logic-generated noise because of the skin effect.Total surface area is more impor-tant than is total ground plane volume.Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor performance that may seem impossible to isolate and remedy.The solution is to keep the analog circuitry well separated from the digital circuitry.High power digital components should not be located on or near a straight line between the ADC or any linear compo-nent and the power supply area as the resulting common return current path could cause fluctuation in the analog input “ground”return of the ADC.Generally,analog and digital lines should cross each other at 90˚to avoid getting digital noise into the analog path.In high frequency systems,however,avoid crossing analog and digital lines altogether.Clock lines should be isolated from ALL other lines,analog AND digital.Even the generally accepted 90˚crossing should be avoided as even a little coupling can cause problems at high frequencies.Best per-formance at high frequencies is obtained with a straight signal path.The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.Any external component (e.g.,a filter capacitor)connected be-tween the converter’s input and ground should be connected to a very clean point in the analog ground plane.Figure 5gives an example of a suitable layout.All analog circuitry (input amplifiers,filters,reference components,etc.)should be placed together away from any digital compo-nents.6.0DYNAMIC PERFORMANCEThe ADC08200is ac tested and its dynamic performance is guaranteed.To meet the published specifications,the clock source driving the CLK input must exhibit less than 2ps (rms)of jitter.For best ac performance,isolating the ADC clock from any digital circuitry should be done with adequate buffers,as with a clock tree.See Figure 6.It is good practice to keep the ADC clock line as short as possible and to keep it well away from any other signals.Other signals can introduce jitter into the clock signal.The clock signal can also introduce noise into the analog path.7.0COMMON APPLICATION PITFALLSDriving the inputs (analog or digital)beyond the power supply rails.For proper operation,all inputs should not go more than 300mV below the ground pins or 300mV above the supply pins.Exceeding these limits on even a transient basis may cause faulty or erratic operation.It is not uncom-mon for high speed digital circuits (e.g.,74F and 74AC20017936FIGURE yout Example 16Applications Information(Continued) devices)to exhibit undershoot that goes more than a volt below ground.A51Ωresistor in series with the offending digital input will usually eliminate the problem.Care should be taken not to overdrive the inputs of the ADC08200.Such practice may lead to conversion inaccura-cies and even to device damage.Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must charge for each conversion,the more instantaneous digital current is required from V DR and DR GND.These large charging cur-rent spikes can couple into the analog section,degrading dynamic performance.Buffering the digital data outputs(with a74AF541,for example)may be necessary if the data bus capacitance exceeds5pF.Dynamic performance can also be improved by adding33Ωto47Ωseries resistors at each digital output,reducing the energy coupled back into the converter input pins.Using an inadequate amplifier to drive the analog input. As explained in Section2.0,the capacitance seen at theinput alternates between3pF and4pF with the clock.Thisdynamic capacitance is more difficult to drive than is a fixedcapacitance,and should be considered when choosing adriving device.Driving the V RT pin or the V RB pin with devices that cannot source or sink the current required by the ladder.Asmentioned in Section1.0,care should be taken to see thatany driving devices can source sufficient current into the V RTpin and sink sufficient current from the V RB pin.If these pinsare not driven with devices than can handle the requiredcurrent,these reference pins will not be stable,resulting in areduction of dynamic performance.Using a clock source with excessive jitter,using anexcessively long clock signal trace,or having othersignals coupled to the clock signal trace.This will causethe sampling interval to vary,causing excessive output noiseand a reduction in SNR performance.The use of simplegates with RC timing is generally inadequate as a clocksource.ADC0820017。
ADC0804LCNNOPB;ADC0803LCN;ADC0803LCNNOPB;ADC0802LCNNOPB;ADC0804LCWMX;中文规格书,Datasheet资料
ADC0801/ADC0802/ADC0803/ADC0804/ADC08058-Bit µP Compatible A/D ConvertersGeneral DescriptionThe ADC0801,ADC0802,ADC0803,ADC0804and ADC0805are CMOS 8-bit successive approximation A/D converters that use a differential potentiometric ladder —similar to the 256R products.These converters are designed to allow operation with the NSC800and INS8080A derivative control bus with TRI-STATE output latches directly driving the data bus.These A/Ds appear like memory loca-tions or I/O ports to the microprocessor and no interfacing logic is needed.Differential analog voltage inputs allow increasing the common-mode rejection and offsetting the analog zero input voltage value.In addition,the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8bits of resolution.Featuresn Compatible with 8080µP derivatives —no interfacing logic needed -access time -135nsn Easy interface to all microprocessors,or operates “stand alone”n Differential analog voltage inputsn Logic inputs and outputs meet both MOS and TTL voltage level specificationsn Works with 2.5V (LM336)voltage reference n On-chip clock generatorn 0V to 5V analog input voltage range with single 5V supplyn No zero adjust requiredn 0.3"standard width 20-pin DIP packagen 20-pin molded chip carrier or small outline package n Operates ratiometrically or with 5V DC ,2.5V DC ,or analog span adjusted voltage referenceKey Specificationsn Resolution 8bitsn Total error±1⁄4LSB,±1⁄2LSB and ±1LSBn Conversion time100µsConnection DiagramOrdering InformationTEMP RANGE0˚C TO 70˚C 0˚C TO 70˚C−40˚C TO +85˚C ±1⁄4Bit Adjusted ADC0801LCN ERROR±1⁄2Bit Unadjusted ADC0802LCWM ADC0802LCN ±1⁄2Bit Adjusted ADC0803LCN±1Bit UnadjustedADC0804LCWM ADC0804LCN ADC0805LCN/ADC0804LCJPACKAGE OUTLINEM20B —SmallOutlineN20A —Molded DIPZ-80®is a registered trademark of Zilog Corp.ADC080XDual-In-Line and Small Outline (SO)PackagesDS005671-30See Ordering InformationNovember 1999ADC0801/ADC0802/ADC0803/ADC0804/ADC08058-Bit µP Compatible A/D Converters©2001National Semiconductor Corporation Typical ApplicationsError Specification (Includes Full-Scale,Zero Error,and Non-Linearity)Part Full-V REF /2=2.500V DC V REF /2=No Connection Number Scale (No Adjustments)(No Adjustments)AdjustedADC0801±1⁄4LSBADC0802±1⁄2LSBADC0803±1⁄2LSBADC0804±1LSBADC0805±1LSBDS005671-18080InterfaceDS005671-31A D C 0801/A D C 0802/A D C 0803/A D C 0804/A D C 0805 2Absolute Maximum Ratings(Notes1,2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Supply Voltage(V CC)(Note3) 6.5V VoltageLogic Control Inputs−0.3V to+18V At Other Input and Outputs−0.3V to(V CC+0.3V) Lead Temp.(Soldering,10seconds)Dual-In-Line Package(plastic)260˚C Dual-In-Line Package(ceramic)300˚C Surface Mount PackageVapor Phase(60seconds)215˚CInfrared(15seconds)220˚C Storage Temperature Range−65˚C to+150˚C Package Dissipation at T A=25˚C875mW ESD Susceptibility(Note10)800VOperating Ratings(Notes1,2)Temperature Range T MIN≤T A≤T MAX ADC0804LCJ−40˚C≤T A≤+85˚C ADC0801/02/03/05LCN−40˚C≤T A≤+85˚C ADC0804LCN0˚C≤T A≤+70˚C ADC0802/04LCWM0˚C≤T A≤+70˚C Range of V CC 4.5V DC to6.3V DCElectrical CharacteristicsThe following specifications apply for V CC=5V DC,T MIN≤T A≤T MAX and f CLK=640kHz unless otherwise specified.Parameter Conditions Min Typ Max UnitsADC0801:Total Adjusted Error(Note8)With Full-Scale Adj.±1⁄4LSB(See Section2.5.2)ADC0802:Total Unadjusted Error(Note8)V REF/2=2.500V DC±1⁄2LSBADC0803:Total Adjusted Error(Note8)With Full-Scale Adj.±1⁄2LSB(See Section2.5.2)ADC0804:Total Unadjusted Error(Note8)V REF/2=2.500V DC±1LSBADC0805:Total Unadjusted Error(Note8)V REF/2-No Connection±1LSBV REF/2Input Resistance(Pin9)ADC0801/02/03/05 2.58.0kΩADC0804(Note9)0.75 1.1kΩAnalog Input Voltage Range(Note4)V(+)or V(−)Gnd–0.05V CC+0.05V DCDC Common-Mode Error Over Analog Input Voltage±1/16±1⁄8LSBRangePower Supply Sensitivity V CC=5V DC±10%Over±1/16±1⁄8LSBAllowed V IN(+)and V IN(−)Voltage Range(Note4)AC Electrical CharacteristicsThe following specifications apply for V CC=5V DC and T MIN≤T A≤T MAX unless otherwise specified.Symbol Parameter Conditions Min Typ Max UnitsT C Conversion Time f CLK=640kHz(Note6)103114µsT C Conversion Time(Notes5,6)66731/f CLKf CLK Clock Frequency V CC=5V,(Note5)1006401460kHzClock Duty Cycle4060%CR Conversion Rate in Free-Running INTR tied to WR with87709708conv/s Mode CS=0V DC,f CLK=640kHzt W(WR)L Width of WR Input(Start Pulse Width)CS=0V DC(Note7)100nst ACC Access Time(Delay from Falling C L=100pF135200ns Edge of RD to Output Data Valid)t1H,t0H TRI-STATE Control(Delay C L=10pF,R L=10k125200ns from Rising Edge of RD to(See TRI-STATE TestHi-Z State)Circuits)t WI,t RI Delay from Falling Edge300450ns of WR or RD to Reset of INTRC IN Input Capacitance of Logic57.5pFControl InputsADC0801/ADC0802/ADC0803/ADC0804/ADC08053AC Electrical Characteristics(Continued)The following specifications apply for V CC =5V DC and T MIN ≤T A ≤T MAX unless otherwise specified.Symbol ParameterConditionsMinTyp Max Units C OUTTRI-STATE Output 57.5pFCapacitance (Data Buffers)CONTROL INPUTS [Note:CLK IN (Pin 4)is the input of a Schmitt trigger circuit and is therefore specified separately]V IN (1)Logical “1”Input Voltage V CC =5.25V DC2.015V DC(Except Pin 4CLK IN)V IN (0)Logical “0”Input Voltage V CC =4.75V DC0.8V DC(Except Pin 4CLK IN)I IN (1)Logical “1”Input Current V IN =5V DC0.0051µA DC(All Inputs)I IN (0)Logical “0”Input Current V IN =0V DC−1−0.005µA DC(All Inputs)CLOCK IN AND CLOCK R V T +CLK IN (Pin 4)Positive Going 2.73.13.5V DCThreshold Voltage V T −CLK IN (Pin 4)Negative 1.51.82.1V DCGoing Threshold Voltage V HCLK IN (Pin 4)Hysteresis 0.61.32.0V DC(V T +)−(V T −)V OUT (0)Logical “0”CLK R Output I O =360µA 0.4V DCVoltageV CC =4.75V DC V OUT (1)Logical “1”CLK R Output I O =−360µA 2.4V DCVoltageV CC =4.75V DCDATA OUTPUTS AND INTR V OUT (0)Logical “0”Output Voltage Data Outputs I OUT =1.6mA,V CC =4.75V DC 0.4V DC INTR OutputI OUT =1.0mA,V CC =4.75V DC 0.4V DC V OUT (1)Logical “1”Output Voltage I O =−360µA,V CC =4.75V DC 2.4V DC V OUT (1)Logical “1”Output Voltage I O =−10µA,V CC =4.75V DC 4.5V DC I OUT TRI-STATE Disabled Output V OUT =0V DC −3µA DC Leakage (All Data Buffers)V OUT =5V DC3µA DC I SOURCE V OUT Short to Gnd,T A =25˚C 4.56mA DC I SINKV OUT Short to V CC ,T A =25˚C9.016mA DCPOWER SUPPLY I CCSupply Current (Includes f CLK =640kHz,Ladder Current)V REF /2=NC,T A =25˚C and CS =5VADC0801/02/03/04LCJ/05 1.1 1.8mA ADC0804LCN/LCWM1.92.5mANote 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions.Note 2:All voltages are measured with respect to Gnd,unless otherwise specified.The separate A Gnd point should always be wired to the D Gnd.Note 3:A zener diode exists,internally,from V CC to Gnd and has a typical breakdown voltage of 7V DC .Note 4:For V IN (−)≥V IN (+)the digital output code will be 00000000.Two on-chip diodes are tied to each analog input (see block diagram)which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the V CC supply.Be careful,during testing at low V CC levels (4.5V),as high level analog inputs (5V)can cause this input diode to conduct–especially at elevated temperatures,and cause errors for analog inputs near full-scale.The spec allows 50mV forward bias of either diode.This means that as long as the analog V IN does not exceed the supply voltage by more than 50mV,the output code will be correct.To achieve an absolute 0V DC to 5V DC input voltage range will therefore require a minimum supply voltage of 4.950V DC over temperature variations,initial tolerance and loading.Note 5:Accuracy is guaranteed at f CLK =640kHz.At higher clock frequencies accuracy can degrade.For lower clock frequencies,the duty cycle limits can be extended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275ns.Note 6:With an asynchronous start pulse,up to 8clock periods may be required before the internal clock phases are proper to start the conversion process.The start request is internally latched,see Figure 4and section 2.0.A D C 0801/A D C 0802/A D C 0803/A D C 0804/A D C 0805 4AC Electrical Characteristics(Continued)Note7:The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width.An arbitrarily wide pulse width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse(see timing diagrams).Note8:None of these A/Ds requires a zero adjust(see section2.5.1).To obtain zero code at other analog input voltages see section2.5and Figure7.Note9:The V REF/2pin is the center point of a two-resistor divider connected from V CC to ground.In all versions of the ADC0801,ADC0802,ADC0803,and ADC0805,and in the ADC0804LCJ,each resistor is typically16kΩ.In all versions of the ADC0804except the ADC0804LCJ,each resistor is typically2.2kΩ. Note10:Human body model,100pF discharged through a1.5kΩresistor.Typical Performance CharacteristicsLogic Input Threshold Voltage vs.Supply VoltageDS005671-38Delay From Falling Edge ofRD to Output Data Validvs.Load CapacitanceDS005671-39CLK IN Schmitt Trip Levelsvs.Supply VoltageDS005671-40f CLK vs.Clock CapacitorDS005671-41Full-Scale Error vsConversion TimeDS005671-42Effect of Unadjusted Offset Errorvs.V REF/2VoltageDS005671-43Output Current vsTemperatureDS005671-44Power Supply Currentvs Temperature(Note9)DS005671-45Linearity Error at LowV REF/2VoltagesDS005671-46ADC0801/ADC0802/ADC0803/ADC0804/ADC08055TRI-STATE Test Circuits and WaveformsTiming Diagrams(All timing is measured from the 50%voltage points)t 1HDS005671-47t 1H ,C L =10pFDS005671-48t r =20nst 0H DS005671-49t 0H ,C L =10pFDS005671-50t r =20nsDS005671-51A D C 0801/A D C 0802/A D C 0803/A D C 0804/A D C 0805 6Timing Diagrams(All timing is measured from the 50%voltage points)(Continued)Typical ApplicationsOutput Enable and Reset with INTRDS005671-52Note:Read strobe must occur 8clock periods (8/f CLK )after assertion of interrupt to guarantee reset of INTR .6800InterfaceDS005671-53Ratiometeric with Full-Scale AdjustDS005671-54Note:before using caps at V IN or V REF /2,see section 2.3.2Input Bypass Capacitors.ADC0801/ADC0802/ADC0803/ADC0804/ADC08057Typical Applications(Continued)Absolute with a 2.500V ReferenceDS005671-55*For low power,see also LM385–2.5Absolute with a 5V ReferenceDS005671-56Zero-Shift and Span Adjust:2V ≤V IN ≤5V DS005671-57Span Adjust:0V ≤V IN ≤3VDS005671-58A D C 0801/A D C 0802/A D C 0803/A D C 0804/A D C 0805 8Typical Applications(Continued)Directly Converting a Low-Level SignalDS005671-59V REF /2=256mVA µP Interfaced ComparatorDS005671-60For:V IN (+)>V IN (−)Output=FF HEX For:V IN (+)<V IN (−)Output=00HEX1mV Resolution with µP Controlled RangeDS005671-61V REF /2=128mV 1LSB=1mVV DAC ≤V IN ≤(V DAC +256mV)0≤V DAC <2.5VADC0801/ADC0802/ADC0803/ADC0804/ADC08059Typical Applications(Continued)Digitizing a Current FlowDS005671-62Self-Clocking Multiple A/Ds DS005671-63*Use a large R value to reduce loading at CLK R output.External ClockingDS005671-64100kHz ≤f CLK ≤1460kHzA D C 0801/A D C 0802/A D C 0803/A D C 0804/A D C 0805 10分销商库存信息:NATIONAL-SEMICONDUCTORADC0804LCN/NOPB ADC0803LCN ADC0803LCN/NOPB ADC0802LCN/NOPB ADC0804LCWMX ADC0804LCWMX/NOPB ADC0804LCWM/NOPB ADC0801LCN/NOPB ADC0804LCWMADC0802LCWM/NOPB ADC0805LCN/NOPB ADC0804LCJADC0802LCWMX/NOPB。
ADC--ADC0832及其应用
DAC0832一） D/A转换器DAC0832DAC0832是采用CMOS工艺制成的单片直流输出型8位数/模转换器。
如图4-82所示，它由倒T型R-2R电阻网络、模拟开关、运算放大器和参考电压VREF四大部分组成。
运算放大器输出的模拟量V0为：图4-82由上式可见，输出的模拟量与输入的数字量（）成正比，这就实现了从数字量到模拟量的转换。
一个8位D/A转换器有8个输入端（其中每个输入端是8位二进制数的一位），有一个模拟输出端。
输入可有28=256个不同的二进制组态，输出为256个电压之一，即输出电压不是整个电压范围内任意值，而只能是256个可能值。
图4-83是DAC0832的逻辑框图和引脚排列。
图4-83D0~D7：数字信号输入端。
ILE：输入寄存器允许，高电平有效。
CS：片选信号，低电平有效。
WR1：写信号1，低电平有效。
XFER：传送控制信号，低电平有效。
WR2：写信号2，低电平有效。
IOUT1、IOUT2：DAC电流输出端。
Rfb：是集成在片内的外接运放的反馈电阻。
Vref：基准电压（-10~10V）。
Vcc：是源电压（+5~+15V）。
AGND：模拟地 NGND：数字地，可与AGND接在一起使用。
DAC0832输出的是电流，一般要求输出是电压，所以还必须经过一个外接的运算放大器转换成电压。
实验线路如图4-84所示。
图4-85IN0~IN7：8路模拟信号输入端。
A1、A2、A0 ：地址输入端。
ALE地址锁存允许输入信号，在此脚施加正脉冲，上升沿有效，此时锁存地址码，从而选通相应的模拟信号通道，以便进行A/D转换。
START：启动信号输入端，应在此脚施加正脉冲，当上升沿到达时，内部逐次逼近寄存器复位，在下降沿到达后，开始A/D转换过程。
EOC：转换结束输出信号（转换接受标志），高电平有效。
OE：输入允许信号，高电平有效。
CLOCK(CP)：时钟信号输入端，外接时钟频率一般为640kHz。
Vcc：+5V单电源供电。
常用芯片资料对照表
型号资料名称备注4N35/ 4N36/ 4N37 光电耦合器AD752 0/AD7521/A D7530 /AD75 21 D/A转换器10-Bit,12-Bit,Multiplying D/A ConvertersAD754 1 12位D/A转换器12-Bit,Multiplying D/A ConverterADC0802/AD C0803 /ADC0 804 8位A/D转换器8-Bit,Microprocessor-Compatibie,A/D ConvertersADC08 08/AD C0809 8位A/D转换器8-Bit μP Compatibie A/D Converters with 8-ChannelMultiplexerADC08 31/ADC0832 /ADC0 834/A DC083 8 8位A/D转换器8-Bit Serial I/O A/D Converters with Multiplexer OptionsCA308 0/CA3 080A OTA跨导运算放大器CA314 0/CA3 140A BiMOS运算放大器DAC08 30/DA C0832 8位D/A转换器8-Bit μP Compatibie,Double-Buffered D to A ConvertersICL71 06,IC L7107 3位半A/D转换器ICL7106,ICL7107,ICL7106S,ICL7107S 3位半LCD/LED显示A/D转换器（ICL7106,ICL7107,ICL7106S,ICL7107S,3 1/2Digit,LCD/LED Display,A/D Converters）ICL71 16,IC L7117 3位半A/D转换器ICL7116,ICL7117 3位半LCD/LED显示数据保持A/D转换器（ICL7116,ICL7117 ,3 1/2 Digit,LCD/LED Display,A/DConverter with Display Hold）ICL76 50 载波稳零运算放大器ICL76 60/MA X1044 CMOS电源电压变换器ICL80 38 单片函数发生器ICM72 16 10MHz通用计数器ICM7216A/ICM7216B/ICM7216D 10MHz通用计数器、数字频率计、计数器、周期测量仪等仪器的单片专用电路，只须少量的外围元件就能构成10MHz的数字频率计等数字测量仪表。
adc0808中文资料[整理版]
![adc0808中文资料[整理版]](https://img.taocdn.com/s3/m/02ae1a6e84254b35effd345a.png)
adc0808中文资料[整理版]11.2.4 典型的集成ADC芯片为了满足多种需要，目前国内外各半导体器件生产厂家设计并生产出了多种多样的ADC芯片。
仅美国AD公司的ADC产品就有几十个系列、近百种型号之多。
从性能上讲，它们有的精度高、速度快，有的则价格低廉。
从功能上讲，有的不仅具有A/D转换的基本功能，还包括内部放大器和三态输出锁存器;有的甚至还包括多路开关、采样保持器等，已发展为一个单片的小型数据采集系统。
尽管ADC芯片的品种、型号很多，其内部功能强弱、转换速度快慢、转换精度高低有很大差别，但从用户最关心的外特性看，无论哪种芯片，都必不可少地要包括以下四种基本信号引脚端:模拟信号输入端(单极性或双极性);数字量输出端(并行或串行);转换启动信号输入端;转换结束信号输出端。
除此之外，各种不同型号的芯片可能还会有一些其他各不相同的控制信号端。
选用ADC芯片时，除了必须考虑各种技术要求外，通常还需了解芯片以下两方面的特性。
(1)数字输出的方式是否有可控三态输出。
有可控三态输出的ADC芯片允许输出线与微机系统的数据总线直接相连，并在转换结束RD后利用读数信号选通三态门，将转换结果送上总线。
没有可控三态输出(包括内部根本没有输出三态门和虽有三态门、但外部不可控两种情况)的ADC芯片则不允许数据输出线与系统的数据总线直接相连，而必须通过I/O接口与MPU交换信息。
(2)启动转换的控制方式是脉冲控制式还是电平控制式。
对脉冲启动转换的ADC 芯片，只要在其启动转换引脚上施加一个宽度符合芯片要求的脉冲信号，就能启动转换并自动完成。
一般能和MPU配套使用的芯片，MPU的I/O写脉冲都能满足ADC芯片对启动脉冲的要求。
对电平启动转换的ADC芯片，在转换过程中启动信号必须保持规定的电平不变，否则，如中途撤消规定的电平，就会停止转换而可能得到错误的结果。
为此，必须用D触发器或可编程并行I/O接口芯片的某一位来锁存这个电平，或用单稳等电路来对启动信号进行定时变换。
0808芯片引脚介绍
1. ADC 0808/0809ADC 0808和ADC 0809除精度略有差别外(前者精度为8位、后者精度为7位，其余各方面完全相同。
它们都是CMOS器件，不仅包括一个8位的逐次逼近型的ADC部分，而且还提供一个8通道的模拟多路开关和通道寻址逻辑，因而有理由把它作为简单的“数据采集系统”。
利用它可直接输入8个单端的模拟信号分时进行A/D转换，在多点巡回检测和过程控制、运动控制中应用十分广泛。
1 主要技术指标和特性（1）分辨率： 8位。
（2）总的不可调误差： ADC0808为±LSB,ADC 0809为±1LSB。
（3）转换时间：取决于芯片时钟频率，如CLK=500kHz时，TCONV=128μs。
（4）单一电源： +5V。
（5）模拟输入电压范围：单极性0～5V；双极性±5V,±10V(需外加一定电路。
（6）具有可控三态输出缓存器。
（7）启动转换控制为脉冲式(正脉冲，上升沿使所有内部寄存器清零，下降沿使A/D转换开始。
（8）使用时不需进行零点和满刻度调节。
2 内部结构和外部引脚ADC0808/0809的内部结构和外部引脚分别如图11.19和图11.20所示。
内部各部分的作用和工作原理在内部结构图中已一目了然，在此就不再赘述，下面仅对各引脚定义分述如下：图11.19 ADC0808/0809内部结构框图（1）IN0～IN7——8路模拟输入，通过3根地址译码线ADDA、ADDB、ADDC来选通一路。
（2）D7～D0——A/D转换后的数据输出端，为三态可控输出，故可直接和微处理器数据线连接。
8位排列顺序是D7为最高位，D0为最低位。
（3）ADDA、ADDB、ADDC——模拟通道选择地址信号，ADDA为低位，ADDC为高位。
地址信号与选中通道对应关系如表11.3所示。
（4）VR(+、VR(-——正、负参考电压输入端，用于提供片内DAC 电阻网络的基准电压。
在单极性输入时，VR(+=5V，VR(-=0V；双极性输入时，VR(+、VR(-分别接正、负极性的参考电压。
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VREF/2 = 2.500VDC (No Adjustments)
0 to 70 -40 to 85 -40 to 85
Pinout
ADC0802, ADC0803, ADC0804 (PDIP, CERDIP) TOP VIEW
CS RD WR CLK IN INTR VIN (+) VIN (-) AGND VREF/2 1 2 3 4 5 6 7 8 9 20 V+ OR VREF 19 CLK R
CLK B MSB V+ (VREF) 20 LADDER AND DECODER 9 SUCCESSIVE APPROX. REGISTER AND LATCH D 8-BIT SHIFT REGISTER R RESET DAC VOUT V+ COMP LSB CLK A D DFF2 Q + Q
Operating Conditions
Temperature Range ADC0802/03LD. . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC ADC0802/03/04LCD . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC ADC0802/03/04LCN . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC ADC0803/04LCWM . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CONVERTER SPECIFICATIONS V+ = 5V, TA = 25oC and fCLK = 640kHz, Unless Otherwise Specified Total Unadjusted Error ADC0802 ADC0803 ADC0804 VREF/2 Input Resistance Analog Input Voltage Range DC Common-Mode Rejection Power Supply Sensitivity VREF/2 = 2.500V VREF/2 Adjusted for Correct Full Scale Reading VREF/2 = 2.500V Input Resistance at Pin 9 (Note 2) Over Analog Input Voltage Range V+ = 5V ±10% Over Allowed Input Voltage Range 1.0 GND-0.05 1.3 ±1/16 ±1/16
START CONVERSION
IF RESET = “0”
VREF/2
INTR F/F
AGND
8
VIN (+)
6
∑
+
-
THREE-STATE OUTPUT LATCHES MSB LSB CONV. COMPL. 11 12 13 14 15 16 17 18 8 X 1/f DIGITAL OUTPUTS THREE-STATE CONTROL “1” = OUTPUT ENABLE XFER G2 SET
READ
SET
Q
RESET
CLK R 19 CLK A CLK IN 4 CLK OSC 10 DGND CLK GEN CLKS
INPUT PROTECTION FOR ALL LOGIC INPUTS INPUT G1 TO INTERNAL CIRCUITS RESET BV = 30V START F/F D DFF1 Q CLK
Thermal Information
Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . 125 N/A CERDIP Package . . . . . . . . . . . . . . . . . . 80 20 SOIC Package . . . . . . . . . . . . . . . . . . . . . 120 N/A Maximum Junction Temperature Hermetic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Q
VIN (-)
7
5 INTR
6-6
元器件交易网
ADC0802, ADC0803, ADC0804
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V Voltage at Any Input . . . . . . . . . . . . . . . . . . . . . . -0.3V to (V+ +0.3V)
Typical Application Schematic
1 2 3 5 11 µP BUS ANY µPROCESSOR 12 13 14 15 16 17 18 CS RD WR INTR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VIN (+) VIN (-) 6 7 DIFF INPUTS VREF/2 8-BIT RESOLUTION OVER ANY DESIRED ANALOG INPUT VOLTAGE RANGE V+ 20 CLK R 19 CLK IN 4 +5V 10K 150pF
EXTERNAL CONDITIONS VREF/2 = 2.500VDC (No Adjustments)
TEMP. RANGE (oC) 0 to 70 -40 to 85 -55 to 125
PACKAGE 20 Ld PDIP 20 Ld CERDIP 20 Ld CERDIP 20 Ld PDIP 20 Ld CERDIP 20 Ld SOIC 20 Ld CERDIP 20 Ld PDIP 20 Ld CERDIP 20 Ld SOIC
元器件交易网
ADC0802, ADC0803 ADC0804
August 1997
8-Bit, MicroprocessorCompatible, A/D Converters
Description
The ADC0802 family are CMOS 8-Bit, successive-approximation A/D converters which use a modified potentiometric ladder and are designed to operate with the 8080A control bus via three-state outputs. These converters appear to the processor as memory locations or I/O ports, and hence no interfacing logic is required. The differential analog voltage input has good commonmode-rejection and permits offsetting the analog zero-inputvoltage value. In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution.
18 DB0 (LSB) 17 DB1 16 DB2 15 DB3 14 DB4 13 DB5 12 DB6 11 DB7 (MSB)
AGND 8 VREF/2 9 DGND 10
DGND 10ຫໍສະໝຸດ CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number
3094.1
6-5
元器件交易网
ADC0802, ADC0803, ADC0804 Functional Diagram
2 1 3 “1” = RESET SHIFT REGISTER “0” = BUSY AND RESET STATE
RD CS WR
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.