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MC68341UMAD中文资料

元器件交易网Parts Not Suitable for New DesignsFor Additional InformationEnd-Of-Life Product Change NoticeOrder this document by MC68341UMAD/ADThis document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.ADDENDUM TOMC68341 Integrated Processor User's ManualMC68341Microprocessor and Memory Technologies GroupApril 19, 1995This addendum to the initial release of the MC68341UM/AD User’s Manual provides corrections to the original text, plus additional information not included in the original. This document and other information on this product is maintained on the AESOP BBS, which can be reached at (800)843-3451 (from the US and Canada) or (512)891-3650. Configure modem for up to 14.4Kbaud, 8 bits, 1 stop bit, and no parity. Terminal software should support VT100 emulation. Internet access is provided by telneting to [129.38.233.1] or through the World Wide Web at .1. Signal IndexOn page 2-4, Table 2-4, the QSPI serial clock QSCLK should be listed as an I/O signal. At the bottom of Table 2-5, FC3/DTC is an output-only signal.2. Operand AlignmentOn page 3-9, last paragraph, change the first two lines to: “The CPU32 restricts all operands (both data and instructions) to be word-aligned. That is, word and long-word operands must be located on a word boundary.”Long-word operands do not have to be long-word aligned.3. WE on Fast TerminationOn page 3-17, Figure 3-6, UWE and LWE do not assert for fast termination writes.4. Write Cycle Timing WaveformsOn page 3-25, the M68300 write cycle timing diagram (Figure 3-12) shows incorrect timing for DS, UWE, and LWE. On page 3-28, the M68000 write cycle timing diagram (Figure 3-14) shows incorrect timing for AS68K,CSx, UDS/LDS, and UWE/LWE. Replace these figures with the following corrected figures.5. Additional Note on MBAR DecodeAdd to the CPU Space Cycles description on page 3-31: The CPU space decode logic allocates the 256-byte block from $3FF00-3FFFF to the SIM module. An internal 2-clock termination is provided by this initial decode for any access to this range, but selection of specific registers depends on additional decode.Accesses to the MBAR register at long word $3FF00 are internal only, and are only visible by enabling show cycles. Users should directly access only the MBAR register, and use the LPSTOP instruction to generate the LPSTOP broadcast access to $3FFFE. The remaining address range $3FF04-3FFFD is Motorola reserved and should not be accessed.元器件交易网Figure 3-12. M68300 Write Cycle timingFigure 3-14. M68000 Write Cycle Timing元器件交易网6. Additional Notes on CPU Space Address EncodingOn page 3-31, Figure 3-16, the BKPT field for the Breakpoint Acknowledge address encoding is on bits 4-2, and the T bit is on bit 1. The Interrupt Acknowledge LEVEL field is on bits 3-1.7. BreakpointsOn page 3-31, the last paragraph implies that either a software breakpoint (BKPT instruction) or hardware breakpoint can be used to insert an instruction. As noted in the following paragraphs, only a software breakpoint can be used to insert an instruction on the breakpoint acknowledge cycle.8. Interrupt LatencyAdd to the Interrupt Acknowledge Bus Cycles section on page 3-36: Interrupt latency from IRQx assert to prefetch of the first instruction in the interrupt handler is about 37 clocks + worst case instruction length in clocks (using 2-clock memory and autovector termination). From the instruction timing tables, this gives 37+71 (DIVS.L with worst-case <fea>) = 108 clocks worst case interrupt latency time. For applications requiring shorter interrupt response time the latency can be reduced by using simpler addressing modes and/or avoiding use of longer instructions (specifically DIVS.L, DIVU.L, MUL.L).9. Interrupt Hold Time and Spurious InterruptsAdd to the Interrupt Acknowledge Bus Cycles section on page 3-36: Level sensitive interrupts must remain asserted until the corresponding IACK cycle; otherwise, a spurious interrupt exception may result or the inter-rupt may be ignored entirely. This is also true for level sensitive external interrupts which are autovectored us-ing either the AVEC signal or the AVEC register, since the SIM will not respond to an interrupt arbitration cycle on the IMB if the external interrupt at that level has been removed. External interrupts configured as edge sen-sitive only have to be held a minimum of 1.5 clocks - see section 4.3.5.8 PROGRAMMABLE INTERRUPT REGISTER (PIR).Note that the level 7 interrupt is also level sensitive, and must be held until a level 7 IACK begins. The level 7 interrupt is unique in that it cannot be masked - another level 7 interrupt exception can be created after the IACK cycle by negating IRQ7 and reasserting, even though the interrupt mask level in the SR is now set to level 7.10. Typos in IACK Cycle Timing WaveformsOn page 3-38, Figure 3-21, the text “VECTOR FROM 16-BIT PORT” should be on D7-D0, and “VECTOR FROM 8-BIT PORT” should be on D15-D8. The responding device returns the vector number on the least sig-nificant byte of the data port.11. Additional Note on Internal Autovector OperationAdd to the Autovector Interrupt Acknowledge Cycle section on page 3-38: If an external interrupt level is autovectored either by the AVEC register programming or the external AVEC signal, an external IACK will be started and terminated internally. The interrupting device should not respond to this IACK in any way, or the resulting operation is undefined.12. Additional Notes on Retry TerminationOn page 3-42, Table 3-4: When HALT and BERR are asserted together in case #5 to force a retry of the current bus cycle, relative timing of HALT and BERR must be controlled to avoid inadvertently causing bus error ter-元器件交易网mination case #3. This can be done by asserting HALT and BERR either synchronously to the clock to directly control which edge each is recognized on, or asynchronously with HALT asserted for time [spec 47A+spec 47B] ns before BERR to guarantee recognition on or before the same clock edge as BERR.13. Active Negate on Bus ArbitrationThe 68341 actively pulls up all tri-stateable bus pins other than the data bus before tristating them during bus arbitration. This pullup function is not guaranteed to result in spec VOH levels before tristating, but will help reduce rise time on these signals when using weak external bus pullups.14. Additional Note on Bus Arbitration PriorityFor the bus arbitration description beginning on page 3-49: The arbitration priority between possible bus mas-ters for this device is external request via BR (highest priority), DMA, then CPU (lowest). The priority of DMA channels 1 and 2 relative to each other is selected by their respective MAID levels which must be unique.15. Additional Note on Bus Arbitration and Operand CoherencyFor the bus arbitration description beginning on page 3-49: Each bus master maintains operand coherency when a higher priority request is recognized. For example, a CPU write of a long-word operand to a byte port results in a sequence of four bus cycles to complete the operand transfer - the CPU will not release the bus until the completion of the fourth bus cycle. A single address DMA transfer is handled in a similar manner. Fora dual address DMA transfer, the read and write portions are handled as separate operands, allowing arbitra-tion between the read and write bus cycles. Also, if different port sizes are specified in the DMA configuration for the source and destination, arbitration can occur between each of the multiple operand accesses which must be made to the smaller port for each operand access to the larger port. The RMC read/write sequences for a TAS instruction is also indivisible to guarantee data coherency. Arbitration is allowed between each op-erand transfer of a multi-operand operation such as a MOVEM instruction or exception stacking.16. Additional Notes on RESET Interaction with Current Bus CycleAdd to the Reset Operation description beginning page 3-55:Hardware resets are held off until completion of the current operand transfer in order to maintain operand co-herency. The processor resets at the end of the bus cycle in which the last portion of the operand is transferred, or after the bus monitor has timed out. The bus monitor operates for this specific case whether it is enabled or not, for the period of time that the BMT bits are set to.The following reset sources reset all internal registers to their reset state: external, POR, software watchdog, double bus fault, loss of clock. Execution of a RESET instruction resets the peripheral module registers with the exception of the MCR registers. The MCR register in each module, the SIM41 registers, and the CPU state are not affected by execution of a RESET instruction.17. External ResetOn page 3-56, Figure 3-33, the RESET signal negates for two clocks between internal and external assertions, not one. Note that RESET is not actively negated, and its rise time is dependent on the pullup resistor used.18. Power-On ResetOn page 3-57, Figure 3-34. Power-Up Reset Timing Diagram: CLKOUT is not gated by VCO lock or other in-ternal control signals, and can begin toggling as soon as VCC is high enough for the internal logic to begin operating. For crystal mode and external clock with VCO mode, after the VCO frequency has reached an initial元器件交易网stable value, the 328*TCLKIN delay is counted down, and VCO lock is set after completion of the 328 clock delay. For external clock mode without VCO, the 328*TCLKIN delay starts as soon as EXTAL clock transitions are recognized. See note for page11-3 for more POR information.19. Internal IMB ArbitrationOn page 4-6, first paragraph, change the first sentence to read “There are eight arbitration levels for the various bus masters on the MC68341 to access the inter-module bus (IMB).”20. Additional Note for External Clock Mode with PLLOn page 4-9, Table 4-1, External Clock Mode with PLL: the PLL phase locks the CLKOUT falling edge to the falling edge of the EXTCLK input clock. Maximum skew between falling edges of the EXTCLK and CLKOUT signals is specified in the Section 12 Electrical Characteristics.21. External Clock Mode OperationThe next-to-last paragraph on page 4-11 incorrectly states that the SYNCR V, W, X, Y, and Z bits can all affect the system frequency in external clock mode. In external clock mode only the V bit affects the system frequen-cy, by selecting either EXTCLK or EXTCLK/2 as reference input to the phase comparator. The VCO frequency divided by 2 is used both for CLKOUT as well as the feedback input to the phase comparator. A reset forces V=0, resulting in an initial processor operating frequency of 1/2 the EXTCLK frequency.For applications using external clock mode, the 32KHz crystal connected to EXTAL and XTAL is only required if the realtime clock function is needed - ground EXTAL if the RTC is not used. Also, the clock input on EXT-CLK should be very clean when the 32KHz oscillator is used. Excessive undershoot or overshoot, as well as fast edge rates may result in coupling to the adjacent XTAL input, affecting operation of the 32kHz oscillator.22. Recommended XFC Capacitor ValuesOn page 4-12, third paragraph, and page 11-2, last paragraph: The XFC capacitor recommendation of 0.01µF to 0.1µF applies specifically to crystal mode operation. When using external clock with VCO mode, for phase detector refernce frequencies > 1MHz start with a capacitance value of 10000pf/F_MHz. For example at16.0MHz the recommended XFC capacitance is approximately 10000pf/16.0 = 625pf - choose the next higherstandard value available.23. CLKOUT and VCO Frequency ProgrammingOn pages 4-13 and 4-14, the column for W=1:Z=0:X=1 is incorrect - the correct value for each entry in this column is 2x the frequency in the X=0 column immediately to the left. A corrected table is shown on the follow-ing pages. Note that although a complete table is shown for all W:X:Y:Z combinations, both CLKOUT and VCO frequency limits must be observed when programming the SYNCR. For example, a system operating frequen-cy (CLKOUT) of 25.16MHz can be selected with W:X:Y:Z=1:1:23:1, resulting in a VCO frequency of 50.3MHz.However, programming W:X:Y:Z=1:0:47:1 to achieve the same system frequency would result in a VCO fre-quency of greater than 100MHz, which is outside the spec VCO frequency operating range.24. Additional Note for Global Chip SelectOn page 4-16, section 4.2.4.2: When operating as a global chip select, CS0 does not assert for accesses to either the MBAR or to internal peripheral module registers.元器件交易网Table 4-2. System Frequencies from 32.768-kHz Reference元器件交易网Table 4-2. System Frequencies from 32.768-kHz Reference (Continued)1. Some W/X/Y/Z bit combinations shown may select a CLKOUT or VCO frequency higher than spec. Refer to Sec-tion 11 Electrical Characteristics for CLKOUT and VCO frequency limits.2. Any change to W or Y results in a change in the VCO frequency - the VCO should be allowed to relock if necessary.元器件交易网25. Additional Note on PORTA/B Output TimingAdd to the External Bus Interface Operation description on page 4-17: The Port A and Port B output pins tran-sition after the S4 falling edge for the internal write to the respective data register. This places port pin transi-tions at roughly the same time DS negates for the data register write - note this output delay is not currently specified in the Electrical Specifications.26. RTC Memory MapThe RTC register offsets shown on page 4-21 are incorrect - a corrected memory map is shown below. Ad-dresses within the RTC can be accessed as either bytes or words, with the exception of the reserved byte at offset $0CE. Note that RTC registers marked S/U are read/write in supervisor mode, but can only be read in user mode.ADDR FC15 8ADDR FC7 00C0S RTC INTERRUPT CONTROL (RICR)0C2S/U MINUTES (MIN)0C3S/U SECONDS (SEC)0C4S/U DA TE0C5S/U HOUR0C6S/U MONTH0C7S/U YEAR0C8S RTC CONTROL/ST A TUS (RCR)0C9S/U DAY0CA S/U MINUTES ALARM (MINA)0CB S/U SECONDS ALARM (SECA)0CC S/U DA TE ALARM (DA TEA)0CD S/U HOURS ALARM (HOURA)0CE-RESERVED0CF S RTC CALIBRA TION (RCCR)27. MBAR Register Reset ValuesOn page 4-22, the reset values for MBAR bits 31-12 are undefined.28. MBAR AS7 Bit and IACK CyclesOn page 4-23, the second code sequence initializes the MBAR register with AS7 set. This prevents the ad-dress decode for the internal 4K register block from responding to CPU space accesses. In particular, it pre-vents the register block decode of $FFFFFxxx from interfering with IACK cycles (address $FFFFFFFx), and possibly corrupting the vector number returned. Normal interrupt acknowledge operation for the internal mod-ules is not affected by this change.Early versions of the MC68330 User’s Manual (original release) and MC68340 User’s Manual (original and Rev. 1 releases) did not show AS7 set. Code which was developed based on these manual revisions should be checked for this problem when porting to the MC68341 - this change should also be applied back to the MC68330 and/or MC68340.29. Additional Note on VCO OvershootOn page 4-30 place the following note under the Y-bits description:A VCO overshoot can occur when increasing the operating frequency by changing the Y bits in the SYNCR register. The effects of this overshoot can be controlled by following this procedure:1. Write the X bit to zero. This will reduce the previous frequency by one half.2. Write the Y bits to the desired frequency divided by 2.3. After the VCO lock has occurred, write the X bit to one. This changes theclock frequency to the desired frequency.Steps 1 and 2 may be combined.30. RCCR InitializationAdd to the RCCR description on page 4-41: the RCCR register is unaffected by a processor reset, and contains an arbitrary value on initial powerup of the RTC. Calibration software should clear the RCCR register before beginning the calibration process, since RTC operation with an invalid RCDx value is undefined. RCCR[7] is reserved - on current silicon it always reads 0, and should always be written 0.31. RCCR TyposOn page 4-42, delete the first description for RCD4-RCD0 near the top of the page.32. MONTH Register RangeThe valid range for the MONTH register on page 4-43 is 1-12, with “1” corresponding to January and “12” cor-responding to December.33. SIM41 Example CodeOn page 4-49, about mid-page, change “MOVEQ #8-1,D0” to “MOVEQ #16-1,D0” to initialize all 8 chip se-lects.34. Bus Error Stack FrameOn page 5-61, in the next-to-last paragraph, delete “(the internal transfer count register is located at SP+$10 and the SSW is located at SP+12)”. The stack space allocation is the same for both faults - the location of the internal count register and SSW remains the same. The only difference is that the faulted instruction program counter location SP+10 and SP+12 will contain invalid data. To tell the difference between the two stack frames, look at the first nibble of the faulted exception format vector word located at SP+$E - it will be $0 for the four-word frame, and $2 for the six-word frame.35. DSO TimingOn page 5-71, Figure 5-23, DSO transitions one clock later than shown.36. Typo on BDM RSREG CommandOn page 5-77, Section 5.6.2.8.6, RSREG register bit #8 should be a “1”.37. IPIPE TimingOn page 5-88, Figure 5-29 shows the third IPIPE assertion low lasting for 1.5 CLKs - it actually asserts for an additional 0.5 CLKs. IPIPE transitions occur after the falling edge of CLKOUT.38. Additional Notes on DMA FeaturesIn the feature set listed on page 6-1, bullet six is “Operand Packing and Unpacking for Dual-Address Trans-fers”. This packing is for transfers between different port sizes selected in the DMA channel control register, e.g. Byte <> Word transfers. The DMA controller does not do packing for byte > byte transfers, eliminating the problem of residual bytes left in the controller when a channel is stopped after an odd byte transfer count. 39. Additional Note on Internal Request GenerationAdd to the Internal Request Generation section on page 6-5: For internal request operation, DACKx and DON-Ex are not active as outputs during transfers. DONEx is valid as an input though and will terminate channel operation if asserted - pull up if not used.40. Additional Note on DMA Transfer Latency from DREQAdd to the External Request Generation section beginning 6-5: DREQx assertions require two clocks for input synchronization and IMB bus arbitration activity before the resulting DMA bus cycle can start. A DREQx as-sertion will preempt the next CPU bus cycle if it is recognized two or more clocks before the end of the current bus cycle, unless the current cycle is not the last cycle of an operand transfer, or is the read of an RMC cycle. Operand transfers and RMC read/write sequences are indivisible to guarantee data coherency - the bus can-not be arbitrated from the CPU until the complete operand transfer completes, even if operand and memory sizing results in multiple bus cycles.For a DREQx assertion during an idle bus period, bus state S0 of the DMA bus cycle starts 2.5 clocks after the clock falling edge which DREQx is recognized on. The maximum latency from the clock falling edge that DREQx is recognized on to the falling edge that AS for the DMA cycle asserts from is shown in the following table for various memory speeds.DREQ Latency (Clocks) vs. Bus Width and Access Times41. Additional Note on Burst Transfer DREQx Negation and OverheadOn page 6-5, replace the 2nd paragraph of 6.3.2.1 External Burst Mode with the following: DREQx must be negated one clock before the end of the last DMA bus cycle of a burst to prevent another DMA transfer from being generated. Also, DREQx must be negated two clocks before the end of the last DMA bus cycle to prevent an idle clock between that transfer and the following CPU access.42. Additional Note on Cycle steal DMA arbitration overheadAdd to the External Cycle Steal Mode description on page 6-6: In general, DMA arbitration occurs transpar-ently. However, for some 2-clock accesses using cycle steal an idle clock can follow the DMA transfer due to incomplete overlap of the DMA transfer with internal IMB arbitration. Specifically, an idle clock can follow 1) single address 2-clock transfers and 2) dual address transfers from memory to 2-clock devices. Arbitration is completely overlapped for all other cases.43. Additional Note on Cycle StealFor the external cycle steal mode description on page 6-6, the initial DREQx assertion does not have to be held off until after the channel is started. If DREQx is already asserted when the channel is started by setting the channel start bit, an internal DREQx assertion is generated, providing the edge needed for the DMA cycle to start.44. DREQx Negation on BurstOn page 6-8, Figure 6-5, and on page 6-10, Figure 6-7, DREQx should negate before the falling edge of S2 (one clock earlier than shown) to prevent another DMA transfer from occurring. See the note above for page 6-5 on Burst Transfer DREQx Negation.45. DREQ Assert TimeOn page 6-21, Figure 6-13: The second DREQx assertion should be shown held for an additional clock to guar-antee recognition on 2 consecutive clock falling edges. The figure shows it as just being 1 clock period. Note 1 should be deleted.46. Fast Termination and Burst Request ModeOn the last paragraph of page 6-21, delete the reference to Figure 6-14. Figure 6-14 on page 6-22 is labeled incorrectly - it actually shows operation with fast termination, cycle steal, and dual address transfers. Also, the second DREQx signal should be held for 2 consecutive falling edges - the figure shows it being held for only 1 clock edge. Note 1 of Figure 6-14 should be deleted.47. Typo in DAPIOn page 6-26, for DAPI = 1, the DAR is incremented according to the destination size (not the source size).48. Additional note on DMA limited rate operationOn page 6-27, in the BB-Bus Bandwidth Field: The DMA “active” count increments only when the DMA channel is the bus master (each channel has its own counter). If a higher priority bus master forces the channel to relinquish the bus before completion of the active count, the counter stops until the channel regains the bus. Higher priority requests could come from 1) the other DMA channel (if it has a higher MAID level), 2) the CPU32 core (if either the interrupt mask level in the SR or the interrupt request level is higher than the DMA channel's ISM level), or 3) an external bus request. When the active count is exhausted, the DMA channel releases the bus, and the “idle” count increments regardless of bus activity.49. Configuration ErrorThe Configuration Error description paragraph at the top of page 6-29 should be replaced with “A configuration error results when 1) either the SAR or DAR contains an address that does not match the port size specified in the CCR, or 2) the BTC register does not match the larger port size or is zero.”50. Additional Note on DMA Interrupt PrioritizationAdd to the Interrupt Register description on page 6-31: When both DMA channels are programmed to the same interrupt level, channel 1 is higher priority than channel 2.51. Single Address Enable6-33 SE-Single Address Enable: The note “used for intermodule DMA” should be for the SE=1 case. The 68341 does not support intermodule single address transfers, so the SE bit should always be programmed to “0”.52. Code Examples - Immediate Addressing ModeOn pages 6-40 through 6-44 make the following change as shown for each occurrence of SARADD, DARADD, and NUMBYTE (change to immediate addressing mode for source operand):MOVE.L SARADD,DMASAR1(A0) should be MOVE.L #SARADD,DMASAR1(A0).MOVE.L DARADD,DMADAR1(A0) should be MOVE.L #DARADD,DMADAR1(A0).MOVE.L NUMBYTE,DMABTC1(A0) should be MOVE.L #NUMBYTE,DMABTC1(A0).53. Serial Oscillator Problems with DMA activityAdd to the Crystal Input or External Clock (X1) section on page 7-5: A high DREQ1 request rate (greater than 1MHz) with excessive undershoot on DREQ1 can result in internal signal coupling to the serial module oscil-lator X1 pin, damping out oscillation. Avoid routing DREQ1 near the serial oscillator external components, and use termination techniques such as series termination of the DREQ1 driver (start with 33Ω) to limit edge rate of the signal and accompanying undershoot.54. Additional Note on RTSx operation detailsAdd to the RTSA and RTSB descriptions on page 7-6: The RTSx outputs are active low signals - they drive a logic “0” when set, and a logic “1” when cleared.RTSx can be set (output logic level 0) by any of the following:• Writing a “1” to the corresponding bit in the OPSET register $71E• Issuing an “Assert RTS” command using command register CR• If RxRTS=1, set by receiver FIFO transition from FULL to not-FULLRTSx can be cleared (output logic level 1) by any of the following:• Hardware reset of the serial module• Writing a “1” to the corresponding bit in the OPRESET register $71F• Issuing a “Negate RTS” command using command register CR• If RxRTS=1, cleared by receiver FIFO transition from not-FULL to FULL• If TxRTS=1, cleared by completion of last character, including transmission of stop bits55. Serial Frequency RestrictionOn page 7-8, place the following notes at the end of Section 7.3.1 Baud Rate Generator:The current implementation of the serial module restricts the minimum CLKOUT frequency at which the baud rate generators can be used to approximately 8.3MHz. Operation below this frequency results in a synchro-nized internal clock which is at a lower frequency than the X1 input, which then results in incorrect baud rates. One method to extend the minimum CLKOUT frequency is to reduce the X1 frequency by powers of 2 as shown in the table below. The corresponding baud rates selected by the clock select register programming arescaled by the same factor. This method preserves most of the standard baud rates (19200, 9600, 4800, etc.).CLKOUT min = 2.25*XTAL frequencyAlternatively, the baud rate clock can be supplied directly through the SCLK input. Since there is a single SCLK input, both serial channels must use the same baud rate clock, although one could be clocked in the 1x mode and the other in the 16x mode. When using this method, the X1 input can be tied to ground - no crystal is re-quired.56. 68341 Serial Module RTS Difference from 68681Add to the description for receiver-controlled RTS operation in the next-to-last paragraph on page 7-13: Unlike the 68681, the RTSx signal does not have to be manually asserted the first time in the mode to support control-flow capability on the receiver.57. Additional Note on Serial multidrop operationAdd to the Multidrop Mode section beginning on page 7-15: For multidrop mode, it is not necessary to disable the transmitter to manipulate the A/D bit, as generally implied in the manual, nor is it necessary to wait until the previous character completes transmission (i.e. TxEMP). The serial module logic latches this bit and ap-pends it to the data character when the character is transferred from the transmit buffer to the serial output shift register. Once this transfer occurs (as indicated by the TxRDY assertion), the A/D bit in MR1 can be changed without affecting the character in progress. The proper programming sequence to change the A/D bit for the next character would be:1.)poll TxRDY until asserted (or interrupt on TxRDY)2.) set/clear A/D bit in MR1 for new character3.) write character to transmit buffer (TB)4.) A/D bit can be changed only after TxRDY asserts againNo other bits in MR1 should be modified when changing the A/D bit.58. Typo in CPE DescriptionThe CPE bit header on page 8-20 should be "Counter/Prescaler Enable".59. Typo in Status Register ConfigurationOn page 8-26, Section 8.5.1, the Status Register (SR) description should say: "• Clear the TO, TG, and TC bits to reset the interrupts."60. Typos in Timer Initialization ExamplesOn pages 8-27 and 8-29, the Timer register offsets should be from the timer base address, not from the SIM41 base address. The correct equates for the Timer register offsets are:。

【参考文档】我的世界如何制作简易4格家-word范文 (1页)

【参考文档】我的世界如何制作简易4格家-word范文
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我的世界如何制作简易4格家
导语：相信玩MC的新手玩家都会遇到一个困扰，前期自己不会建家，火柴盒又不喜欢，而且收集材料不容易收集，很多时候撑不过第一个晚上就被怪打死了，下面小编教大家如何用最少的材料，最少的土地，造一个4格小空间，但却全能的小家。

首先找一块空地，标注出4格位置
然后在这4格附近都放上木门
然后在左数第二格，放一个泥土，泥土上面放南瓜灯
打掉下面的泥土，并放上小床。

左数第一格放刚才打掉的泥土，并用锄头耕地种上胡萝卜。

左数第三格向下挖一格并放上工作台
在工作台上按住Shift并倒上水。

在南瓜灯上放木梯。

到此胡萝卜生长的光照跟水源都满足了，胡萝卜茁壮成长。

在南瓜灯上面放熔炉，熔炉左边按住Shift再放一个熔炉，再按住Shift 在熔炉这边放一个石台阶
在石台阶这边放一个活板门，熔炉上面放两块蛋糕。

这样4格简易小家就完成了。

既有工作台可以造东西，又有熔炉可以烧东西。

还有胡萝卜蛋糕可以吃，怪物也不会进来。

我的世界透视BUG寻找地下要塞地牢必备

我的世界-透视BUG 寻找地下要塞地牢必备
我的世界怎么透视?在游戏中有很多透视的B U G，今天⼩编就来为⼤家来介绍⼀个⽐较简单的我的世界透视B U G，⽤来寻找地牢和地下要塞最合适不过。

希望可以帮助到各位玩家朋友。

我的世界矿车树叶透视B U G操作流程：
需要⽤到的⼯具有:矿车*1铁轨*2树叶*1
⾸先在地下挖成如下图所⽰的长2*⾼2*宽1的隧道
然后铺上普通铁轨
在上图位置放上树叶
在设置/视频设置/图像品质中选择流畅。

在图中所⽰位置放上矿车
坐上矿车开进隧道，利⽤树叶来卡视野，奇迹出现了，真的可以透视。

⼩伙伴们学会了吗?
逗游⽹——中国2亿游戏⽤户⼀致选择的”⼀站式“游戏服务平台。

我的世界0 12 1b14启动器下载 0 12 1b14启

我的世界0.12.1b14启动器下载 0.12.1b14启动器下载我的世界手机版0.12.1b14启动器下载，今天搞趣网小编为大家带来的是我的世界手机
版0.12.1b14启动器的资源下载，希望对大家有所帮助。

我的世界手机版0.12.1b14启动器下载：敬请期待
我的世界手机版0.12.1build13安卓版：下载地址
我的世界手机版0.12.1build13ios版：下载地址
我的世界手机版0.12.1build13共存版：下载地址
我的世界0.12.1build13更新：
增加特性：
修复了水靠着墙爬升；
修复了生物的碰撞箱在栅栏里面；
修复了一些声音的响度；
区块加载速度加快，减少未加载区块；
bug修复：
修复了一个当玩家加入封禁的服务器时的崩溃；
修复释放按钮后回不去未按下的状态；
修复了花盆在半砖和台阶上上下颠倒；
修复了创造旧世界时编辑菜单故障；
修复了声音在玩家在雪上跳的时候不播放；
修复了下界门加载不正确；
修复了第三人称时手持物品的错误；
加上了一些失去的声音；（僵尸的脚步声和恶魂死掉的声音）修复了多人联机时不能钓鱼；
修复了浮标在岩浆上不消失。

小编推荐：
下载更多我的世界攻略，敬请关注搞趣网我的世界专区。

我的世界跑酷操作方法

我的世界跑酷操作方法
以下是我的世界跑酷的基本操作方法：
1. 跳跃：按空格键跳跃。

2. 冲刺：按下“前进”键两次进行冲刺。

3. 滑行：按下“下”箭头键，可以在狭窄的通道下滑行。

4. 上升：按下“跳跃”键两次连跳可以在单独的墙壁上上升。

5. 前滚：按下“左/右”箭头键，然后按下“跳跃”键，可以进行前滚。

6. 飞跃：可以使用附魔金靴子进行飞跃。

7. 利用道具：你可以使用眼镜蛇杖来进行魔法传送、药水来提高速度和跳跃等。

除了上述的基本操作方法外，你还需要提高自己的反应速度和运动习惯，才能更好地进行跑酷操作。

MICAPS4帮助文档

MICAPS4.0 用户手册
目录
0 快速入门手册.........................................................................................................................6 0.1 安装.............................................................................................................................. 6 0.2 快速配置......................................................................................................................6 0.2.1 数据源配置.......................................................................................................6 0.2.2 综合图配置.......................................................................................................7 0.2.3 单站雷达默认配置（工具栏）...................................................................... 9 0.2.4 模式剖面默认配置（工具栏）...................................................................... 9 0.2.5 累积降水默认配置（工具栏）.................................................................... 10 0.2.6 表格数据默认配置（工具栏）.....................................................................11 0.2.7 模式探空默认配置.........................................................................................11 0.2.8 基础地图信息配置.........................................................................................12 0.2.9 交互层“另存为”保存................................................................................ 13 0.2.10 系统启动配置与出图配置.......................................................................... 14 0.2.11 传真图配置.................................................................................................15

我的世界：故事模式第三章-绝望之地(4)全剧情流程图文攻略

我的世界：故事模式第三章-绝望之地(4)全剧情流程图文攻略《我的世界故事模式》是风靡世界的沙盘游戏《我的世界》的剧情化版，这回第三章的剧情又会如何发展呢，下面为大家带来我的世界：故事模式第三章-绝望之地(4)全剧情流程图文攻略，一起来看看吧。

第三章-绝望之地(4)Soren与Jesse同时找齐了Tnt与火药，接下来就是需要制造超级tnt。

用火药将tnt 围在中间。

”1.我们来制造超级tnt吧“2.我用它干什么3.这是什么Soren对于制造超级tnt之后要做的事声称已经忘记。

1.我们去阻止Ivor”2.我们去摧毁凋零风暴““Soren”会记住的3.找到Magnus和Ellegaard。

也只有靠Jesse的提醒，才步入正轨。

面对身后逼近的末影人，现在可以坐上矿车速度逃走了。

来到外面，终于看到了Magnus，Ellegaard，”1.谢天谢地你安然无恙。

“2.你们是来加入我们的吗?3.你为什么离开我们对于两人能够安全无恙，Jesse终于放下了心。

Jesse提议该来个恐怖炸弹了。

“1.是时候制造恐怖炸弹了。

”2.这肯定很糟糕3.来吧但在决定谁要拿着恐怖炸弹消灭凋零时，却没有人愿意站出，1.没人自告奋勇吗”2.这是我挺身而出的机会“3.我从来不想当英雄Jesse只能靠自己来完成这个艰巨的任务。

我的世界:故事模式Petra对于没自告奋勇的岩石成员吐槽了句，该感到羞愧。

要确保我们的安全，岩石成员纷纷将自己的盔甲捐献出来。

1.拿走Ellegaard的盔甲2.拿走Magnus的盔甲由于Magnus是爆破专家，Jesse选择了Magnus的盔甲。

我的世界:故事模式在工作台上将超级tnt摆好。

1.拿着，是你的”2.说“啊”“3.吃我一记将超级tnt送入凋零的口中，巨大的破坏威力将凋零炸了粉碎。

1.没有你我肯定不会成功2.谢谢你救了我的命”3.我真的成功了“但失去盔甲的Magnus受了凋零一击，奄奄一息。

”1.千万别走“2.这盔甲属于你3.非常感谢你所做的一切Jesse只在意Magnus的生死，只字未提要拿走盔甲的事。

CH酷凡解说电脑Java 版我的世界下载教程

CH酷凡解说电脑Java 版我的世界下载教
程
《我的世界》是一款沉浸式的沙盒游戏，玩家可以创建自己的世界，并且可以自由探索、建筑、创造等，已经成为无数玩家最喜欢的游戏之
一。

CH酷凡解说电脑Java版我的世界下载是玩家需要完
成下载游戏的第一步。

一、下载CH酷凡解说电脑 Java 版我的世界
1、首先要确保电脑系统支持Java，如果没有安装，可以
从官网下载Java，安装完成后，打开CH酷凡解说电脑官网，
点击下载按钮，选择安装Java版我的世界。

2、下载完成后，在桌面双击打开CH酷凡解说电脑 Java
版我的世界，弹出安装窗口，点击“下一步”，点击“安装”，安
装完成后，点击“完成”，开始启动游戏。

二、安装CH酷凡解说电脑 Java 版我的世界
1、玩家可以选择游戏模式，比如单人模式、多人模式等，也可以选择游戏难度，比如普通、困难等，然后点击“创建游戏”，游戏开始，玩家可以开始探索、建筑和创造。

2、玩家可以把自己想要的事情建立在自己的世界里，比如玩家可以建造房屋，创建自己的小岛，也可以挖掘，收集矿物，制作工具和武器。

NEMA TS2

TS 2-2003 v02.06 Page i
CONTENTS
................................................................................................................................................xv Scope ..........................................................................................................................................................xvi History .........................................................................................................................................................xix TS 2-1998 Update.......................................................................................................................................xxi TS 2-2003 Update........................................................................................................................

我的世界生存全局操作方法

我的世界生存全局操作方法
以下是我的世界生存全局操作方法：
1. 移动：使用WASD键或上下左右键来移动。

2. 安放方块：右键使用方块来安放它。

3. 挖掘方块：使用左键挖掘，用手挖掘速度较慢，需要使用正确的工具来挖掘。

4. 跳跃：使用空格键进行跳跃。

5. 攻击：使用鼠标左键攻击怪物或其他玩家。

6. 制作：打开工作台，使用物品来制作新的物品。

7. 打开物品栏：使用E键打开物品栏，存取物品。

8. 焚烧物品：将物品放入熔炉中来熔炼它们成为其他物品。

9. 攻略世界：探索世界并击败难敌来探索新领域。

10. 保存：将世界保存到本地或网络存储空间中，以备下次启动游戏时继续游戏。

MC80 PDA使用说明书-002

附录 .................................................................................................32
简介
MC80 外观
图 1-1 MC80 正面视图
图 1-2 MC80 背面视图
安装 SD 卡
维护与故障排........................................................29
维护MC80...............................................................................................29 故障排除 ................................................................................................. 30
当电量不足时，MC80 主屏幕显示警告信息，同时电池电量显示为。电量过低时，MC80 将自动关机。 ★ 注意电池充电时间可以超过或少于 3 小时。中断充电不会对电池造成损坏。电池使用时长由 MC80 的不同使用情况决定。例如，使用 MC80 的所选功能、使用模式、数据传输情况等。
图 1-5 安装电池
电池充电
可通过以下两种方式为电池充电：方式一：通过充电器为 MC80 充电。方式二：通过 USB 连接线将 MC80 与个人电脑连接，为 MC80 充电。在充电状态下，LED 指示灯显示红色，当 LED 指示灯显示绿色时，表示电已充满。如果在开机状态下充电，屏幕右上方的电池图标会变换，标识充电开始进行。
管理MC80 ....................................................................................... 27

《我的世界》十大好玩MOD推荐十大RPG地图推荐及详解

《我的世界》十大好玩MOD推荐十大RPG地图推荐及详解《我的世界》盘灵古域地图是世界最大的东方RPG地图，场景版图约二十多个,四十多个精英区王,百多款道具,不知道的小伙伴们跟小编一起来看看《我的世界》十大RPG地图推荐及详解，希望大家玩的开心。

RPG地图-盘灵古域我的世界盘灵古域地图是由台湾的MayorTW和红石口袋耗时数年所制成，是世界最大的东方RPG地图。

它使用了超过20万的命令方块，十万字剧情，700名npc，是一大巨作。

注意事项：1、请以「官方提供的1.8.3伺服器」以及玩家端使用「1.8.3」版本进行游玩(Minecraft 官方下载页面)。

若使用了不正确的版本或是第叁方伺服器，会出现无法游玩或是BUG之情形，请玩家务必要遵守。

2、请将以下伺服器选项调整：allow-nether=falsepvp=truedifficulty=3enable-command-block=truegamemode=23、游玩本地图时，请单独使用盘灵古域专用资源包，不要与其他资源包叠加使用，以免出现问题。

3、若电脑可以负荷，建议游玩时将视野调整为至少4chunk以上，以免电路出现异常。

RPG地图-亡灵战争作者：ZWH007下载地址：MOD下载：点击进入游戏特色环环相扣，跌宕起伏的剧情：整个游戏共使用了1205个命令方块!其中有至少1100个是剧情电路!剧情文字量上万!六大剧情让你玩个够!精挑细选的游戏BGM：游戏内置了21首精选背景音乐，会在各个章节自动播放，让玩家体验剧情的时候更具带入感。

丰富且有挑战性的游戏玩法：不仅仅是打怪!挖掘、破坏、跑酷、搜集、潜入。

让你一玩到底也不厌烦!酣畅淋漓的战斗：前方是海啸般袭来的亡灵，身后，就是人类赖以生存的家园，你，是选择当一个懦弱的逃兵，还是选择和身边同生共死的战友一起，战至最后一滴血流尽!RPG地图-丧魂村请注意必须使用此指定材质包游玩，16X16不需要高清补丁也可以使用)材质包主要取自SMP survival’s texture pack请务必使用1.4以上版本，并且不要使用小地图，请将其关闭来确保游戏品质。

我的世界乐高地狱,安装步骤说明书

我的世界乐高地狱,安装步骤说明书
安装《我的世界乐高地狱》的步骤说明如下：
1. 下载和安装Java：在电脑上打开浏览器，搜索并下载Java
的最新版本。

双击下载的安装程序，按照指示进行安装。

2. 下载适用于我的世界的乐高地狱模组：通过搜索引擎找到可信赖的乐高地狱模组下载链接。

确保下载的模组版本与你的"
我的世界"游戏版本相匹配。

3. 下载和安装Minecraft Forge：通过搜索引擎找到Minecraft Forge的官方网站，并下载与你的"我的世界"游戏版本相匹配
的Forge。

双击下载的安装程序，按照指示进行安装。

4. 打开游戏目录：在电脑上打开文件资源管理器，找到你的"
我的世界"游戏文件目录。

通常可以在游戏启动器中找到"资源
管理器"选项。

5. 安装乐高地狱模组：在文件资源管理器中找到名为"mods"的文件夹。

将之前下载的乐高地狱模组文件拖拽到该文件夹中。

6. 启动游戏：打开"我的世界"游戏启动器，选择安装了乐高地
狱模组的游戏版本，并启动游戏。

7. 验证安装成功：在游戏主界面中，点击"Mod"或"模组"选项，确保乐高地狱模组已成功安装并启用。

现在你已经完成了《我的世界乐高地狱》的安装步骤，可以尽情享受游戏中新增的乐高地狱元素了！。

我的世界1.14更新

墙加入了砖、安山岩、闪长岩、花岗岩、海晶石、石砖、苔石砖、砂岩、红砂岩、下界石砖、红色下界石砖和末地石砖墙。
4.
旗帜图案由纸和其他相关的物品制作而成。例如制作Mojang徽标需要附魔金苹果。
弩由线、铁锭、木棍和绊线钩合成。使用方式和弓类似的武器。拥有更高的伤害，更远的射程，但需要更长的时间拉弦蓄力。按住使用键拉弦蓄力，点按使用键发射。蓄力状态会被储存在物品栏内，留待之后使用。当主手上拿着弩，副手上拿着烟花火箭时，可以发射烟花火箭。可以附上新的附魔：多重射击一次发射三支不同方向的箭，与穿透不兼容。快速装填拉弦蓄力速度加快。有三个等级，每级减少0.25秒蓄力时间。穿透发射的箭会穿透生物。 4个等级，与多重射击不兼容。它的箭能造成6（）至11（ × 5.5）伤害。
）。
被击杀时掉落1根竹子（不受抢夺附魔影响）。
通常是被动的。
生成在竹林（位于丛林）。
会寻找竹子和蛋糕物品并吃掉它们。
拥有不同的性格：
可以是普通、进攻性的、懒惰的、体弱的、担心的和贪玩的（由两个NBT决定：HiddenGene 和MainGene）。
有稀有的白色和棕色变种（棕色熊猫的main和hidden gene都是棕色）。
营火在针叶林村庄生成。作为不会燃烧方块的火源。不会燃烧物品。可使用三根木棍、1个木炭或煤炭、任意2个木头、原木、或去皮木头合成。煮熟4个食物物品，但是比熔炉烧炼要慢（30秒）。按使用键将食物放到营火上。烧好的食物会掉落发出一种新的颗粒；从营火发出的烟雾颗粒可在更远的距离看见这个颗粒可穿透1-2个方块在营火下方放置干草块可以使烟雾颗粒飘得更高、不消散时间更长。一种光源，发出15级的光亮,而火把为14级。火焰不会蔓延，可用水桶或水瓶扑灭，并可以再次用火矢、打火石或火焰弹点燃。站在上面会持续受到1（Half Heart.svg）火焰伤害，但离开营火后不会受到后续的持续火焰伤害。

我的世界做生化地图的指令代码

我的世界做生化地图的指令代码我的世界指令代码大全•/seen name -查看某人最后退出的时间•/tp name1 name2 -将人物1传送至人物2身旁•/tp name -将自己传送至某人身旁•/tphere name -将某人传送至自己身旁•/tpall -将服务器内的所有人传送至自己身旁(大传送阵)•/unlimited id -给予自己无限的某物品•/weather storm/sun time -改变天气，雷雨或晴天•【箭术】 - Archery•【斧头技能】 - Axes•【采矿】- mining•【修理】 - Repair•/forestgen -在自己身旁形成森林•/pumpkins -在自己身旁形成南瓜林(带叶子的南瓜林)•/snow -在自己的身旁成为雪后的样子•/thaw -融雪(和冰)•/butcher -杀死附近的怪物•/tree 树形 -生成一棵树(树形不填也可以)•树形：•big - 大树•ewquoia - 红木•Tall sequoia - 高大的红木•Birch - 衫树•Random - 随机•/up 高度 - 将自己提升到某高度，脚下用一块可能悬空的玻璃支撑•ascend - 把自己提升到上一个平台•bind <命令> {命令关键字} - 设置一键命令•clear - 清空控制台•damage - 关闭或者开启伤害即无敌•descend - 把自己移动到下面一个的平台•destroy [all] - 破坏当前的东西(背包)•defuse [all] - 拆弹(拆除已经点燃了的TNT炸药)•diff - X•difficulty - 设置游戏难度•dropstore - 在身边创建一个储物柜•*drops - 开关物品掉落，关闭的话采矿打怪不掉东西。

•dupe [all] - 复制东西•duplicate [all] - 复制手上的东西并丢出来•explode [范围] - 设置一个地方爆炸(在自家慎用)•extinguish [all] - 熄灭周围所有的火•ext [all] - 一样是熄灭火•falldamage - 开关高空落下伤害•firedamage - 开关火的伤害•fly - 飞行模式•*freeze - 冻结怪物•give <物品> [数量] - 给一样物品•goto <名字> - 去一个地方•grow [all] - 让立即小麦成长•h [COMMAND] - 命令列表/帮助•heal - 补指定的血•health - 设置生命值•help [COMMAND] - 命令列表/帮助•home 回到出生点•i <物品代码> [数量] - 刷东西•instantmine - 开关即时采矿(采矿无延迟)•item <物品代码|物品名称> [数量] [费用] 给玩家物品, 如果不指定则是最大的数量•itemname - 显示当前手上的物品名称•itemstack <物品代码> [数量] - 给玩家指定数量的物品•kill 自杀不解释•jump - 瞬移到鼠标所指的地方•killnpc [all] - 杀死周围全部NPC 或者叫杀了附近所有除自己外的活体生物•l - X•*light - 把光永久性关闭•listwaypoints - 列出所有路径点•macro <文件名> {参数} - 允许运行宏•maxstack [物品ID|物品名称|全部] [数量] - 最大的把某物品堆起来•*mobdamage - 怪物不会给你伤害•msg <消息> - 添加一个消息到控制台•music [音量] - 播放音乐•noclip - 穿墙•p - 显示当前坐标•pos 现在玩家的坐标•reach - 玩家到指定地方•return - 传送到之前传送的地方•rem - 删除指定路点•removedrops [all] - 删掉地上物品•*rename - 修改命令名称•replenish [all] - X•repair [all] - 修复当前物品耐久•reset - 恢复默认设置•s <名字> - Same as /set•search <关键词> - 搜索物品名称•set <名字> - 在这世界标记一个路径点•setjump [JUMP|reset] - 设置跳跃的高度落地伤害和移动 1:1•setspawn [ ] 设置当前位置 X轴 Y轴 Z轴•setspeed [速度|重置] - 设置移动速度•setspeed [速度|重置] - 设置移动速度•spawn [QTY] - 产生一个生物•spawnstack {NAME|ID|random} - 产生一个合体的怪物NPC•tele - 传送到此坐标•time [set|get|day|night [minute|hour|day [TIME]]] - 设置指定时间得到物品•timeschedule > - 设定一段时间段，让世界永远保持在这段时间之间•unbind - 解除一个命令•useportal - 传送到地狱•waterdamage - 开关潜水伤害•world - 世界情报•world load - 加载指定的文件•world save - 保存退出游戏•world seed [SEED] - 给你看看你世界里有多少个方块•world new [] [SEED] - 在指定位置创建新地图•world exit - 不保存退出游戏•world list - 列出所有存档你可以去这看".minecraft/saves"。

我的世界映射下载方法ios

我的世界映射下载方法ios
如果您想下载您的iOS设备上的Minecraft世界地图，您需要先确保您有一个支持地图下载的Minecraft版本。

然后，您可以按照以下步骤下载地图：
1. 打开Minecraft游戏并登录您的帐户。

2. 在游戏主界面上，单击“游戏”按钮。

3. 在游戏列表中，找到您想要下载的地图，并单击其名称。

4. 单击“下载”按钮，然后等待地图下载完成。

5. 下载完成后，单击“播放”按钮，进入世界地图。

请注意，某些地图可能需要您先安装其他软件或使用第三方应用程序才能下载和使用。

为了确保您的设备的安全性，我们建议您只从官方渠道下载软件和地图，并且避免下载来自未知来源的地图或软件。

乐高我的世界梦幻空系列史蒂夫人仔的木房子说明书

乐高我的世界梦幻空系列史蒂夫人仔的木房子说明书尊敬的用户：欢迎您选择乐高我的世界梦幻空系列史蒂夫人仔的木房子。

这款乐高套装是专为我的世界游戏爱好者设计的，有着精致的细节和可玩性，可以让玩家在游戏中建造自己的梦幻世界。

在这份说明书中，我们将为您详细介绍如何组装和使用这个乐高套装。

组装说明：1.打开包装，取出所有乐高积木和说明书。

请仔细检查是否有缺失或损坏的部件。

2.根据说明书上的示意图开始组装，逐步将积木连接起来。

请确保每个积木连接稳固，以确保模型的稳定性。

3.按照步骤，依次连接每一部分。

在连接零件时，您可能需要施加一些力量，但请确保不要过度施力，以防零件损坏。

4.当您完成全部组装步骤后，请仔细检查是否有未连接好的零件或松动的部件。

如果有任何问题，请重新组装或调整零件位置。

5.当所有部件都被正确组装后，您可以根据个人喜好来增添一些额外的装饰，例如小花园、小树木等。

使用说明：1.完成组装的乐高我的世界梦幻空系列史蒂夫人仔的木房子可以作为展示模型，也可以作为玩具进行游戏。

2.您可以配备乐高我的世界梦幻空系列史蒂夫人仔和其他角色来进行角色扮演或想象游戏。

通过搭建模型、探索和冒险，您可以创造属于自己的独特故事。

3.史蒂夫人仔的木房子有着宽敞的内部空间，您可以使用积木搭建家具、工作台和其它设施。

同时，在模型顶部的花园区域也可以种植一些小型植物。

4.您可以将其与其他乐高我的世界系列套装进行组合，打造一个庞大而绚丽的游戏场景。

多个场景可以互相连接，形成一个更加复杂和多样化的世界。

维护与储存：1.当您玩完之后，请注意将积木进行分类和归置，以免零件丢失。

2.尽量将乐高套装保存在整洁、干燥的地方，远离阳光直射和潮湿环境，以保证其色彩和质量长久不变。

总结：。

《我的世界史蒂夫和爱丽克丝大冒险 9逃亡之旅》读书笔记思维导图

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