RDS82580XXOO中文资料
RDA5807FP datasheet_v1.2
RDA5807FP S INGLE-C HIP B ROADCAST FM R ADIO T UNER Rev.1.2–April.2012 1The RDA5807FPThe RDA5807FP1.1 Features●●●50 -108 MHz●Support flexible channel spacing mode100KHz, 200KHz, 50KHz and 25KHz ●Support RDS/RBDS●Digital low-IF tunerImage-reject down-converterHigh performance A/D converterIF selectivity performed internally●Fully integrated digital frequency synthesizerFully integrated on-chip RF and IF VCOFully integrated on-chip loop filter●Autonomous search tuning●Support 32.768KHz crystal oscillator●Digital auto gain control (AGC) ●Bass boost●Volume control and mute●I2●Line-level analog output voltageS digital output interface●32.768 KHz 12M,24M,13M,26M,19.2M,38.4MHzReference clock●Only support 2-wire bus interface●Directly support 32Ω resistance loading●Integrated LDO regulator2.7 to3.3 V operation voltage●SOP16 package.1.2 Applications●Cellular handsets ●MP3, MP4 players ●Portable radios●PDAs, Notebook2 Table of Contents1General Description (1)1.1 Features (1)1.2Applications (2)2Table of Contents (3)3Functional Description (4)3.1 FM Receiver (4)3.2 Synthesizer (4)3.3 Power Supply (4)3.4 RESET and Control Interface select (4)3.5 Control Interface (5)3.6 I2S Audio Data Interface (5)3.7 GPIO Outputs (5)4Electrical Characteristics (6)5Receiver Characteristics (7)6Serial Interface (8)6.1 I2C Interface Timing (8)7Register Definition (9)8Pins Description (15)9Application Diagram (17)9.1 RDA5807FP Common Application : (17)9.1.1 Bill of Materials: (17)10Physical Dimension (18)11PCB Land Pattern： (19)12Change List (22)Contact Information (23)3 Functional Description3.1Thestrong adjacent channels.The multi-phase mixer array down converts theLNA output differential RF signal to low-IF, it also has image-reject function and harmonic tones rejection.The PGA amplifies the mixer output IF signal and then digitized with ADCs.The DSP core finishes the channel selection, FM demodulation, stereo MPX decoder and output audio signal. The MPX decoder can autonomous switch from stereo to mono to limit the output noise.The DACs convert digital audio signal to analog and change the volume at same time. The DACs has low-pass feature and -3dB frequency is about 3.3 Power SupplyThe RDA5807FP integrated one LDO which supplies power to the chip. The external supply voltage range is 2.7-3.3 V.3.4 RESET and Control Interface selectThe RDA5807FP is RESET itself When VDD is Power up. And also support soft reset by trigger 02H BIT1 from 0 to 1. T h e RDA5807FP only support I2C control interface bus mode.3.5 Control InterfaceThe RDA5807FP only supports I 2The I C control interface.2C interface is compliant to I 2C Bus Specification 2.1. It includes two pins: SCLK andSDIO. A I 2C interface transfer begins with START condition, a command byte and data bytes, each byte has a followed ACK (or NACK) bit, and ends with STOP condition. The command byte includes a 7-bit chip address (0010000b) and a R/W bit. The ACK (or NACK) is always sent out by receiver. When in write transfer, data bytes is written out from MCU, and when in read transfer, data bytes3.6 I out NACK for last data byte, and then RDA5807FP will return the bus to MCU, and MCU will give out STOP condition. 2The RDA5807FP supports I S Audio Data Interface2S (Inter_IC Sound Bus) audio interface. The interface is fullycompliant with I 2S bus specification. When setting I2SEN bit high, RDA5807FP will output SCK, WS,SD signals from GPIO3, GPIO1, GPIO2 as I 2S master and transmitter, the sample rate is 48Kbps ，44.1kbps,32kbps….. RDA5807FP alsosupport as I 2S slaver mode and transmitter, the sample rate is less than 100kbps. SCKWS4 Electrical CharacteristicsTable 4-1 DC Electrical Specification (Recommended Operation Conditions):5 Receiver CharacteristicsTable 5-1Receiver Characteristics(VDD = 3 V, T A = 25 °C, unless otherwise specified)Notes:1. F in =65 to 115MHz; F mod 2. ∆f=22.5KHz; 3. B =1KHz; de-emphasis=75µs; MONO=1; L=R unless noted otherwise;AF = 300Hz to 15KHz, RBW <=10Hz; 4. |f 2-f 1|>1MHz, f 0=2xf 1-f 2, AGC disable, F in 5. P =76 to 108MHz; RF =60dB U V; 6. ∆f=75KHz,fpilot=10% 7. Measured at V EMF = 1 m V, f RF 8. At LOUT and ROUT pins 9. Adjustable = 65 to 108MHz6 Serial Interface6.1 I 2Table 6-1I C Interface Timing2(VDD = 3.0 V, T C Interface Timing CharacteristicsA = 25°C, unless otherwise specified)Figure 6-1. I 2C Interface Write Timing DiagramSCLKSDIOSTARTACKdata high byte ACKr/waddressdata low byteNACKSTOP STARTtFigure 6-2. I 2C Interface Read Timing Diagram7 Register Definition1If 0x07h_bit<9> ( band )=1, 65-76MHz; =0, 50-76MHz2This value is SNR threshold for seeking, and the default value 1000 is about 32dB SNR.3 This function is open when I2S_Enabled=1.40x20H_bit<14:12>, Seek_Mode register. Default value is 000; When = 001, will add the 5807SP seek mode.The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in8 Pins Description12345678161514131211109Table 8-2 Internal Pin Configuration9 Application Diagram9.1 RDA5807FP Common Application :10 Physical DimensionFigure 10-1illustrates the package details for the RDA5807FP. The package is lead-free and RoHS-compliant.Figure 10-1. 16 PIN SOP PCB Land Pattern 11 PCB Land Pattern：Table-I Classification Reflow ProfilesTable – II SnPb Eutectic Process – Package Peak Reflow TemperaturesNote 3:Package volume excludes external terminals(balls, bumps, lands, leads) and/or non integral heat sinks.Note 4: The maximum component temperature reached during reflow depends on package the thickness and volume. The use of convection reflow processes reduces the thermal gradients between packages. However, thermal gradients due to differences in thermal mass of SMD package may sill exist.Note 5: Components intended for use in a “lead-free” assembly process shall be evaluated using the “lead free” classification temperatures and profiles defined in Table-I II III whether or not lead free.RoHS CompliantThe product does not contain lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyls (PBB) or polybrominated diphenyl ethers (PBDE), and are therefore considered RoHS compliant.ESD SensitivityIntegrated circuits are ESD sensitive and can be damaged by static electricity. Proper ESD techniques should be used when handling these devices.12 Change ListContact InformationRDA Microelectronics (Shanghai), Inc.Suite 1108 Block A, e-Wing Center, 113 Zhichun Road Haidian District, Beijing Tel: 86-10-62635360Fax: 86-10-82612663Postal Code: 100086Suite 302 Building 2, 690 Bibo Road Pudong District, ShanghaiTel: 86-21-50271108Fax: 86-21-50271099Postal Code: 201203Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.。
LDEExxxx中文资料
Series Rated voltage (C = 50Vdc) Size code (D = 22.20) Capacitance = 0.47μF Tolerance (J = 5%) Dielectric (A = PEN) Version (5 = standard) Packing (N= Tape) Internal use
28.24
7.1
6.1
1000
40.30
10.2
7.6
1000
50.40
12.7
10.2
500
60.54
15.2
13.7
500
All dimensions are in mm. In accordance with IEC 60286-3. Material used: - Carrier tape: antistatic material - Cover tape: polyester + PE - Reel: recyclable polystyrene All parts in bulk or on reel are packed in hermetically sealed moisture barrier bag (MBB).
L
3.2 3.2 4.5 5.7
W
(mm) 1.6 2.5 3.2 5.1
H max
(mm) 1.1 1.5--2.0 1.7 2.3--2.6 2.3--2.7 3.3 4.2--4.4 3.5 4.5 5.4 3.6 4.5 5.4--5.6 3.6 4--4.5 5.5--5.7 3.6 4.5--4.9 5.5--5.7
25AA1024中文资料
7
pF TA = 25°C, CLK = 1.0 MHz,
VCC = 5.0V (Note)
10
mA VCC = 5.5V; FCLK = 20.0 MHz;
SO = Open
5
mA VCC = 2.5V; FCLK = 10.0 MHz;
SO = Open
7
mA VCC = 5.5V
5
mA VCC = 2.5V
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability.
25AA256_07中文资料
• Block Write Protection:
- Protect none, 1/4, 1/2 or all of array
• Built-In Write Protection:
- Power-on/off data protection circuitry
- Write enable latch
-0.3
— 0.3 VCC V
-0.3
— 0.2 VCC V
D004 VOL D005 VOL
Low-level output voltage
—
—
0.4
V
—
—
0.2
V
D006 VOH
High-level output
VCC -0.5 —
—
V
voltage
D007 ILI
Input leakage current —
VCC = 5.5V; FCLK = 10.0 MHz; SO = Open VCC = 2.5V; FCLK = 5.0 MHz; SO = Open VCC = 5.5V VCC = 2.5V CS = VCC = 5.5V, Inputs tied to VCC or VSS, 125°C CS = VCC = 5.5V, Inputs tied to VCC or VSS, 85°C
DS21822F-page 2
© 2007 Microchip Technology Inc.
元器件交易网
25AA256/25LC256
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I): TA = -40°C to +85°C Automotive (E): TA = -40°C to +125°C
K4T1G164QQ资料
1Gb Q-die DDR2 SDRAM Specification60FBGA & 84FBGA with Pb-Free & Halogen-Free(RoHS compliant)INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDEDON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.1. For updates or additional information about Samsung products, contact your nearest Samsung office.2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.* Samsung Electronics reserves the right to change products or specification without notice.Table of Contents1.0 Ordering Information (4)2.0 Key Features (4)3.0 Package Pinout/Mechanical Dimension & Addressing (5)3.1 x4/x8 package pinout (Top View) : 60ball FBGA Package (5)3.2 x16 package pinout (Top View) : 84ball FBGA Package (6)3.3 FBGA Package Dimension (x4/x8) (7)3.4 FBGA Package Dimension (x16) (8)4.0 Input/Output Functional Description (9)5.0 DDR2 SDRAM Addressing (10)6.0 Absolute Maximum DC Ratings (11)7.0 AC & DC Operating Conditions (11)7.1 Recommended DC Operating Conditions (SSTL - 1.8) (11)7.2 Operating Temperature Condition (12)7.3 Input DC Logic Level (12)7.4 Input AC Logic Level (12)7.5 AC Input Test Conditions (12)7.6 Differential input AC logic Level (13)7.7 Differential AC output parameters (13)8.0 ODT DC electrical characteristics (13)9.0 OCD default characteristics (14)10.0 IDD Specification Parameters and Test Conditions (15)11.0 DDR2 SDRAM IDD Spec Table (17)12.0 Input/Output capacitance (18)13.0 Electrical Characteristics & AC Timing for DDR2-800/667 (18)13.1 Refresh Parameters by Device Density (18)13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin (18)13.3 Timing Parameters by Speed Grade (19)14.0 General notes, which may apply for all AC parameters (21)15.0 Specific Notes for dedicated AC parameters (23)Revision HistoryRevision Month Year History1.0September2007 - Initial Release1.01November2007 - Typo CorrectionSpeed DDR2-800 5-5-5DDR2-800 6-6-6DDR2-667 5-5-5Units CAS Latency 565tCK tRCD(min)12.51515ns tRP(min)12.51515ns tRC(min)57.56060nsNote :1. Speed bin is in order of CL-tRCD-tRP.2. RoHS Compliant.3. “H” of Part number(12th digit) stand for RoHS compliant and Halogen-free products.Org.DDR2-800 5-5-5DDR2-800 6-6-6DDR2-667 5-5-5Package 256Mx4K4T1G044QQ-HC(L)E7K4T1G044QQ-HC(L)F7K4T1G044QQ-HC(L)E660 FBGA 128Mx8K4T1G084QQ-HC(L)E7K4T1G084QQ-HC(L)F7K4T1G084QQ-HC(L)E660 FBGA 64Mx16K4T1G164QQ-HC(L)E7K4T1G164QQ-HC(L)F7K4T1G164QQ-HC(L)E684 FBGA•JEDEC standard 1.8V ± 0.1V Power Supply •VDDQ = 1.8V ± 0.1V•333MHz f CK for 667Mb/sec/pin, 400MHz f CK for 800Mb/sec/pin •8 Banks •Posted CAS•Programmable CAS Latency: 3, 4, 5, 6•Programmable Additive Latency: 0, 1, 2, 3, 4, 5•Write Latency(WL) = Read Latency(RL) -1•Burst Length: 4 , 8(Interleave/nibble sequential)•Programmable Sequential / Interleave Burst Mode •Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)•Off-Chip Driver(OCD) Impedance Adjustment •On Die Termination•Special Function Support- PASR(Partial Array Self Refresh)- 50ohm ODT- High Temperature Self-Refresh rate enable •Average Refresh Period 7.8us at lower than T CASE 85°C, 3.9us at 85°C < T CASE < 95 °C •All of Lead-free products are compliant for RoHSThe 1Gb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x 8banks, 16Mbit x 8 I/Os x 8banks or 8Mbit x 16 I/Os x 8 banks device. This synchronous device achieves high speed double-data-rate transfer rates of up to 800Mb/sec/pin (DDR2-800) for general applications.The chip is designed to comply with the following key DDR2SDRAM features such as posted CAS with additive latency, write latency = read latency - 1, Off-Chip Driver(OCD) impedance adjustment and On Die Termination.All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. For example, 1Gb(x8) device receive 14/10/3 addressing.The 1Gb DDR2 device operates with a single 1.8V ±0.1V power supply and 1.8V ±0.1V VDDQ.The 1Gb DDR2 device is available in 60ball FBGAs(x4/x8) and in 84ball FBGAs(x16).Note : The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “DDR2 SDRAM Device Operation & Timing Diagram”.1.0 Ordering Information2.0 Key FeaturesNote:1. Pins B3 and A2 have identical capacitance as pins B7 and A8.2. For a read, when enabled, strobe pair RDQS & RDQS are identical in function and timing to strobe pair DQS & DQS and input masking function is disabled.3. The function of DM or RDQS/RDQS are enabled by EMRS command.4. VDDL and VSSDL are power and ground for the DLL.A B C D E F G H J K LVDD NU/VSSDQ6VSSQ VDDQ VDDQ VDDQ VSSQ VSSQ DQS DQS DQ7DQ0VDDQ DQ2VSSQ DQ5VSSDL VDD CK RAS CK CAS CS A2A6A4A11A8NCA13NCA12A9A7A5A0VDD A10/APVSSVDDQ VSSQ DQ1DQ3DQ4VDDLA1A3BA1VREF VSS CKEWE BA01 2 3 7 8 9VDDVSS ODTBA2Ball Locations (x4/x8): Populated Ball +: Depopulated BallTop View (See the balls through the Package)++++++++++++++++++++++++++++++123456789A B C D E F G H J K L++++++++DM /RDQSRDQS+3.1 x4/x8 package pinout (Top View) : 60ball FBGA Package3.0 Package Pinout/Mechanical Dimension & AddressingNote :1. VDDL and VSSDL are power and ground for the DLL.2. In case of only 8 DQs out of 16 DQs are used, LDQS, LDQSB and DQ0~7 must be used.A B C D E F G H J K L VDD NC VSS DQ14VSSQ UDM VDDQ VDDQ VDDQ VSSQ VSSQ UDQS UDQS DQ15DQ8VDDQ DQ10VSSQ DQ13VSSQ VDDQ RAS CK CAS CS A2A6A4A11A8NCNCNCA12A9A7A5A0VDDA10/APVSSVDDQ VSSQ DQ9DQ11DQ12VDD A1A3BA1NC VSS CKEWE BA0 1 2 3 7 8 9VDDVSSODTBA2Ball Locations (x16): Populated Ball +: Depopulated BallTop View (See the balls through the Package)M N P RDQ6VSSQ LDM VDDQ VDDQ VSSQ LDQS DQ7DQ0VDDQ DQ2VSSQ DQ5VSSDL VDD CK VDDQ VSSQ DQ1DQ3DQ4VDDLVREF VSS LDQS 123456789++++++++++++++++++++++++++++++++++++++++++++++++++A B C D E F G H J K L M N P R+3.2 x16 package pinout (Top View) : 84ball FBGA Package3.3 FBGA Package Dimension (x4/x8)A B CD E F H J K LG3.4 FBGA Package Dimension (x16)A B C D E FH J K L M N P RGSymbol Type FunctionCK, CK Input Clock:CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing).CKE Input Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and out-put drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. After V REF has become stable during the power on and initialization swquence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, V REF must be maintained to this input. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self refresh.CS Input Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on sys-tems with multiple Ranks. CS is considered part of the command code.ODT Input On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS, RDQS, RDQS, and DM signal for x4/x8 configurations. For x16 configuration ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal. The ODT pin will be ignored if the Extended Mode Register (EMRS(1)) is programmed to disable ODT.RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.DM Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coinci-dent with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For x8 device, the function of DM or RDQS/RDQS is enabled by EMRS command.BA0 - BA2Input Bank Address Inputs: BA0, BA1 and BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle.A0 - A13Input Address Inputs: Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code dur-ing Mode Register Set commands.DQ Input/Out-putData Input/ Output: Bi-directional data bus.DQS, (DQS)(LDQS), (LDQS) (UDQS), (UDQS) (RDQS), (RDQS)Input/Out-putData Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15. For the x8, an RDQS option using DM pin can be enabled via the EMRS(1) to simplify read timing. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single ended mode or paired with optional complementary signals DQS, LDQS, UDQS, and RDQS to provide differential pair signaling to the system during both reads and writes. An EMRS(1) control bit enables or disables all complementary data strobe signals.In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMRS(1)x4 DQS/DQSx8 DQS/DQS if EMRS(1)[A11] = 0x8 DQS/DQS, RDQS/RDQS, if EMRS(1)[A11] = 1x16 LDQS/LDQS and UDQS/UDQS"single-ended DQS signals" refers to any of the following with A10 = 1 of EMRS(1)x4 DQSx8 DQS if EMRS(1)[A11] = 0x8 DQS, RDQS, if EMRS(1)[A11] = 1x16 LDQS and UDQSNC No Connect: No internal electrical connection is present.V DD/V DDQ Supply Power Supply: 1.8V +/- 0.1V, DQ Power Supply: 1.8V +/- 0.1V V SS/V SSQ Supply Ground, DQ GroundV DDL Supply DLL Power Supply: 1.8V +/- 0.1VV SSDL Supply DLL GroundV REF Supply Reference voltage4.0 Input/Output Functional Description5.0 DDR2 SDRAM Addressing1Gb AddressingConfiguration256Mb x4128Mb x 864Mb x16 # of Bank888Bank Address BA0 ~ BA2BA0 ~ BA2BA0 ~ BA2Auto precharge A10/AP A10/AP A10/APRow Address A0 ~ A13A0 ~ A13A0 ~ A12Column Address A0 ~ A9,A11A0 ~ A9A0 ~ A9 * Reference information: The following tables are address mapping information for other densities.256MbConfiguration64Mb x432Mb x 816Mb x16 # of Bank444Bank Address BA0,BA1BA0,BA1BA0,BA1Auto precharge A10/AP A10/AP A10/APRow Address A0 ~ A12A0 ~ A12A0 ~ A12Column Address A0 ~ A9,A11A0 ~ A9A0 ~ A8512MbConfiguration128Mb x464Mb x 832Mb x16 # of Bank444Bank Address BA0,BA1BA0,BA1BA0,BA1Auto precharge A10/AP A10/AP A10/APRow Address A0 ~ A13A0 ~ A13A0 ~ A12Column Address A0 ~ A9,A11A0 ~ A9A0 ~ A92GbConfiguration512Mb x4256Mb x 8128Mb x16 # of Bank888Bank Address BA0 ~ BA2BA0 ~ BA2BA0 ~ BA2Auto precharge A10/AP A10/AP A10/APRow Address A0 ~ A14A0 ~ A14A0 ~ A13Column Address A0 ~ A9,A11A0 ~ A9A0 ~ A9 4GbConfiguration 1 Gb x4512Mb x 8256Mb x16 # of Bank888Bank Address BA0 ~ BA2BA0 ~ BA2BA0 ~ BA2Auto precharge A10/AP A10/AP A10/APRow Address A0 - A15A0 - A15A0 - A14 Column Address/page size A0 - A9,A11 A0 - A9 A0 - A9Note :1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.2. Storage Temperature is the case surface temperature on the center/top side of the DRAM.Symbol ParameterRating Units Notes V DD Voltage on V DD pin relative to V SS - 1.0 V ~ 2.3 V V 1V DDQ Voltage on V DDQ pin relative to V SS - 0.5 V ~ 2.3 V V 1V DDL Voltage on V DDL pin relative to V SS - 0.5 V ~ 2.3 V V 1V IN, V OUT Voltage on any pin relative to V SS - 0.5 V ~ 2.3 V V1T STGStorage Temperature-55 to +100°C 1, 2Note : There is no specific device V DD supply voltage requirement for SSTL-1.8 compliance. However under all conditions V DDQ must be less than or equalto V DD .1. The value of V REF may be selected by the user to provide optimum noise margin in the system. Typically the value of V REF is expected to be about 0.5 x V DDQ of the transmitting device and V REF is expected to track variations in V DDQ .2. Peak to peak AC noise on V REF may not exceed +/-2% V REF (DC).3. V TT of transmitting device must track V REF of receiving device.4. AC parameters are measured with V DD , V DDQ and V DDL tied together.Symbol ParameterRatingUnits NotesMin.Typ. Max.V DD Supply Voltage 1.7 1.8 1.9V V DDL Supply Voltage for DLL 1.7 1.8 1.9V 4V DDQ Supply Voltage for Output 1.7 1.8 1.9V 4V REF Input Reference Voltage 0.49*V DDQ 0.50*V DDQ0.51*V DDQ mV 1,2V TTTermination VoltageV REF -0.04V REFV REF +0.04V37.0 AC & DC Operating Conditions6.0 Absolute Maximum DC Ratings7.1 Recommended DC Operating Conditions (SSTL - 1.8)7.2 Operating Temperature Condition1.Operating Temperature is the case surface temperature on the center/top side of the DRAM.2.At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.7.3 Input DC Logic Level7.4 Input AC Logic Level7.5 AC Input Test ConditionsNote :1. Input waveform timing is referenced to the input signal crossing through the V IH/IL (AC) level applied to the device under test.2. The input signal minimum slew rate is to be maintained over the range from V REF to V IH (AC) min for rising edges and the range from V REF to V IL (AC)max for falling edges as shown in the below figure.3. AC timings are referenced with input waveforms switching from V IL (AC) to V IH (AC) on the positive transitions and V IH (AC) to V IL (AC) on the negative transitions.Symbol Parameter Rating UnitsNotesTOPEROperating Temperature0 to 95°C 1, 2Symbol Parameter Min.Max.Units NotesV IH (DC)DC input logic high V REF + 0.125V DDQ + 0.3V V IL (DC)DC input logic low- 0.3V REF - 0.125VSymbol ParameterDDR2-667, DDR2-800Units Min.Max.V IH (AC)AC input logic high V REF + 0.200V V IL (AC)AC input logic lowV REF - 0.200VSymbol Condition Value Units Notes V REF Input reference voltage0.5 * V DDQV 1V SWING(MAX)Input signal maximum peak to peak swing1.0V 1SLEWInput signal minimum slew rate1.0V/ns2, 3V DDQ V IH (AC) minV IH (DC) min V REFV IL (DC) max V IL (AC) maxV SS< AC Input Test Signal Waveform >V SWING(MAX)delta TRdelta TFV REF - V IL (AC) maxdelta TFFalling Slew =Rising Slew =V IH (AC) min - V REFdelta TRV DDQCrossing pointV SSQV TR V CPV IDV IX or V OX< Differential signal levels >7.6 Differential input AC logic LevelNote :1. V ID (AC) specifies the input differential voltage |V TR -V CP | required for switching, where V TR is the true input signal (such as CK, DQS, LDQS or UDQS) and V CP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH (AC) - V IL (AC).2. The typical value of V IX (AC) is expected to be about 0.5 * VDDQ of the transmitting device and V IX (AC) is expected to track variations in VDDQ . V IX (AC) indicates the voltage at which differential input signals must cross.7.7 Differential AC output parametersNote :1. The typical value of V OX (AC) is expected to be about 0.5 * VDDQ of the transmitting device and V OX (AC) is expected to track variations in VDDQ . V OX (AC) indicates the voltage at which differential output signals must cross.Symbol ParameterMin.Max.Units Notes V ID(AC)AC differential input voltage 0.5V DDQ + 0.6V 1V IX(AC)AC differential cross point voltage0.5 * VDDQ - 0.1750.5 * VDDQ + 0.175V2Symbol ParameterMin.Max.Units Note V OX (AC)AC differential cross point voltage0.5 * VDDQ - 0.1250.5 * VDDQ + 0.125V1Note : Test condition for Rtt measurementsMeasurement Definition for Rtt(eff):Apply V IH (ac) and V IL (ac) to test pin separately, then measure current I(V IH (ac)) and I( V IL (ac)) respectively. V IH (ac), V IL (ac), and VDDQ values defined in SSTL_18Measurement Definition for VM: Measure voltage (V M ) at test pin (midpoint) with no load.PARAMETER/CONDITIONSYMBOL MIN NOM MAX UNITS NOTES Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 ohm Rtt1(eff)607590ohm 1Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 ohm Rtt2(eff)120150180ohm 1Rtt effective impedance value for EMRS(A6,A2)=1,1; 50 ohm Rtt3(eff)405060ohm 1Deviation of VM with respect to VDDQ/2delta VM- 6+ 6%1Rtt(eff) =V IH (ac) - V IL (ac)I(V IH (ac)) - I(V IL (ac))delta VM =2 x Vm VDDQx 100%- 18.0 ODT DC electrical characteristicsNote :1. Absolute Specifications (0°C ≤ T CASE ≤ +95°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)2. Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ- 280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV.3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage.4. Slew rate measured from V IL (AC) to V IH (AC).5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaranteed by design and characterization.6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process and represents only the DRAM uncertainty. Output slew rate load :7. DRAM output slew rate specification applies to 667Mb/sec/pin and 800Mb/sec/pin speed bins.8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS specification.DescriptionParameterMinNomMaxUnit Notes Output impedanceNormal 18ohmsSee full strength default driver characteristics ohms 1,2Output impedance step size for OCD calibration 0 1.5ohms 6Pull-up and pull-down mismatch 04ohms 1,2,3Output slew rateSout 1.55V/ns1,4,5,6,7,825 ohmsV TTOutput (V OUT)Reference Point9.0 OCD default characteristics(IDD values are for full operating range of Voltage and Temperature, Notes 1 - 5)Symbol Proposed Conditions Units NotesIDD0Operating one bank active-precharge current;t CK = t CK(IDD), t RC = t RC(IDD), t RAS = t RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;Address bus inputs are SWITCHING; Data bus inputs are SWITCHINGmAIDD1Operating one bank active-read-precharge current;IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; t CK = t CK(IDD), t RC = t RC (IDD), t RAS = t RASmin(IDD), t RCD =t RCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address businputs are SWITCHING; Data pat-tern is same as IDD4WmAIDD2P Precharge power-down current;All banks idle; t CK = t CK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATINGmAIDD2Q Precharge quiet standby current;All banks idle; t CK = t CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputsare STABLE; Databus inputs are FLOATINGmAIDD2N Precharge standby current;All banks idle; t CK = t CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING;Data bus inputs are SWITCHINGmAIDD3P Active power-down current;All banks open; t CK = t CK(IDD); CKE is LOW; Other control and address businputs are STABLE; Data bus inputs are FLOATINGFast PDN Exit MRS(12) = 0mASlow PDN Exit MRS(12) = 1mAIDD3N Active standby current;All banks open; t CK = t CK(IDD), t RAS = t RASmax(IDD), t RP = t RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHINGmAIDD4W Operating burst write current;All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; t CK = t CK(IDD), t RAS = t RASmax(IDD), t RP= t RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data businputs are SWITCHINGmAIDD4R Operating burst read current;All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; t CK = t CK(IDD), t RAS = t RAS-max(IDD), t RP = t RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCH-ING; Data pattern is same as IDD4WmAIDD5B Burst auto refresh current;t CK = t CK(IDD); Refresh command at every t RFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid com-mands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHINGmAIDD6Self refresh current;CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs areFLOATING; Data bus inputs are FLOATINGNormal mALow Power mAIDD7Operating bank interleave read current;All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = t RCD(IDD)-1*t CK(IDD); t CK = t CK(IDD), t RC= t RC(IDD), t RRD = t RRD(IDD), t FAW = t FAW(IDD), t RCD = 1*t CK(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the fol-lowing page for detailed timing conditionsmA10.0 IDD Specification Parameters and Test ConditionsNote :1. IDD specifications are tested after the device is properly initialized2. Input slew rate is specified by AC Parametric Test Condition3. IDD parameters are specified with ODT disabled.4. Data bus consists of DQ, DM, DQS, DQS\, RDQS, RDQS\, LDQS, LDQS\, UDQS, and UDQS\. IDD values must be met with all combinations of EMRS bits 10 and 11.5. Definitions for IDD LOW is defined as Vin ≤ VILAC(max) HIGH is defined as Vin ≥ VIHAC(min)STABLE is defined as inputs stable at a HIGH or LOW level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as:inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and controlsignals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes.For purposes of IDD testing, the following parameters are utilizedDetailed IDD7The detailed timings are shown below for IDD7.Legend: A = Active; RA = Read with Autoprecharge; D = DeselectIDD7: Operating Current: All Bank Interleave Read operationAll banks are being interleaved at minimum t RC(IDD) without violating t RRD(IDD) and t FAW(IDD) using a burst length of 4. Control and address bus inputs are STABLE during DESELECTs. IOUT = 0mATiming Patterns for 8bank devices x4/ x8-DDR2-667 5/5/5 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D-DDR2-800 6/6/6 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D -DDR2-800 5/5/5 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D DTiming Patterns for 8bank devices x16-DDR2-667 5/5/5 : A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D-DDR2-800 6/6/6 : A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D -DDR2-800 5/5/5 : A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D DDDR2-800DDR2-800DDR2-667Units Parameter 5-5-56-6-65-5-5CL(IDD)565tCK t RCD(IDD)12.51515ns t RC(IDD)57.56060ns t RRD(IDD)-x4/x87.57.57.5ns t RRD(IDD)-x16101010ns t CK(IDD) 2.5 2.53ns t RASmin(IDD)454545ns t RP(IDD)12.51515ns t RFC(IDD)127.5127.5127.5ns(T A=0o C, VDD= 1.9V)Symbol256Mx4 (K4T1G044QQ)Unit Notes 800@CL=5800@CL=6667@CL=5CE7LE7CF7LF7CE6LE6IDD0757570mAIDD1858580mAIDD2P158158158mAIDD2Q303030mAIDD2N353535mAIDD3P-F353535mAIDD3P-S181818mAIDD3N555550mAIDD4W110110100mAIDD4R130130115mAIDD5140140135mAIDD6156156156mAIDD7245245225mA(T A=0o C, VDD= 1.9V)Symbol128Mx8 (K4T1G084QQ)Unit Notes 800@CL=5800@CL=6667@CL=5CE7LE7CF7LF7CE6LE6IDD0757570mAIDD1858580mAIDD2P158158158mAIDD2Q303030mAIDD2N353535mAIDD3P-F353535mAIDD3P-S181818mAIDD3N555550mAIDD4W115115105mAIDD4R135135120mAIDD5145145140mAIDD6156156156mAIDD7250250230mA11.0 DDR2 SDRAM IDD Spec Table(T A=0o C, VDD= 1.9V)Symbol64Mx16 (K4T1G164QQ)Unit Notes 800@CL=5800@CL=6667@CL=5CE7LE7CF7LF7CE6LE6IDD0909085mA IDD110010095mA IDD2P158158158mA IDD2Q303030mA IDD2N353535mA IDD3P-F353535mA IDD3P-S181818mA IDD3N555550mA IDD4W130130115mA IDD4R175175155mA IDD5145145140mA IDD6156156156mA IDD7265265245mASpeedDDR2-800(E7)DDR2-800(F7)DDR2-667(E6)UnitsBin (CL - tRCD - tRP)5-5-56-6-65 - 5 - 5Parameter min max min max min max tCK, CL=358--58ns tCK, CL=4 3.758 3.758 3.758ns tCK, CL=5 2.583838ns tCK, CL=6-- 2.58--ns tRCD 12.5-15-15-ns tRP 12.5-15-15-ns tRC 57.5-60-60-ns tRAS457000045700004570000ns ParameterSymbol DDR2-667DDR2-800Units Min Max Min Max Input capacitance, CK and CK CCK 1.0 2.0 1.0 2.0pF Input capacitance delta, CK and CK CDCK x 0.25x 0.25pF Input capacitance, all other input-only pins CI 1.0 2.0 1.0 1.75pF Input capacitance delta, all other input-only pins CDI x 0.25x 0.25pF Input/output capacitance, DQ, DM, DQS, DQS CIO 2.5 3.5 2.5 3.5pF Input/output capacitance delta, DQ, DM, DQS, DQSCDIOx0.5x0.5pF13.0 Electrical Characteristics & AC Timing for DDR2-800/667(0 °C < T OPER < 95 °C; V DDQ = 1.8V + 0.1V; V DD = 1.8V + 0.1V)13.1 Refresh Parameters by Device DensityParameterSymbol256Mb 512Mb 1Gb 2Gb 4Gb Units Refresh to active/Refresh command time tRFC 75105127.5195327.5ns Average periodic refresh intervaltREFI0 °C ≤ T CASE ≤ 85°C 7.87.87.87.87.8µs 85 °C < T CASE ≤ 95°C3.93.93.93.93.9µs13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin 12.0 Input/Output capacitance。
CommScope 8-口扇区押发器说明书
8-port sector antenna, 2x 698–803, 2x 824-894 and 4x 1695–2690MHz, 33° HPBW, low bands each have a RET and high bands sharea RETOne RET for 700MHz, one RET for 850MHz, and one RET for both high bands to ensure same tiltlevel for 4x Rx or 4x MIMOInternal filter on low band and interleaved dipole technology providing for attractive, low windload mechanical packageNarrow beamwidth capacity antenna for higher level of densification and enhanced datathroughputGeneral SpecificationsAntenna Type SectorBand MultibandColor Light Gray (RAL 7035)Grounding Type RF connector body grounded to reflector and mounting bracketPerformance Note Outdoor usageRadome Material Fiberglass, UV resistantReflector Material AluminumRF Connector Interface 4.3-10 FemaleRF Connector Location BottomRF Connector Quantity, mid band4RF Connector Quantity, low band4RF Connector Quantity, total8Remote Electrical Tilt (RET) InformationRET Hardware CommRET v2RET Interface8-pin DIN Female | 8-pin DIN MaleRET Interface, quantity 1 female | 1 maleInput Voltage10–30 VdcInternal RET Low band (2) | Mid band (1)Power Consumption, active state, maximum10 WPower Consumption, idle state, maximum 2 WProtocol3GPP/AISG 2.0 (Single RET)15Page ofPage of 25DimensionsWidth 640 mm | 25.197 in Depth 235 mm | 9.252 in Length2438 mm | 95.984 in Net Weight, antenna only64 kg | 141.096 lbArray LayoutPort ConfigurationElectrical SpecificationsImpedance50 ohmOperating Frequency Band1695 – 2690 MHz | 698 – 803 MHz | 824 – 894 MHzPolarization±45°Total Input Power, maximum800 W @ 50 °CElectrical SpecificationsFrequency Band, MHz698–803824–8941695–18801850–19901920–22002300–2690Gain, dBi18.3192020.320.821.7353134343327Beamwidth, Horizontal,degreesBeamwidth, Vertical, degrees9.98.7 5.8 5.4 5.1 4.4Beam Tilt, degrees0–100–102–122–122–122–12Horizontal Sidelobe, dB212019171716USLS (First Lobe), dB171818171820323634353736Front-to-Back Ratio at 180°,dBIsolation, Cross Polarization,252525252525dBIsolation, Inter-band, dB30303030303035Page ofVSWR | Return loss, dB 1.5 | 14.0 1.5 | 14.0 1.5 | 14.0 1.5 | 14.0 1.5 | 14.0 1.5 | 14.0PIM, 3rd Order, 2 x 20 W, dBc-153-153-153-153-153-153150150250250250200Input Power per Port at 50°C,maximum, wattsElectrical Specifications, BASTAFrequency Band, MHz698–803824–8941695–18801850–19901920–22002300–269018.118.819.620.120.421.3Gain by all Beam Tilts,average, dBi±0.4±0.4±0.7±0.3±0.5±0.5Gain by all Beam TiltsTolerance, dB±3.3±0.7±3.3±1±1.6±2.3Beamwidth, HorizontalTolerance, degrees±0.5±0.4±0.3±0.2±0.3±0.3Beamwidth, VerticalTolerance, degrees171716171717USLS, beampeak to 20° abovebeampeak, dB282829303030Front-to-Back Total Power at180° ± 30°, dBCPR at Boresight, dB181718212021CPR at 10 dB Horizontal81613141312Beamwidth, dBMechanical SpecificationsWind Loading @ Velocity, frontal954.0 N @ 150 km/h (214.5 lbf @ 150 km/h)Wind Loading @ Velocity, lateral355.0 N @ 150 km/h (79.8 lbf @ 150 km/h)Wind Loading @ Velocity, maximum1,434.0 N @ 150 km/h (322.4 lbf @ 150 km/h)Wind Loading @ Velocity, rear1,086.0 N @ 150 km/h (244.1 lbf @ 150 km/h)Wind Speed, maximum241 km/h (150 mph)Packaging and WeightsWidth, packed752 mm | 29.606 inDepth, packed382 mm | 15.039 inLength, packed2590 mm | 101.969 inWeight, gross88 kg | 194.007 lbRegulatory Compliance/CertificationsAgency Classification45Page ofCHINA-ROHS Above maximum concentration valueISO 9001:2015Designed, manufactured and/or distributed under this quality management system ROHS Compliant/ExemptedUK-ROHSCompliant/ExemptedIncluded ProductsBSAMNT-4–Wide Profile Antenna Downtilt Mounting Kit for 2.4 - 4.5 in (60 - 115 mm) OD round members.Kit contains one scissor top bracket set and one bottom bracket set.BSAMNT-M4–Middle Downtilt Mounting Kit for Long Antennas for 2.4 - 4.5 in (60 - 115 mm) OD roundmembers. Kit contains one scissor bracket set.* FootnotesPerformance Note Severe environmental conditions may degrade optimum performancePage of55。
Transcend 8X Slim Portable CD DVD Writer TS8XDVDS
User’s Manual Slim Portable CD/DVD WriterTS8XDVDS(Version 1.1)Table of ContentsIntroduction︱ (1)Features︱ (2)System Requirements︱ (2)General Use (2)Writing Data (3)Power (3)Reminders (4)Product Overview︱ (5)Basic Operation︱ (6)Plugging in the CD/DVD Writer (6)Inserting a Disc (6)Ejecting a Disc (9)Disconnecting from a Computer︱ (11)Software Download︱ (11)Troubleshooting︱ (13)System Requirements︱ (14)Ordering Information︱ (14)Recycling & Environmental Considerations︱ (15)Two-year Limited Warranty︱ (16)Introduction︱Congratulations on purchasing Transcend’s 8X Slim Portable CD/DVD Writer.This slim, elegant high-speed portable CD/DVD writer is perfect for playing, backing up your vital data and discs. With its slim easy-to-carry size and advanced high-speed media writing capabilities, the CD/DVD Writer is ideal for playing movies, installing software, or backing up your files, folders, documents, photos, music and videos when using a compact notebook computer or netbook. In addition, the CD/DVD Writer comes with a full-version of CyberLink’s extremely useful Power2Go* software that lets you easily create your own CDs and DVDs. This User’s Manual is designed to help you get the most from your new device. Please read it in detail before using the CD/DVD Writer.*Power2Go is a registered trademark of CyberLink®. This software can be only used in Windows®XP, Windows Vista® , Windows®7 and Windows®8.Features︱USB 2.0 interface for high-speed data transfer8x DVD±R read/write, 24x CD-R/RW read/writeCompatible with CD-R/RW, DVD±R, DVD±RW, DVD±R DL, DVD-RAM mediaReads and writes Dual Layer discsUSB powered –No external power adapter neededElegant slim modern design with rounded edgesCompact and easy-to-carryEasy Plug and Play installationAnti-slip rubber feetSystem Requirements︱Desktop or notebook computer with two working USB ports.One of following Operating Systems:•Windows®XP•Windows Vista®•Windows® 7•Windows® 8•Mac OS® X 10.4 or laterSafety Precautions︱These usage and safety guidelines are IMPORTANT! Please follow them carefully.Please ensure that you connect the USB cable to the CD/DVD Writer and your computer correctly (small end CD/DVD Writer, large end PC)General Use•During operation, avoid exposing your CD/DVD writer to extreme temperatures above 40℃or below 5℃.•Never drop your CD/DVD Writer.•Only use the CD/DVD Writer face-up, on a stable flat surface•Do not allow your CD/DVD Writer to come in contact with water or any other liquids.•Do not use a damp/wet cloth to wipe or clean the exterior case.•Never look directly into the laser lens, as it can be harmful to your eyes.•Do not attempt to open the outer case (doing so will void your product warranty).•Do not store your CD/DVD Writer in any of the following environments:o Direct sunlighto Next to an air conditioner, electric heater or other heat sourceso In a closed car that is in direct sunlighto In an area with strong magnetic fields or excessive vibration• Never touch the laser lens.Writing Data• Do not touch, pick up, or move the CD/DVD Writer during the write process. This candamage the device and will cause errors on the disc being written• Transcend does not take any responsibility for data loss or damage resulting fromuse of this product . If using this product to backup data, we strongly advise using high-quality recordable media, and that you fully test and verify the contents of all written discs. It is also a good idea to regularly backup important data to a different computer or other storage medium.• To ensure High-Speed USB 2.0 data transfer rates when using your CD/DVD Writer witha computer, please check that the computer has the relevant USB drivers. If you are unsure about how to check this, please consult the computer or motherboard User’sManual for USB driver information.Power• The CD/DVD Writer is powered directly from your computer’s USB port. However, theUSB ports of certain computers may not supply enough power to use the CD/DVD Writer when using a single USB port. Please make sure to connect both large connector ends of the provided USB Cable to the USB ports on your computer. This will ensure the CD/DVD Writer receives adequate power for stable operation.• Only use the USB cable that came with the CD/DVD Writer to connect it to a computer,and always ensure that the cable is in good condition. NEVER use a cable that is frayedThe second USB connector provides additional power forthe CD/DVD Writer. Please make sure to connect bothUSB connectors to your computer’s USB ports.or damaged.•Ensure nothing is resting on the USB cable and that the cable is not located where it can be tripped over or stepped on.•If you have connected all ends of the USB cable and still have power-related problems while reading / writing data, we recommend that you purchase a Transcend USB Power Adapter (TS-PA2A) to provide the power necessary to operate the CD/DVD Writer.Reminders•Always follow the procedures in the “Disconnecting from a Computer” section to remove the CD/DVD Writer from your computer.Product Overview︱A Disc TrayB Read/Write Activity IndicatorC Eject ButtonD Emergency EjectE Anti-slip Rubber FeetF USB ConnectorBasic Operation︱Plugging in the CD/DVD Writer1. Plug the small end of the USB Cable into the Mini USB port on the CD/DVD Writer.2. Plug the large end(s) of the cable into available USB ports on your desktop computer, notebookor netbook.Note: Please be sure to connect the CD/DVD Writer to two USB ports on your computer using the provided USB Cable.3. When the CD/DVD Writer is successfully connected to a computer, a new drive with a newlyassigned drive letter will appear in the My Computer window, and a Removable Hardwareicon will appear on the Windows System Tray.*D: is an example drive letter. The letter in your "My Computer" window may differ4. Once properly connected, you can use the CD/DVD Writer as an optical device to read CDsand DVDs, and create/write your own discs with the included Power2Go software.Inserting a Disc1. Press the Eject Button on the front of the CD/DVD Writer to release the disc tray.2. Gently pull the disc tray out until it stops.3. Place a CD or DVD onto the tray.4. Using two or more fingers, press down on the center of the disc until it snaps into place.5. Push the disc tray back into the CD/DVD Writer. When completely closed, the LED indicatorwill flash.Ejecting a Disc1. Press the Eject Button on the front of the CD/DVD Writer to release the disc tray.2. Gently pull the disc tray out until it stops.3. Place your thumb on the spindle and use your other fingers to gently pry the disc upwards untilit pops free.Disconnecting from a Computer︱NEVER disconnect the CD/DVD Writer from a Computer when the disc is spinning.1. Select the Hardware icon on the system tray.2. The Safely Remove Hardware pop-up window will appear. Select it to continue.3. A window will appear stating, “The ‘USB Mass Storage Device’ device can now be safelyremoved from the system.”Always use this procedure to safely remove the device from a Windows computer.Software Download︱The free software download includes: CyberLink® Power2Go (LE Version) and CyberLink®MediaShow (trial version).Note: CyberLink®Power2Go and MediaShow can only be installed in Windows® XP/Vista/7/8.Make sure that the DVDS is connected to your computer before installing:1. Download the CyberLink Media Suite 10 from Transcend’s online Download Center at/downloads.2. Double click on the CyberLink.Media.Suite.10.zip Zip file you have just downloaded fromthe Transcend website.3. Extract the file to a temporary directory on your hard disk and double click on the fileCyberLink.Media.Suite.10.exe to run the setup program.4. Follow the on-screen instructions to complete the installation process.CyberLink Power2Go: Power2Go lets you burn music, data, video and even bootable discs in a variety of CD and DVD formats. CyberLink Power2Go also includes several handy discutilities and an express mode that makes burning convenient and easy.CyberLink MediaShow: MediaShow is a useful tool for compiling, arranging, and producing media files with a simple and straightforward software interface.Troubleshooting︱If a problem occurs with your CD/DVD Writer,please check the information listed below before sending your CD/DVD Writer in for repair. If you are unable to remedy a problem after trying the following suggestions, please consult your dealer, service center, or local Transcend branch office. We also have FAQ and Support services on our website at .Operating system cannot detect the CD/DVD WriterCheck the following:1. Is your CD/DVD Writer properly connected to the USB port? If not, unplug it and plug it inagain. If it is properly connected, try using another available USB port.2. Are you using the USB cable that came in the CD/DVD Writer package? If not, try using theTranscend-supplied USB cable to connect the CD/DVD Writer to your computer.3. The CD/DVD Writer is powered directly via a computer USB port; however, the power suppliedby the USB port on some older computers is below the 5V DC required to power the CD/DVD Writer. Please make sure to connect the USB cable to both USB ports on your computer. This will provide the additional power necessary to run the drive.Both USB connectors are required to provide adequate power.4. Is the USB port enabled? If not, refer to the user’s manual of your computer (or motherboard)to enable it.5. If you have connected all ends of the USB cable and still have power-related problems whilereading / writing data, we recommend that you purchase a Transcend USB Power Adapter (TS-PA2A) to provide the power necessary to operate the CD/DVD Writer. (Please see the Transcend Website or contact your local dealer for availability)My computer does not recognize CD/DVD Writer1. A single USB port may not provide enough power for the CD/DVD Writer to function. Makesure you plug both large ends of the USB cable directly into your computer’s USB ports.2. Avoid connecting the CD/DVD Writer through a USB hub.The CD/DVD Writer does not Power On (LED does not flash)Check the following:1. Ensure that the CD/DVD Writer is properly connected to the USB port(s) on your computer.2.Ensure that the USB port is working properly. If not, try using an alternate USB port.The CD/DVD Writer Cannot Read a DiscThe disc may be dirty, scratched or damaged. Try cleaning the disc with water or a CD/DVDcleaning solution.Writing to a Blank Disc FailsIn most cases, this problem is a result of trying to write to poor quality recordable media. For best results, please use only retail-packaged name brand recordable discs.System Requirements ︱Hardware CPU: Intel Pentium III 800 MHz or equivalent (minimum )Intel Pentium IV 2.0 GHz or higher (recommended )Memory: 256MB or greaterHard Drive: 20GB of free space requiredSoftwareOperating System: Windows ® XP , Windows Vista ® , Windows ® 7 or Windows ® 8Ordering Information ︱Device Description Transcend P/N USB Power Adapter TS-PA2ARecycling & Environmental Considerations︱Recycling the Product (WEEE): Your product is designed and manufactured with high quality materials and components, which can be recycled and reused. When you see the crossed-out wheel bin symbol attached to a product, it means the product is covered by the European Directive 2002/96/EC:Never dispose of your product with other household waste. Please inform yourself about the local rules on the separate collection of electrical and electronic products. The correct disposal of your old product helps prevent potential negative consequences on the environment and human health.Battery Disposal: Your product contains a built-in rechargeable battery covered by the European Directive 2006/66/EC, which cannot be disposed of with normal household waste.Please inform yourself about the local rules on separate collection of batteries. The correct disposal of batteries helps prevent potentially negative consequences on the environment and human health.For products with non-exchangeable built in batteries: The removal of (or the attempt to remove) the battery invalidates the warranty. This procedure is only to be performed at the end of the product’s life.Two-year Limited Warranty︱This product is covered by a Two-year Limited Warranty.Should your product fail under normal use within two years from the original purchase date, Transcend will provide warranty service pursuant to the terms of the Transcend Warranty Policy. Proof of the original purchase date is required for warranty service. Transcend will inspect the product and in its sole discretion repair or replace it with a refurbished product or functional equivalent. Under special circumstances, Transcend may refund or credit the current value of the product at the time the warranty claim is made. The decision made by Transcend shall be final and binding upon you. Transcend may refuse to provide inspection, repair or replacement service for products that are out of warranty, and will charge fees if these services are provided for out-of-warranty products.LimitationsAny software or digital content included with this product in disc, downloadable, or preloaded form, is not covered under this Warranty. This Warranty does not apply to any Transcend product failure caused by accident, abuse, mishandling or improper usage (including use contrary to the product description or instructions, outside the scope of the product’s intended use, or for tooling or testing purposes), alteration, abnormal mechanical or environmental conditions (including prolonged exposure to humidity), acts of nature, improper installation (including connection to incompatible equipment), or problems with electrical power (including undervoltage, overvoltage, or power supply instability). In addition, damage or alteration of warranty, quality or authenticity stickers, and/or product serial or electronic numbers, unauthorized repair or modification, or any physical damage to the product or evidence of opening or tampering with the product casing will also void this Warranty. This Warranty shall not apply to transferees of Transcend products and/or anyone who stands to profit from this Warranty without Transcend’s prior written authorization. This Warranty only applies to the product itself, and excludes integrated LCD panels, rechargeable batteries, and all product accessories (such as card adapters, cables, earphones, power adapters, and remote controls). Transcend Warranty PolicyPlease visit /warranty to view the Transcend Warranty Policy.By using the product, you agree that you accept the terms of the Transcend Warranty Policy, which may be amended from time to time.Online registrationTo expedite warranty service, please access /register to register your Transcend product within 30 days of the purchase date.Transcend Information, Inc.*The Transcend logo is a registered trademark of Transcend Information, Inc.*The specifications mentioned above are subject to change without notice.*All logos and marks are trademarks of their respective companies.。
SPW17N80C3中文资料
IGSS
VGS=20V, VDS=0V
-
- 100 nA
Drain-source on-state resistance RDS(on) VGS=10V, ID=11A,
Ω
Tj=25°C
- 0.25 0.29
Tj=150°C
- 0.78 -
Gate input resistance
RG
f=1MHz, open Drain
ID
TC = 25 °C
TC = 100 °C
Pulsed drain current, tp limited by Tjmax
ID puls
Avalanche energy, single pulse
EAS
ID = 3.4 A, VDD = 50 V
Avalanche energy, repetitive tAR limited by Tjmax1) EAR
Values
Unit
min. typ. max.
Drain-source breakdown voltage V(BR)DSS VGS=0V, ID=0.25mA 800
-
Drain-Source avalanche
V(BR)DS VGS=0V, ID=17A
-
870
breakdown voltage
Symbol
Value
Unit Symbol
Value
typ.
typ.
Thermal resistance
Thermal capacitance
Rth1 Rth2 Rth3 Rth4 Rth5 Rth6
0.00812 0.016 0.031 0.114 0.135 0.059
wap-223_101-httpsm-20010928-a
Specification Information NoteWAP-223_101-HTTPS-20010928-a28-Sept-2001forHTTP State Management Specification13-DEC-2000Wireless Application ProtocolWAP-223-HTTPS-20001213-a A list of errata and updates to this document is available from the WAP Forum™ Web site, /,in the form of SIN documents, which are subject to revision or removal without notice.©2001, Wireless Application Protocol Forum, Ltd. All Rights Reserved. Terms and conditions of use are available fromWAP-223_101-20010928-a, Version 28-September-2001 Page 2 (15)© 2001, Wireless Application Forum, Ltd. All rights reserved.Terms and conditions of use are available from the WAP Forum™ Web site at/docs/copyright.htm.You may use this document or any part of the document for internal or educational purposes only, provided you do not modify, edit or take out of context the information in this document in any manner. You may not use this document in any other manner without the prior written permission of the WAP Forum™. The WAP Forum authorises you to copy this document, provided that you retain all copyright and other proprietary notices contained in the original materials on any copies of the materials and that you comply strictly with these terms. This copyright permission does not constitute an endorsement of the products or services offered by you.The WAP Forum™ assumes no responsibility for errors or omissions in this document. In no event shall the WAP Forum be liable for any special, indirect or consequential damages or any damages whatsoever arising out of or in connection with the use of this information.WAP Forum™ members have agreed to use reasonable endeavors to disclose in a timely manner to the WAP Forum the existence of all intellectual property rights (IPR's) essential to the present document. The members do not have an obligation to conduct IPR searches. This information is publicly available to members and non-members of the WAP Forum and may be found on the "WAP IPR Declarations" list at /what/ipr.htm. Essential IPR is available for license on the basis set out in the schedule to the WAP Forum Application Form.No representations or warranties (whether express or implied) are made by the WAP Forum™ or any WAP Forum member or its affiliates regarding any of the IPR's represented on this list, including but not limited to the accuracy, completeness, validity or relevance of the information or whether or not such rights are essential or non-essential.This document is available online in PDF format at /.Known problems associated with this document are published at /. Comments regarding this document can be submitted to the WAP Forum™ in the manner published at /.CONTENTS1.Scope (4)2.Document Status (5)2.1Copyright Notice (5)2.2Errata (5)2.3Comments (5)2.4Document Changes (5)2.5Document History (5)3.References (7)3.1Normative References (7)3.2Informative References (7)4.Definitions and Abbreviations (8)4.1Definitions (8)4.2Abbreviations (8)5.Overview (9)6.HTTP State Management Headers (9)6.1Cookie (9)6.2Set-Cookie (9)7.WAP Specific HTTP State Management Headers (10)7.1X-Wap-Proxy-Cookie (10)7.2X-Wap-Proxy-Set-Cookie (10)8.WAP Gateway Responsibilities (11)9.Cookie Proxy Responsibilities (11)9.1Pass Through Cookie Proxy (11)9.2Cookie Management And Storage (11)9.3Associating Cookie Storage With Clients (13)9.4Managing Proxy Cookies (13)er Agent Responsibilities (13)10.1HTTP State Management (13)10.2Cookie Proxy Management (13)11.Static Conformance Requirements (14)11.1User Agent Features (14)11.2Cookie Proxy Features (14)1. SCOPEWireless Application Protocol (WAP) is a result of continuous work by the WAP Forum to define an industry-wide specification for developing applications that operate over wireless communication networks. The scope of the WAP Forum is to define a set of specifications to be used by service applications for wireless communication devices. The wireless market is growing very quickly and reaching new customers and services. To enable operators and manufacturers to meet the challenges in advanced services, differentiation and fast/flexible service creation, WAP defines a set of protocols in transport, session and application layers. For additional information on the WAP architecture, refer to "Wireless Application Protocol Architecture Specification" [WAP].This specification defines the HTTP state management model for the WAP architecture. The WAP HTTP state management model is an implementation of the HTTP State Management Mechanism, also known as "cookie management", as defined in [RFC2109]. On the World Wide Web, the HTTP State Management mechanism stores state information in a file ("cookie") on the client, as defined in [RFC2109]. The same mechanism can also be used over the WAP protocols, as HTTP headers are used to convey all state and state manipulation information.Some WAP user agents may have motivation to store and manage cookies locally, as defined in [RFC2109]. This functionality follows precisely the current World Wide Web model, where cookies are typically stored and managed by regular web browsers.This specification defines an additional mechanism to let an intermediate proxy store and manage cookies on behalf of the WAP client, as an alternative to client-local storage and management. Storing cookies in the network has many advantages. WAP user agents may have a limited storing capacity. When cookies are stored in the proxy, they do not have to be transmitted across the air, for every request/response transaction. In case the user changes device, and cannot move the cookies from the old device to the new one, the user can still access the cookies in the proxy via the new device. On the other hand, storing and managing cookies in the client allows the user to gain the benefit of the same cookies independent of the access point used. This aspect becomes more important in the future in conjunction with WAP gateway roaming architecture. Some users may prefer storing private information in the client, instead of depending on the security of the network. Because both models are complementary, this specification defines a dual approach to WAP HTTP state management, while still maintaining full interoperability between the implementations and RFC2109.2. DOCUMENT STATUSThis document is available online in the following formats:• PDF format at /.2.1 Copyright Notice© Copyright Wireless Application Forum Ltd, 2000 all rights reserved.Terms and conditions of use are available from the Wireless Application Forum Ltd. web site at /docs/copyright.htm.2.2 ErrataKnown problems associated with this document are published at /.2.3 CommentsComments regarding this document can be submitted to the WAP Forum in the manner published at /.2.4 Document ChangesChange Request Title CommentsCR-WAP-223-HTTP-STATE-MGMT-NOKIA-20000913 Backward Compatibility toearlier releasesThese changes are as aresult of architecturalconsistency review of thedocument.CR-WAP-223-HTTP-STATE-MGMT-NOKIA-20001031 Clarifications from initial Architectural Consistency reviewCR-WAP-223-HTTP-STATE-MGMT-NOKIA-20001213 Editorial changes from closeout architectural consistency review2.5 Document HistoryDocument Name Date of ReleaseWAP-223-HTTPSM-20000530-d 30-MAY-2000 Draft accepted by WAGWAP-223-HTTPSM-20000922-d 22-SEP-2000 Draft submitted for proposedWAP-223-HTTPSM-20001213-d 13-DEC-2000 Reviewed For ArchitecturalConsistencyWAP-223-HTTPSM-20001213-p 24-JAN-2001 Proposed (No changes)WAP-223-HTTPSM-20001213-a Approved (No changes)WAP-223_101-HTTPSM-20010928-p 28-Sept-2001 Replaced underscores with dashes in SCRs. No substantive changes, editorial only. Fixed format for dependency in HSM-S-002 through 006 (no change to intent)3. REFERENCES3.1 Normative References[RFC2616] "Hypertext Transfer Protocol - HTTP/1.1", R. Fielding, et al., June 1999. URL: /rfc/rfc2616.txt[RFC2109] "HTTP State Management Mechanism", D. Kristol, et al, February 1997. URL: /rfc/rfc2109.txt[WAE] "Wireless Application Environment Specification", WAP Forum, 04-November-1999. URL: /3.2 Informative References[RFC2119] "Key words for use in RFC's to Indicate Requirement Levels", S. Bradner, March 1997. URL: /rfc/rfc2119.txt[WAP] "Wireless Application Protocol Architecture Specification", WAP Forum, 30-April-1998. URL: /[WSP] "Wireless Session Protocol", WAP Forum, 30-April-1998. URL:/4. DEFINITIONS AND ABBREVIATIONS4.1 DefinitionsThe following are terms and conventions used throughout this specification.The key words "MUST", "MUST NOT", "REQUIRED", "SHALL", "SHALL NOT", "SHOULD", "SHOULD NOT", "RECOMMENDED", "MAY" and "OPTIONAL" in this document are to be interpreted as described in [RFC2119].Client - a device (or application) that initiates a request for a connection with a server.Cookie Proxy - an intermediate program that acts as a user agent for the purpose of managing cookies and cookie storage on behalf of other user agents.Origin Server - the server, on which a given resource resides or is to be created, often referred to as a web server or an HTTP server. (also referred to as a "server" in this specification.)Proxy - an intermediate program that acts as both a server and a client for the purpose of making requests on behalf of other clients ([RFC2616]).Server - see "origin server".User - a person, who interacts with a user agent to view, hear or otherwise use a resource.User Agent - a user agent is any software or device that interprets WML, WMLScript or other content. This may include textual browsers, voice browsers and search engines.User Agent Session – a session which begins when user agent is activated and ends when it exits.4.2 AbbreviationsFor the purposes of this specification, the following abbreviations apply.HTTP Hypertext Transfer Protocol [RFC2616]RFC Request For CommentsURI Universal Resource IdentifierURL Universal Resource LocatorW3C World Wide Web ConsortiumWAE Wireless Application Environment [WAE]WAP Wireless Application Protocol [WAP]WSP Wireless Session Protocol [WSP]5. OVERVIEWThe HTTP State Management Mechanism is defined in [RFC2109]. In short, RFC2109 defines a means whereby an origin server can request that a small unit of state (a "cookie") is stored in the user agent, and included in subsequent requests to the origin server. A variety of controls are available to the origin server, allowing it to control when the "cookie" is included in subsequent requests, when the "cookie" expires as well as other state management and transport controls. As defined in [RFC2109], the user agent is responsible for cookie management. In this model, the WAP gateway conveys state information between the user agents and the origin servers. It is then the responsibility of the user agent to manage and store the cookies and to offer the user means for control over these functions.Although RFC2109 puts cookie management in the user agent, it may, in some cases be convenient to take advantage of an architecture, which enables network elements to manage and store cookies. The WAP HTTP State Management Architecture defines the concept of a Cookie Proxy. The cookie proxy is an HTTP proxy or proxy equivalent (e.g., WAP Gateway) that manages cookies on behalf of WAP user agents that do not implement the HTTP state function directly. The cookie proxy is responsible for managing and storing cookies on behalf of the user agents, and modifies HTTP requests and responses to and from the user agent to implement this function.This architecture supports clients with and without local cookie storage, and enables the user agent to control whether proxy cookie storage is enabled. In addition to this, WAP specific HTTP state management headers allow a simple synchronization scheme for user agent and proxy-based cookies. User agents can indicate if they rely on having cookies stored in the Cookie Proxy for a specific user agent session, and Cookie Proxy can notify the user agent if it has problems with their management.The cookie proxy operation has three stages:• Enabling or disabling the storage of cookies on the proxy. The user agent controls this function with an HTTP header.• Origin server request for a cookie to be stored for the duration of the user agent session or fora certain predefined period of time. This is performed via the HTTP Set-Cookie header, asspecified in [RFC2109].• Delivery of the cookie to the origin server in subsequent requests. This is performed via the HTTP Cookie header, as specified in [RFC2109].6. HTTP STATE MANAGEMENT HEADERS6.1 CookieCookie header is defined in [RFC2109].6.2 Set-CookieSet-Cookie header is defined in [RFC2109].7. WAP SPECIFIC HTTP STATE MANAGEMENT HEADERS7.1 X-Wap-Proxy-CookieThis header is sent in the request from the user agent to indicate whether the Cookie Proxy should store cookies from origin servers or not. X-Wap-Proxy-Cookie header is also used to send status information from user agent to the Cookie Proxy.x-wap-proxy-cookie = "X-Wap-Proxy-Cookie:" choicechoice = "cache" | "cache-has-state" | "delete" |"none" | "session" | "session-has-state" The choices are introduced briefly as follows:• When the value is "cache" or "cache-has-state", the Cookie Proxy caches cookies and sends them to the origin server on behalf of the user agent. Requests and responsesbetween the Cookie Proxy and the origin server include Cookie and Set-Cookieheaders, as they are defined in RFC2109. User agent appends cache-has-state value instead of cache in case it has received at least one X-Wap-Proxy-Set-Cookie header during the ongoing user agent session. This mechanism enables simple method forsynchronization between user agents and Cookie Proxy. On account of this informationCookie Proxy can e.g. detect if the user agent session based cookies from the previoususage time should be discarded.• When the value is "delete", the Cookie Proxy does not send any cookies to the origin server or store any received cookies. That is, the proxy acts as a filter ("cookie monster")and deletes all cookies before they are sent to the user agent.• If the header is not present, or has a value of "none", the proxy passes all HTTP cookie headers through between the user agent and the origin server without interception. In this document, a Cookie Proxy executing this function is known as a Pass-Through CookieProxy. This is the default condition.• When the value is "session", or "session-has-state", Cookie Proxy and user agent functionalities are combined. If Cookie Proxy receives a response containing a Set-Cookie header from the origin server, it decides the place for cookie storage according to the presence of the Max-Age attribute in the Set-Cooki e header. This method can beused to separate session-based cookies from long-lived ones. The difference betweensession and session-has-state values is similar to the difference between cacheand cache-has-state values, which is described above.Note that status of the session is bound to the user agent session, which begins when the user agent starts and ends when it exits. Status is not related to a certain cookie-derived session, but it simply tells if the user agent has cookies managed by the Cookie Proxy during a particular user agent session. The user agent session is not related to the concept of session defined in [WSP].7.2 X-Wap-Proxy-Set-CookieThis header is sent in the response to the user agent from the Cookie Proxy to indicate that one or more cookies were received in a response from an origin server and stored in the cookie proxyand/or at least one cookie was sent in the corresponding request. In addition to this, Cookie Proxy uses X-Wap-Proxy-Set-Cookie header to report an erroneous status to the user agents.x-wap-proxy-set-cookie = "X-Wap-Proxy-Set-Cookie: choice"choice = "state" | "error"The choices are introduced briefly as follows:• When value is "state", the user-agent is able to detect that a stateful session is in progress. Cookie Proxy sends this value in the response to the user agent when it receivesa Set-Cookie header from the origin server and chooses to manage the cookie. Thisheader is also sent when the Cookie Proxy has added a Cookie header in the relatedHTTP request.• When the value is "error", Cookie Proxy has detected a mismatch between the status of the user agent and the Cookie Proxy (i.e. Cookie Proxy has lost the cookies during aparticular user agent session).8. WAP GATEWAY RESPONSIBILITIESThe WAP gateway is responsible for delivering state management information between the user agent and the origin server. Header encoding for HTTP state management headers and WAP specific state management headers are defined in [WSP].9. COOKIE PROXY RESPONSIBILITIES9.1 Pass Through Cookie ProxyThe Cookie Proxy MUST implement Pass Through Cookie Proxy functionality, i.e. passing the HTTP headers between the user agent and the origin server without interference. If HTTP state management is not implemented in the client user agent, then the actions taken by the Cookie Proxy are undefined in this specification.9.2 Cookie Management And StorageThe Cookie Proxy MAY be responsible for managing and storing cookies on behalf of user agents. If this functionality is implemented, the X-Wap-Proxy-Cookie and X-Wap-Proxy-Set-Cookie headers MUST be used for communication between the client and the proxy. The proxy emulates user agent functionality when communicating with origin servers. User agent role in HTTP state management mechanism is defined in RFC2109.The user agent MAY control the cookie management in the Cookie Proxy with X-Wap-Proxy-Cookie header. The Cookie Proxy MUST enforce the following rules when receiving WAP specific HTTP headers from the client (precondition: Cookie Proxy has identified and authenticated the client and chosen to manage cookies on behalf of the user agents)1. If the choice in X-Wap-Proxy-Cookie header equals cache or cache-has-state,Cookie Proxy MUST cache cookies and send them to the origin server on behalf of the user agent. In addition to this, when Cookie Proxy receives X-Wap-Proxy-Cookie: cacheheader, it MUST discard all the current user agent session -based cookies (i.e. cookies which were sent from the origin server without Max-Age –attribute).2. If the choice in X-Wap-Proxy-Cookie header equals delete, Cookie Proxy MUST NOTsend cookies to the origin server or store any received cookies. In addition to this, CookieProxy MUST NOT send any received cookies to the client. Cookie Proxy MUST NOT delete any cookies stored prior to receiving the delete header.3. If the choice in X-Wap-Proxy-Cookie header equals none or the header is missing from therequest, Cookie Proxy MUST act as a Pass Through Cookie Proxy.4. If the choice in X-Wap-Proxy-Cookie header equals session or session-has-state,Cookie Proxy MUST include cookies in the requests to the origin servers. If the Cookie Proxy receives a response containing the Set-Cookie header from the origin server, it MUSTdecide the place for cookie storage according to the presence of the Max-Age attribute in the Set-Cooki e header. If Max-Age attribute is present, cookie MUST be transmitted to the user agent without interception. Otherwise it MUST be stored by the Cookie Proxy until it receivesa subsequent X-Wap-Proxy-Cookie: session (or X-Wap-Proxy-Cookie: cache)header from the user agent. Similarly to X-Wap-Proxy-Cookie: cache header, X-Wap-Proxy-Cookie: session effectively indicates that user agent does not have any cookies bound to the current user agent session and thus all stored cookies without Max-Age attribute MUST be discarded.The Cookie Proxy MUST NOT perform any cookie management, including storage or filtering, without the receipt of an X-Wap-Proxy-Cookie: cache, X-Wap-Proxy-Cookie: cache-has-state,X-Wap-Proxy-Cookie: session or X-Wap-Proxy-Cookie: session-has-state header from the user agent, indicating that cookie management is desired.The Cookie Proxy MUST be prepared to receive Cookie headers from the user agent, regardless of the presence of an X-Wap-Proxy-Cookie header. If this situation occurs, the Cookie Proxy MUST transmit the state present in the Cookie header to the origin server, with the following criteria:1. If a cookie proxy receives both Cookie and X-Wap-Proxy-Cookie: cache/cache-has-state or X-Wap-Proxy-Cookie: session/session-has-state headers, the Cookie Proxy may append other cookies to the Cookie header prior to performing the subsequent HTTP request. In the case where a user agent and a Cookie Proxy have an identical cookie to send, i.e. both cookies have identical values for path, domain and NAME attributes, the cookie MUST be delivered to the origin server as it is specified by the user agent. Cookies MUST be ordered in the Cookie header as specified in [RFC2109].2. If cookie proxy receives both Cookie and X-Wap-Proxy-Cookie: delete or X-Wap-Proxy-Cookie: none headers, it MUST deliver the cookie header to the origin server without interception.Cookie Proxy MUST include X-Wap-Proxy-Set-Cookie: state header in the response to the client, if it has received a cookie in the response from the origin server and chosen to manage it or it has sent a Cookie header in the associated HTTP request. . This header MUST NOT be sent if neither of the Cookie and Set-Cookie headers was present in the HTTP request and response, or if the cookie proxy has not cached any cookie information.Cookie Proxy MUST include X-Wap-Proxy-Set-Cookie: error header in the response if user agent sends status information which is conflicting with the status recorded by the Cookie Proxy. This will happen when a user agent sends a request with X-Wap-Proxy-Cookie:cache-has-state or X-Wap-Proxy-Cookie: session-has-state header, but the Cookie Proxy does not have any cookies in storage for this particular user agent.Cookie Proxy MUST NOT store the received cookie, if Set-Cookie header includes secure attribute. If secure attribute is present, Cookie Proxy MUST deliver the cookie to the client without interception. This attribute MAY be used by content authors to indicate that a specific cookie contains private or confidential information, and that the preferred storage is in the client.If a cookie proxy receives an X-Wap-Proxy-Cookie header from a client and chooses to manage and store cookies on its behalf, it MUST remove the X-Wap-Proxy-Cookie header from the request and thus prevent it from going further to the network. If Cookie Proxy chooses not to manage cookies on behalf of the client, it MUST let the headers pass without interception.9.3 Associating Cookie Storage With ClientsThe Cookie Proxy MUST associate cookies with a single client and prevent another client from gaining access to the cookies. This may be achieved by associating the cookies with an authenticated client identifier. Content authors should be advised that different user agents located in the same client may use the same Cookie Proxy facilities and the same cookie storage.The Cookie Proxy MUST NOT provide cookie proxy facilities to anonymous clients.9.4 Managing Proxy CookiesThe Cookie Proxy SHOULD provide a Web application to let the user browse and control the stored cookies.10. USER AGENT RESPONSIBILITIES10.1 HTTP State ManagementThe user agent MUST implement HTTP State Management, as specified in [RFC2109]. User agents with non-conforming implementations (i.e. no support) have undefined semantics. WAP user agents MUST be able to save and manage at least four cookies, with a maximum size of 125 bytes each (size includes fully-qualified host name, expiration date, and cookie data).10.2 Cookie Proxy ManagementSupport for use of Cookie Proxy functionality in the user agent is optional. User agent MAY include WAP Specific HTTP State Management Headers in requests to utilize Cookie Proxy facilities.If Cookie Proxy functionality is supported, end-user MUST have an opportunity to elect to use either cookie proxy facilities or their own local cookie management or both.User agent MUST send X-Wap-Proxy-Cookie: cache-has-state header instead of X-Wap-Proxy-Cookie: cache and X-Wap-Proxy-Cookie: session-has-state header instead of X-Wap-Proxy-Cookie: session in case it has received at least one X-Wap-Proxy-Set-Cookie header during the ongoing user agent session. When user agent receivesX-Wap-Proxy-Set-Cookie: error header, it MAY notify the user that inconsistent service behavior might occur. WAP user agents MUST be prepared to receive Set-Cookie HTTP headers even when they have requested Cookie Proxy functionality alone, and must act in accordance with [RFC2109] in this situation (e.g., the user agent should make a best effort attempt to manage the cookie (See section 10.2)).11. STATIC CONFORMANCE REQUIREMENTSThese static conformance requirements define a minimum set of features that must be implemented to support the WAP HTTP State Management mechanism. A feature can be optional (O), mandatory (M) or conditional (C (<condition>)). If optional/conditional features have labels (O.<n> or C.<n>), support of at least one of the group of options labeled by the same number is required.11.1 User Agent FeaturesItem Functionality Reference Status Requirement HSM-C-001 User agent support for HTTP StateManagement Mechanism10.1 MHSM-C-002 User agent support for at least fourcookies of at least 125 bytes totalstorage space.10.1 MHSM-C-003 User agent support for more than500 bytes of cookie storage space10.1 OHSM-C-004 User agent support for use ofCookie Proxy functionality10.2 OHSM-C-005 User agent support for WAPspecific HTTP State managementheaders10.2 C:HSM-C-004Item Functionality Reference Status Requirement HSM-S-001 Cookie Proxy support for passingof HTTP headers between the useragent and the origin server withoutinterference.9.1 MHSM-S-002 Cookie Proxy support for CookieManagement and Storagefunctionality. 9.2 O HSM-S-003AND HSM-S-004 ANDHSM-S-005AND HSM-S-006HSM-S-003 Cookie Proxy support for useragent role in HTTP StateManagement Mechanism.9.2 OHSM-S-004 Cookie Proxy support for WAPspecific HTTP State Managementheaders and mechanisms.9.2 OHSM-S-005 Cookie Proxy does not store thecookie if origin server includessecure attribute in Set-Cookieheader.9.2 OHSM-S-006 Cookie Proxy associates HTTPstate with a particular client, anddoes not provide cookiemanagement or storage foranonymous clients.9.3 OItem Functionality Reference Status Requirement HSM-S-007 Cookie Proxy support for WAP9.4 OHTTP State Management userinterface。
374体育
年级编号班号班级名称学籍号民族姓名性别出生日期身份证号3110P06374100281040276汉陈彩云女1995-05-17430281199505175827 3110P06374100281040313汉李梦妮女1994-11-18430281199411182049 3110P06374100281040282汉黄婷女1994-07-04430281199407044065 3110P06374100281040319汉张赛女1995-11-2943028119951129008x 3110P06374100281040315汉袁驰方男1995-01-29430281199501295311 3110P06374100281040298汉金磊男1994-04-06430281199404063316 3110P06374100281040292汉周夏女1994-05-20430281199405206040 3110P06374100281040289汉邓友园男1993-12-15430281199312154050 3110P06374100281040300汉谢璇婵女1995-12-24430281199512240025 3110P06374100281040287汉刘礼平女1995-05-03430281199505035824 3110P06374100281040304汉汤海军男1994-09-12430281199409127913 3110P06374100281040279汉李智男1996-02-08430281199602083617 3110P06374100281040302汉邓明慧女1995-10-13430281199510134667 3110P06374100281040295汉吴莉女1993-06-25430281199306259147 3110P06374100281040311汉曾涛男1994-05-143110P06374100281040274汉黎明男1995-05-12430281199505123613 3110P06374100281040314汉何远哲男1994-08-15430281199408151030 3110P06374100281040306汉张念女1996-02-12430281199602127720 3110P06374100281040305汉罗钰女1995-02-27430281199502272322 3110P06374100281040290汉陈铁龙男1994-11-11430281199411111339 3110P06374100281040294汉丁宇豪男1995-03-19430281199503199112 3110P06374100281040291汉江丹女1994-09-27430281199409274665 3110P06374100281040312汉朱琳女1995-07-09430281199507099223 3110P06374100281040317汉汤旺男1995-08-06430281199508064313 3110P06374100281040296汉刘璐女1994-12-31430281199412310022 3110P06374100281040275汉唐子雄男1995-01-09430281199501090017 3110P06374100281040004汉王志翔男1994-06-23430281199406231010 3110P06374100281040321汉罗一波男1994-10-03430281199410031011 3110P06374100281040309汉梁天添女1995-12-08430281199512081327 3110P06374100281040285汉苏子沙女1995-07-17430281199507174668 3110P06374100281040299汉李亮男1994-03-21430281199403217715 3110P06374100281040288汉胡雅怡女1995-06-133110P06374100281040307汉刘浩男1994-06-04430281199406041313 3110P06374100281040323汉黎自强男1994-10-02430281199410021016 3110P06374100281040284汉陈慧芳女1995-03-11430281199503116022 3110P06374100281040310汉田娅琪女1995-01-06430281199501061347 3110P06374100281040283汉叶鑫文女1995-01-313110P06374100281040272汉周为女1995-08-20430281199508204320 3110P06374100281040278汉朱仕豪男1995-04-16430281199504169118 3110P06374100281040308汉陈妙女1995-06-023110P06374100281040280汉林红梅女1995-03-20430281199503204065 3110P06374100281040301汉钟逸男1995-08-05430219199508051717 3110P06374100281040318汉江健男1994-11-13430281199411130011 3110P06374100281040297汉瞿优利女1994-11-183110P06374100281040281汉曾琴女1993-12-10430281199312105427 3110P06374100281040273汉彭易男1994-10-02430281199410024655 3110P06374100281040286汉吴永和男1994-10-02430281199410027370 3110P06374100281040322汉张子豪男1995-06-28430281199506281314 3110P06374100281040303汉周雨彤女1994-11-19430281199411199246 3110P06374100281040320汉吴永优男1994-08-034302811994080373503110P06374100281040316汉黄玲女1995-04-203110P06374100281040293汉邓本威男1994-06-27430281199406279110 3110P06374100281040277汉杨纬华女1995-04-17430281199504177468 3110P07375100281040335汉陆科强男1994-04-02430281199404023613 3110P07375100281040364汉瞿颖婷女1994-12-18430281199412181021 3110P07375100281040368汉潘斌男1995-09-11430281199509113017 3110P07375100281040367汉张芬玲女1995-09-13430281199509136825 3110P07375100281040328汉邹婷女1995-01-09430281199501091327 3110P07375100281040338汉陈云华女1994-10-03430281199410034669 3110P07375100281040346汉方文秀女1995-11-09430281199511095348 3110P07375100281040342汉刘驰男1995-04-25430281199504252317 3110P07375100281040361汉邓杨清芬女1995-04-05430281199504051320 3110P07375100281040333汉刘秀女1995-03-06430281199503060727 3110P07375100281040329汉匡沙女1994-03-06430281199403065627 3110P07375100281040349汉兰武平男1995-09-25430281199509257010 3110P07375100281040341汉潘婷女1994-12-18430219199412186166 3110P07375100281040357汉黄娟女1994-01-15430281199401153324 3110P07375100281040331汉陈兵男1995-08-25430281199508259153 3110P07375100281040324汉郑涛男1995-06-28430281199506289113 3110P07375100281040332汉陈丽女1994-07-07430281199407079268 3110P07375100281040351汉龙竹英女1994-11-23430281199411230725 3110P07375100281040373汉鲁旺林男1994-08-09430281199408091314 3110P07375100281040359汉陈晶瑶女1995-06-13430281199506133629 3110P07375100281040354汉吴智斌男1994-08-21430281199408219250 3110P07375100281040362汉李鹏辉男1994-11-30430281199411303613 3110P07375100281040353汉李雪男1994-12-04430281199412046014 3110P07375100281040325汉杨敏婷女1995-08-13430281199508135927 3110P07375100281040343汉兰聪林男1993-10-22430281199310226815 3110P07375100281040330汉兰静茹女1993-04-27430281199304276162 3110P07375100281040327汉巫刚沛男1995-01-13430219199501133939 3110P07375100281040365汉张思远男1995-07-2743028119950727161x 3110P07375100281040366汉丁晓倩女1996-05-29430281199605290048 3110P07375100281040360汉钟佳琳女1995-06-06430281199506069225 3110P07375100281040369汉蒋琪男1994-10-12430281199410121316 3110P07375100281040347汉吕昶怡女1995-10-07430281199510071029 3110P07375100281040356汉易桂平女1995-11-03430281199511030720 3110P07375100281040337汉段毅男1995-12-11430224199512115518 3110P07375100281040340汉宋蓓女1993-11-09430281199311095423 3110P07375100281040358汉易伟琪男1995-01-0143028119950101003x 3110P07375100281040334汉朱兴文男1995-05-11430281199505117352 3110P07375100281040363汉兰志勇男1995-01-16430281199501164653 3110P07375100281040348汉周宏男1993-04-043110P07375100281040376汉万锦弘男1994-09-23430281199409232334 3110P07375100281040326汉黄丽佳女1995-04-02430281199504022722 3110P07375100281040345汉易洪女1995-10-04362201199510043425 3110P07375100281040352汉张权男1995-08-10430281199508100011 3110P07375100281040339汉黄瑞芳女1994-11-20430281199411205829 3110P07375100281040355汉黄洁华女1995-07-26430281199507262326 3110P07375100281040350汉陈丹女1995-11-26430281199511263620 3110P07375100281040344汉吴富童男1994-10-2943028119941029361x 3110P07375100281040336汉宋雅玲女1994-11-134302811994111313213110P07375100281040375汉张维男1995-02-07430281199502073315 3110P07375100281040374汉谢浩男1995-06-23430281199506230031 3110P07375100281040371汉周宇阳男1994-08-01430281199408011310 3110P07375100281040370汉何恬恬女1995-06-03430281199506032326 3110P07375100281040372汉梁潇女1995-05-20430281199505201327 3110P08376100281040392汉林旖旎女1995-04-22430281199504227728 3110P08376100281040425汉刘三亚男1994-09-07430281199409079114 3110P08376100281040406汉王宇豪男1994-03-283110P08376100281040418汉文强男1994-07-08430281199407080015 3110P08376100281040399汉黎珂男1995-01-05430281199501056011 3110P08376100281040420汉张可男1995-03-303110P08376100281040387汉帅小满女1995-04-1243028119950412602X 3110P08376100281040378汉张才勇男1993-03-263110P08376100281040384汉王洁纯女1996-01-22430281199601220026 3110P08376100281040381汉刘子豪男1995-07-073110P08376100281040410汉潘裕婷女1995-04-29430281199504299123 3110P08376100281040395汉李志勇男1994-12-03430281199412030055 3110P08376100281040417汉谭由芝女1995-09-0243022419950902392x 3110P08376100281040383汉杨鹏男1996-02-12430281199602129216 3110P08376100281040404汉张敏超男1995-10-20430281199510200759 3110P08376100281040427汉邹佳威男1995-05-25430281199505252319 3110P08376100281040390汉吴禹其女1995-04-3043028119950430202X 3110P08376100281040403汉李铭武男1993-05-0543028119930505465X 3110P08376100281040397汉徐利娟女1995-05-11430281199505117467 3110P08376100281040408汉胡巧莉女1995-03-20430281199503201323 3110P08376100281040419汉邓洋男1995-01-113110P08376100281040393汉林婉女1995-01-13430281199501139183 3110P08376100281040944汉黄昊媛女1996-12-15430281199612151628 3110P08376100281040421汉邹淳男1995-09-17430281199509172316 3110P08376100281040424汉张琦男1993-11-19430281199311191335 3110P08376100281040396汉黄晚晴女1994-05-15430281199405153321 3110P08376100281040389汉李雁瓷女1995-08-07430281199508077923 3110P08376100281040398汉邹志豪男1995-06-26430281199506267555 3110P08376100281040407汉易娟女1994-03-293110P08376100281040422汉张志豪男1995-03-01430281199503013955 3110P08376100281040401汉陈婉婷女1995-10-25430281199510256023 3110P08376100281040416汉樊玉群女1994-05-21430281199405217364 3110P08376100281040413汉凌巧女1994-11-27430281199411277566 3110P08376100281040409汉杨磊男1994-11-02430281199411020031 3110P08376100281040405汉黄凌颖女1995-09-03430281199509031329 3110P08376100281040377汉廖紫薇女1995-01-25430281199501254667 3110P08376100281040382汉袁柳丹女1995-02-0343028119950203616X 3110P08376100281040423汉丁雨晴女1994-05-1243028119940512132X 3110P08376100281040394汉谢彪男1994-06-29430281199406297714 3110P08376100281040400汉肖婷女1994-07-05430281199407050027 3110P08376100281040428汉谢俊豪男1995-07-05430281199507051035 3110P08376100281040379汉蒋龙男1995-04-05430281199504057351 3110P08376100281040411汉易婷女1995-11-09430281199511095321 3110P08376100281040402汉唐斌女1995-05-05430281199505055729 3110P08376100281040415汉谭亚敏女1995-11-21430281199511211329 3110P08376100281040385汉汤细华男1995-10-114302811995101179123110P08376100281040388汉肖欢女1995-04-08430281199504087729 3110P08376100281040414汉文国庆男1995-10-01430281199510015617 3110P08376100281040380汉胡丰明女1994-11-05430281199411051022 3110P08376100281040386汉周金鑫女1996-10-07430281199610070322 3110P08376100281040426汉徐杨宇男1995-01-17430281199501171319 3110P08376100281040391汉兰阳男1994-06-24430281199406247012 3110P08376100281040412汉夏敏男1995-01-14430281199501147714 3110P09377100281040476汉熊浩男1996-01-253110P09377100281040462汉易璐男1995-08-203110P09377100281040459汉刘力男1994-08-123110P09377100281040441汉康芳女1995-03-153110P09377100281040467汉王茜女1996-01-233110P09377100281040468汉晏得亲女1995-02-243110P09377100281040455汉张柳女1995-01-253110P09377100281040456汉吴自维男1993-01-203110P09377100281040464汉李维进男1995-01-233110P09377100281040451汉江峰男1996-03-293110P09377100281040431汉付磊男1995-07-013110P09377100281040457汉王钰莹女1995-02-133110P09377100281040461汉杨紫依女1995-05-203110P09377100281040447汉汤倩怡女1995-02-213110P09377100281040445汉陈丽女1996-01-103110P09377100281040471汉晏赛女1995-08-013110P09377100281040458汉张丽珍女1905-06-173110P09377100281040463汉杨婷女1995-06-243110P09377100281040437汉王英女1994-04-10430281199404107462 3110P09377100281040473汉陈利恒女1994-12-023110P09377100281040446汉唐志武男1995-07-113110P09377100281040466汉贺钱锋男1995-06-143110P09377100281040440汉吴淼女1995-06-163110P09377100281040472汉周炜龙男1995-07-213110P09377100281040460汉张文女1994-10-123110P09377100281040477汉周慧女1994-10-073110P09377100281040439汉邓晓寒女1994-12-25430281199412250023 3110P09377100281040430汉李衡男1995-04-04430281199504047751 3110P09377100281040448汉陈端喜男1995-09-213110P09377100281040469汉张师与女1994-09-153110P09377100281040436汉陈小青女1994-02-26430281199402263621 3110P09377100281040481汉岳俊良男1994-10-083110P09377100281040432汉王怡武男1995-05-063110P09377100281040442汉潘鸿麒男1994-12-22430281199412224693 3110P09377100281040443汉李亚敏女1995-08-173110P09377100281040454汉张丽波女1994-08-093110P09377100281040475汉李思怡女1994-12-213110P09377100281040444汉汤金娇女1995-11-21430219199511217925 3110P09377100281040434汉江雨莎女1996-04-08430281199604085325 3110P09377100281040452汉刘涛男1995-07-043110P09377100281040480汉张灏男1994-10-13430281199410132314 3110P09377100281040453汉付益玲女1994-02-233110P09377100281040479汉张龙雨男1994-07-17430281199407171312 3110P09377100281040470汉黄顺男1996-08-064302811996080679173110P09377100281040465汉易志超男1996-03-223110P09377100281040429汉汤婷女1995-04-033110P09377100281040474汉邹嘉意女1995-03-2343028119950323132x 3110P09377100281040478汉江华钦男1994-11-123110P09377100281040438汉刘宇明男1993-05-17430281199305173333 3110P09377100281040433汉唐芳女1994-10-053110P09377100281040435汉丁银桥男1995-04-01430281199504014052 3110P09377100281040449汉李江女1992-06-103110P09377100281040450汉张婉婷女1995-09-063110P10378100281040533汉杨天一男1995-05-26430281199505262330 3110P10378100281040532汉彭源盛男1995-02-2343028119950223131x 3110P10378100281040514汉张雅女1996-07-3043028119960730794x 3110P10378100281040529汉肖慧惠女1994-10-09430281199410091364 3110P10378100281040527汉杨瀚波男1994-11-01430281199411011311 3110P10378100281040489汉赖周强男1994-10-30430281199410304059 3110P10378100281040518汉吴龙男1993-11-1243028119931112161x 3110P10378100281040502汉骆晋宇男1994-12-11430281199412112018 3110P10378100281040483汉罗丰武男1994-07-14430281199407147718 3110P10378100281040498汉荣雾女1994-11-21430281199411214063 3110P10378100281040511汉汤九五女1995-08-273110P10378100281040512汉易金成男1995-08-19430281199508190715 3110P10378100281040522汉周思宇女1996-01-24430281199601242022 3110P10378100281040517汉游迪生男1995-01-21430281199501213638 3110P10378100281040497汉唐雅女1996-06-27430281199606274664 3110P10378100281040484汉凌宏男1994-12-03430281199412034056 3110P10378100281040513汉瞿珊珊女1993-06-0243028119930602740x 3110P10378100281040494汉易思女1995-07-20430281199507207722 3110P10378100281040519汉王彪男1995-04-043110P10378100281040504汉丁滔男1994-10-20430281199410202714 3110P10378100281040488汉袁志沙女1995-10-14430281199510147927 3110P10378100281040482汉黄宇玲女1995-08-01430281199508012724 3110P10378100281040500汉朱琳芳女1995-12-05430281199512054660 3110P10378100281040486汉张佳女1995-05-03430281199505031583 3110P10378100281040520汉彭慧敏女1994-10-16430281199410160040 3110P10378100281040531汉黄明江男1994-05-04430281199405044651 3110P10378100281040516汉刘婷女1996-10-233110P10378100281040526汉邹琬婷女1995-08-1143028119950811232x 3110P10378100281040485汉荣宇豪男1995-08-04430281199508040039 3110P10378100281040487汉李练男1995-05-25430281199505253610 3110P10378100281040515汉张旺男1995-08-013110P10378100281040490汉兰雨芝女1995-11-22430281199511227400 3110P10378100281040528汉贺中麟男1994-09-16430281199409161337 3110P10378100281040503汉李维久男1994-07-24430281199407247735 3110P10378100281040507汉张白露女1994-08-03430281199408030028 3110P10378100281040501汉汤迁女1995-08-26430281199508269124 3110P10378100281040492汉易清女1994-11-27430281199411277742 3110P10378100281040530汉黄轩男1994-07-16430281199407160330 3110P10378100281040506汉蒋响玲女1992-07-11430281199207119229 3110P10378100281040524汉邓明女1994-09-23430281199409237960 3110P10378100281040495汉洪利辉女1995-03-19430281199503195824 3110P10378100281040491汉易芳女1994-10-023603121994100220213110P10378100281040525汉易益鹏男1995-01-02430281199501024810 3110P10378100281040508汉唐灏男1994-05-193110P10378100281040499汉周翔男1995-11-12430281199511120056 3110P10378100281040496汉李孟男1995-07-11430281199507117735 3110P10378100281040523汉文振宇男1995-04-12430281199504125617 3110P10378100281040509汉李自粮男1995-09-0243028119950902601x 3110P10378100281040534汉刘志成男1995-07-13430281199507132310 3110P10378100281040493汉张天乐女1995-12-26430281199512262021 3110P10378100281040521汉杨娟女1994-08-09430281199408097927 3110P10378100281040505汉李春燕女1995-02-23430281199502234326 3110P10378100281040510汉杨迷女1994-08-26430281199408265820 3110P11379100281040543汉张新旺男1995-12-09430281199512090012 3110P11379100281040541汉钟琰女1995-02-23430281199502234684 3110P11379100281040568汉张婷女1995-10-08430281199510085324 3110P11379100281040555汉黄昌启男1995-01-02430281199501022719 3110P11379100281040561汉汤婉女1995-12-05430281199512057925 3110P11379100281040573汉张湘都女1993-08-1143028119930811534x 3110P11379100281040583汉李家晰男1994-08-1843028119940818131x 3110P11379100281040565汉温柔女1995-08-13430219199508133309 3110P11379100281040580汉彭增伟男1995-02-02430281199502023318 3110P11379100281040577汉黄庆宇男1995-05-02430281199505020016 3110P11379100281040558汉刘彩霞女1994-11-29430281199411290728 3110P11379100281040556汉林君娴女1996-04-05430281199604053622 3110P11379100281040535汉朱志强男1994-07-17430281199407170010 3110P11379100281040581汉殷小东男1995-02-073110P11379100281040559汉张林根男1993-09-08430281199309083917 3110P11379100281040544汉荣东男1994-06-06430281199406064056 3110P11379100281040546汉刘亚女1994-12-1643028119941216466x 3110P11379100281040586汉叶凯男1994-07-2343028119940723423x 3110P11379100281040537汉阙巧红女1995-11-10430281199511107927 3110P11379100281040566汉邓友情女1995-07-29430281199507292728 3110P11379100281040539汉陈俐女1996-01-29430281199601290024 3110P11379100281040562汉李惠女1994-11-22430281199411224069 3110P11379100281040538汉李锤男1996-05-02430281199605029210 3110P11379100281040579汉杨妮女1994-10-29430281199410299149 3110P11379100281040585汉汤子豪男1995-02-12430281199502120011 3110P11379100281040584汉张敏女1995-02-04430281199502041321 3110P11379100281040569汉熊希女1995-06-23430281199506239247 3110P11379100281040578汉贺智文女1995-05-14430281199505140026 3110P11379100281040563汉邓奇男1994-06-07430281199406073331 3110P11379100281040557汉易琼伶女1995-01-1043028119950110102x 3110P11379100281040576汉周怡君女1995-02-07430281199502072021 3110P11379100281040551汉王娟女1995-09-02430281199509022326 3110P11379100281040560汉郭志维男1995-06-03430281199506033011 3110P11379100281040572汉谢露罗华女1995-08-1743028119950817132x 3110P11379100281040570汉罗威男1996-02-14430903199602140617 3110P11379100281040542汉张潇妮女1995-08-22430281199508226845 3110P11379100281040536汉汪丹女1994-01-03430281199401033322 3110P11379100281040587汉徐雅琴女1995-07-013110P11379100281040567汉彭建男1994-06-24430281199406249034 3110P11379100281040571汉卜亚根女1992-07-014302811992070177403110P11379100281040575汉肖岳斌男1995-08-20430281199508201314 3110P11379100281040548汉刘文琴女1995-09-16430281199509164324 3110P11379100281040553汉付添凤女1995-04-113110P11379100281040547汉李正金男1994-11-12430281199411123612 3110P11379100281040564汉李韬男1994-07-20430281199407202318 3110P11379100281040554汉杨君男1995-04-1143028119950411503x 3110P11379100281040550汉黄市庆男1995-05-05430281199505050012 3110P11379100281040540汉李奇男1994-02-10430281199402107012 3110P11379100281040582汉杨海宇女1995-05-1043028119950510202x 3110P11379100281040545汉蒋文慧女1994-07-27430281199407276165 3110P11379100281040574汉杨海波男1994-09-25430281199409259238 3110P11379100281040549汉孔秋香女1995-08-19430281199508193625 3110P11379100281040552汉陈琴女1994-11-22430281199411223648 3110P12380100281040624汉吴旭女1995-11-18430281199511187381 3110P12380100281040614汉林森男1995-07-06430281199507063618 3110P12380100281040622汉刘雅婷女1995-04-25430281199504251023 3110P12380100281040619汉周文男1994-10-02430281199410029034 3110P12380100281040616汉刘天宇男1995-07-18430281199507181016 3110P12380100281040594汉余广女1996-03-05430281199603056522 3110P12380100281040629汉丁宇骁男1995-06-03430281199506031315 3110P12380100281040609汉黎政文男1994-11-21430281199411214311 3110P12380100281040630汉宋艺女1994-09-29430281199409290024 3110P12380100281040635汉龚飞龙男1995-05-29430281199505291019 3110P12380100281040591汉文佳俊男1995-07-27430281199507273017 3110P12380100281040608汉熊厚芳女1996-02-24431002199602245027 3110P12380100281040607汉张翔女1995-09-10430281199509100021 3110P12380100281040620汉江英杰男1996-03-14430281199603146819 3110P12380100281040589汉甘海丽女1994-05-20430281199405207721 3110P12380100281040612汉田园女1995-06-2743028119950627072x 3110P12380100281040592汉廖婷女1995-07-11430281199507113320 3110P12380100281040615汉李响女1993-12-06430281199312067723 3110P12380100281040636汉曾思文男1994-05-25430281199405252039 3110P12380100281040640汉丁盛男1994-06-17430281199406171310 3110P12380100281040606汉谢那英女1994-09-12430281199409123680 3110P12380100281040638汉杨景女1995-02-08430281199502081323 3110P12380100281040628汉邱礼毅男1994-08-08430281199408082012 3110P12380100281040632汉刘诗瑶女1995-07-28430281199507284189 3110P12380100281040639汉黄源女1994-09-17430281199409171340 3110P12380100281040625汉丁旺男1995-03-12430281199503124655 3110P12380100281040618汉荣昊男1995-05-30430281199505302312 3110P12380100281040596汉李桔华女1994-08-28430281199408283623 3110P12380100281040595汉黄纯女1994-09-13430281199409134662 3110P12380100281040603汉刘瑶女1995-01-173110P12380100281040634汉刘雍男1995-04-29430281199504291316 3110P12380100281040641汉黎青花女1994-11-25500101199411257144 3110P12380100281040588汉罗天龙男1995-06-29430281199506296153 3110P12380100281040627汉宋荣华男1995-05-02430281199505029213 3110P12380100281040601汉钟国洪男1994-12-27430281199412279133 3110P12380100281040605汉王诚男1994-06-273110P12380100281040610汉刘顺女1996-08-20430281199608207924 3110P12380100281040593汉昌建伟男1995-03-234302811995032358143110P12380100281040637汉唐芳女1994-04-12430221199404125621 3110P12380100281040617汉吴雅文女1995-08-23430281199508237763 3110P12380100281040597汉黄家豪男1994-05-303110P12380100281040613汉刘三柳女1995-03-03430281199503032726 3110P12380100281040602汉陈水兵女1995-09-0643028119950906362x 3110P12380100281040633汉黄政男1995-03-09430281199503091339 3110P12380100281040626汉刘雅琪女1995-08-26430281199508266628 3110P12380100281040623汉凌洁女1995-05-08430281199505080043 3110P12380100281040590汉曹鑫女1994-12-24430281199412242023 3110P12380100281040621汉张雅文女1995-08-26430281199508263021 3110P12380100281040604汉钟蝉女1995-08-07430281199508074327 3110P12380100281040631汉赖敏男1994-11-18430281199411184650 3110P12380100281040598汉黄沁女1995-01-15430281199501153620 3110P12380100281040611汉欧阳威男1995-07-15430281199507159134 3110P12380100281040599汉匡鹏男1995-01-03430281199501031316 3110P12380100281040600汉陈云男1995-02-25430281199502256015 3110P13381100281040683汉黄仕豪男1993-09-05430281199309050031 3110P13381100281040671汉陈思颖男1996-01-06430281199601065919 3110P13381100281040649汉管群女1995-05-2043028119950520072x 3110P13381100281040661汉赵宇萌男1995-11-29430281199511291314 3110P13381100281040670汉刘苏其女1993-06-18430281199306184325 3110P13381100281040679汉朱玲英女1994-07-283110P13381100281040690汉吴昕女1995-07-25430281199507259143 3110P13381100281040645汉付都女1994-09-03430281199409036667 3110P13381100281040681汉黎莎女1996-06-26430281199606265821 3110P13381100281040665汉李钰婷女1995-10-24430281199510247725 3110P13381100281040692汉柳思琪女1994-08-31430281199408311321 3110P13381100281040651汉陈雨香女1995-03-0343028119950303772x 3110P13381100281040674汉兰柳女1994-01-2943028119940129002x 3110P13381100281040642汉黄晓男1994-01-12430281199401129017 3110P13381100281040658汉肖娅女1995-08-17430281199508170044 3110P13381100281040652汉刘子铭男1995-06-23430281199506230058 3110P13381100281040673汉易优女1993-06-19430281199306197388 3110P13381100281040685汉罗龙雪男1995-01-11430281199501111017 3110P13381100281040660汉林露女1995-09-12430281199509127742 3110P13381100281040656汉兰张洋男1995-09-08430281199509081035 3110P13381100281040657汉陈程女1994-09-3043028119940930756x 3110P13381100281040672汉郑鹏男1995-05-31430281199505311016 3110P13381100281040006汉唐汝珩男1993-09-2443028119930924133X 3110P13381100281040643汉谢薇女1995-05-20430281199505203023 3110P13381100281040655汉张茜女1995-08-13430281199508133921 3110P13381100281040650汉李汪洋男1994-10-05430281199410054512 3110P13381100281040648汉蔡安女1996-04-06430281199604063644 3110P13381100281040667汉杨许斌女1994-11-03430281199411037466 3110P13381100281040688汉肖晨男1995-11-15430281199511151012 3110P13381100281040668汉易兵男1992-10-14430281199210147378 3110P13381100281040659汉黄李林女1995-08-03430281199508030041 3110P13381100281040680汉李璐男1995-08-053110P13381100281040662汉张洋男1995-04-27430281199504274655 3110P13381100281040647汉苏道军男1994-12-15430281199412150313 3110P13381100281040666汉刘晋男1995-06-044302811995060478193110P13381100281040669汉李志红女1995-10-20430281199510207723 3110P13381100281040678汉何莉女1994-08-263110P13381100281040664汉刘煜荣女1994-09-20430281199409202047 3110P13381100281040646汉张礼成男1994-04-22430281199404224650 3110P13381100281040676汉肖仁清男1994-08-02430281199408021316 3110P13381100281040654汉丁强男1995-03-21430281199503213017 3110P13381100281040684汉漆莹洁女1996-08-20430281199608200327 3110P13381100281040943汉邓逸琪男1994-11-09430281199411097717 3110P13381100281040677汉罗莎女1994-12-233110P13381100281040002汉兰宗裕男1993-10-17430281199310170014 3110P13381100281040689汉邓兴国男1995-03-26430281199503261318 3110P13381100281040682汉李堂男1995-08-113110P13381100281040675汉刘旭男1994-08-17430281199408173037 3110P13381100281040687汉朱婷女1994-11-29430281199411297380 3110P13381100281040686汉罗顺女1996-01-19430281199601194526 3110P13381100281040653汉张欢女1996-02-02430281199602025329 3110P13381100281040644汉刘新婉女1996-06-07430281199606070020 3110P13381100281040691汉匡世杰男1995-04-1143028119950411001x 3110P13381100281040663汉李拼女1995-09-15430281199509157466 3110P14382100281040726汉吴思女1995-06-26430281199506267360 3110P14382100281040741汉曾乐女1994-09-29430624199409297327 3110P14382100281040746汉朱新理男1994-07-28430281199407281351 3110P14382100281040711汉易林英女1995-10-11430281199510117963 3110P14382100281040696汉戴玉宁女1995-08-06430281199508062721 3110P14382100281040719汉谭海洋男1994-10-17430281199410174813 3110P14382100281040733汉陈敏男1994-11-2143028119941121571x 3110P14382100281040724汉黄园女1994-01-12430281199401127724 3110P14382100281040734汉张翔男1995-06-053110P14382100281040707汉钟林香女1993-11-17430281199311179221 3110P14382100281040727汉唐婷女1995-07-09430281199507095425 3110P14382100281040712汉陈容女1995-08-19430281199508195647 3110P14382100281040725汉廖志强男1995-06-13430281199506137451 3110P14382100281040706汉冯柱男1996-01-24430281199601243017 3110P14382100281040716汉沈贤娟女1995-01-14430281199501142729 3110P14382100281040699汉丁莎莎女1995-06-08430281199506084062 3110P14382100281040729汉黄凤姣女1994-06-27430281199406276024 3110P14382100281040704汉易鑫男1995-08-19430281199508194652 3110P14382100281040728汉刘超男1995-03-19430281199503192316 3110P14382100281040731汉曾雪女1994-09-25430521199409252888 3110P14382100281040715汉李珊女1993-10-06430281199310067869 3110P14382100281040730汉骆益红女1994-08-2943028119940829236x 3110P14382100281040732汉易勇男1995-08-2643028119950826071x 3110P14382100281040709汉胡子琴女1995-08-16430281199508169123 3110P14382100281040745汉周维明男1994-10-11430281199410117376 3110P14382100281040700汉邓斌男1995-05-15430281199505152318 3110P14382100281040708汉彭柳女1995-11-22430281199511229123 3110P14382100281040701汉吴丽莹女1995-08-17430281199508173624 3110P14382100281040713汉王幸红男1995-06-04430281199506049216 3110P14382100281040698汉刘胜强男1994-08-22430281199408225714 3110P14382100281040705汉易悠悠女1995-09-29430281199509290726 3110P14382100281040744汉李志男1995-05-284302811995052833183110P14382100281040737汉贺兴男1994-08-30430281199408301318 3110P14382100281040722汉李宇峰男1995-08-13430281199508134676 3110P14382100281040695汉李南英女1995-06-04430281199506043623 3110P14382100281040742汉吴子岑女1994-08-30430219199408301029 3110P14382100281040694汉黎望男1995-07-1043028119950710431x 3110P14382100281040740汉周锋男1994-05-02430281199405027376 3110P14382100281040710汉谢栋男1994-12-23430281199412231316 3110P14382100281040718汉汤鹏男1995-03-19430281199503194311 3110P14382100281040702汉张玉女1994-10-12430281199410126045 3110P14382100281040721汉张琳女1994-06-10430281199406104521 3110P14382100281040736汉邓慧女1995-10-09430281199510091329 3110P14382100281040714汉刘勇男1994-04-27430281199404272716 3110P14382100281040720汉张立女1996-07-16430281199607163325 3110P14382100281040723汉彭涛男1996-01-23430281199601239114 3110P14382100281040697汉刘理平男1994-07-03430281199407037551 3110P14382100281040717汉易雨柔女1994-08-30430281199408300024 3110P14382100281040743汉黄敏女1995-07-31430281199507314528 3110P14382100281040735汉吴丹女1994-12-09430281199412091026 3110P14382100281040703汉刘滔女1993-03-163110P14382100281040739汉张佳琲男1994-08-22430281199408221019 3110P14382100281040738汉汤洋女1995-05-06430281199505061643 3110P15383100281040780汉易春男1995-05-2343028119950523361X 3110P15383100281040755汉温子良男1995-08-08430281199508086619 3110P15383100281040787汉邓婷女1994-08-1843028119940818916X 3110P15383100281040779汉吴谢婷女1995-02-05430281199502057366 3110P15383100281040781汉易红霞女1995-03-153110P15383100281040784汉欧阳晓晴女1994-11-18430281199411185928 3110P15383100281040751汉凌宇女1995-08-04430281199508045622 3110P15383100281040783汉张骁虬男1995-08-07430281199508070035 3110P15383100281040782汉潘益民男1995-09-033110P15383100281040762汉柳敏女1995-10-03430281199510037461 3110P15383100281040768汉许智涛男1994-06-06430281199406061314 3110P15383100281040759汉谢露女1995-08-14430281199508143644 3110P15383100281040770汉易双女1994-03-01430281199403013923 3110P15383100281040788汉曾繁煜男1994-08-04430281199408043312 3110P15383100281040773汉吴惠敏女1995-01-2243028119950122736X 3110P15383100281040790汉钟任兵男1994-11-07430281199411075112 3110P15383100281040786汉孙学琴女1994-02-12500228199402125065 3110P15383100281040758汉邬梦秋女1994-07-06362202199407064021 3110P15383100281040795汉刘顺男1995-01-06430281199501063019 3110P15383100281040003汉钟羽轩男1994-02-13430281199402131311 3110P15383100281040774汉甘妙男1995-05-0243028119950502771X 3110P15383100281040775汉钟梓钰女1996-02-01430281199602012325 3110P15383100281040750汉潘志雄男1995-11-10430281199511107038 3110P15383100281040769汉李孝许男1994-05-25430281199405253613 3110P15383100281040756汉喻娟女1995-01-14430281199501140029 3110P15383100281040765汉郭鹏飞女1995-10-2743028119951027466X 3110P15383100281040753汉张强男1995-03-1143028119950311465X 3110P15383100281040761汉李勇男1996-01-14430281199601142718 3110P15383100281040748汉张雅玉女1996-01-0943021919960109616X 3110P15383100281040789汉余敏女1995-05-154302811995051553243110P15383100281040796汉吴驰男1995-02-28430281199502287399 3110P15383100281040749汉陈登男1996-03-01430281199603017750 3110P15383100281040793汉刘鹏琳男1994-08-20360313199408200331 3110P15383100281040763汉张美林女1994-03-26430281199403264060 3110P15383100281040777汉李威明男1995-08-14430281199508142713 3110P15383100281040797汉殷志成男1995-01-25430281199501251319 3110P15383100281040757汉柳英女1996-01-22430281199601224668 3110P15383100281040791汉张羽健女1994-12-18430281199412181320 3110P15383100281040792汉刘飞宇男1994-06-1143028119940611771X 3110P15383100281040767汉刘检男1994-11-17430281199411177717 3110P15383100281040747汉吴锐女1996-02-25430281199602259168 3110P15383100281040752汉陈汝婷女1996-02-21430281199602213629 3110P15383100281040776汉李云珑女1995-02-11430281199502110323 3110P15383100281040760汉侯蓓女1994-11-22430281199411227024 3110P15383100281040754汉李志辉女1994-11-19430281199411194066 3110P15383100281040764汉周威男1994-01-07432503199401077471 3110P15383100281040778汉陈雅琪女1995-07-22430281199507224661 3110P15383100281040794汉丁维男1995-12-24430281199512244050 3110P15383100281040785汉漆子毅男1995-07-1443028119950714133X 3110P15383100281040772汉王玺芳女1995-09-083110P15383100281040766汉汤子峰男1996-04-07430281199604077915 3110P15383100281040771汉陈威男1995-06-02430281199506020018 3110P15383100281040798汉叶雨男1993-08-01430281199308017352 3110P16384100281040839汉黄溪坤男1995-05-26430281199505261610 3110P16384100281040822汉陈莎女1995-05-17430281199505174525 3110P16384100281040835汉曾慧女1995-06-28430281199506289121 3110P16384100281040851汉陈治湘男1994-08-1243028119940812231x 3110P16384100281040830汉文玉霜女1994-07-09430281199407095620 3110P16384100281040814汉钟领女1995-02-01430281199502019220 3110P16384100281040799汉钟磊男1995-03-25430281199503252710 3110P16384100281040832汉钟韶明女1994-08-14430281199408145845 3110P16384100281040834汉宋君男1994-09-03430281199409031014 3110P16384100281040810汉张萍女1994-11-22430281199411223621 3110P16384100281040829汉文鹏程男1994-10-163110P16384100281040820汉李宇成男1994-08-19430281199408191315 3110P16384100281040837汉朱婉琴女1995-11-25430281199511252323 3110P16384100281040800汉徐旭女1995-06-20430281199506207923 3110P16384100281040821汉黄鑫成男1995-03-05430281199503059216 3110P16384100281040808汉张剑男1994-07-09362204199407095111 3110P16384100281040850汉李俊辰男1994-07-21430281199407210035 3110P16384100281040805汉汤慧娟女1996-06-1043028119960610792x 3110P16384100281040818汉郭婷女1995-02-0443028119950204272x 3110P16384100281040843汉吴莎女1995-01-29430281199501297384 3110P16384100281040844汉吴兴新男1995-01-16430281199501163634 3110P16384100281040846汉唐玉蓉女1995-12-10430281199512101324 3110P16384100281040841汉张志豪男1995-09-27430281199509272018 3110P16384100281040852汉赖响男1994-09-24430281199409247915 3110P16384100281040806汉吴峥女1995-10-2843028119951028362x 3110P16384100281040809汉黎云男1996-12-03360313199612031037 3110P16384100281040847汉郭远鹏男1995-02-07430281199502072312 3110P16384100281040804汉吴密男1994-06-06。
Z80180中文资料(zilog)中文数据手册「EasyDatasheet - 矽搜」
芯片中文手册,看全文,戳
Z8018x
家庭MPU
用户手册
UM005001-ZMP0400
芯片中文手册,看全文,戳
Z8018x 系 列 MPU用 户 手 册
本出版物受置换以后版本.要确定是否以后版本
文档免责声明 应用程序,或技术描述意在暗示可能用途,并且可以被替代. ZILOG, INC.不承担责任或提供精度表示 资料,设备或技术描述这份文件 .
直流特性
介绍直流参数,绝对最大额定值为 Z8X180微处理器. AC特征 介绍交流参数Z8018x主控板.
时序图
包含时序图和标准测试条件为Z8018x MPUs.
SA5888
ѻક SA5888
ᇕ㺙 HSOP-28-375-0.8
* DVD
ݙ䚼Ḛ
众 市
圳
深
MUTE +-
NC NC TRB_2 VINLD +GND VCTL VOLDVOLD+ VOTKVOTK+
++-
+REGO1 REGO2 VINSL+ VOTRVOTR+ VCC REV FWD VOSL+ VOSLVOFCVOFC+
公 HSOP-28-375-0.8
* 㢃⠛ݙ㕂⬉ᑇ䕀ᤶ⬉䏃DŽ * ݙ㕂䖛⛁ֱᡸ⬉䏃DŽ
限
* ݙ㕂䴭ా⬉䏃DŽ
有 * ݙ㕂ϸϾ〇य़ࠊ⬉䏃DŽ 技 * ݙ㕂ѨϾ偅ࡼ఼˖ϸϾ▔ࢅ偅ࡼ఼ˈϔϾ㺙䕑偅ࡼ఼ˈ
ѻક㾘Ḑߚ㉏
ϔϾЏ䕈偅ࡼ఼ϔϾⲬܝ䖯ߎ偅ࡼ఼DŽ
科
ᑨ⫼
* CD * CD-ROM
安 达
°C
䌂ᄬ⏽ᑺ
Tstg
-55~+150
°C
司 ⊼˖ᔧᅝ㺙⦏⩗㑸㓈ᑩᵓ˄䴶鳥Ў70mm x 70mmˈ८ᑺ1.6 mm˅ˈTamb >25°Cᯊˈ↣Ϟछϔᑺ 公 ֓Ӯޣᇥ13.6 mWDŽ
⬉⇨খ᭄
限
有 (䰸䴲⡍߿ᣛᯢˈTamb=25°CˈVCC=8VˈPVCC = 5VˈBIAS=2.5VˈRL=8Ω/10Ω/20Ω/45Ω)
共９页 第７页
电话：（０７５５）２７８５８６６７ ２７８５８６６１ 传真：（０７５５）２７８５８７０７
深
圳
市
众
达
安
科
ൟᑨ⫼⬉䏃
技
有
限
公
司
FQP8N80C中文资料
FQP8N80C/FQPF8N80C
FQP8N80C/FQPF8N80C
800V N-Channel MOSFET
QFET TM
General Description
These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switch mode power supplies.
Features
• 8A, 800V, RDS(on) = 1.55Ω @VGS = 10 V • Low gate charge ( typical 35 nC) • Low Crss ( typical 13 pF) • Fast switching • 100% avalanche tested • Improved dv/dt capability
td(off)
Turn-Off Delay Time
tf
Turn-Off Fall Time
Qg
用户手册
dopod C858 用户手册2006.12多普达通讯有限公司敬告：在操作本机之前请阅读下述内容在提示不能使用手机的场合，如医院、飞机机舱内、加油站、怕无线干扰的地方，请您关闭本设备！在飞机上除了打开飞行模式外，请关闭整个设备的电源。
插入SIM 卡时请确保外接电源已经断开，且SIM 卡放置到位。
第一次充电请充满8小时。
在充电的过程中，请不要从手机上取下电池，以防损伤设备。
本机型不具有防水功能，请您注意防水，保持手机的干燥。
如果自行打开或者损伤外壳将不再享受保修服务。
请使用由多普达公司指定的附件和认可的第三方软件,否则如果设备出现问题多普达公司将不承担任何责任。
请注意保护好手机屏幕，防止磨损或挤伤。
此类损伤均被认为是人为损坏。
请及时备份数据！多普达公司不承担因产品故障导致信息丢失而造成的一切直接或间接损失。
尤其在更换电池前更加需要备份数据。
本设备中包含有一个锂电池电池。
如果电池处理不当，将会有着火和燃烧的危险。
不要分解、挤压、刺穿电池，不要短路电池外部的接头，更不要将其投入火中或者水中。
不要试图打开或者维修该电池，只能使用产品指定的电池来进行更换。
请正确处理电池不要随意丢弃。
由于软件版本更新而造成界面和功能变更，恕不另行通知。
友情提示：亲爱的用户，由于多普达智能手机内含一套完整的电脑系统，类似于个人电脑的系统架构和运行规则。
1.充足的系统内存，将有助于手机良好高效的运行，所以建议您每天至少重新启动手机一次，以彻底清空内存，恢复系统至最佳状态。
2.请正确合理地使用您的手机内存，建议您不要同时运行过多的程序，否则将使手机运行速度变慢。
如发生此类情况，建议您重新启动手机，即可恢复如初。
注意：对于预装或捆绑于本机中的任何游戏、应用程序包括相应文件（以下简称软件），或通过本机取得的视听资料、内容、服务以及相关文件资料，包括但不限于任何图像、照片、动画、录像、录音、音乐、文字，（以下简称服务）皆由相应软件/服务提供商（以下简称提供商）负责其合法、真实和准确，并由提供商保证不违反国家法律、法规、公共道德及侵犯任何第三方之合法权益。
xSub版本3.0.2数据包说明书
Package‘xSub’October14,2022Title Cross-National Data on Sub-National ViolenceVersion3.0.2Description Tools to download and merge datafiles on sub-national conflict,violence and protests from<>.URL https:///zhukovyuri/xSubDepends R(>=3.3.2)Imports countrycode,haven,RCurlLicense GPL-3Encoding UTF-8LazyData trueRoxygenNote7.1.1NeedsCompilation noAuthor Yuri Zhukov[aut,cre],Christian Davenport[aut],Nadiya Kostyuk[aut]Maintainer Yuri Zhukov<****************>Repository CRANDate/Publication2022-06-3016:40:02UTCR topics documented:get_xSub (2)get_xSub_multi (4)info_xSub (6)xSub_census_individual_raw (7)xSub_census_individual_spatial (8)xSub_census_multiple_raw (9)xSub_census_multiple_spatial (9)Index111get_xSub Get xSubfileDescriptionThis function downloads individualfiles from .Function produces a data.frame, for the user’s choice of data source,country,spatial and temporal units,and(optionally)writes this data.frame to disk,in multiple formats.Usageget_xSub(data_source,sources_type="individual",data_type="spatial panel",country_iso3=NULL,country_name=NULL,space_unit,time_unit,geo_window="1km",time_window="1day",dyad_type="undirected",out_dir=getwd(),write_file=TRUE,write_format="csv",verbose=FALSE)Argumentsdata_source Name of data source.See info_xSub()for full list.sources_type Type of data sources("individual"or"multiple").Character string.data_type Type of dataset("event"or"panel").Character string.country_iso3Country code(ISO3).See info_xSub()for full list.country_name Country name.See info_xSub()for full list.space_unit Geographic level of analysis.Character string.Can be one of"adm0"(country), "adm1"(province),"adm2"(district),"priogrid"(grid cell),"clea"(electoralconstituency).See info_xSub(details=TRUE)for availability by country.time_unit Temporal level of analysis.Character string.Can be one of"year","month", "week","day".See info_xSub(details=TRUE)for availability by country.geo_window Geographic window(if source_type="multiple").Could be either of"1km"(default)or"5km".Character string or vector.time_window Time window(if source_type="multiple").Could be either of"1day"(default) or"2day".Character string or vector.dyad_type Time window(if source_type="multiple").Could be either of"undirected"(de-fault)or"directed".Character string or vector.out_dir Path to directory wherefiles will be saved.write_file Logical.If write_file=TRUE,selectedfile will be written to disk,at location specified by out_dir.write_format Outputfile format.Can be one of"csv"(comma-separated values,default),"R"(RData format,compatible with R statistical programming language),"STATA"(dta format,compatible with Stata14).verbose Logical.When verbose=TRUE,file download progress is printed to console.See Alsoinfo_xSub,get_xSub_multiExamples#Check which countries are available for ACLEDinfo_xSub(data_source="ACLED")#Download ACLED data for Egypt,at country-year level##Not run:my_file<-get_xSub(data_source="ACLED",country_iso3="EGY",space_unit="adm0",time_unit="year")##End(Not run)#Download ACLED data for Egypt,at district-month level##Not run:my_file<-get_xSub(data_source="ACLED",country_iso3="EGY",space_unit="adm2",time_unit="month")##End(Not run)#With country name instead of ISO3code##Not run:my_file<-get_xSub(data_source="ACLED",country_name="Egypt",space_unit="adm2",time_unit="month")##End(Not run)##Not run:#Download ACLED data for Egypt,event levelmy_file<-get_xSub(data_source="ACLED",country_iso3="EGY",data_type="event")##End(Not run)##Not run:#Download multiple source data for Egypt,at province-month levelmy_file<-get_xSub(sources_type="multiple",country_iso3="EGY",space_unit="adm1",time_unit="month",geo_window="1km",time_window="1day",dyad_type="undirected")##End(Not run)get_xSub_multi Get xSubfiles for multiple countriesDescriptionThis function downloads and merges mutiple countryfiles from .Syntax is similar to get_xSub().Usageget_xSub_multi(data_source,sources_type="individual",data_type="spatial panel",country_iso3=NULL,space_unit,time_unit,geo_window="1km",time_window="1day",dyad_type="undirected",merge_files=TRUE,out_dir=getwd(),write_file=FALSE,write_format="csv",verbose=FALSE)Argumentsdata_source Name of data source.Character string.See info_xSub()for full list.sources_type Type of data sources("individual"or"multiple").Character string.data_type Type of dataset("event"or"panel").Character string.country_iso3Country codes(ISO3).Character string or vector.See info_xSub()for full list.If left blank,function will download all available countries for selected datasource.space_unit Geographic level of analysis.Character string.Can be one of"adm0"(country), "adm1"(province),"adm2"(district),"priogrid"(grid cell),"clea"(electoralconstituency).See info_xSub(details=TRUE)for availability by country.time_unit Temporal level of analysis.Character string.Can be one of"year","month", "week","day".See info_xSub(details=TRUE)for availability by country.geo_window Geographic window(if source_type="multiple").Could be either of"1km"or "5km".Character string or vector.time_window Time window(if source_type="multiple").Could be either of"1day"or"2day".Character string or vector.dyad_type Time window(if source_type="multiple").Could be either of"undirected"or"directed".Character string or vector.merge_files Logical.If merge_files=TRUE(default),function will combine individual coun-tryfiles into single data.frame,and write singlefile to disk.If merge_files=FALSE,function produces a list,and writes individual countryfiles to disk separately.out_dir Path to directory wherefiles will be saved.Character string.write_file Logical.If write_file=TRUE,selectedfile will be written to disk,at locationspecified by out_dir.write_format Outputfile format.Character string.Can be one of"csv"(comma-separatedvalues,default),"R"(RData format,compatible with R statistical programminglanguage),"STATA"(dta format,compatible with Stata14).verbose Logical.When verbose=TRUE,file download progress is printed to console..See Alsoinfo_xSub,get_xSubinfo_xSub,get_xSubExamples#Check which countries are available for GEDinfo_xSub(data_source="GED")#Example with two countries##Not run:my_file<-get_xSub_multi(data_source="PITF",country_iso3=c("ALB","ARM"),space_unit="adm0",time_unit="year")##End(Not run)#Example with two countries##Not run:my_file<-get_xSub_multi(data_source="GED",country_iso3=c("EGY","AGO"),space_unit="adm1",time_unit="month")##End(Not run)#Example with two countries,multiple sources,event-level##Not run:my_file<-get_xSub_multi(sources_type="multiple",data_type="event",country_iso3=c("EGY","AGO")) ##End(Not run)#Example with all countries(WARNING:this can take a long time to run)##Not run:my_file<-get_xSub_multi(data_source="BeissingerProtest",country_iso3=NULL,space_unit="adm0",time_unit="year")6info_xSub ##End(Not run)info_xSub Information on available xSubfilesDescriptionThis function reports the availability offiles on the server,and corresponding coun-try codes and units of analysis.For additional info,see /about/what-is-xsub. Usageinfo_xSub(details=FALSE,sources_type="individual",data_type="panel",data_source=NULL,country_iso3=NULL,country_name=NULL,geo_window=NULL,time_window=NULL,dyad_type=NULL)Argumentsdetails Logical.If details=TRUE,function returns information on available units of analysis for each country.sources_type Type of data sources("individual"or"multiple").Character string.data_type Type of dataset("event"or"panel").Character string.data_source Subset results by data sources.Character string or vector.country_iso3Subset results by country codes(ISO3).Character string or vector.country_name Subset results by country name.Character string or vector.geo_window Geographic window(if source_type="multiple").Could be either of"1km"or "5km".Character string or vector.time_window Time window(if source_type="multiple").Could be either of"1day"or"2 day".Character string or vector.dyad_type Time window(if source_type="multiple").Could be either of"undirected"or "directed".Character string or vector.See Alsoget_xSub,get_xSub_multiExamples#General info on data sources and countriesinfo_xSub()#Available files for Pakistaninfo_xSub(country_name="Pakistan")#Detailed info for Pakistaninfo_xSub(details=TRUE,country_name="Pakistan")#Available files for SCAD data sourceinfo_xSub(data_source="SCAD")#Available files for SCAD data source,event-levelinfo_xSub(data_source="SCAD",data_type="event")#Multiple data sources,directed dyadsinfo_xSub(sources_type="multiple",dyad_type="directed")#Multiple data sources,directed dyads,Russiainfo_xSub(sources_type="multiple",dyad_type="directed",country_name="Russia")xSub_census_individual_rawCensus of individual-source event-level datasets in xSub(updated June15,2020)DescriptionA list of data sources and countries available for ed by info_xSub()UsagexSub_census_individual_rawFormatA list with4elements:level0_bysource Countries organized by data_source.List object,where each sub-entry is also alist,containing entries for data_source,country_iso3,country_name.level0_bycountry Data sources organized by country.List of data.frames,where each row is acountry,with columns for country_iso3,country_name,data_sources.level1Detailed information on data sources,countries and spatial levels of analysis.data.frame,where each row is a source-country combination,with columns for data_source,country_iso3,country_name,units.all_countries Vector of all country ed by get_xSub_multi.Source/xSub_census_individual_spatialCensus of individual-source panel datasets in xSub(updated June15,2020)DescriptionA list of data sources,countries and levels of analysis available for ed by info_xSub()UsagexSub_census_individual_spatialFormatA list with6elements:level0_bysource Countries organized by data_source.List object,where each sub-entry is also alist,containing entries for data_source,country_iso3,country_name.level0_bycountry Data sources organized by country.List of data.frames,where each row is acountry,with columns for country_iso3,country_name,data_sources.level1Detailed information on data sources,countries and spatial levels of analysis.data.frame,where each row is a source-country combination,with columns for data_source,country_iso3,country_name,space_ level2Detailed information on data sources,countries,spatial and temporal levels of analysis.data.frame,where each row is a source-country-spatial unit combination,with columns fordata_source,country_iso3,country_name,space_unit,time_units.level3File census.data.frame,where each row is a singlefile,with columns for file_name,data_source,country_iso3,cou all_countries Vector of all country ed by get_xSub_multi.Source/xSub_census_multiple_rawCensus of multiple-source event-level datasets in xSub(updated June15,2020)DescriptionA list of data sources,countries and levels of analysis available for ed by info_xSub()UsagexSub_census_multiple_rawFormatA list with4elements:level0_bysource Countries organized by data_source.List object,where each sub-entry is also alist,containing entries for data_source,geo_window,time_window,dyad_type,country_iso3,country_name.level0_bycountry Data sources organized by country.List of data.frames,where each row is acountry,with columns for country_iso3,country_name,geo_window,time_window,dyad_type,data_sources.level1Detailed information on data sources,countries and spatial levels of analysis.data.frame,where each row is a source-country combination,with columns for data_source,geo_window,time_window,dyad_type all_countries Vector of all country ed by get_xSub_multi.Source/xSub_census_multiple_spatialCensus of multiple-source panel datasets in xSub(updated June15,2020)DescriptionA list of data sources,countries and levels of analysis available for ed by info_xSub()UsagexSub_census_multiple_spatialFormatA list with6elements:level0_bysource Countries organized by data_source.List object,where each sub-entry is also alist,containing entries for data_source,geo_window,time_window,dyad_type,country_iso3,country_name.level0_bycountry Data sources organized by country.List of data.frames,where each row is acountry,with columns for country_iso3,country_name,geo_window,time_window,dyad_type,data_sources.level1Detailed information on data sources,countries and spatial levels of analysis.data.frame,where each row is a source-country combination,with columns for data_source,geo_window,time_window,dyad_type level2Detailed information on data sources,countries,spatial and temporal levels of analysis.data.frame,where each row is a source-country-spatial unit combination,with columns fordata_source,geo_window,time_window,dyad_type,country_iso3,country_name,space_unit,time_units.level3File census.data.frame,where each row is a singlefile,with columns for file_name,data_source,geo_window,time_ all_countries Vector of all country ed by get_xSub_multi.Source/Index∗datasetsxSub_census_individual_raw,7xSub_census_individual_spatial,8xSub_census_multiple_raw,9xSub_census_multiple_spatial,9get_xSub,2,5,6get_xSub_multi,3,4,6info_xSub,3,5,6xSub_census_individual_raw,7xSub_census_individual_spatial,8xSub_census_multiple_raw,9xSub_census_multiple_spatial,911。
K4T1G084QQ资料
1Gb Q-die DDR2 SDRAM Specification60FBGA & 84FBGA with Pb-Free & Halogen-Free(RoHS compliant)INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDEDON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.1. For updates or additional information about Samsung products, contact your nearest Samsung office.2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.* Samsung Electronics reserves the right to change products or specification without notice.Table of Contents1.0 Ordering Information (4)2.0 Key Features (4)3.0 Package Pinout/Mechanical Dimension & Addressing (5)3.1 x4/x8 package pinout (Top View) : 60ball FBGA Package (5)3.2 x16 package pinout (Top View) : 84ball FBGA Package (6)3.3 FBGA Package Dimension (x4/x8) (7)3.4 FBGA Package Dimension (x16) (8)4.0 Input/Output Functional Description (9)5.0 DDR2 SDRAM Addressing (10)6.0 Absolute Maximum DC Ratings (11)7.0 AC & DC Operating Conditions (11)7.1 Recommended DC Operating Conditions (SSTL - 1.8) (11)7.2 Operating Temperature Condition (12)7.3 Input DC Logic Level (12)7.4 Input AC Logic Level (12)7.5 AC Input Test Conditions (12)7.6 Differential input AC logic Level (13)7.7 Differential AC output parameters (13)8.0 ODT DC electrical characteristics (13)9.0 OCD default characteristics (14)10.0 IDD Specification Parameters and Test Conditions (15)11.0 DDR2 SDRAM IDD Spec Table (17)12.0 Input/Output capacitance (18)13.0 Electrical Characteristics & AC Timing for DDR2-800/667 (18)13.1 Refresh Parameters by Device Density (18)13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin (18)13.3 Timing Parameters by Speed Grade (19)14.0 General notes, which may apply for all AC parameters (21)15.0 Specific Notes for dedicated AC parameters (23)Revision HistoryRevision Month Year History1.0September2007 - Initial Release1.01November2007 - Typo CorrectionSpeed DDR2-800 5-5-5DDR2-800 6-6-6DDR2-667 5-5-5Units CAS Latency 565tCK tRCD(min)12.51515ns tRP(min)12.51515ns tRC(min)57.56060nsNote :1. Speed bin is in order of CL-tRCD-tRP.2. RoHS Compliant.3. “H” of Part number(12th digit) stand for RoHS compliant and Halogen-free products.Org.DDR2-800 5-5-5DDR2-800 6-6-6DDR2-667 5-5-5Package 256Mx4K4T1G044QQ-HC(L)E7K4T1G044QQ-HC(L)F7K4T1G044QQ-HC(L)E660 FBGA 128Mx8K4T1G084QQ-HC(L)E7K4T1G084QQ-HC(L)F7K4T1G084QQ-HC(L)E660 FBGA 64Mx16K4T1G164QQ-HC(L)E7K4T1G164QQ-HC(L)F7K4T1G164QQ-HC(L)E684 FBGA•JEDEC standard 1.8V ± 0.1V Power Supply •VDDQ = 1.8V ± 0.1V•333MHz f CK for 667Mb/sec/pin, 400MHz f CK for 800Mb/sec/pin •8 Banks •Posted CAS•Programmable CAS Latency: 3, 4, 5, 6•Programmable Additive Latency: 0, 1, 2, 3, 4, 5•Write Latency(WL) = Read Latency(RL) -1•Burst Length: 4 , 8(Interleave/nibble sequential)•Programmable Sequential / Interleave Burst Mode •Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)•Off-Chip Driver(OCD) Impedance Adjustment •On Die Termination•Special Function Support- PASR(Partial Array Self Refresh)- 50ohm ODT- High Temperature Self-Refresh rate enable •Average Refresh Period 7.8us at lower than T CASE 85°C, 3.9us at 85°C < T CASE < 95 °C •All of Lead-free products are compliant for RoHSThe 1Gb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x 8banks, 16Mbit x 8 I/Os x 8banks or 8Mbit x 16 I/Os x 8 banks device. This synchronous device achieves high speed double-data-rate transfer rates of up to 800Mb/sec/pin (DDR2-800) for general applications.The chip is designed to comply with the following key DDR2SDRAM features such as posted CAS with additive latency, write latency = read latency - 1, Off-Chip Driver(OCD) impedance adjustment and On Die Termination.All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. For example, 1Gb(x8) device receive 14/10/3 addressing.The 1Gb DDR2 device operates with a single 1.8V ±0.1V power supply and 1.8V ±0.1V VDDQ.The 1Gb DDR2 device is available in 60ball FBGAs(x4/x8) and in 84ball FBGAs(x16).Note : The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “DDR2 SDRAM Device Operation & Timing Diagram”.1.0 Ordering Information2.0 Key FeaturesNote:1. Pins B3 and A2 have identical capacitance as pins B7 and A8.2. For a read, when enabled, strobe pair RDQS & RDQS are identical in function and timing to strobe pair DQS & DQS and input masking function is disabled.3. The function of DM or RDQS/RDQS are enabled by EMRS command.4. VDDL and VSSDL are power and ground for the DLL.A B C D E F G H J K LVDD NU/VSSDQ6VSSQ VDDQ VDDQ VDDQ VSSQ VSSQ DQS DQS DQ7DQ0VDDQ DQ2VSSQ DQ5VSSDL VDD CK RAS CK CAS CS A2A6A4A11A8NCA13NCA12A9A7A5A0VDD A10/APVSSVDDQ VSSQ DQ1DQ3DQ4VDDLA1A3BA1VREF VSS CKEWE BA01 2 3 7 8 9VDDVSS ODTBA2Ball Locations (x4/x8): Populated Ball +: Depopulated BallTop View (See the balls through the Package)++++++++++++++++++++++++++++++123456789A B C D E F G H J K L++++++++DM /RDQSRDQS+3.1 x4/x8 package pinout (Top View) : 60ball FBGA Package3.0 Package Pinout/Mechanical Dimension & AddressingNote :1. VDDL and VSSDL are power and ground for the DLL.2. In case of only 8 DQs out of 16 DQs are used, LDQS, LDQSB and DQ0~7 must be used.A B C D E F G H J K L VDD NC VSS DQ14VSSQ UDM VDDQ VDDQ VDDQ VSSQ VSSQ UDQS UDQS DQ15DQ8VDDQ DQ10VSSQ DQ13VSSQ VDDQ RAS CK CAS CS A2A6A4A11A8NCNCNCA12A9A7A5A0VDDA10/APVSSVDDQ VSSQ DQ9DQ11DQ12VDD A1A3BA1NC VSS CKEWE BA0 1 2 3 7 8 9VDDVSSODTBA2Ball Locations (x16): Populated Ball +: Depopulated BallTop View (See the balls through the Package)M N P RDQ6VSSQ LDM VDDQ VDDQ VSSQ LDQS DQ7DQ0VDDQ DQ2VSSQ DQ5VSSDL VDD CK VDDQ VSSQ DQ1DQ3DQ4VDDLVREF VSS LDQS 123456789++++++++++++++++++++++++++++++++++++++++++++++++++A B C D E F G H J K L M N P R+3.2 x16 package pinout (Top View) : 84ball FBGA Package3.3 FBGA Package Dimension (x4/x8)A B CD E F H J K LG3.4 FBGA Package Dimension (x16)A B C D E FH J K L M N P RGSymbol Type FunctionCK, CK Input Clock:CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing).CKE Input Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and out-put drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. After V REF has become stable during the power on and initialization swquence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, V REF must be maintained to this input. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self refresh.CS Input Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on sys-tems with multiple Ranks. CS is considered part of the command code.ODT Input On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS, RDQS, RDQS, and DM signal for x4/x8 configurations. For x16 configuration ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal. The ODT pin will be ignored if the Extended Mode Register (EMRS(1)) is programmed to disable ODT.RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.DM Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coinci-dent with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For x8 device, the function of DM or RDQS/RDQS is enabled by EMRS command.BA0 - BA2Input Bank Address Inputs: BA0, BA1 and BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle.A0 - A13Input Address Inputs: Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code dur-ing Mode Register Set commands.DQ Input/Out-putData Input/ Output: Bi-directional data bus.DQS, (DQS)(LDQS), (LDQS) (UDQS), (UDQS) (RDQS), (RDQS)Input/Out-putData Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15. For the x8, an RDQS option using DM pin can be enabled via the EMRS(1) to simplify read timing. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single ended mode or paired with optional complementary signals DQS, LDQS, UDQS, and RDQS to provide differential pair signaling to the system during both reads and writes. An EMRS(1) control bit enables or disables all complementary data strobe signals.In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMRS(1)x4 DQS/DQSx8 DQS/DQS if EMRS(1)[A11] = 0x8 DQS/DQS, RDQS/RDQS, if EMRS(1)[A11] = 1x16 LDQS/LDQS and UDQS/UDQS"single-ended DQS signals" refers to any of the following with A10 = 1 of EMRS(1)x4 DQSx8 DQS if EMRS(1)[A11] = 0x8 DQS, RDQS, if EMRS(1)[A11] = 1x16 LDQS and UDQSNC No Connect: No internal electrical connection is present.V DD/V DDQ Supply Power Supply: 1.8V +/- 0.1V, DQ Power Supply: 1.8V +/- 0.1V V SS/V SSQ Supply Ground, DQ GroundV DDL Supply DLL Power Supply: 1.8V +/- 0.1VV SSDL Supply DLL GroundV REF Supply Reference voltage4.0 Input/Output Functional Description5.0 DDR2 SDRAM Addressing1Gb AddressingConfiguration256Mb x4128Mb x 864Mb x16 # of Bank888Bank Address BA0 ~ BA2BA0 ~ BA2BA0 ~ BA2Auto precharge A10/AP A10/AP A10/APRow Address A0 ~ A13A0 ~ A13A0 ~ A12Column Address A0 ~ A9,A11A0 ~ A9A0 ~ A9 * Reference information: The following tables are address mapping information for other densities.256MbConfiguration64Mb x432Mb x 816Mb x16 # of Bank444Bank Address BA0,BA1BA0,BA1BA0,BA1Auto precharge A10/AP A10/AP A10/APRow Address A0 ~ A12A0 ~ A12A0 ~ A12Column Address A0 ~ A9,A11A0 ~ A9A0 ~ A8512MbConfiguration128Mb x464Mb x 832Mb x16 # of Bank444Bank Address BA0,BA1BA0,BA1BA0,BA1Auto precharge A10/AP A10/AP A10/APRow Address A0 ~ A13A0 ~ A13A0 ~ A12Column Address A0 ~ A9,A11A0 ~ A9A0 ~ A92GbConfiguration512Mb x4256Mb x 8128Mb x16 # of Bank888Bank Address BA0 ~ BA2BA0 ~ BA2BA0 ~ BA2Auto precharge A10/AP A10/AP A10/APRow Address A0 ~ A14A0 ~ A14A0 ~ A13Column Address A0 ~ A9,A11A0 ~ A9A0 ~ A9 4GbConfiguration 1 Gb x4512Mb x 8256Mb x16 # of Bank888Bank Address BA0 ~ BA2BA0 ~ BA2BA0 ~ BA2Auto precharge A10/AP A10/AP A10/APRow Address A0 - A15A0 - A15A0 - A14 Column Address/page size A0 - A9,A11 A0 - A9 A0 - A9Note :1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.2. Storage Temperature is the case surface temperature on the center/top side of the DRAM.Symbol ParameterRating Units Notes V DD Voltage on V DD pin relative to V SS - 1.0 V ~ 2.3 V V 1V DDQ Voltage on V DDQ pin relative to V SS - 0.5 V ~ 2.3 V V 1V DDL Voltage on V DDL pin relative to V SS - 0.5 V ~ 2.3 V V 1V IN, V OUT Voltage on any pin relative to V SS - 0.5 V ~ 2.3 V V1T STGStorage Temperature-55 to +100°C 1, 2Note : There is no specific device V DD supply voltage requirement for SSTL-1.8 compliance. However under all conditions V DDQ must be less than or equalto V DD .1. The value of V REF may be selected by the user to provide optimum noise margin in the system. Typically the value of V REF is expected to be about 0.5 x V DDQ of the transmitting device and V REF is expected to track variations in V DDQ .2. Peak to peak AC noise on V REF may not exceed +/-2% V REF (DC).3. V TT of transmitting device must track V REF of receiving device.4. AC parameters are measured with V DD , V DDQ and V DDL tied together.Symbol ParameterRatingUnits NotesMin.Typ. Max.V DD Supply Voltage 1.7 1.8 1.9V V DDL Supply Voltage for DLL 1.7 1.8 1.9V 4V DDQ Supply Voltage for Output 1.7 1.8 1.9V 4V REF Input Reference Voltage 0.49*V DDQ 0.50*V DDQ0.51*V DDQ mV 1,2V TTTermination VoltageV REF -0.04V REFV REF +0.04V37.0 AC & DC Operating Conditions6.0 Absolute Maximum DC Ratings7.1 Recommended DC Operating Conditions (SSTL - 1.8)7.2 Operating Temperature Condition1.Operating Temperature is the case surface temperature on the center/top side of the DRAM.2.At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.7.3 Input DC Logic Level7.4 Input AC Logic Level7.5 AC Input Test ConditionsNote :1. Input waveform timing is referenced to the input signal crossing through the V IH/IL (AC) level applied to the device under test.2. The input signal minimum slew rate is to be maintained over the range from V REF to V IH (AC) min for rising edges and the range from V REF to V IL (AC)max for falling edges as shown in the below figure.3. AC timings are referenced with input waveforms switching from V IL (AC) to V IH (AC) on the positive transitions and V IH (AC) to V IL (AC) on the negative transitions.Symbol Parameter Rating UnitsNotesTOPEROperating Temperature0 to 95°C 1, 2Symbol Parameter Min.Max.Units NotesV IH (DC)DC input logic high V REF + 0.125V DDQ + 0.3V V IL (DC)DC input logic low- 0.3V REF - 0.125VSymbol ParameterDDR2-667, DDR2-800Units Min.Max.V IH (AC)AC input logic high V REF + 0.200V V IL (AC)AC input logic lowV REF - 0.200VSymbol Condition Value Units Notes V REF Input reference voltage0.5 * V DDQV 1V SWING(MAX)Input signal maximum peak to peak swing1.0V 1SLEWInput signal minimum slew rate1.0V/ns2, 3V DDQ V IH (AC) minV IH (DC) min V REFV IL (DC) max V IL (AC) maxV SS< AC Input Test Signal Waveform >V SWING(MAX)delta TRdelta TFV REF - V IL (AC) maxdelta TFFalling Slew =Rising Slew =V IH (AC) min - V REFdelta TRV DDQCrossing pointV SSQV TR V CPV IDV IX or V OX< Differential signal levels >7.6 Differential input AC logic LevelNote :1. V ID (AC) specifies the input differential voltage |V TR -V CP | required for switching, where V TR is the true input signal (such as CK, DQS, LDQS or UDQS) and V CP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH (AC) - V IL (AC).2. The typical value of V IX (AC) is expected to be about 0.5 * VDDQ of the transmitting device and V IX (AC) is expected to track variations in VDDQ . V IX (AC) indicates the voltage at which differential input signals must cross.7.7 Differential AC output parametersNote :1. The typical value of V OX (AC) is expected to be about 0.5 * VDDQ of the transmitting device and V OX (AC) is expected to track variations in VDDQ . V OX (AC) indicates the voltage at which differential output signals must cross.Symbol ParameterMin.Max.Units Notes V ID(AC)AC differential input voltage 0.5V DDQ + 0.6V 1V IX(AC)AC differential cross point voltage0.5 * VDDQ - 0.1750.5 * VDDQ + 0.175V2Symbol ParameterMin.Max.Units Note V OX (AC)AC differential cross point voltage0.5 * VDDQ - 0.1250.5 * VDDQ + 0.125V1Note : Test condition for Rtt measurementsMeasurement Definition for Rtt(eff):Apply V IH (ac) and V IL (ac) to test pin separately, then measure current I(V IH (ac)) and I( V IL (ac)) respectively. V IH (ac), V IL (ac), and VDDQ values defined in SSTL_18Measurement Definition for VM: Measure voltage (V M ) at test pin (midpoint) with no load.PARAMETER/CONDITIONSYMBOL MIN NOM MAX UNITS NOTES Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 ohm Rtt1(eff)607590ohm 1Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 ohm Rtt2(eff)120150180ohm 1Rtt effective impedance value for EMRS(A6,A2)=1,1; 50 ohm Rtt3(eff)405060ohm 1Deviation of VM with respect to VDDQ/2delta VM- 6+ 6%1Rtt(eff) =V IH (ac) - V IL (ac)I(V IH (ac)) - I(V IL (ac))delta VM =2 x Vm VDDQx 100%- 18.0 ODT DC electrical characteristicsNote :1. Absolute Specifications (0°C ≤ T CASE ≤ +95°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)2. Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ- 280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV.3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage.4. Slew rate measured from V IL (AC) to V IH (AC).5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaranteed by design and characterization.6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process and represents only the DRAM uncertainty. Output slew rate load :7. DRAM output slew rate specification applies to 667Mb/sec/pin and 800Mb/sec/pin speed bins.8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS specification.DescriptionParameterMinNomMaxUnit Notes Output impedanceNormal 18ohmsSee full strength default driver characteristics ohms 1,2Output impedance step size for OCD calibration 0 1.5ohms 6Pull-up and pull-down mismatch 04ohms 1,2,3Output slew rateSout 1.55V/ns1,4,5,6,7,825 ohmsV TTOutput (V OUT)Reference Point9.0 OCD default characteristics(IDD values are for full operating range of Voltage and Temperature, Notes 1 - 5)Symbol Proposed Conditions Units NotesIDD0Operating one bank active-precharge current;t CK = t CK(IDD), t RC = t RC(IDD), t RAS = t RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;Address bus inputs are SWITCHING; Data bus inputs are SWITCHINGmAIDD1Operating one bank active-read-precharge current;IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; t CK = t CK(IDD), t RC = t RC (IDD), t RAS = t RASmin(IDD), t RCD =t RCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address businputs are SWITCHING; Data pat-tern is same as IDD4WmAIDD2P Precharge power-down current;All banks idle; t CK = t CK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATINGmAIDD2Q Precharge quiet standby current;All banks idle; t CK = t CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputsare STABLE; Databus inputs are FLOATINGmAIDD2N Precharge standby current;All banks idle; t CK = t CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING;Data bus inputs are SWITCHINGmAIDD3P Active power-down current;All banks open; t CK = t CK(IDD); CKE is LOW; Other control and address businputs are STABLE; Data bus inputs are FLOATINGFast PDN Exit MRS(12) = 0mASlow PDN Exit MRS(12) = 1mAIDD3N Active standby current;All banks open; t CK = t CK(IDD), t RAS = t RASmax(IDD), t RP = t RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHINGmAIDD4W Operating burst write current;All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; t CK = t CK(IDD), t RAS = t RASmax(IDD), t RP= t RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data businputs are SWITCHINGmAIDD4R Operating burst read current;All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; t CK = t CK(IDD), t RAS = t RAS-max(IDD), t RP = t RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCH-ING; Data pattern is same as IDD4WmAIDD5B Burst auto refresh current;t CK = t CK(IDD); Refresh command at every t RFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid com-mands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHINGmAIDD6Self refresh current;CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs areFLOATING; Data bus inputs are FLOATINGNormal mALow Power mAIDD7Operating bank interleave read current;All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = t RCD(IDD)-1*t CK(IDD); t CK = t CK(IDD), t RC= t RC(IDD), t RRD = t RRD(IDD), t FAW = t FAW(IDD), t RCD = 1*t CK(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the fol-lowing page for detailed timing conditionsmA10.0 IDD Specification Parameters and Test ConditionsNote :1. IDD specifications are tested after the device is properly initialized2. Input slew rate is specified by AC Parametric Test Condition3. IDD parameters are specified with ODT disabled.4. Data bus consists of DQ, DM, DQS, DQS\, RDQS, RDQS\, LDQS, LDQS\, UDQS, and UDQS\. IDD values must be met with all combinations of EMRS bits 10 and 11.5. Definitions for IDD LOW is defined as Vin ≤ VILAC(max) HIGH is defined as Vin ≥ VIHAC(min)STABLE is defined as inputs stable at a HIGH or LOW level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as:inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and controlsignals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes.For purposes of IDD testing, the following parameters are utilizedDetailed IDD7The detailed timings are shown below for IDD7.Legend: A = Active; RA = Read with Autoprecharge; D = DeselectIDD7: Operating Current: All Bank Interleave Read operationAll banks are being interleaved at minimum t RC(IDD) without violating t RRD(IDD) and t FAW(IDD) using a burst length of 4. Control and address bus inputs are STABLE during DESELECTs. IOUT = 0mATiming Patterns for 8bank devices x4/ x8-DDR2-667 5/5/5 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D-DDR2-800 6/6/6 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D -DDR2-800 5/5/5 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D DTiming Patterns for 8bank devices x16-DDR2-667 5/5/5 : A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D-DDR2-800 6/6/6 : A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D -DDR2-800 5/5/5 : A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D DDDR2-800DDR2-800DDR2-667Units Parameter 5-5-56-6-65-5-5CL(IDD)565tCK t RCD(IDD)12.51515ns t RC(IDD)57.56060ns t RRD(IDD)-x4/x87.57.57.5ns t RRD(IDD)-x16101010ns t CK(IDD) 2.5 2.53ns t RASmin(IDD)454545ns t RP(IDD)12.51515ns t RFC(IDD)127.5127.5127.5ns(T A=0o C, VDD= 1.9V)Symbol256Mx4 (K4T1G044QQ)Unit Notes 800@CL=5800@CL=6667@CL=5CE7LE7CF7LF7CE6LE6IDD0757570mAIDD1858580mAIDD2P158158158mAIDD2Q303030mAIDD2N353535mAIDD3P-F353535mAIDD3P-S181818mAIDD3N555550mAIDD4W110110100mAIDD4R130130115mAIDD5140140135mAIDD6156156156mAIDD7245245225mA(T A=0o C, VDD= 1.9V)Symbol128Mx8 (K4T1G084QQ)Unit Notes 800@CL=5800@CL=6667@CL=5CE7LE7CF7LF7CE6LE6IDD0757570mAIDD1858580mAIDD2P158158158mAIDD2Q303030mAIDD2N353535mAIDD3P-F353535mAIDD3P-S181818mAIDD3N555550mAIDD4W115115105mAIDD4R135135120mAIDD5145145140mAIDD6156156156mAIDD7250250230mA11.0 DDR2 SDRAM IDD Spec Table(T A=0o C, VDD= 1.9V)Symbol64Mx16 (K4T1G164QQ)Unit Notes 800@CL=5800@CL=6667@CL=5CE7LE7CF7LF7CE6LE6IDD0909085mA IDD110010095mA IDD2P158158158mA IDD2Q303030mA IDD2N353535mA IDD3P-F353535mA IDD3P-S181818mA IDD3N555550mA IDD4W130130115mA IDD4R175175155mA IDD5145145140mA IDD6156156156mA IDD7265265245mASpeedDDR2-800(E7)DDR2-800(F7)DDR2-667(E6)UnitsBin (CL - tRCD - tRP)5-5-56-6-65 - 5 - 5Parameter min max min max min max tCK, CL=358--58ns tCK, CL=4 3.758 3.758 3.758ns tCK, CL=5 2.583838ns tCK, CL=6-- 2.58--ns tRCD 12.5-15-15-ns tRP 12.5-15-15-ns tRC 57.5-60-60-ns tRAS457000045700004570000ns ParameterSymbol DDR2-667DDR2-800Units Min Max Min Max Input capacitance, CK and CK CCK 1.0 2.0 1.0 2.0pF Input capacitance delta, CK and CK CDCK x 0.25x 0.25pF Input capacitance, all other input-only pins CI 1.0 2.0 1.0 1.75pF Input capacitance delta, all other input-only pins CDI x 0.25x 0.25pF Input/output capacitance, DQ, DM, DQS, DQS CIO 2.5 3.5 2.5 3.5pF Input/output capacitance delta, DQ, DM, DQS, DQSCDIOx0.5x0.5pF13.0 Electrical Characteristics & AC Timing for DDR2-800/667(0 °C < T OPER < 95 °C; V DDQ = 1.8V + 0.1V; V DD = 1.8V + 0.1V)13.1 Refresh Parameters by Device DensityParameterSymbol256Mb 512Mb 1Gb 2Gb 4Gb Units Refresh to active/Refresh command time tRFC 75105127.5195327.5ns Average periodic refresh intervaltREFI0 °C ≤ T CASE ≤ 85°C 7.87.87.87.87.8µs 85 °C < T CASE ≤ 95°C3.93.93.93.93.9µs13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin 12.0 Input/Output capacitance。
TRSL-5380-CXX0资料
Optoway TRSL-5380-CXX0************************************************************************************************************************************************************************************************************************************************************************************************************************************************************OPTOWAY TECHNOLOGY INC. No .38, Kuang Fu S. Road, Hu Kou, Hsin Chu Industrial Park, Hsin Chu, Taiwan 303Tel: 886-3-5979798 Fax: 886-3-59797376/30/2004 V2.0TRSL-5380-CXX0 / TRSL-5380C-CXX03.3V / CWDM / 622 Mbps SFF LC SINGLE-MODE TRANSCEIVER******************************************************************************************************************************************************************************FEATURESl Duplex LC Single Mode Transceiver l SONET OC-12 LR / SDH STM-1 Compliant l Small Form Factor, RJ-45 size, 2X5 pin Package l 18-Wavelength CWDM DFB LD Transmitter from 1270 nm to 1610 nm, with step 20 nm l 29 dB Link Budget at Least l LVPECL Signal Input / Output l LVTTL Transmitter Disable Input l LVPECL Signal Detection Output (TRSL-5380-CXX0) l LVTTL Signal Detection Output (TRSL-5380C-CXX0) l Single +3.3 V Power Supply l 0 to 70o C Operation l Wave Solderable and Aqueous Washable l Class 1 Laser International Safety Standard IEC 60825 CompliantAPPLICATIONSl ATM 622 Mbps Links l SONET/SDH Equipment Interconnect l Fiber Channel 533 Mb/s LinksDESCRIPTIONThe TRSL-5380-CXX0 series single mode transceivers is low power, high performance CWDM modules for bi-directional serial optical data communications such as long-reach SONET OC-12 LR / SDH STM-4 and Fiber Channel. There are eighteen center wavelengths available from 1270 nm to 1610 nm, each step 20 nm. A guaranteed minimum optical link budget of 29 dB is offered. The transmitter section uses a multiple quantum well CWDM DFB laser and is a class 1 laser compliant according to International Safety Standard IEC 60825. The receiver section uses an integrated InGaAs detector preamplifier (IDP) mounted in an optical header and a limiting post-amplifier IC. A PECL logic interface simplifies interface to external circuitry.LASER SAFETYThis single mode transceiver is a Class 1 laser product. It complies with IEC-60825 and FDA 21 CFR 1040.10 and 1040.11. The transceiver must be operated within the specified temperature and voltage limits. The optical ports of the module shall be terminated with an optical connector or with a dust plugORDER INFORMATIONP/No.Bit Rate (Mb/s) SONET /SDH Power Budget (dB) Wavelength (nm) PackageTemp. (o C) TX Power (dBm) RX Sens. (dBm) SignalDetect TRSL-5380-CXX0622LR > 29CWDM *2X5 LC0 to 705 to 0-29LVPECLCWDM Wavelength (0 to 70oC) Central Wavelength Min. (nm) Typ. (nm) Max. (nm) Central Wavelength Min. (nm) Typ. (nm) Max. (nm) -C270 1264.5 1270 1277.5 -C450 1444.5 1450 1457.5 -C290 1284.5 1290 1297.5 -C470 1464.5 1470 1477.5 -C310 1304.5 1310 1317.5 -C490 1484.5 1490 1497.5 -C330 1324.5 1330 1337.5 -C510 1504.5 1510 1517.5 -C350 1344.5 1350 1357.5 -C530 1524.5 1530 1537.5 -C370 1364.5 1370 1377.5 -C550 1544.5 1550 1557.5 -C390 1384.5 1390 1397.5 -C570 1564.5 1570 1577.5 -C410 1404.5 1410 1417.5 -C590 1584.5 1590 1597.5 -C430 1424.5 1430 1437.5 -C610 1604.5 1610 1617.5CWDM *: 18 Wavelengths from 1270 nm to 1610 nm, each step 20 nm.***************************************************************************************************************************************************************************** Absolute Maximum RatingsParameter Symbol Min Max Units NotesStorage Temperature Tstg -40 85 o COperating Temperature Topr 0 70 o C With air flow 1m/sec Soldering Temperature --- 260 o C 10 seconds on leads only Power Supply Voltage Vcc 0 4.5 VInput Voltage --- GND Vcc VOutput Current Iout 0 30 mARecommended Operating ConditionsParameter Symbol Min Typ Max Units / NotesPower Supply Voltage Vcc 3.135 3.3 3.465 VOperating Temperature Topr 0 70 o C / air flow 1m/secData Rate 50 622 Mb/sPower Supply Current Icc 280 mA Transmitter Specifications (0o C < Topr < 70o C, 3.135V < Vcc < 3.465V)Parameter Symbol Min Typ Max Units NotesOpticalOptical Transmit Power Po 0 --- 5 dBm 1Output Center Wavelength λλ-5.5 λλ+7.5 nm 2Output Spectrum Width ∆λ--- --- 1 nm -20 dB WidthSide Mode Suppression Ratio SMSR 30 dBExtinction Ratio E R10 --- --- dBOutput Eye Compliant with Bellcore GR-253-CORE and ITU recommendation G.957Optical Rise Time t r 1.2 ns 10% to 90% Values Optical Fall Time t f 1.2 ns 10% to 90% Values Relative Intensity Noise RIN -120 dB/HzTotal Jitter TJ 0.55 ns 3ElectricalData Input Current – Low I IL-350 µAData Input Current – High I IH350 µADifferential Input Voltage V IH - V IL300 mVData Input Voltage – Low V IL - V CC-2.0 -1.58 V 4Data Input Voltage -- High V IH - V CC-1.1 -0.74 V 4Disable Input Voltage -- Low V TDIS,L0 0.5 V TX Output Enabled Disable Input Voltage -- High V TDIS,H Vcc – 1.3 Vcc V TX Ouput Disabled Shut Off Time for TxDis t DIS 1 msNotes: 1. Output power is power coupled into a 9/125 µm single mode fiber.2. ITU-T G.694.2 CWDM wavelength from 1270 nm to 1610 nm, each step 20 nm.3. Measured with a 223-1 PRBS with 72 ones and 72 zeros.4. These inputs are compatible with 10K, 10KH and 100K ECL and PECL inputs.************************************************************************************************************************************************************************** OPTOWAY TECHNOLOGY INC. No.38, Kuang Fu S. Road, Hu Kou, Hsin Chu Industrial Park, Hsin Chu, Taiwan 303 Tel: 886-3-5979798 Fax: 886-3-5979737************************************************************************************************************************************************************************** OPTOWAY TECHNOLOGY INC. No.38, Kuang Fu S. Road, Hu Kou, Hsin Chu Industrial Park, Hsin Chu, Taiwan 303 Tel: 886-3-5979798 Fax: 886-3-5979737**************************************************************************************************************************************************************************OPTOWAY TECHNOLOGY INC. No .38, Kuang Fu S. Road, Hu Kou, Hsin Chu Industrial Park, Hsin Chu, Taiwan 303Tel: 886-3-5979798 Fax: 886-3-5979737RECOMMENDED CIRCUIT SCHEMATICV e e r 1V c c r 2S D 3R D -4R D +5V c c t6V e e t 7T D i s 8T D + 9T D - 10SFF2X5TDis(LVTTL)1uH10uF10nF10uF10nF Vcc3.3V1uH10uF10nF1KPHY DEVICETD-TD+RD+RD-SD130R82RVcc3.3V 130R82RVcc3.3VVcc3.3VLVPE CLVcc3.3VLVPE CLTO LVPECL STAGE150ohm150ohmMICROSTRIP2Z=5ORMICROSTRIP1Z=50RMICROSTRIP4Z=5ORMICROSTRIP3Z=50RNote: 1. 1000ΩSD Output pull-down resistor required for TRSL-5380-CXX0 (LVPECL SD Output) 2. No pull-down resistor required for TRSL-5380C-CXX0C (LVTTL SD Output)3. Veer and Veet are not internally connected to each other.4. 50 Ω line pattern and component placements on TD+/TD- and RD+/RD- lines shall be symmetrical for better impedance matching.PACKAGE DIAGRAMUnits in mm1) Standard CaseTRSL-5380-CXX0 / TRSL-5380C-CXX02) Extended CaseTRSL-5380E-CXX0 / TRSL-5380CE-CXX0Note: Specifications subject to change without notice.************************************************************************************************************************************************************************** OPTOWAY TECHNOLOGY INC. No.38, Kuang Fu S. Road, Hu Kou, Hsin Chu Industrial Park, Hsin Chu, Taiwan 303 Tel: 886-3-5979798 Fax: 886-3-5979737。
8025t中文使用详细说明
V
5.0
3.0
V
3.0
GND+0.5
GND+0.8
V
GND+0.1
GND+0.25
GND+0.4
V
GND+0.4
0.5
uA
0.5
uA
III
8、推荐电路：
RX-8025T 使用说明概要
注意：若不需要 FOUT 输出，FOE 引脚可悬空或接地。
9、I2C 总线协议（时序图）
注意：当访问该器件的时候，所有的通讯从传输开始条件到传输结束条件为止，所有的操作 必须在 0.95 秒内完成。 如果这样的通讯需要 0.95s 或更长时间，那么 I2C 总线接口将由内 部总线时间溢出功能复位。
及其它信号。该引脚为开漏输出引脚。
11：GND
-
电源接地端
12：T2
-
*工厂测试用
13：SDA
I/O
I2C 总线通讯，数据传输端。该引脚为 N-ch 开漏输出，所
以一定要连接到一个有上拉电阻的相关信号线上。
注意：确认在 VDD 和 GND 之间连接一个至少 0.1uF 的旁路电容。
4、绝对电气指标：
7、电气特性：
项目 符号
条件
Min
电流功耗 1 IDD1 Fscl=0 Hz
VDD=5V
电流功耗 2 IDD2 /INT=VDD;FOE=GND
VDD=3V
电流功耗 3 IDD3 Fscl=0 Hz /INT,FOE=VDD
电流功耗 4 IDD4 FOUT:32.768K,CL=0pF
VDD=5V VDD=3V
扩展寄存器 D
该寄存器用来说明闹钟功能或定时更新中断功能以及用来选择或设定等操作。
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
FEATURES:
Low On-State Voltage
Hermetic Ceramic Package Excellent Surge and I 2t Ratings
APPLICATIONS:
DC Power Supplies ORDERING INFORMATION
Input Rectifiers Plating Supplies
Select the complete 12 digit Part Number using the table below.
EXAMPLE: RDS82280XXOO is a 2200V-8000A General Purpose Diode
Revised:
916/2002
Powerex General Purpose Rectifier Diodes are designed with high locking voltage capability and low forward voltage drop to minimize conduction losses. These are packaged in hermetic, ceramic Pow-R-Disc packages which can be mounted using commercially available clamps and heatsinks or fully assembled to a variety of air or water cooled heat exchangers.
Absolute Maximum Ratings
Characteristic Symbol Rating Units
Repetitive Peak Reverse Voltage V RRM2500Volts
Non-repetitive Transient Peak Reverse Voltage V RSM V RRM + 100Volts
Average On-State Current, T C=90°C I F(Avg.)8000A
RMS On-State Current, T C=90°C I F(RMS)12566A
Peak One Cycle Surge Current, 60Hz, V R=V RRM I FSM100,000A
Fuse Coordination I2t, 60Hz I2t 4.17E+07A2s Peak One Cycle Surge Current, 50Hz, V R=0V I FSM92,500A
Fuse Coordination I2t, 50Hz I2t 3.57E+07A2s Operating Temperature Tj-40 to+175°C
Storage Temperature T Stg.-50 to+200°C
Approximate Weight 6.5lb
2.95Kg
Mounting Force16,000 - 20,000lbs
71.2 - 89.0Knewtons
Electrical Characteristics, Tj=25°C unless otherwise specified
Rating
Characteristic Symbol Test Conditions min typ max Units Repetitive Peak Reverse
Leakage Current I
Tj=175°C, V RRM=Rated150300ma
RRM
Peak On-State Voltage V FM Tj=175°C, I FM=4000A0.82V
V FM Model, Low Level V0Tj=175°C0.654V VFM = V O +r•I FM r15% I FM- π•I FM 3.82E-05Ω
V FM Model, High Level V0Tj=175°C0.786V VFM = V O +r•I FM rπ•I FM - I FSM 3.27E-05Ω
V FM Model, 4-Term A Tj=175°C0.218 V FM=A + B•Ln(I FM) +B15%I FM - I FSM 5.70E-02 C•(I FM) + D•(I FM)½C 3.14E-05
D8.51E-05
Reverse Recovery Time t RR Tj=25°C, I FM=400A25µs
di R/dt = 25 A/µs
Thermal Characteristics
Rating
Characteristic Symbol Test Conditions min typ max Units Thermal Resistance
Junction to Case RΘjc Double side cooled0.0070.0075°C/Watt
Case to Sink RΘcs Double side cooled0.0010.0015°C/Watt Thermal Impedance Model ZΘjc Double side cooled
ZΘjc(t) =Σ(A(N)•(1-exp(-t/Tau(N))))where:N =1234
A(N) = 1.426E-049.077E-04 2.373E-03 4.080E-03
T au(N) = 2.622E-03 2.313E-02 3.049E-01 3.600E+00。