SIGNALINTEGRITY（信号完整性）外文翻译

SIGNAL INTEGRITY
Raymond Y. Chen, Sigrid, Inc., Santa Clara, California
Introduction
In the realm of high-speed digital design, signal integrity has become a critical issue, and is posing increasing challenges to the design engineers. Many signal integr ity problems are electromagnetic phenomena in nature and hence related to the EMI/EMC discussions in the previous sections of this book. In this chapter, we will discuss what the typical signal integrity problems are, where they come from, why it is important to understand them and how we can analyze and solve these issues. Several software tools available at present for signal integrity analysis and current trends in this area will also be introduced.
The term Signal Integrity (SI) addresses two concerns in the electrical design aspects – the timing and the quality of the signal. Does the signal reach its destination when it is supposed to? And also, when it gets there, is it in good condition? The goal of signal integrity analysis is to ensure reliable high-speed data transmission. In a digital system, a signal is transmitted from one component to another in the form of logic 1 or 0, which is actually at certain reference voltage levels. At the input gate of a receiver, voltage above the reference value Vih is considered as logic high, while voltage below the reference value Vil is considered as logic low. Figure 14-1 shows the ideal voltage waveform in the perfect logic world, whereas Figure 14-2 shows how signal will look like in a real system. More complex data, composed of a string of bit 1 and 0s, are actually continuous voltage waveforms. The receiving component needs to sample the waveform in order to obtain the binary encoded information. The data sampling process is usually triggered by the rising edge or the falling edge of a clock signal as shown in the Figure 14-3. It is clear from the diagram that the data must arrive at the receiving gate on time and settle down to a non-ambiguous logic state when the receiving component starts to latch in. Any delay of the data or distortion of the data waveform will result in a failure of the data transmission. Imagine if the signal waveform in Figure 14-2 exhibits excessive ringing into the logic gray zone while the sampling occurs, then the logic level cannot be reliably detected.
SI Problems
T ypical SI Problems
“Timing” is everything in a high-speed system. Signal timing depends on the delay caused by the physical length that the signal must propagate. It also depends on the shape of the waveform w hen the threshold is reached. Signal waveform distortions can be caused by different mechanisms. But there are three mostly concerned noise problems:
•Reflection Noise Due to impedance mismatch, stubs, visa and other interconnect discontinuities. •Crosstalk Noise Due to electromagnetic coupling between signal traces and visa.
•Power/Ground Noise Due to parasitic of the power/ground delivery system during drivers’ simultaneous switching output (SSO). It is sometimes also called Ground Bounce, Delta-I Noise or Simultaneous Switching Noise (SSN).
Besides these three kinds of SI problems, there is other Electromagnetic Compatibility or Electromagnetic Interference (EMC/EMI) problems that may contribute to the signal waveform distortions. When SI problems happen and the system noise margin requirements are not satisfied – the input to a switching receiver makes an inflection below Vih minimum or above Vil maximum; the input to a quiet receiver rises above V il maximum or falls below Vih minimum; power/ground voltage fluctuations disturb the data in the latch, then logic error, data drop, false switching, or even system failure may occur. These types of noise faults are extremely difficult to diagnose and solve after the system is built or prototyped. Understanding and solving these problems before they occur will eliminate having to deal with them further into the project cycle,
and will in turn cut down the development cycle and reduce the cost[1]. In the later part of this
chapter, we will have further investigations on the physical behavior of these noise phenomena, their causes, their electrical models for analysis and simulation, and the ways to avoid them.
1. Where SI Problems Happen
Since the signals travel through all kinds of interconnections inside a system, any electrical impact happening at the source end, along the path, or at the receiving end, will have great effects on the signal timing and quality. In a typical digital system environment, signals originating from the off-chip drivers on the die (the chip) go through c4 or wire-bond connections to the chip package. The chip package could be single chip carrier or multi-chip module (MCM). Through the solder bumps of the chip package, signals go to the Printed Circuit Board (PCB) level. At this level, typical packaging structures include daughter card, motherboard or backplane. Then signals continue to go to another system component, such as an ASIC (Application Specific Integrated Circuit) chip, a memory module or a termination block. The chip packages, printed circuit boards, as well as the cables and connecters, form the so-called different levels of electronic packaging systems, as illustrated in Figure 14-4. In each level of the packaging structure, there are typical interconnects, such as metal traces, visa, and power/ground planes, which form electrical paths to conduct the signals. It is the packaging interconnection that ultimately influences the signal integrity of a system.
2. SI In Electronic Packaging
Technology trends toward higher speed and higher density devices have pushed the package performance to its limits. The clock rate of present personal computers is approaching gigahertz range. As signal rise-time becomes less than 200ps, the significant frequency content of digital signals extends up to at least 10 GHz. This necessitates the fabrication of interconnects and packages to be capable of supporting very fast varying and broadband signals without degrading signal integrity to unacceptable levels. While the chip design and fabrication technology have undergone a tremendous evolution: gate lengths, having scaled from 50 µm in the 1960s to 0.18 µm today, are projected to reach 0.1 µm in the next few years; on-chip clock frequency is doubling every 18 months; and the intrinsic delay of the gate is decreasing exponentially with time to a few tens of Pico-seconds. However, the package design has lagged considerably. With current technology, the package interconnection delay dominates the system timing budget and becomes the bottleneck of the high-speed system design. It is generally accepted today that package performance is one of the major limiting factors of the overall system performance.
Advances in high performance sub-micron microprocessors, the arrival of gigabit networks, and the need for broadband Internet access, necessitate the development of high performance packaging structures for reliable high-speed data transmission inside every electronics system.
Signal integrity is one of the most important factors to be considered when designing these packages (chip carriers and PCBs) and integrating these packages together.
3、SI Analysis
3.1. SI Analysis in the Design Flow
Signal integrity is not a new phenomenon and it did not always matter in the early days of the digital era. But with the explosion of the information technology and the arrival of Internet age, people need to be connected all the time through various high-speed digital communication/computing systems. In this enormous market, signal integrity analysis will play a more and more critical role to guarantee the reliable system operation of these electronics products. Without pre-layout SI guidelines, prototypes may never leave the bench; without post-layout SI verifications, products may fail in the field. Figure 14-5 shows the role of SI analysis in the high-speed design process. From this chart, we will notice that SI analysis is applied throughout the design flow and tightly integrated into each design stage. It is also very common to categorize SI analysis into two main stages: reroute analysis and post route analysis.
In the reroute stage, SI analysis can be used to select technology for I/Os, clock distributions, chip package types, component types, board stickups, pin assignments, net topologies, and termination strategies. With various design parameters considered, batch SI simulations on different corner cases will progressively formulate a set of optimized guidelines for physical designs of later stage. SI analysis at this stage is also called constraint driven SI design because the guidelines developed will be used as constraints for component placement and routing. The objective of constraint driven SI design at the reroute stage is to ensure that the signal integrity of the physical layout, which follows the placement/routing constraints for noise and timing budget, will not exceed the maximum allowable noise levels. Comprehensive and in-depth reroute SI analysis will cut down the redesign efforts and place/route iterations, and eventually reduce design cycle.
With an initial physical layout, post route SI analysis verifies the correctness of the SI design guidelines and constraints. It checks SI violations in the current design, such as reflection noise, ringing, crosstalk and ground bounce. It may also uncover SI problems that are overlooked in the reroute stage, because post route analysis works with physical layout data rather than estimated data or models, therefore it should produce more accurate simulation results.
When SI analysis is thoroughly implemented throughout the whole design process, a reliable high performance system can be achieved with fast turn-around.
In the past, physical designs generated by layout engineers were merely mechanical drawings when very little or no signal integrity issues were concerned. While the trend of higher-speed electronics system design continues, system engineers, responsible for developing a hardware system, are getting involved in SI and most likely employ design guidelines and routing constraints from signal integrity perspectives. Often, they simply do not know the answers to some of the SI problems because most of their knowledge is from the engineers doing previous generations of products. To face this challenge, nowadays, a design team (see Figure 14-6) needs to have SI engineers who are specialized in working in this emerging technology field. When a new technology is under consideration, such as a new device family or a new fabrication process for chip packages or boards, SI engineers will carry out the electrical characterization of the technology from SI perspectives, and develop layout guideline by running SI modeling and simulation software [2]. These SI tools must be accurate enough to model individual interconnections such as visa, traces, and plane stickups. And they also must be very efficient so what-if analysis with alternative driver/load models and termination schemes can be easily performed. In the end, SI engineers will determine a set of design rules and pass them to the design engineers and layout engineers. Then, the design engineers, who are responsible for the overall system design, need to ensure the design rules are successfully employed. They may run some SI simulations on a few critical nets once the board is initially placed and routed. And they may run post-layout verifications as well. The SI analysis they carry out involves many nets. Therefore, the simulation must be fast, though it may not require the kind of accuracy that SI engineers are looking for. Once the layout engineers get the placement and routing rules specified in SI terms, they need to generate an optimized physical design based on these constraints. And they will provide the report on any SI violations in a routed system using SI tools. If any violations are spotted, layout engineers will work closely with design engineers and SI engineers to solve these possible SI problems.
3.2.Principles of SI Analysis
A digital system can be examined at three levels of abstraction: log ic, circuit theory, and electromagnetic (EM) fields. The logic level, which is the highest level of those three, is where SI problems can be easily identified. EM fields, located at the lowest level of abstraction, comprise the foundation that the other levels are built upon [3]. Most of the SI problems are EM problems in nature, such as the cases of reflection, crosstalk and ground bounce. Therefore, understanding the physical behavior of SI problems from EM perspective will be very helpful. For instance, in the following multi-layer packaging structure shown in Figure 14-7, a switching current in via a will generate EM waves propagating away from that via in the radial direction between metal planes. The fields developed between metal planes will cause voltage variations between planes (voltage is the integration of the E-field). When the waves reach other visa, they will induce currents in those visa. And the induced currents in that visa will in turn generate EM waves propagating between the planes. When the waves reach the edges of the package, part of them will radiate into the air and part of them will get reflected back. When the waves bounce back and forth inside the packaging structure and superimpose to each other, resonance will occur. Wave propagation, reflection, coupling and resonance are the typical EM phenomena happening inside a packaging structure during signal transients. Even though EM full wave analysis is much more accurate than the circuit analysis in the modeling of packaging structures, currently, common approaches of interconnect modeling are based on circuit theory, and SI analysis is carried out with circuit simulators. This is because field analysis usually requires much more complicated algorithms and much larger computing resources than circuit analysis, and circuit analysis provides good SI solutions at low frequency as an electrostatic approximation.
Typical circuit simulators, such as different flavors of SPICE, employ nodal analysis and solve voltages and currents in lumped circuit elements like resistors, capacitors and inductors. In SI analysis, an interconnect sometimes will be modeled as a lumped circuit element. For instance, a piece of trace on the printed circuit board can be simply modeled as a resistor for its finite conductivity. With this lumped circuit model, the voltages along both ends of the trace are assumed to change instantaneously and the travel time for the signal to propagate between the two ends is neglected. However, if the signal propagation time along the trace has to be considered, a distributed circuit model, such as a cascaded R-L-C network, will be adopted to model the trace. To determine whether the distributed circuit model is necessary, the rule of thumb is – if the signal rise time is comparable to the round-trip propagation time, you need to consider using the distributed circuit model.
For example, a 3cm long stripling trace in a FR-4 material based printed circuit board will exhibits 200ps propagation delay. For a 33 MHz system, assuming the signal rise time to be 5ns, the trace delay may be safely ignored; however, with a system of 500 MHz and 300ps rise time, the 200ps propagation delay on the trace becomes important and a distributed circuit model has to be used to model the trace. Through this example, it is easy to see that in the high-speed design, with ever-decreasing signal rise time, distributed circuit model must be used in SI analysis.
Here is another example. Considering a pair of solid power and ground planes in a printed circuit board with the dimension of 15cm by 15cm, it is very natural to think the planes acting as a large, perfect, lumped capacitor, from the circuit theory point of view. The capacitor model C= erA/d, an electro-static solution, assumes anywhere on the plane the voltages are the same and all the charges stored are available instantaneously anywhere along the plane. This is true at DC and low frequency. However, when the logics switch with a rise time of 300ps, drawing a large amount of transient currents from the power/ground planes, they perceive the power/ground structure as a two-dimensional distributed network with significant delays. Only some portion of the plane charges located within a small radius of the switching logics will be able to supply the demand. And voltages between the power/ground planes will have variations at different locations. In this case, an ideal lumped capacitor model is obviously not going to account for the propagation effects. Two-dimensional distributed R-L-C circuit networks must be used to model the power/ground pair.
In summary, as the current high-speed design trend continues, fast rise time reveals the distributed nature of package interconnects. Distributed circuit models need to be adopted to simulate the propagation delay in SI analysis. However, at higher frequencies, even the distributed circuit modeling techniques are not good enough, full wave electromagnetic field analysis based on solving Maxwell’s equations must come to play. As presen ted in later discussions, a trace will not be modeled as a lumped resistor, or a R-L-C ladder; it will be analyzed based upon transmission line theory; and a power/ground plane pair will be treated as a parallel-plate wave guide using radial transmission line theory.
Transmission line theory is one of the most useful concepts in today’s SI analysis. And it is a basic topic in many introductory EM textbooks. For more information on the selective reading materials, please refer to the Resource Center in Chapter 16.
In the above discussion, it can be noticed that signal rise time is a very important quantity in SI issues. So a little more expanded discussion on rise time will be given in the next section.
信号完整性
介绍
在高速数字设计领域，信号完整性已经成为一个严重的问题，是造成越来越多的挑战的设计工程师。

许多信号完整性问题是电磁现象的性质，因此有关的EMI / EMC公SI 在本书的前几节的讨论。

在这一章中，我们将讨论什么是典型的信号完整性问题，他们来自哪里，为什么它是重要的，了解他们，我们如何能够分析和解决这些问题。

在几个软件工具的信号完整性分析和在这一领域目前的趋势目前可将同时推出。

这个词的信号完整性（SI）的两个问题解决在电气设计方面- 的时机和信号的质量。

是否信号到达目的地时，应该？还有，当它到达的是，是否完好？对信号完整性分析的目标是确保可靠的高速数据传输。

在数字系统中，信号从一个组件传输到另一个逻辑1或0，这实际上是在一定的参考电压等级的形式。

在一个接收器输入门，高于参考值Vih认为是逻辑高电压，而电压低于参考值村子里为逻辑低考虑。

图14-1显示了完美的逻辑理想的电压波形的世界，而图14-2显示了如何在信号的外观像一个真正的系统。

更复杂的数据，1位1和0组成的字符串，实际上是连续的电压波形。

接收组件需要样品的波形，以获取二进制编码信息。

数据采样过程通常是由上升沿或时钟信号的下降沿触发，如图14-3所示。

它是从图中的数据表明，必须在规定的时间到达接收门，定居下来到非模糊逻辑状态时，接收组件开始锁存英寸的任何数据或数据波形失真延迟将导致1数据传输失败。

想象一下，如果在信号波形图14-2展示过度到逻辑铃声灰色地带，而取样时，则逻辑水平不能可靠地检测到。

SI的问题
1.Typical SI 问题
“时机”是一切高速系统。

信号的时间取决于由物理长度的信号传播造成一定的延误。

这也取决于对达到阈值时，波形的形状。

信号波形畸变可能造成不同的机制。

但是，有三个主要涉及噪音问题：
•反射噪音由于阻抗不匹配，存根，过孔和其它互连的不连续性。

•由于串扰噪声信号跟踪和过孔之间的电磁耦合。

•电源/地噪声，由于电力寄生/地在SI 机的同步开关输出（SSO）的输送系统。

它有时也被称为地弹跳，三角洲，我噪声或同步开关噪声（SSN）。

除了这三种SI 的问题，还有其他的电磁兼容性或电磁干扰（电磁兼容/电磁干扰）问题，可能导致信号波形失真。

当问题发生，SI 系统噪声保证金要求得不到满足- 输入接收到一个开关，使低于Vih最低或以上村子里最大转折点;到一个以上的村子里的最高安静接收上升输入或以下Vih最低下降;电源/地电压波动干扰的锁存数据，然后逻辑错误，数据下降，虚假切换，甚至可能会出现系统故障。

这些类型的噪声故障是很难诊断和解决系统建成后，或原型。

认识和解决这些问题发生之前将消除与他们不必处理到项目周期进一步，反过来会减少开发周期，降低成本[1]。

在本章的稍后部分，我们将会对这些噪音现象物理行为作进一步调查，其原因，他们的电气模型进行分析和模拟，以及如何避免它们。

2、SI问题出现在哪里
由于信号的传播，通过系统内所有的互连种，任何电器的影响发生在源端，沿路径，或在接收端，都会对信号的时间和质量影响很大。

在一个典型的数字系统环境中，信号从芯片上的片外驱动原（即芯片）经过C4或焊线连接到芯片封装。

该芯片是单芯片封装可以承运人或者多芯片模块（MCM）。

通过对芯片封装焊料凸点，信号到印刷电路板（PCB）的水平。

在这个级别，典型包装结构包括子卡，主板或背板。

然后信号继续到另一个系统的组成部分，例如一个ASIC（专用集成电路）芯片，内存模块或终止块。

该芯片封装，印刷电路板，以及电缆和电脑连接，形成了电子包装系统所谓的不同层次，如图14-4所示。

在每个包装的结构，水平有是典型的互连，如金属痕迹，过孔和电源/地平面，形成电气通路进行信号。

这是包装的互连，最终影响了系统的信号完整性。

2、元件封装的SI
向更高的速度和更高密度器件技术的发展趋势已推动了包的性能极限。

目前个人电脑的时钟频率是接近千兆赫兹范围。

由于信号上升时间小于200ps变得，数字信号的重要内容，频率延伸到至少10千兆赫。

这就需要对制造和封装互连是支持非常快变，在不影响信号完整性，不可接受的水平宽带信号。

虽然芯片设计和制造技术已发生了巨大的变化：门长，有50微米尺度在20世纪60年代至0.18微米的今天，预计将在未来数达到年0.1微米，对芯片的时钟频率是每18倍个月，以及内在的门延迟随时间呈指数下降至微微秒的数万元不等。

但是，包装设计已经相当落后。

随着当前
技术，封装互连延迟主导系统时序预算，并成为在高速系统设计的瓶颈。

人们普遍接受的今天，包装性能是主要限制了系统整体性能的因素之一。

在高性能亚微米微处理器的进步，千兆网络的到来，以及宽带互联网接入的需要，有必要对质量可靠的高速数据传输系统内每一个电子的高性能包装结构的发展。

信号完整性是最重要的因素之一，设计时考虑这些包（芯片载体和PCBs）和整合这些包一起。

3、SI分析
3.1、SI分析的设计流程
信号完整性是不是一个新现象，它并不总是问题在数码时代的初期。

但是，随着信息技术爆炸，互联网时代的到来，人们需要通过各种连接高速数字通信的所有时间/计算机系统。

在这个巨大的市场，信号完整性分析将发挥越来越重要的作用，以保证这些电子产品的可靠系统的运作。

如果没有预先布局SI 指导方针，原型可能永远不会离开板凳，没有专SI 核查布局，产品可能无法在外地。

图14-5显示了高速设计过程中的SI分析的作用。

从这个图表，我们会发现，SI分析是适用于整个设计流程和紧密集成到每个设计阶段。

这也是很常见的分类主要分为两个阶段：preroute分析和postroute分析SI分析。

在preroute阶段，SI分析可以用来选择，因为我的技术/ O口，时钟分配芯片封装类型，组件类型，板stackups，引脚分配，网拓扑结构，并终止战略。

随着各种设计考虑的参数，在不同的角落一批案件SI 模拟将逐步制定一套适用于稍后阶段的物理设计优化的指引。

SI 在此阶段的分析也被称为驱动SI 设计
约束的准则，因为发达国家将作为组件布局布线的限制使用。

目标驱动的约束在preroute阶段SI 设计是确保物理布局，遵循/路由噪声和时序预算约束布局讯号完整性，不会超过最大允许的噪音水平。

全面和深入的preroute SI分析将努力减少重新设计和地点/路由迭代，并最终缩短设计周期。

有了一个初步的物理布局，postroute SI分析，验证了设计准则的SI和限制的正确性。

它检查SI 反映噪音行为，如在目前的设计，振铃，串扰和地面反弹。

它也可能发现SI 是忽视的问题
在preroute阶段，因为数据，而不是估计或模型的物理布局数据postroute分析工作，因此它应该产生更准确的模拟结果。

当SI分析是彻底贯穿整个设计过程中，实现可靠的高性能系统可以实现快速掉头。

由工程师在布局所产生的过去，仅仅是物理设计的机械图纸时很少或根本没有信号完整性问题的关注。

虽然更高速度的电子系统设计的趋势继续下去，系统工程师，负责开发一个硬件系统，越来越涉及在SI和最可能采用的设计准则和路由信号完整性角度的限制。

通常情况下，他们根本不知道到的SI一些问题的答案，因为他们的知识，其中大部分来自前代产品做工程师的。

面对这一挑战，现在，一个设计团队（见图14-6）需要有圣莱科特谁是在这一新兴技术领域工作的专业工程师。

当一种新技术正在考虑一个新的设备，如家庭或一个新的芯片封装或板制造过程中，SI 工程师将开展的角度，从SI技术电特性，并通过运行SI 开发建模和仿真布局指引软件[2]。

这些SI 工具必须足够精确的模型，如孔，跟踪个人互连，和飞机stickups。

他们还必须非常高效，从而假设分析与替代驱动器/负荷模型和终止计划，可以很容易地进行。

最后，SI 工程师将确定的设计规则，并通过他们的设计工程师和设计工程师。

然后，设计工程师，谁是负责整个系统的设计，必须确保设计规则是成功就业。

他们可以运行在几个关键的一次模拟网的一些SI 董事会最初放置和路由。

他们可能运行后布局验证以及。

分析他们的SI进行涉及许多网。

因此，模拟必须快，但不得要求的精度那种SI 的工程师正在寻找。

一旦设计工程师们的安置和在SI方面指定的路由规则，它们需要生成一个优化的物理设计基于这些限制。

他们将提供在任何一个路由系统用硅工具SI 侵犯的报告。

如果发现有任何侵犯，布局工程师将与设计工程师和系统集成工程师密切合作，以解决这些可能的SI 的问题。

3.2、SI分析原则
数字系统可以在三个层次研究的抽象：逻辑，电路理论，电磁（EM）的领域。

逻辑电平，这是这三个最高水平，正是SI 问题就容易识别。

电磁场，在抽象位于最低水平，包括水平，其他经[3]的基础。

该SI 的问题大多是电磁性质的问题，如反映的情况，串扰和地面反弹。

因此，了解问题，从新兴市场的角度SI 物理行为将是非常有益的。

例如，在下面的多层包装结构如图14-7，通过一个开关电流会产生电磁波传播距离，在金属面之间通过在径向方向显示。

金属之间的飞机开发的领域会导致飞机之间的电压变化（电压是电场集成）。

当波到达其他通孔，它们将诱导电流的通孔。

在那些过孔的感应电流会产生电磁波，从而飞机之间的传播。

当波到达的包边，其中一部分将辐射到空气中，其中一部分将被反射回来。

当海浪来回反弹内包装结构和相互叠加，共振会发生。

波的传播，反射，耦合共振现象是典型的电磁信号瞬变期间内包装结构发生。

虽然电磁全波分析远比在包装结构，目前，普通的互连模型建模方法准确电路分析是基于电路理论，和SI进行分析与电路模拟出来。

这是因为场分析通常需要更复杂的算法和
电路分析比大得多的计算资源，并作为电路分析提供了一个良好的低频静电近似SI 的解决方案。

典型的电路模拟器，如SPICE的不同口味，采用节点分析和解决电压和集总电路元件如电阻，电流，电容器和电感器。

在SI分析，互连有时将作为一个集总电路元件为蓝本。

举例来说，微量的印刷电路板一块可以简单地模仿其作为有限导电电阻。

有了这个集总电路模型，沿着痕迹两端的电压被假定为瞬时变化的信号和传播两端之间的旅行时间是被忽视的。

但是，如果沿着必须考虑，分布式电路模型，如级联RLC网络，跟踪信号传播时间，将采用模型跟踪。

要确定是否分布式电路模型是必要的，经验法则是- 如果信号的上升时间是相当于往返传播时间，你需要考虑使用分布式电路模型。

例如，一个3厘米长的带状线微量元素的的FR - 4印刷电路板材料的基础将展品200ps传输延时。

对于一个33 MHz系统，假设信号的上升时间来为5ns，跟踪延迟可以安全地忽略，但是，一个500兆赫，仅为300ps上升时间，就成为重要的跟踪和分布式电路模型200ps传输延时系统已被用来模型跟踪。

通过这个例子，可以很容易地看到，在高速设计，不断降低信号的上升时间，分布式电路模型必须在SI分析。

下面是另一个例子。

考虑到印刷电路板所用的15厘米15厘米尺寸的固体电源和地平面对，这是很自然的认为，作为一个大型飞机，完善，集总电容从电路理论的观点来看，。

电容模型C =时代/ D有静电解决方案，在飞机上的任何地方承担的电压是相同的，所有的费用，可随时随地存储沿面瞬间。

这才是真正的直流和低频。

然而，当一个逻辑开关，仅为300ps上升时间，吸取/地平面的权力大量的瞬态电流，他们认为权力/作为一个二维分布式网络与地面结构重大延误。

只有一些飞机的部分费用的开关设在一个小半径逻辑将能够满足需求。

与电源/地平面的电压将在不同地点的变化。

在这种情况下，一个理想的集总电容模型，显然是不会考虑的传播效应。

二维分布RLC电路必须使用网络模型的电源/地对。

总之，作为当前的高速设计的趋势继续下去，快速上升时间揭示了包分配的性质互连。

分布式电路模型需要通过模拟分析，在SI的传播延迟。

然而，在更高的频率，甚至分布式电路建模技术并不好不够，全波电磁场分析解决麦克斯韦方程组必须开始发挥基础。

由于在以后的讨论中，提出将不跟踪建模为一个集总电阻，或观RLC梯子，它会分析基于传输线理论和A /接地平面对将作为一个平行板波对待权力使用指南径向传输线理论。

传输线理论，是在今天的SI分析中最有用的概念之一。

它是许多新兴市场入门教科书的基本主题。

欲了解更多有关选择性阅读材料的资料，请参阅第16章资源中心。

在上面的讨论中，可以看到，信号的上升时间是很重要的问题在SI数量。

因此，多一点的时间就上升扩大讨论将刊载于下一节。