74LVQ14SJX资料

© 2001 Fairchild Semiconductor Corporation DS011345
February 1992Revised June 2001
74LVQ14 Low Voltage Hex Inverter with Schmitt Trigger Input
74LVQ14
Low Voltage Hex Inverter with Schmitt Trigger Input
General Description
The LVQ14 contains six inverter gates each with a Schmitt trigger input. They are capable of transforming slowly changing input signals into sharply defined, jitter-free out-put signals. In addition, they have a greater noise margin than conventional inverters.
The LVQ14 has hysteresis between the positive-going and negative-going input thresholds (typically 1.0V) which is determined internally by transistor ratios and is essentially insensitive to temperature and supply voltage variations.Features
s Ideal for low power/low noise 3.3V applications
s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Guaranteed incident wave switching into 75Ω
Ordering Code:
Devices also available in T ape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Truth Table
H = HIGH Voltage Level L = LOW Voltage Level
Order Number Package Number
Package Description
74LVQ14SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVQ14SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Pin Names
Description I n Inputs O n
Outputs
Input Output I O L H H
L
2
74L V Q 14
Absolute Maximum Ratings (Note 1)
Recommended Operating Conditions (Note 2)
Note 1: The “Absolute Maximum Ratings ” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings.The “Recommended Operating Conditions ” table will define the conditions for actual device operation.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Note 3: All outputs loaded; thresholds on input associated with output under test.Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed for 74LVQ.Note 6: Worst case package.
Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND.
Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (V ILD ), 0V to threshold (V IHD ), f = 1 MHz.
Supply Voltage (V CC ) −0.5V to +7.0V
DC Input Diode Current (I IK ) V I = −0.5V −20 mA
V I = V CC + 0.5V
+20 mA
DC Input Voltage (V I )
−0.5V to V CC + 0.5V
DC Output Diode Current (I OK ) V O = −0.5V −20 mA
V O = V CC + 0.5V
+20 mA
DC Output Voltage (V O ) −0.5V to V CC + 0.5V
DC Output Source
or Sink Current (I O ) ±50 mA DC V CC or Ground Current (I CC or I GND )
±200 mA
Storage Temperature (T STG ) −65°C to +150°C DC Latch-Up Source or Sink Current
±100 mA Supply Voltage (V CC ) LVQ
2.0V to
3.6V Input Voltage (V I ) 0V to V CC Output Voltage (V O ) 0V to V CC
Operating Temperature (T A )−40°C to +85°C
Minimum Input Edge Rate (∆V/∆t) V IN from 0.8V to 2.0V V CC @ 3.0V
125 mV/ns
Symbol Parameter
V CC T A = +25°C T A = −40°C to +85°C Units Conditions
(V)Typ Guaranteed Limits
V OH
Minimum High Level 3.0 2.99
2.9 2.9V I OUT = −50 µA
Output Voltage
3.0 2.58 2.48V V IN = V IL or V IH (Note 3)I OH = −12 mA V OL
Maximum Low Level 3.00.002
0.10.1V I OUT = 50 µA
Output Voltage
3.00.360.44V V IN = V IL or V IH (Note 3)I OL = 12 mA I IN Maximum Input Leakage Current 3.6±0.1±1.0µA V I = V CC , GND V t +Maximum Positive Threshold 3.0 2.2 2.2V T A = Worst Case V t −Minimum Negative Threshold 3.00.50.5V T A = Worst Case V h(max)Maximum Hysteresis 3.0 1.2 1.2V T A = Worst Case V h(min)Minimum Hysteresis 3.00.3
0.3V T A = Worst Case
I OLD Minimum Dynamic 3.636mA V OLD = 0.8V Max (Note 5)I OHD Output Current (Note 4) 3.6−25mA V OHD = 2.0V Min (Note 5)I CC Maximum Quiescent 3.6 2.020.0
µA V IN = V CC or GND Supply Current V OLP Quiet Output
3.30.9 1.1V (Note 6)(Note 7)Maximum Dynamic V OL V OLV Quiet Output
3.3−0.8−1.1V (Note 6)(Note 7)Minimum Dynamic V OL V IHD Maximum High Level 3.3 1.9 2.0V (Note 6)(Note 8)Dynamic Input Voltage V ILD
Maximum Low Level 3.3
1.3
2.0
V
(Note 6)(Note 8)
Dynamic Input Voltage
74LVQ14
AC Electrical Characteristics
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t OSHL ) or LOW-to-HIGH (t OSLH ). Parameter guaranteed by design.
Capacitance
Note 10: C PD is measured at 10 MHz.
Symbol Parameter
T A = +25°C
T A = −40°C to +85°C
Units
V CC C L = 50 pF
C L = 50 pF (V)Min Typ Max Min Max t PLH Propagation Delay 2.7 1.511.419.0 1.521.0ns 3.3 ± 0.3 1.59.513.5 1.515.0t PHL Propagation Delay 2.7 1.59.016.2 1.519.0ns 3.3 ± 0.3 1.5
7.511.5 1.5
13.0t OSHL,Output to Output Skew 2.7 1.0 1.5 1.5ns t OSLH
Data to Output (Note 9)
3.3 ± 0.3
1.0
1.5
1.5
Symbol Parameter
Typ Units Conditions
C IN
Input Capacitance
4.5pF V CC = Open C PD (Note 10)
Power Dissipation Capacitance
20
pF
V CC = 3.3V
4
74L V Q 14
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
5
74LVQ14 Low Voltage Hex Inverter with Schmitt Trigger Input
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICY
FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user.
2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。