FPGA可编程逻辑器件芯片XC2V6000-4FFG1152C中文规格书

Chapter 2
Configuration Interfaces
Virtex ®-5 devices have six configuration interfaces. Each configuration interface
corresponds to one or more configuration modes and bus width, shown in Table 2-1. For detailed interface timing information, see DS202, Virtex-5 FPGA Data Sheet: DC and Switching Characteristic .
Serial Configuration Interface
In serial configuration modes, the FPGA is configured by loading one configuration bit per CCLK cycle:∙In Master Serial mode, CCLK is an output.∙
In Slave Serial mode, CCLK is an input.
Figure 2-1 shows the basic Virtex-5 serial configuration interface.There are four methods of configuring an FPGA in serial mode:∙Master serial configuration ∙Slave serial configuration ∙
Serial daisy-chain configuration
Table 2-1:Virtex-5 Device Configuration Modes
Configuration Mode M[2:0]Bus Width
CCLK Direction
Master Serial (2)0001Output Master SPI (2)0011Output Master BPI-Up (2)0108, 16Output Master BPI-Down (2)0118, 16Output Master SelectMAP (2)1008, 16Output JTAG
1011Input (TCK)Slave SelectMAP 1108, 16, 32
Input Slave Serial
111
1
Input
Notes:
1.Parallel configuration mode bus is auto-detected by the configuration logic.
2.In Master configuration mode, the CCLK pin is the clock source for the Virtex-5 internal configuration logic. The Virtex-5 CCLK output pin must be free from reflections to avoid double-clocking the
internal configuration logic. Refer to the “Board Layout for Configuration Clock (CCLK)” section for more details.
Ganged serial configuration
Table 2-2 describes the Serial Configuration Interface.
Figure 2-1:Virtex-5 FPGA Serial Configuration Interface
Table 2-2:Virtex-5 FPGA Serial Configuration Interface Pins Pin Name
Type
Dedicated or Dual-Purpose
Description
M[2:0]Input Dedicated Mode Pins – determine configuration mode CCLK Input or Output Dedicated Configuration clock source for all configuration modes except JTAG
D_IN Input Dedicated Serial configuration data input, synchronous to rising CCLK edge
DOUT_BUSY
Output
Dedicated
Serial data output for downstream daisy-chained devices
DONE
Bidirectional, Open-Drain, or Active
Dedicated
Active High signal indicating configuration is complete:
0 = FPGA not configured 1 = FPGA configured
Refer to the BitGen section of the Development System Reference Guide for software settings. INIT_B
Input or Output, Open-Drain
Dedicated
Before the Mode pins are sampled, INIT_B is an input that can be held Low to delay configuration.
After the Mode pins are sampled, INIT_B is an open-drain active Low output indicating whether a CRC error occurred during configuration:0 = CRC error 1 = No CRC error
PROGRAM_B Input Dedicated Active-Low asynchronous full-chip reset
DOUT
DONE
CCLK
PROGRAM_B
INIT_B
D_IN M[2:0]
UG191_c2_01_072407
Byte Peripheral Interface Parallel Flash Mode
Byte Peripheral Interface Parallel Flash Mode
In BPI-Up (M[2:0]=010) or BPI-Down (M[2:0]=011) mode, the Virtex-5 FPGA configures itself from an industry-standard parallel NOR Flash PROM, as illustrated in Figure 2-22. The FPGA drives up to 26 address lines to access the attached parallel Flash. For
configuration, only async read mode is used, where the FPGA drives the address bus, and the Flash PROM drives back the bitstream data. Bus widths of x8 and x16 are supported. Bus widths are auto detected, as described in “Bus Width Auto Detection.” Refer to DS617, Platform Flash XL High-Density Configuration and Storage Device data sheet for the BPI-compatible Flash device from Xilinx.
In BPI modes, the CCLK output is not connected to the BPI Flash device. However, Flash data is still sampled on the rising edge of CCLK. The CCLK output is driven during the BPI modes and therefore must receive the same parallel termination as in the other Master modes. See “Board Layout for Configuration Clock (CCLK),” page 73. The timing parameters related to BPI use CCLK as a reference. Virtex-5 BPI modes also support asynchronous page-mode reads to allow an increase in the CCLK frequency. See “Page Mode Support,” page 71 for details.
In the BPI-Up mode, the address starts at 0 and increments by 1 until the DONE pin is asserted. If the address reaches the maximum value (26’h3FFFFFF) and configuration is not done (DONE is not asserted), an error flag is raised in the status register, and fallback reconfiguration starts. See “Fallback MultiBoot,” page 153.
In the BPI-Down mode, the address start at 26’h3FFFFFF and decrements by 1 until the DONE pin is asserted. If the address reaches the bottom (26’h0), and configuration is still not done (DONE is not asserted), an error flag is raised in the status register and fallback reconfiguration starts. See “Fallback MultiBoot,” page 153.
Additional notes related to Figure 2-22:∙M[2:0]=010 for BPI-Up mode and M[2:0]=011 for BPI-Down mode.
∙
Figure 2-22 shows the x16 BPI interface. For x8 BPI interfaces, only D[7:0] are used.See “Bus Width Auto Detection.”
Figure 2-22:Virtex-5 BPI Configuration Interface
UG191_c2_25_061108
4.7 k Note: The BPI Flash vendor data sheet should be referred to for details on the specific Flash signal connectivity.
To prevent address misalignment, close attention should be paid to the Flash family address LSB for the byte/word mode used. Not all Flash families use the A0 as the address LSB.
Board Layout for Configuration Clock (CCLK)。