接口软件说明书clock
iclock server使用指南
iClock Server使用指南版本：1.0日期：2008年10月适用机型:iClock300、iClock360、iClock660、iClock2500、iClock2800等机型。
内容介绍本文档主要介绍了iClock Server 系列产品的使用说明，包括软件的安装与卸载，iClock Server的适用。
重要申明首先感谢您选择本系列产品。
在使用前，请您仔细阅读本产品的说明书。
以避免设备受到不必要的损害！本公司提醒您正确使用，将得到良好的使用效果和验证速度。
非经ZKSoftware书面同意，任何单位和个人不得擅自摘抄、复制本手册内容的部分或全部，并不得以任何形式传播。
本手册中描述的产品中，可能包含ZKSoftware及其可能存在的许可人享有版权的软件，除非获得相关权利人的许可，否则，任何人不能以任何形式对前述软件进行复制、分发、修改、摘录、反编译、反汇编、解密、反向工程、出租、转让、分许可以及其他侵权软件版权的行为，但是适用法禁止此类限制的除外。
目录1. iClock Server安装与卸载 (1)1.1 软件的安装 (1)1.2 软件的卸载 (5)2. 登录iClock Server (6)2.1 iClock Server管理 (6)2.2 系统登录及注销 (7)2.3 语言选择 (8)2.4 密码修改 (8)3. iClock Server的使用 (10)3.1 快速使用 (10)3.2 设备管理 (10)3.2.1 设备维护与管理 (10)3.2.2 设备操作日志 (15)3.2.3 实时记录监控 (16)3.3 数据维护 (17)3.3.1 部门管理 (17)3.3.2 人员管理 (19)3.3.3 考勤记录 (24)3.4 系统日志 (27)3.4.1 设备上传数据日志 (27)3.4.2 服务器下发命令日志 (28)3.4.3 管理员操作日志 (30)3.4.4 系统管理员维护 (31)附录 (35)附录1 如何将终端设备连入网络 (35)附录2 常用操作 (37)1. iClock Server安装与卸载1.1 软件的安装1、将安装光盘放入光驱，安装程序会自动运行。
AT32F403A 407时钟配置入门指南说明书
AN0082入门指南AT32F403A/407时钟配置前言本应用入门指南主要介绍两部分内容：1、基于雅特力提供的V2.x.x的板级支持包来进行时钟源码的配置及修改2、如何使用配套的时钟配置工具来进行时钟路径及参数的设定，生成相应的时钟流程代码并使用。
支持型号列表：AT32F403Axx支持型号AT32F407xx目录1简介 (6)2时钟树 (7)3代码配置解析 (9)3.1函数接口 (9)3.2时钟配置流程 (10)3.2.1复位（CRM Reset） (10)3.2.2时钟源配置（Clock Source Configuration） (10)3.2.3PLL配置（PLL Configuration） (11)3.2.4总线分频（Set Bus Frequency Division） (11)3.2.5切换系统时钟（Switch System Clock） (11)3.2.6更新核心频率（Update Core Frequency） (12)3.3时钟配置示例 (13)4时钟工具 (14)4.1环境要求 (14)4.2安装 (14)4.3功能介绍 (14)4.4菜单栏 (15)4.5新建配置项目 (15)4.6配置界面的使用 (16)4.7生成代码 (18)5注意事项 (19)5.1外部时钟源(HEXT)修改 (19)5.2工具使用 (19)6案例系统时钟切换 (20)6.1功能简介 (20)6.2资源准备 (20)6.3软件设计 (20)6.4实验效果 (22)7案例时钟失效检测 (23)7.1功能简介 (23)7.2资源准备 (23)7.3软件设计 (23)7.4实验效果 (24)8文档版本历史 (25)表1. 文档版本历史 (25)图1. 时钟框图 (7)图2. 时钟配置流程图 (10)图3. 启动界面 (14)图4. 配置界面 (15)图5. 菜单栏 (15)图6. MCU选择界面 (16)图7. 配置界面框架 (16)图8. 时钟配置框 (17)1 简介时钟是芯片正确高效运行的基础，正确的时钟配置是芯片能正确运行的必要条件，其重要性不言而喻。
Matrox Solios eCL XCL摄像头接口应用说明书
Photonfocus MV-D1024-28-CL-10 October 5, 2006 Basics about thecameraCamera DescriptionsEffective resolution: 1024 × 1024 × 10-bit @ 27 fps.Camera Link BASE interface (10-bit, single tap).Progressive scan.Internal sync.Internal exposure control.28 MHz pixel clock rate.Mode of operations as per Matrox Imaging (in parentheses as per camera manufacturer)Interface ModeContinuous (Free Running) Pseudo-continuous (Trigger) Asynchronous reset (Trigger)Basics about theinterface modesCamera Interface BriefsMode 1: Continuous1024 × 1024 × 10-bit @ 27 fps.Camera Link BASE interface (10-bit, single tap).Matrox Solios eCL/XCL receiving LVAL, FVAL, PIXEL CLOCK (CLK @28 MHz) and video from camera.DCF used: MVD102428CL10_1024x1024_10bitCon.DCFMode 2: Pseudo-continuous1024 × 1024 × 10-bit.Camera Link BASE interface (10-bit, single tap).Matrox Solios eCL/XCL sending EXPOSURE1 (CC1) signal to camera toinitiate and control the exposure.Matrox Solios eCL/XCL receiving LVAL, FVAL, PIXEL CLOCK (CLK @28 MHz) and video from camera.DCF used: MVD102428CL10_1024x1024_10bitPcon.DCFContinued…Photonfocus MV-D1024-28-CL-10 October 5, 2006 Basics about theCamera Interface Briefs (cont.)interface modesMode 2: Pseudo-continuousMode 3: Asynchronous reset1024 × 1024 × 10-bit.Camera Link BASE interface (10-bit, single tap).Matrox Solios eCL/XCL receiving external trigger signal.Matrox Solios eCL/XCL sending EXPOSURE1 (CC1) signal to camera toinitiate and control the exposure.Matrox Solios eCL/XCL receiving LVAL, FVAL, PIXEL CLOCK (CLK @28 MHz) and video from camera.DCF used: MVD102428CL10_1024x1024_10bitAsync.DCFPhotonfocus MV-D1024-28-CL-10 October 5, 2006 Specifics about theCamera Interface Detailsinterface modesMode 1: ContinuousFrame rate: Matrox Solios eCL/XCL receives the continuous video fromthe camera at 27 frames per second. To increase the frame rate, reduceexposure time in the PhotonFocus PFRemote Camera Configurationutility (PFRemote.EXE).Exposure time: Exposure time is determined by the Exposure TimeField setting in the PFRemote utility. Refer to the camera manual formore information.Camera settings: The camera mode is set to the following setting in thePFRemote utility. Refer to the camera manual for more information.Mode SettingTrigger Free RunningOutput 10-bitConstant Frame Rate uncheckedMode 2: Pseudo-continuousFrame rate: The frame rate is determined by the frequency of theEXPOSURE1 (CC1) signal.Exposure time: The EXPOSURE1 (CC1) signal active duration (high tolow) initiates and controls the camera’s internal exposure time. To modifythe exposure time, in Matrox Intellicam change the Timer 1 value in theDCF or use the MIL MdigControl function. Refer to the MIL on-line Helpfor more information.Camera settings: The camera mode is set to the following setting in thePFRemote utility. Refer to the camera manual for more information.Mode SettingTrigger External TriggerOutput 10-bitSYNC Pulse Active High checkedCombined trigger/exposure checkedConstant Frame Rate uncheckedPhotonfocus MV-D1024-28-CL-10 October 5, 2006 Specifics about theCamera Interface Details (cont.)interface modesMode 3: Asynchronous Reset▪Frame rate: The frame rate is determined by the frequency of theexternal trigger signal. The period between the external trigger signalsmust be larger than the frame readout period and the exposure time.▪Exposure time: Refer to Mode 2: Pseudo-continuous.▪Camera settings: Refer to Mode 2: Pseudo-continuous.Cabling details for theCabling Requirementsinterface modesMode 1 and 2: Continuous and Pseudo-continuous▪Cable and Connection: Standard Camera Link cable.Mode 2: Asynchronous reset▪Cable and Connection: Standard Camera Link.▪External trigger: External trigger should be connected to the OPTOTRIG input of the 9-pin connector (pins 7 and 2) on the Expanded I/Oadapter bracket.EXPANDED I/O BRACKET(9-pin connector) External Trigger SourceOPTOTRIG + 07 ←SIGNAL --OPTOTRIG - 02 ←GROUND --The DCFs mentioned in this application note are also attached (embedded) to this PDF file – use the Adobe Reader’s View File Attachment to access the DCF files. The information furnished by Matrox Electronics System, Ltd. is believed to be accurate and reliable. Please verify all interface connections with camera documentation or manual. Contact your local sales representative or Matrox Sales office or Matrox Imaging Applications at 514-822-6061 for assistance. © Matrox Electronic Systems Ltd, 2006-2011.Matrox Electronic Systems Ltd.1055 St. Regis Blvd.Dorval, Quebec H9P 2T4CanadaTel: (514) 685-2630Fax: (514) 822-6273。
Aurora接口使用说明
在AMC-2C667X平台上使用FPGA的Aurora接口说明声明：本文档仅面向初学者。
1、针对平台用的V6芯片型号新建一个ISE工程，工程中加入Aurora IP核，IP核的设置如下（当然也可以选择其他设置，以下均是针对本测试设置而言）图1主要参数：lanes-通道数，即使用的GTX收发器个数Lane width:aurora 核与用户接口的数据位宽（一般可选2B或者4B）Lane rate:Aurora核的对外通信速率，由于采用8B/10B编码，实际有效速率要乘以0.8。
GT REFCLK:GTX参考时钟频率采用全双工，流水通信模式。
详细请参考Aurora的UG。
好了，最后一页了，这IP核设置够简单吧！！！（一共才两页好伐…），让你选择GTX位置平台上的V6片子一共有6组GTX QUAD，每个QUAD有4个GTX，选择一个GTX与平台的SFP+ F2相连，平台说明书写清楚了，是MGT_113_1，就是它了。
生成了这个核以后，核的文件夹下会多出一堆文件，这就是XILINX给你的一个示例工程-example design.图3接下来就可以仿真啦。
仿真：你可以直接使用它提供的testbench仿真，没问题。
但是有更简单的方法，其实你仿真只是为了看看它的时序，看看你加的东西对不对，因为只要你加对了，仿真一定通过。
那么简单的方法呢？打开modelsim，不要告诉我你没装，或者装了没有关联ISE仿真库，那你得先把这个问题解决了再说。
好了之后，新建一个modelsim工程（file-new…）在你之前那堆文件的/simulation/functional文件夹下，看图说话~下一个界面叫你create new files啥的直接close。
然后你就在modelsim命令窗口轻轻地敲了一行命令：do simulate_mti.do这个simulate_mti.do就是人家已经仿真好的仿真文件，就在那个文件夹里，意思就是我仿好了，你拿去用吧，看看就好，没什么技术含量。
ICS557-01 Datasheet说明书
PCI-EXPRESS CLOCK SOURCEDescriptionThe ICS557-01 is a clock chip designed for use inPCI-Express Cards as a clock source. It provides a pair of differential outputs at 100 MHz in a small 8-pin SOIC package.Using IDT’s patented Phase-Locked Loop (PLL) techniques, the device takes a 25 MHz crystal input and produces HCSL (Host Clock Signal Level) differential outputs at 100 MHz clock frequency. LVDS signal levels can also be supported via an alternative termination scheme.Features•Supports PCI-Express TM HCSL Outputs0.7 V current mode differential pair •Supports LVDS Output Levels•Packaged in 8-pin SOIC•RoHS 5 (green ) or RoHS 6 (green and lead free) compliant packaging•Operating voltage of 3.3 V•Low power consumption•Input frequency of 25 MHz•Short term jitter 100 ps (peak-to-peak)•Output Enable via pin selection•Industrial temperature range availableBlock DiagramPin Assignment Pin DescriptionsPin NumberPinNamePinTypePin Description1OE Input Output Enable signal(H = outputs are enabled, L = outputs are disabled/tristated).Internal pull-up resistor.2X1Input Crystal or clock input. Connect to a 25 MHz crystal or single ended clock. 3X2XO Crystal Connection. Connect to a parallel mode crystal.Leave floating if clock input.4GND Power Connect to ground.5IREF Output A 475Ω precision resistor connected between this pin and groundestablishes the external reference current.6CLK Output HCSL differential complementary clock output.7CLK Output HCSL differential clock output.8VDD Power Connect to +3.3 V.Applications Information External ComponentsA minimum number of external components are required for proper operation.Decoupling CapacitorsDecoupling capacitors of 0.01 μF should be connected between VDD and the ground plane (pin 4) as close to the VDD pin as possible. Do not share ground vias between components. Route power from power source through the capacitor pad and then into IDT pin.CrystalA 25 MHz fundamental mode parallel resonant crystal with C L = 16 pF should be used. This crystal must have less than 300 ppm of error across temperature in order for theICS557-01 to meet PCI Express specifications.Crystal CapacitorsCrystal capacitors are connected from pins X1 to ground and X2 to ground to optimize the accuracy of the output frequency.C L= Crystal’s load capacitance in pFCrystal Capacitors (pF) = (C L- 8) * 2For example, for a crystal with a 16 pF load cap, each external crystal cap would be 16 pF. (16-8)*2=16.Current Source (Iref) Reference Resistor - R RIf board target trace impedance (Z) is 50Ω, then R R = 475Ω(1%), providing IREF of 2.32 mA. The output current (I OH) is equal to 6*IREF.Output TerminationThe PCI-Express differential clock outputs of the ICS557-01 are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are shown in detail in thePCI-Express Layout Guidelines section.The ICS557-01can also be configured for LVDS compatible voltage levels. See the LVDS Compatible Layout Guidelines sectionGeneral PCB Layout RecommendationsFor optimum device performance and lowest output phase noise, the following guidelines should be observed.1. Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible.2. No vias should be used between decoupling capacitor and VDD pin.3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical.4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from the ICS557-01.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device.PCI-Express Layout GuidelinesFigure 1: PCI-Express Device RoutingTypical PCI-Express (HCSL) WaveformLVDS Compatible Layout GuidelinesFigure: LVDS Device RoutingTypical LVDS WaveformAbsolute Maximum RatingsStresses above the ratings listed below can cause permanent damage to the ICS557-01. These ratings are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.DC Electrical CharacteristicsUnless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85°C1 Single edge is monotonic when transitioning through region.2 Inputs with pull-ups/-downs are not included.ItemRatingSupply Voltage, VDD, VDDA 5.5 VAll Inputs and Outputs-0.5 V to VDD+0.5 V Ambient Operating Temperature (commercial)0 to +70°C Ambient Operating Temperature (industrial)-40 to +85°C Storage Temperature -65 to +150°C Junction Temperature 125°C Soldering Temperature 260°CESD Protection (Input)2000 V min. (HBM)ParameterSymbolConditions Min.Typ.Max.UnitsSupply Voltage V 3.135 3.465Input High Voltage 1V IH 2.0VDD +0.3V Input Low Voltage 1V IL VSS-0.30.8V Input Leakage Current 2I IL 0 < Vin < VDD-55μA Operating Supply Current I DD With 50Ω and 2 pF load 55mA I DDOE OE =Low35mA Input Capacitance C IN Input pin capacitance 7pF Output Capacitance C OUT Output pin capacitance 6pF Pin Inductance L PIN 5nH Output Resistance Rout CLK outputs 3.0k ΩPull-up ResistorR PUPOE60k ΩAC Electrical Characteristics - CLK/CLKUnless stated otherwise, VDD=3.3 V ±5%, Ambient Temperature -40 to +85°C1 Test setup is R L =50 ohms with2 pF , R R = 475Ω (1%).2 Measurement taken from a single-ended waveform.3 Measurement taken from a differential waveform.4Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal.5 CLKOUT pins are tri-stated when OE is low asserted. CLKOUT is driven differential when OE is high.Thermal Characteristics (8-pin SOIC)ParameterSymbolConditions Min.Typ.Max.UnitsInput Frequency 25MHz Output Frequency 100MHzOutput High Voltage 1,2V OH 660700850mV Output Low Voltage 1,2V OL-150027mV Crossing Point Voltage 1,2Absolute250350550mV Crossing Point Voltage 1,2,4Variation over all edges140mV Jitter, Cycle-to-Cycle 1,380ps Rise Time 1,2t OR From 0.175 V to 0.525 V 175332700ps Fall Time 1,2t OFFrom 0.525 V to 0.175 V175344700ps Rise/Fall Time Variation 1,2125ps Duty Cycle 1,34555%Output Enable Time 5All outputs 30µs Output Disable Time 5All outputs30µs Stabilization Time t STABLEFrom power-up VDD=3.3 V3.0ms Spread Change Timet SPREAD Settling period after spread change3.0msParameterSymbolConditionsMin.Typ.Max.UnitsThermal Resistance Junction to AmbientθJA Still air150°C/W θJA 1 m/s air flow 140°C/W θJA 3 m/s air flow120°C/W Thermal Resistance Junction to CaseθJC40°C/WMarking Diagram (ICS557M-01LF) Marking Diagram (ICS557MI-01LF)Notes:1. ###### is the lot code.2. YYWW is the last two digits of the year, and the week number that the part was assembled.3. “L ” designates Pb (lead) free packaging.4. “I” denotes industrial temperature.5. Bottom marking: (orgin). Origin = country of origin if not USA.Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95Ordering InformationPart / Order Number Marking Shipping Packaging Package Temperature 557M-01LF See Page 8Tubes8-pin SOIC0 to +70° C557M-01LFT Tape and Reel8-pin SOIC0 to +70° C557MI-01LF Tubes8-pin SOIC-40 to +85° C557MI-01LFT Tape and Reel8-pin SOIC-40 to +85° C"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.Corporate HeadquartersIntegrated Device Technology, For Sales800-345-7015408-284-8200Fax: 408-284-2775For Tech Support/go/clockhelpInnovate with IDT and accelerate your future networks. Contact:www.IDT .com。
RME MADIface XT音频接口用户手册说明书
用户手册MADIface XT全球首款USB3音频接口!USB 3 / USB 2.0 / PCI Express数字输入/输出系统24 Bit / 192 kHz数字音频192通道3个MADI接口AES/EBU输入/输出2 + 4通道模拟输入/输出196 x 198矩阵路由器1 x MIDI输入/输出3 x 嵌入MADI的MIDI重要的安全说明 (6)概述 (7)1. 简介 (8)2. 包装清单 (8)3. 系统要求 (8)4. 简介及主要特点 (8)5. 首次使用——快速上手 (9)5.1 接口、控制与显示 (9)5.2 快速上手 (10)安装与操作——Windows (11)6. 硬件、驱动和固件安装 (12)6.1 驱动安装 (12)6.2 驱动卸载 (12)6.3 固件升级 (12)7. 设置MADIface XT (13)7.1 Settings（设置）对话框—主标签 (13)7.2 WDM Devices（WDM设备）选项 (16)7.3 Global选项卡（PCI Express模式） (18)7.4 Pitch（仅E-PCIe支持） (19)7.5 时钟模式–同步 (20)8. 操作和使用 (21)8.1 播放 (21)8.2 播放DVD (AC-3/DTS) (22)8.3 多客户端操作 (23)8.4 数字录音 (23)8.5 模拟录音 (23)9. ASIO下的操作 (24)9.1 概述 (24)9.2 已知问题 (24)10. 使用多个MADIface XT (25)11. DIGICheck Windows (26)12. 热线–故障处理 (27)安装与操作——Mac OS X (28)13.驱动和Flash更新 (29)13.1 驱动安装 (29)13.2 驱动卸载 (29)13.3 固件升级 (30)14. 设置MADIface XT (31)14.1 Settings（设置）对话框 (31)14.2 时钟模式–同步 (33)15. Mac OS X FAQ (34)15.1 MIDI不工作 (34)15.2 修复磁盘权限 (34)15.3 支持的采样率 (34)15.4 各种信息 (34)16. 使用多个MADIface XT (35)17. DIGICheck Mac (35)18. 热线–故障处理 (36)19. 前面板操作 (38)19.1 概述 (38)19.2 Encoders（旋钮） (38)19.3 Menu（菜单）键— MIC/GAIN（话筒/增益）和METERS（电平表） (39)19.4 Channel（通道）菜单 (39)19.5 Setup（设置）菜单 (41)19.5.1 Options（选项）菜单 (41)19.5.2 Setups（设置）菜单 (42)19.6 Clock（时钟） (43)输入和输出 (44)20. 模拟输入/输出 (45)20.1 Mic / Line In (话筒/线路输入，XLR/TRS) (45)20.2 幻象供电 (45)20.3 AutoSet（自动设置） (45)20.4 Balanced Line Outputs（平衡线路输出） (46)20.5 Line – Headphones（线路-耳机） (46)21. 数字输入和输出 (47)21.1 MADI输入/输出 (47)21.2 AES/EBU (47)21.3 MIDI (47)21.4 D-sub针脚 (48)22. 字时钟 (49)22.1 字时钟输入和输出 (49)22.2 技术描述和使用 (50)22.3 布线和终止 (51)独立工作模式 (52)23. 操作和使用 (53)23.1 概述 (53)23.2 在设备上设置 (53)24. 实例 (54)24.1 2/4通道AD/DA转换器 (54)24.2 2通道话筒放大器 (54)24.3 194通道监听混音器 (54)24.4 模拟和数字插入器 (54)24.5 带有监听的3端口MADI路由器 (54)TotalMix FX (55)25. TotalMix:路由和监听 (56)25.1 概述 (56)25.2 用户界面 (58)25.3 通道 (59)25.3.1 设置 (61)25.3.2 均衡器 (62)25.3.3 动态 (64)25.4 控制室栏 (65)25.5 控制条 (66)25.5.1 视图选项 (67)25.5.2 快照-组 (68)25.5.3 通道布局-布局预设 (68)25.5.4 滚动位置标记 (70)25.7 首选项 (74)25.7.1 为当前所有用户保存（Windows） (75)25.8 设置 (76)25.8.1 混音器页面 (76)25.8.2 MIDI 页面 (77)25.8.3 OSC页面 (78)25.8.4 辅助设备 (79)25.9 热键与使用 (80)25.10 菜单选项 (80)25.11 菜单窗口 (82)26. 矩阵 (82)26.1 概述 (82)26.2 矩阵视图元素 (82)26.3 操作 (82)27. 操作技巧 (83)27.1 ASIO直接监听（Windows） (83)27.2 复制子混音 (83)27.3 复制一个输出信号（镜像） (83)27.4 删除子混音 (83)27.5 任意复制和粘贴 (84)27.6 录制子混音–回路 (84)27.7 MS 处理 (85)28. MIDI 远程控制 (86)28.1 概述 (86)28.2 规划 (86)28.3 设置 (87)28.4 操作 (87)28.5 MIDI控制 (88)28.6 回路检测 (89)28.7 OSC (89)技术参考资料 (90)29. 技术指标 (91)29.1 模拟 (91)29.2 数字输入 (92)29.3 数字输出 (92)29.4 数字 (93)29.5 MIDI (93)29.6 通用 (93)30. 技术背景 (94)30.1 MADI基础 (94)30.2 锁定（Lock）与SyncCheck（同步检查） (95)30.3 延时（Latency）与监听（Monitoring） (95)30.4 USB音频 (97)30.5 External PCI Express (98)30.6 DS –双倍速 (99)30.7 QS –四倍速 (99)30.8 SteadyClock（稳定时钟） (100)30.9 WDM的注意事项 (101)30.10 术语 (102)其他 (103)31. 配件 (104)32. 产品保证 (104)33. 附录 (105)34. 符合性声明 (105)重要的安全说明注意! 不要打开底盘，以防触电。
时钟（AnalogClock和DigitalClock）的功能与用法
时钟（AnalogClock和DigitalClock）的功能与⽤法时钟UI组件是两个⾮常简单的组件，DigitalClock本⾝就继承了TextView——也就是说它本⾝就是⽂本框，只是它⾥⾯显⽰的内容总是当前时间。
与TextView不同的是为DigitalClock设置android:text属性没什么作⽤。
AnalogClock则继承了View组件，他重写了View的OnDraw⽅法，它会在View上绘制模拟时钟。
表2.16显⽰了AnalogClock所⽀持的XML属性的说明。
表2.16 AnalogClock⽀持的XML属性的说明XML属性说明android:dial设置该模拟时钟的表盘使⽤的图⽚android:hand_hour设置该模拟时钟的时针表盘使⽤的图⽚android:hand_minute设置该模拟时钟的分针使⽤的图⽚DigitalClock和AnalogClock都会显⽰当前时间。
不同的是，DigitalClock显⽰数字时钟，可以显⽰当前的秒数；AnalogClock显⽰模拟时钟，不会显⽰当前秒数。
通过下⾯的实例来⽰范AnalogClock和DigitalClock的⽤法。
实例：⼿机⾥的“劳⼒⼠”由于我们可以通过图⽚定制AnalogClock模拟指针的表盘、时针、分针，因此只要使⽤合适的图⽚，就可以对AnalogClock进⾏任意定制。
下⾯的实例将会使⽤“劳⼒⼠”图⽚来定义模拟时钟，从⽽开发⼿机⾥⾯的“劳⼒⼠”。
下⾯是本实例的布局⽂件。
<LinearLayout xmlns:android="/apk/res/android"android:orientation="vertical"android:layout_width="fill_parent"android:layout_height="fill_parent"android:gravity="center_horizontal"><!-- 定义模拟时钟 --><AnalogClock android:layout_width="wrap_content"android:layout_height="wrap_content"/><!-- 定义数字时钟 --><DigitalClockandroid:layout_width="wrap_content"android:layout_height="wrap_content"android:textSize="14pt"android:textColor="#f0f"android:drawableRight="@drawable/ic_launcher"/><!-- 定义模拟时钟，并使⽤⾃定义表盘，时针图⽚ --><AnalogClock android:layout_width="wrap_content"android:layout_height="wrap_content"android:dial="@drawable/watch"android:hand_minute="@drawable/hand" /></LinearLayout>使⽤Activity显⽰上⾯的界⾯布局，将会看到2.27所⽰的界⾯。
simulink clock模块用法
simulink clock模块用法
SimulinkClock模块是一种用于模拟时钟信号的模块，可以用于控制模型中的事件发生时间和时序。
在使用Simulink Clock模块时，可以设置时钟的周期、启动时间、停止时间、时钟类型等参数。
具体用法如下：
1. 打开Simulink Library Browser，选择Sources库，找到Clock 模块，将其拖放到工作区中。
2. 双击Clock模块，弹出Clock参数对话框。
在该对话框中，可以设置时钟的周期、启动时间、停止时间、时钟类型等参数。
3. 设置时钟周期：在Clock参数对话框中，将Period选项设置为所需的周期，单位为秒。
4. 设置启动时间和停止时间：在Clock参数对话框中，将Start time选项设置为所需的启动时间，将Stop time选项设置为所需的停止时间，单位均为秒。
5. 设置时钟类型：在Clock参数对话框中，将Clock type选项设置为所需的时钟类型，例如Discrete、Continuous、Fixed-step 等。
6. 将Clock模块输出连接到其他模块的输入端口：在模型中使用Clock模块时，将其输出连接到其他模块的输入端口。
通过以上步骤，就可以使用Simulink Clock模块来模拟时钟信号，控制模型中的事件发生时间和时序。
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bc635PCI-V2 PCI时钟同步模块说明书
bc635PCI-V2PCI Time and Frequency ProcessorFeatures• IRIG A, B, G, E, IEEE 1344, NASA 36,XR3 and 2137 time code inputsand outputs• Simultaneous AM and DCLS timecode inputs and outputs• 100 ns clock resolution for timerequests• Programmable << 1 PPS to100 MPPS DDS rate synthesizeroutput/interrupt• 1, 5 or 10 MPPS rate generatoroutput• 1 PPS and 10 MHz inputs• Three external event time capture/interrupts• External event time capture/interrupt• Programmable time compareoutput/interrupt• Zero latency time reads• Battery-backed RTC• PCI local bus operation• Universal signaling (3.3V or 5.0Vbus)• CE RoHS compliant• Linux and Windows softwaredrivers/SDKs included2Precision Time and Frequency in the PCI Form Factor (100-Nanosecond Precision)Inputs••• • • 1 PPS• Outputs• AM time codes • DCLS time codes• Programmable alarm • (strobe/time compare)• <<1 PPS to 100 MPPS rates • 1PPS• 1, 5 or 10 MPPS• Oscillator control voltage• Precise time • Event interrupts• Alarm interrupts (time compare/strobe)• Programmable interrupt rates • Configuration and controlReading the Precise TimeThe bc635PCI-V2 provides precise time on request and extremely fast responses to host applications. This request for time is made using the included SDK software functions. Time can be provided in binary or decimal form.A Multitude of Time CodesThe bc635PCI-V2 has the widest time code input and output support available in any bus-level timing card. Support is available for 30 different time codes including IRIG A, B, G, E, IEEE 1344, NASA 36, XR3 and 2137 in AM and DCLS formats.Measure External or Internal EventsMeasure the exact time up to the occurence of threeindependent external events occur. Bus interrupts instantly notify the CPU that the measurements are made and waiting. Similarly, host application-generated interrupts to thebc635PCI-V2 card over the bus can be precisely time stamped for precise host application-based processes.Flexible Rate GenerationThe DDS on board bc635PCI-V2 can be programmed to generate rates up to 100MPPS or as little as once every 115 days. These rates are available as timing signal outputs or as interrupts on the bus. The rate adjustment resolution is as small as 1/32 HzFrequency OutputsPrecise clocks are excellent sources of frequency outputs. The bc635PCI-V2 offers 1, 5 or 10 MPPS outputs directly from the steered internal oscillator of the clock.External Frequency Inputs and DAC ControlThe external frequency input is a unique feature that allows the time and frequency of the bc635PCI-V2 to be derived from an external oscillator such as a 10 MHz Cesium or Ru-bidium standard. This creates an extremely stable PCI-based clock for all bc635PCI-V2 timing functions. For closed loop control, an external oscillator may be disciplined using DAC voltage control output from the bc635PCI-V2.Time Compare/Strobe/AlarmA useful feature of any precise clock is the ability to notify when a particular time is reached (like an alarm clock). When the preset time precisely matches the actual time, an external signal and an interrupt to the bus are instantly generated, signaling an application that point in time has just occurred. Over-the-Bus FeaturesIn addition to precise time stamps, the bc635PCI-V2 can provide very precisely timed interrupts on the bus at fixed rates, predetermined times or to signal an event has oc-curred on the card. These interrupts can be integrated into user applications requiring more deterministic behavior or application synchronization with other computers. Similarly, user applications can use interrupts as markers in time and later retrieve exactly when the interrupt occurred. Configuration and ControlThe bc635PCI-V2 includes easy-to-use programs to easily configure the card and validate operations. This software is also included with the SDKs and driver software.PCI Card Integration Made Easy With Included SDKs and DriversWindows and Linux SDKs Speed PCI IntegrationThe PCI card includes standard full-featured software devel-opment kits, speeding the integration of Microchip PCI cards into any application.Using an SDK is an easy-to-integrate and highly reliable alter-native to writing lower-level code to address a card's memory registers directly with just a driver. The function calls anddevice drivers in the SDKs make interfacing to a MicrochipPCI card straightforward and help keep the software develop-ment focused on the end application.SDKs Save Time and MoneyProgrammers find the SDK an invaluable resource in acceler-ating the integration of Microchip PCI cards into applications, saving both time and money. The SDK functions address each Microchip PCI timing card feature and the function namesand parameters provide insight into the capability of eachfunction.By using the SDK, you can leverage Microchip's timingexpertise and confidently integrate a Microchip PCI card into your application.License FreeDistribution of embedded Microchip software in customerapplications is royalty free.3Driver ComparisonWindows SDK and Driver• Windows XP/Vista/7/10• Windows Server 2003/2008/2019• 32- and 64-bit support• Kernel mode driver• Code examples• Test application program• Complete documentation• Timekeeping utility programThe Windows SDK for bc635PCI-V2 cards include a Windows XP/Vista/Server/7/10 kernel mode device driver for the 32- and 64-bit PCI interface. The SDK includes .h, .lib and DLL files to support both 32- and 64-bit applications development. The target programming environment is Microsoft Visual Studio (Microsoft Visual C++ V6.0 or higher). Both Visual C++ 6.0 and Visual Studio 2008 project files are supplied with the source code.Also included is Microchip's bc637PCIcfg application program that can be used to ensure proper operation of the PCI card, and the TrayTime application that allows the user to update the system clock in which the card is installed. Source code for these programs and smaller example programs are included.Minimum System RequirementsOperating System• Windows XP/Vista/7/10• Windows server 2003/2008HardwarePC-compatible system with a Pentium or faster processor Memory24 MBDevelopment EnvironmentMicrosoft Visual Studio (Visual C++) 6 or higherLinux SDK and Driver• Linux kernel up to 5.7.1• 64-bit kernel support• Code examples• Test application program• Complete documentationThe Linux SDK for bc635PCI-V2 cards includes PCIe® kernel mode device drivers for 64-bit kernels, an interface libraryaccessing all bc635PCI-V2 features and example programs with the source code.The target programming environment is the GNU compiler collection (GCC) and the C/C++ programming languages.Also included is Microchip's bc63xPCIcfg application program which ensures proper operation of the PCI card in the host computer. The example program includes sample code,exercising the interface library, and conversion examples of the ASCII format data objects passed to and from the device into a binary format suitable for operation and conversion.The example program is developed using discrete functions for each operation, allowing the developer to copy any useful code and use it in their own applications.Minimum System RequirementsOperating System• Linux kernel 5.7.1 or lower• Hardware• ×86 processor• Memory• 32 MB• Development environment• GNU GCC recommended4Windows and Linux SDK Function ReferenceNote: For complete list of functions, see the manual.Basic Time and Frequency Processor (TFP) Functions• bcStartPCI/bcStopPCI Opens/closes underlying device layer.• bcStartInt/bcStopInt Starts/stops the interrupt thread to signal interrupts.• bcSetInt/bcReqInt Enables/returns enabled interrupt.• bcShowInt Interrupt service routine.• bcReadReg/ bcWriteReg Returns/sets requested register contents• bcReadDPReg/bcWriteDPReg Returns/sets requested Dual Port RAM register contents.• bcCommand Sends SW reset command to board.• bcReadBinTime/bcSetBinTime Reads/sets TFP major time in binary format.• bcReadDecTime/bcSetDecTime Reads/sets TFP major time in BCD format.• bcReqTimeFormat Returns selected time format.• bcSetTimeFormat Sets the major time format to binary or grouped decimal.• bcReqYear/bcSetYear Returns/sets year value.• bcSetYearAutoIncFlag Included for backward compatibility to the bc635/637PCI-U card.• bcSetLocalOffsetFlag Enables or disables local time offset in conjunction with bcSetLocOff.• bcSetLocOff Sets board to report time at an offset relative to UTC.• bcSetLeapEvent Inserts or deletes leap second data (in non-GPS modes).• bcSetMode Sets TFP operating mode.• bcSetTcIn Sets time code format for time code decoding mode.• bcSetTcInEx Sets time code and subtype for time code decoding mode.• bcSetTcInMod Sets time code modulation for time code decoding mode.• bcReqTimeData Returns selected time data from the board.• bcReqTimeCodeData Returns selected time code data from the board.• bcReqTimeCodeDataEx Returns selected time code and subtype data from the board.• bcReqOtherData Returns selected data from the board.• bcReqVerData Returns firmware version data from the board.• bcReqSerialNumber Returns board serial number.• bcReqHardwareFab Returns hardware fab part number.• bcReqAssembly Returns assembly part number.• bcReqModel Returns TFP model identification.• bcReqTimeFormat Returns selected time format.• bcReqRevisionID Returns board revision.Event Functions• bcReadEventTime Latches and returns TFP time caused by an external event• bcReadEventTimeEx Latches and returns TFP time caused by an external event with 100 ns resolution.• bcSetHbt Sets a user programmable periodic output.• bcSetPropDelay Sets propagation delay compensation.• bcSetStrobeTime Sets strobe function time.• bcSetDDSFrequency Sets DDS output frequency.• bcSetPeriodicDDSSelect Selects periodic or DDS output.• bcSetPeriodicDDSEnable Enables or disables periodic or DDS output• bcSetDDSDivider Sets DDS divider value.• bcSetDDSDividerSource Sets DDS divider source.• bcSetDDSSyncMode Sets DDS synchronization mode.• bcSetDDSMultiplier Sets DDS multiplier value.• bcSetDDSPeriodValue Sets DDS period value.• bcSetDDSTuningWord Sets DDS turning word value.5Oscillator Functions• bcSetClkSrc Enables or disables on-board oscillator.• bcSetDac Sets oscillator DAC value.• bcSetGain Modifies on-board oscillator frequency control algorithm.• bcReqOscData Returns TFP oscillator data.Generator Mode Functions• bcSetGenCode Sets time code generator format.• bcSetGenCodeEx Sets time code and subtype generator format.• bcSetGenOff Sets an offset to the on-board timecode generation function.GPS Mode Functions• bcGPSReq/bcGPSSnd Returns/sends a GPS receiver data packet.• bcGPSMan Manually sends and retrieves GPS receiver data packets.• bcSetGPSOperMode Sets the GPS receiver to function in static or dynamic mode.• bcSetGPSTmFmt Sets TFP to use GPS or UTC time base.Real-Time Clock (RTC) Functions• bcSyncRtc Synchronizes RTC to current TFP time.• bcDisRtcBatt Sets RTC circuit and battery to disconnect after power is turned off.Backwards Compatibility ProvidesSeamless Migration PathsThe PCI-based bc635 cards have long product lifecycles since the first introduction of PCI timing cards in the mid 1990s. To pre-serve the customer's time and money investments in integrating bc635PCI cards into their systems, Microchip has maintained the bc635PCI cards' existing features and software interface while adding new features and keeping their bus signaling and form factors up to date. This commitment to backward compatibility and current bus architectures assures the bc635PCI cards inte-grate smoothly into any workstation currently available in the market with little to no impact on customer application software. PCI Card Developmentsbc635PCI• Mid-1990s• First PCI timing card introduced bc635PCI-U• 2003• 3.3V and 5.0V universalsignaling backwardcompatibility retainedbc635PCI-V2• 2008• Electronics updatedbackward compatibilityretainedbc635PCI-V2• 2010• Electronics updatedbackward compatibilityretained67Optional Accessories to Speed, Test and Simplify IntegrationBreakout cables with BNC connectors simplify access to the in and out timing signals of the PCI card. These labeled cables mitigate the need to create special cables during project development and ensure that the correct timing signals are being accessed.For more integrated rack mount systems that require easy ac-cess to timing signals, the 1U patch panel and high-frequency signal breakout exposes all available signals. The panel provides an organized and professional appearance to the external timing Input/Output (I/O) of the PCI card functions. The 1U panel fits with a standard or half-rack size chassis. The high-frequency breakout adapter exposes the high-frequency signal as well as the external DC DAC control signal and ground.Input/Output Signals D to BNC Connector Breakout Cables1U Patch Panel of Input/Output and HighFrequency Signals for Standard Rack Mount SizeChassisSpecificationsElectrical• Real-time clock (RTC)• Bus request resolution 100 ns BCD• Latency Zero• Major time format Binary or BCD• Minor time format Binary 1 μS to 999.999 mS• Synchronization sources Time code, 1 PPS• Time code translator (inputs)• Time code formats IRIG A, B, G, E, IEEE 1344, NASA 36, XR3, 2137• Time accuracy <5 μS (AM carrier frequencies 1 kHz or greater) <1 μS (DCLS)• AM ratio range 2:1 to 4:1• AM input amplitude 1 V pp to 8 V pp• AM input impedance >5 kΩ• DCLS input 5V HCMOS >2V high, <0.8V low, 270Ω• Time code generator (outputs)• Time code format IRIG A, B, G, E, IEEE 1344, NASA 36, XR3, 2137• AM ratio 3:1 ±10%• AM amplitude 3.5 V pp ±0.5 V pp into 50Ω• DCLS amplitude 5V HCMOS, >2V high, <0.8V low into 50Ω• Timing functions (outputs are rising edge on time)• DDS rate synthesizer• Frequency range 0.0000001 PPS to 100 MPPS• Output amplitude 5V HCMOS, >2V high, <0.8V low into 50Ω, square wave• Jitter <2 nS p-p• Legacy pulse rate synthesizer (heartbeat, aka periodic)• Frequency range <1 Hz to 250 kHz• Output amplitude 5V HCMOS, >2V high, <0.8V low into 50Ω, square wave• Time compare (strobe)• Compare range 1 μs through days• Output amplitude 5V HCMOS, >2V high, <0.8V low into 50Ω, 1 μs pulse• 1PPS output 5V HCMOS, >2V high, <0.8V low into 50Ω, 60 μs pulse• 1PPS input 5V HCMOS, >2V high, <0.8V low, 270Ω• External event input 5V HCMOS, >2V high, <0.8V low, 270Ω, zero latency• External 10 MHz oscillator Digital 40% to 60% or sine wave, V0.5 pp to 8 V pp, > 10 kΩ• Oscillator control voltage Jumper selectable 0 V dc-5 V dc or 0 V dc-10 V dc into 1 kΩ• On-board disciplined oscillator• Frequency 10 MHz• 1, 5, or 10 MPPS output 5V HCMOS, >2V high, <0.8V low into 50Ω• Stability• Standard TCXO: 5.0 × 10–8 short term tracking 5.0 × 10–7/day long term flywheeling • Real-Time Clock (RTC) Battery-backed time and year information• PCI specification 2.2 compliant 2.3 compatible PCI-X compatible• Size Single-width (4.2" × 6.875")• Device type PCI target, 32-bit, universal signaling• Data transfer 8-bit, 32-bit• Interrupt levels Automatically assigned (PnP)• Power 12V at 50 mA TCXO: 5V at 700 mA• Connector• Firmware update port 6-pin, PS2 mini-DIN J2• Timing I/O 15-pin ‘DS’ J189The Microchip name and logo and the Microchip logo are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. All other trademarks mentioned herein are property of their respective companies. © 2021, Microchip Technology Incorporated. All Rights Reserved. 11/21 DS00004168BEnvironmental• Temperature• Operating 0ºC to 65ºC • Storage –30ºC to +85ºC• Humidity• Operating 5% to 95% non-condensing • Certifications• FCCPart 15, Subpart B. EmissionsEN 55022• Immunity EN 55024• RoHS compliance• EU RoHS 6/6• China RoHSComplete specifications can be found in the manual located at .Pin DiagramStandard Cover PanelSoftwareThe bc635PCI-V2 includes the Microchip bc635pcidemo.exe application program for Windows. Using this program, you can review the bc635PCI-V2 card status and adjust board configuration and output parameters. An additional clock utility program, TrayTime, is provided to update the host computer’s clock.Control Panel InterfaceAdditional FeaturesThis product also includes a bc635PCI-V2 time and frequency processor board, standard height cover panel, one-year war-ranty and an insert sheet that explains how to download the user guide and SDK/driver software.Ordering InformationPart Number: bc635PCI-V2 PCI time and frequency processor Connector accessories that can be ordered:• D connector to x5-BNCs adapter (provides TC in, TC out, 1PPS out, event in, periodic out) p/n BC11576-1000• D connector to x5-BNCs adapter with 1PPS in (pro-vides TC in, TC out, 1PPS in, 1PPS out, event in) p/n BC11576-9860115• D connector to x6-BNCs adapter (provides TC in, TC out, 1PPS in, 1PPS out, event in, DCLS out) p/n PCI-BNC-CCS For GPS synchronization, see bc637PCI-V2 PCI Express Time and Frequency Processor datasheet.Contact Microchip for pricing and availability.815141312109117654321。
logiCLK 可编程时钟发生器 规格书说明书
October 17th, 2018 Data Sheet Version: v1.5Fallerovo setaliste 2210000 Zagreb, CroatiaPhone: +385 1 368 00 26Fax: +385 1 365 51 67E-mail: ***********************URL: Features∙Supports Xilinx® 7 Series, UltraScale TM andUltraScale+TM SoCs and FPGAs∙Provides twelve independent clock outputs thatcan be configured by generic parameters:- Six outputs can be dynamically configuredthrough register interface during operation- Six outputs can be configured by genericparameters only∙Supports phase-locked loop (PLL) and mixed-mode clock manager (MMCM). The user canselect clock primitive through IP configurationGUI∙Selectable output buffer type on clock outputports: BUFG, BUFH and no buffer∙Configurable through AXI4-Lite interface∙Software support for Linux and Microsoft® Windows® Embedded Compact operating systems∙Available for Xilinx Vivado® IP IntegratorTable 1: Example Implementation Statistics for Xilinx® FPGAsthree clock outputs from logiCLK are used.2) Assuming register interface, as well as status signals and generated clock outputs are connected internally.3) The same implementation statistics apply to the Xilinx 7 series FPGAs.4) The same implementation statistics apply to the Xilinx UltraScale and UltraScale+ FPGAs.RST_OUTLOCKEDCLK0CLK1CLK2CLK3CLK4CLK5Figure 1: logiCLK ArchitectureFeatures (cont.)∙Input clock frequency range*:- 7 series PLLs: 19 – 1066 MHz- 7 series MMCMs: 10 – 1066 MHz- UltraScale and UltraScale+ PLLs: 70 – 1066 MHz- UltraScale and UltraScale+ MMCMs: 10 – 1066 MHz∙Output clocks frequency range*:- 7 series PLLs: 6.25 – 741 MHz- 7 series MMCMs: 4.69 – 1066 MHz- UltraScale PLLs: 4.69 – 850 MHz- UltraScale MMCMs: 4.69 – 850 MHz- UltraScale+ PLLs: 5.86 – 891 MHz- UltraScale+ MMCMs: 6.25 – 891 MHz* Depending on the sub-family and device’s speed grade. Please consult the corresponding family data sheet. General DescriptionThe logiCLK Programmable Clock Generator IP core from the Xylon logicBRICKS IP core library is optimized for Xilinx 7 Series, UltraScale and UltraScale+ SoC and FPGA devices, and designed to provide frequency synthesis, clock network de-skew and jitter reduction. Input and output frequency ranges are restricted by PLL, MMCM and Clock Buffer switching characteristics of the specific Xilinx All Programmable device.The logiCLK clock generator IP core has twelve independent and fully configurable clock outputs. While six clock outputs can be fixed by generic parameters prior to the implementation, the other six clock outputs can be either fixed by generics or dynamically reconfigured in a working device. The Dynamic Reconfiguration Port(DRP) interface gives system designers the ability to change the clock frequency and other clock parameters while the design is running by mean of a set of memory-mapped PLL/MMCM configuration and status registers (Figure 1).The ability to dynamically change the clock signals during the operation is an important feature for some SoC applications. For example, the logiCLK IP core enables precise clock adjustments necessary for driving display output with different resolutions, which would be otherwise impossible without an external programmable Phase-Locked Loop (PLL)/Mixed-Mode Clock Manager (MMCM) device.Xylon uses the logiCLK IP core in free and pre-verified Graphics Processing Unit (GPU) reference designs prepared for popular Xilinx Zynq-7000 AP SoC based development kits. Please visit Xylon web site to see the full list of logicBRICKS reference designs:/logicBRICKS/Reference-logicBRICKS-Design.aspxXylon’s software drivers for graphics logicBRICKS IP cores, such as the logiCVC-ML display controller IP core, include support for the logiCLK Programmable Clock Generator IP core and enable its easy use with the Linux and Microsoft Windows Embedded Compact operating systems.Functional DescriptionThe Figure 1 represents internal logiCLK architecture. The logiCLK functional blocks are Dynamic Reconfiguration Parameters module and Registers.Dynamic Reconfiguration Parameters moduleDynamic Reconfiguration Parameters module is an optional IP core’s module that provides six output clocks (CLK_DRP) defined by a set of re-configurable parameters. It is designed in accordance to the Xilinx Application Note XAPP888: “MMCM and PLL Dynamic Reconfiguration” for 7 Series, UltraScale and UltraScale+ FPGAs. RegistersThe CPU has access to logiCLK’s registers through AXI4-Lite bus interface.Core ModificationsThe core is supplied in encrypted VHDL format compatible with Xilinx Vivado IP Integrator. Many logiCLK configuration parameters are selectable prior to VHDL synthesis, and the following table presents a selection from a list of the available parameters:Table 2: logiCLK VHDL configuration parametersNotes:1. Refer to Xilinx Clocking Resources User guides depending on the used device’s family.2. These parameters are used to configure CLK_DRP outputs if dynamic reconfiguration enable bit in control register is cleared, or ifdynamic reconfiguration enable bit in control register set and data address is “0”.Core I/O SignalsThe core signal I/Os have not been fixed to specific device pins to provide flexibility for interfacing with user logic. Descriptions of all signal I/Os are provided in Table 3.Table 3: Core I/O SignalsVerification MethodsThe logiCLK is fully supported by the Xilinx Vivado Design Suite. This tight integration tremendously shortens IP integration and verification. A full logiCLK implementation does not require any particular skills beyond general Xilinx tools knowledge. This IP core has been successfully validated in different designs.Software driversXylon Linux Framebuffer driver includes the software support for the logiCLK IP core. For more information, please get the Linux Framebuffer User’s Manual:URL: /Documentation/Datasheets/SW/Xylon-Linux-FrameBuffer.pdfXylon logiDISP driver for Microsoft Windows Embedded Compact includes the software support for the logiCLK IP core. For more information, please visit:URL: /Products/Xylon-Windows-Embedded-Display.aspxRecommended Design ExperienceThe user should have experience in the following areas:-Xilinx design tools-ModelSimAvailable Support ProductslogiREF-ZGPU-ZED Reference Design –evaluate 2D and 3D logicBRICKS graphics on the ZedBoard from Avnet Electronics Marketing with connected PC monitor. Deliverables include complete software support for Linux OS, from the basic Framebuffer up to the full 3D graphics. Configurable IP cores enable customization of the evaluation hardware, which can also be used with other popular operating systems. This design uses the logiCLK Programmable Clock Generator IP core to support different display resolutions.Email: ***********************URL: /logicBRICKS/Reference-logicBRICKS-Design/Graphics-for-Zynq-AP-SoC-ZedBoard.aspxTo check a full list of Xylon reference designs please visit the web:URL: /logicBRICKS/Reference-logicBRICKS-Design.aspxOrdering InformationThis product is available directly from Xylon under the terms of the Xylon’s IP License. Please visit our web shop or contact Xylon for pricing and additional information:Email: *********************URL: This publication has been carefully checked for accuracy. However, Xylon does not assume any responsibility for the contents or use of any product described herein. Xylon reserves the right to make any changes to product without further notice. Our customers should ensure that they take appropriate action so that their use of our products does not infringe upon any patents. Xylon products are not intended for use in the life support applications. Use of the Xylon products in such appliances is prohibited without written Xylon approval.Related InformationXilinx Programmable LogicFor information on Xilinx programmable logic or development system software, contact your local Xilinx sales office, or:Xilinx, Inc.2100 Logic DriveSan Jose, CA 95124Phone: +1 408-559-7778Fax: +1 408-559-7114URL: Revision History。
swd接口dio和clk默认电平
swd接口dio和clk默认电平
SWD（Serial Wire Debug）接口是一种用于调试和编程嵌入式
系统的接口标准。
它使用两根线进行通信，即DIO（Data
Input/Output）和CLK（Clock）。
对于SWD接口的DIO和CLK，默
认电平通常是指在未进行通信时它们的电平状态。
对于DIO，默认电平通常是高电平（逻辑1），而对于CLK，默
认电平通常是低电平（逻辑0）。
这是因为在未进行通信时，SWD接
口处于空闲状态，DIO保持高电平以便随时准备接收数据，而CLK
则保持低电平以确保时钟同步。
这种默认电平的设定有助于确保在
系统空闲时，接口处于稳定状态，同时也有利于减少功耗。
需要注意的是，不同的硬件或设备可能会有一些微小的差异，
因此在实际应用中，可能会有一些特定的默认电平设置。
在使用SWD接口时，建议查阅相关的数据手册或规格说明以获取准确的默
认电平信息。
总的来说，默认情况下，DIO通常为高电平，CLK通常为低电平，这是为了确保接口在空闲状态下保持稳定，并且有利于通信的准确
进行。
网络LLC精密时钟产品说明说明书
Networking · Communications · Test and measurement · Video and imaging · OTN/SONET and optical · Servers/cloud computing · High performance computing (HPC) · Fibre Channel/storage · Base stations (BTS) · CPRI/OBSAI · LTE/4G/5G · Precision GPS · Jitter attenuators with holdover · RF & high speed data converters · FPGA and high speed SERDES
LLC
The Heartbeat of the IoT™
NETWORKING
Precision Timing for Communication, Networking, High Performance/Cloud Computing, Server, Storage, and RF
PRECISION OVEN CONTROLLED OSCILLATOR (OCXO)
APPLICATIONS
OTN, Synchronous Ethernet, IEEE1588
ADVANCED TIMING FOR NEXT GEN NETWORKING
SERDES, transceivers and RF converters benefit from low phase noise and low jitter clocking to meet the growing market demand for higher data rates and bandwidth. CPUs, FPGAs, RF chipsets and ASSPs driving next generation OTN, 100/400G Ethernet, FibreChannel, RF and PCI Express physical layer interfaces need clock jitter below 100fsec to achieve acceptable design margin. Applications such as base stations (BTS) and high accuracy GPS equipment requiring long periods of holdover utilize ultra-precise 100ppb to 0.1ppb clock references to generate a local time base.
VCL-2112 PTP Slave Clock 产品说明书
Output TypeConnector 1.544Mbits (T1)/2.048Mbits (E1)RJ45compliant with ITU-T G.7032.048MHz,75Ohms,phase-locked to BNC PTP Grandmaster (GPS)Reference 1/5/10MHz,50Ohms,phase-locked to BNC PTP Grandmaster (GPS)Reference IRIG-B,synchronized to PTP BNC Grandmaster (GPS)reference**TOD*(Time-Of-Day)output DB9,compliant to NMEA0183RS-232C 1PPSBNC*ToD Time Of Day**Note:User selectable between IRIG-B and 1PPSOutputsIntroduction:Features and Highlights:Additional Features:Typical Synchronization ApplicationsStandard Frequency and ToD*Outputs:VCL-2112,PTP Slave Clock The VCL-2112,PTP Slave Clock The VCL-2112,PTP Slave Clock is VCL-2112,PTP Slave ClockDescription:is a high precision,high reliability time and frequency synchronization solution which can be used to synchronize with an IEEE-1588v2PTP Grandmaster to provide reference frequency and time-of-day synchronization across all nodes of a PTP network.Multiple 1PPS /IRIG-B Outputs are also provided to synchronize local clock (time-of-day)display units as well as RTUs to a central timing source with nanosecond accuracy.is specifically designed for providing synchronization in 2G,3G,HetNet and LTE mobile telecommunications networks as well as in backhaul wire-line TDM Networks.It may be also used by Railways,Airports (including air-traffic control),Power generation and distribution companies and other Utility companies who need to distribute highly precise time-of-day and frequencies locked to a PTP Grandmaster (GPS)Reference across multiple nodes of their networks.equipped with a highly accurate,low-noise OCXO which provides a high stability holdover that is typical of a Network SSU in the event of a failure of the transmission link.VCL-2112,PTP (IEEE-1588v2)Slave Clock -synchronizes to PTP Grandmaster to provide 1PPS,NMEA,1/5/10MHz, 2.048MHz, 1.544Mbits /2.048Mbits Frequency Outputs with high stability OCXO holdover.Reliable,Cost-Efficient ReferenceBCMA (Best Master Clock Algorithm)-allows the unit to be installed in a redundant PTP Grandmaster networkOCXO Holdover 1/5/10MHz output 1PPS /IRIG-B outputs Nanosecond accuracyStandard RJ45and BNC connectors for all inputs and outputsToD compliant to NMEA0183(DB9Serial Port).Password ProtectionRedundantAC and DC power supply options 10/100BaseT Network Interface Ethernet Ports 1x OAM 1x PTPVLAN and Packet prioritySupports QoS,802.1p based packet priority.Supports 802.1Q based VLANs.Power Contact and Lightening Protection as per Telcordia GR-1089-CORE.Synchronizing mobile communication networks such as UMTS,GPRS,HetNet,2G and 3G networks Wireless and Wireline Telecom synchronizationDistributing Time (ToD)and Frequency reference for power utilities across all nodes of the network Synchronization of Defense NetworksSynchronizing airports and aviation communications Synchronizing railway signaling networks and railway communicationsSynchronizing traffic managementBroadcasting Network and Broadcast equipment synchronization.!!!!!!!!!!!!!!!!!!!!!!!!!VCL-2112IEEE-1588v2PTP SlaveRIONTELECOMNETWORKS1Revision 1.3–May 02,2016Ordering Information VCL-2112VCL-2112,PTP (IEEE-1588v2)Slave Clock19-inch Rack Mount,1U High -Synchronizes to PTP Grandmaster to provide 1PPS,NMEA,1/5/10MHz,2.048MHz,1.544Mbits /2.048Mbits Frequency Outputs with high stability OCXO Holdover-Management:SNMP ,Telnet (RJ45(F)Port),Serial Port (USB,DB-9COM),EMS,Graphical User Interface (GUI)-Installation Kit:System Core Cables,Mounting Hardware,Documentation,User Manual AC2201x 100-240V,,AC Power Supply Input DC0481x (-)48V DC Power Supply InputAC220R 2x 100-240V,,AC Power Supply Input [Redundant]DC048R2x (-)48V DC Power Supply Input [Redundant]Add Power Supply Option 50/60Hz 50/60Hz Management and Monitoring Ports:System Access,Control and Management Options:Security and Protection:Configuration and Monitoring Software:Environmental:Mechanical Specifications:!!!!!!!!!!!RS-232C USB10/100BaseT Ethernet1x External Alarm Relay Contact.TelnetCLI Control Interface (HyperTerminal or VT100)SNMP V2Traps (MIB File provided).Password ProtectionSeparate VLAN on monitoring and access.Telnet,CLIGUI (Graphical User Interface)-Runs on any PC operating on Windows XP ,Windows 7or Windows 8OS.Operational -40°C to +60°C (Typical:+25°C)Cold Start -20°C to +60°C Storage -40°C to +75°CHumidity 95%non-condensing CoolingConvention CooledNo cooling fans are required.Rack mounting Standard 19-Inch.DIN Rack Height 44.00mm.(1RU)Depth 280.00mm.Width 480.00mm.Weight3.20kg.Orion Telecom Networks Inc.VCL-2112。
S7实时时钟模块说明书
Moisture Sensitivity Level: MSL=1• RTC module with built-in crystal oscillating at 32.768 kHz• 350 nA timekeeping current at 3 V • Timekeeping down to 1.0 V• 1.3 V to 4.4 V I2C bus operating voltage • Low operating current of 35 μA (at 400 kHz)• 32.768kHz square wave on power-up to drive a microcontroller inlow-power mode– Programmable from 1 Hz to 32.768kHz;– Can be disabled • 400 kHz I2C serial interface• Oscillator stop detection circuit monitors clock operation• Accurate programmable watchdog– 62.5 ms to 31 min timeout• Counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century• Software clock calibration to compensate deviation of crystal due to temperature • Automatic leap year compensation• Ultra-small, 3.2 x1.5 mm, lead-free 8-pin ceramic leadless chip carrier• Wide range in communication & measuring equipment • Commercial & Industrial applications • Automotive electronics applications • Wireless communications • PDA and Palm Pilots• Credit Cards with Security TechnologyAbsolute Maximum RatingsIn accordance with the Absolute Maximum Rating System IEC 601341) HBM: Human Body Model, according to JESD22-A114. 2) MM: Machine Model, according to JESD22-A115.These data are based on characterization results, not tested in production. Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction.1)Capacitance2) At 25°C, f = 1MHz. 3) Outputs deselected.Frequency Characteristics T amb = +25°C; f OSC = 32.768 kHzStatic CharacteristicsValid for T amb= -40°C to +85°C; V DD= 1.3 V to 4.4 V (except where noted)1. Oscillator startup guaranteed down to 1.5 V only.I2C Interface Dynamic CharacteristicsValid for T amb= -40°C to +85°C; V DD= 1.3 V to 4.4 V (except where note d)1. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of SCL. I2C Interface Timing CharacteristicsPIN DESCRIPTIONS:Dimensions: mmMaximum Reflow Conditions in accordance with IPC/JEDEC J-STD-020C “Pb-free”TemperatureConditions Units Average Ramp-up Rate (T Smax to T P )3°C/second max °C/s Ramp Down Rate (T cool )6°C/second max °C/s Time 25°C to Peak Temperature (T to-peak )8 minutes maxm PreheatTemperature Min (T Smin )150 °C Temperature Max (T Smax )200 °C Time Ts min to Ts max (ts)e s 081 ~ 06 Time Above LiquidusTemperature Liquidus (T L )217 °C Time above Liquidu s (t L )60 ~150 sec Peak TemperaturePeak Temperature (T P )260 °C Time within 5°C of Peak Temperature (t P )20 ~ 40secRECOMMENDED REFLOW PROFILE:Abracon LLC’s products are COTS – Commercial-O -The-Shelf products; suitable for Commercial, Industrial and, where designated, Automotive Applica tions. Abracon’s products are not specifically designed for Military, Aviation, Aerospace, Life-dependent Medical applications or any application requiring high reliability where component failure could result in loss of life and/or property. For applications requiring high reliability and/or presenting an extreme operating environment, written consent and authorization from Abracon LLC is required. Please contact Abracon LLC for more information.。
GCLK&CLKX
GCLK在基站位置产生的时间参考信号包括：1．16.384MHz TDM 时钟2．125μs TDM 高速总线帧参考3．60 ms同步参考4．6.12秒超帧计数器GCLK能够锁定在通过一个MSI/XCDR模块提供的链路选定的2Mbit/s的恢复时钟上。
如果失去了参考时钟，GCLK能够比提供的0.05 ppm参考稳定性更好地自由振荡。
GCLK 模块能够实现自我诊断以检测板上错误，在必要时还可响应选择一个备用GCLK。
每个时钟对都在有和主时钟输出同步的从属时钟的主/从配置下工作。
如果检测到错误，时钟控制电路把主从位置反转。
错误条件将通过MCAP总线报告给控制GPROC。
GCLK的功能：参考振荡器将用一个锁相循环（PLL）和频率倍增器从2Mbit/s参考链路合成得到16.384MHz频率。
PLL包括一个数字相位检测器、一个环路滤波器，一个电压控制石英晶体振荡器和一个由8个循环分配器形成的分隔。
如果失去2Mbit/s参考链路，振荡器能够在石英晶体振荡器维持下稳定地振荡。
参考计数器的输出都接到用来从主或从GCLK交换输出的多路复用器上。
每个参考计数器的输出都接到一个给所有的参考信号编码的参考编码器上，然后又接到一个时钟扩展器便使它们能够通过光纤传给基站的所有机箱。
参考错误检测器监视2Mbit/s参考链路，错误信号将会报告到时钟控制/告警逻辑单元。
如果参考失败，GCLK可以选择第二个参考或者允许GCLK自由振荡。
每一种情况都会有告警通过MCAP总线报告给控制GPROC。
GCLK前面的缓冲检测端口用来测量输入及输出时钟参考信号。
GCLK 配置BSC/RXCDR：BSC/RXCDR位置的最多冗余模式的GCLK数是两个，都安装在同一个数字箱中。
GCLK 时钟信号通过CLKX模块能分布到基站的每个机箱。
GCLK的工作模式有4个，即：自由振荡、保持频率、设置频率以及闭环。
每种模式都将用相应的图来解释。
自由振荡当一个GCLK插入数字箱（或者接通电源后），需要30分钟的加热来使石英晶体振荡器达到正常的工作温度，在这段时间内，GCLK处于自由振荡模式。
接口软件说明书clock
目录第一章卡钟管理 (2)1. 添加设备 (2)2. 基本操作 (4)2.1、读取数据 (4)2.2、设置管理卡 (5)2.3、更改机号 (5)2.4 工作模式 (5)2.5、校正时间 (7)2.6、设置密码 (8)2.7、修改波特率 (8)2.8、实时监控 (8)2.9、取回时间 (9)2.10、机具状态 (10)2.11、清除数据 (10)2.12 在线检测 (11)3. 参数设置 (11)3.1 刷卡间隔 (11)4.显示控制 (12)4.1 自定义显示 (12)5.时段设置 (13)5.1 考勤时段设置 (13)5.2打铃时段设置 (14)6. 考勤名单管理 (14)7. 分组设置和IC卡操作 (16)第二章文件设置 (19)1. 定时间采集 (19)2. 定义文件格式 (19)第三章系统设置 (20)1. 界面风格设置 (20)2. 数据库接口定义 (20)第四章设机器密码 (21)第五章升级机具 (23)第六章IC卡加密 (26)第一章卡钟管理1. 添加设备在进入考勤管理界面后，让我们先看看考勤界面的设备列表中有哪些功能，在列表中右键就会弹出这些功能，都是对机具进行设置的，添加，修改，删除这些也就不用我不介绍了。
主要是看看下面的几项：1、读取参数，就是对机具原有的，或者是已经设置好的参数进行读取，主要读的参数是刷卡间隔时间，重复间隔，外接设备的点亮时间等。
2、下载字库，这项功能是为了适合所有客户的需求，专门下载繁体字库的。
我们的软件也同样配套有繁体版本。
3、参数初始化，是对机具的所有参数进行出厂值的恢复。
4、机具初始化是把机具进行所有设置的初始化，包括存储的纪录，名单等都会被变成“零”。
5、升级模式，是对机具进行升级的程序，可以点击升级模式进入升级界面对机具进行升级处理。
并且我们的软件还支持在线升级，所以在任何时候都可以对机具进行最新版本的轻松升级处理。
在这个操作的流程中要注意很多问题。
主板时钟Clock概要
芯片的连接，要避免用过孔。
第七页，编辑于星期日：十九点 四十九分。
4、锁相环（PLL）变频电路框图
参考时钟输入
FREF
分频比 N
FR
PFD
FFB
VCO
变频输出 FVCO
分频比L
变频输出
FOUT
分频比 M
• 参考时钟输入I经N分频输出FR （ FR = FREF / N）；压控振荡器输出FVCO
外，还与负载电容CL及晶振走线有关
CL= [（CL1 x CL2）/（CL1+CL2）]+CS
CL1、CL2为外接电容；CS为电路的杂散电容
，包括反相器的输入/输出电容。
为保证精度，所购晶振允许的CL要和外接 的CL1、CL2匹配（并考虑反相器
的输入/输出电容的影响）。
QDI主板所用晶振的精度： 14.31818M、24.576M和25.000MHz晶振精度 为+/-30ppm；32768Hz晶振精度为+/-20ppm。
5.2 基本同步时钟接口(续)
• 主要关注要满足在信号接收端，相对于时钟的预置（建立）时间和保持时间的要求.
• 时间关系分析要考虑走线的传输延迟、串扰、时钟周期的抖动和边沿的偏移的影响
• 由器件的规格书可查同步输出相对于时钟输入边沿的延迟时间TCO的最大（max）和 最小（min）值；同步输入相对于时钟输入所需的预置时间Ts和保持时间Th最大和 最小值。
电极
晶振 RLC 等效电路
R为谐振频率下内部振动损耗的等效电阻；C1和L为晶体谐振等效串 联谐振的电容和电感；C2为两电极间的充电电容（包括引线和外壳）。 两个谐振频率：串联谐振频率f s和并联谐振频率f p
iclock server使用指南
iClock Server使用指南版本：1.0日期：2008年10月适用机型:iClock300、iClock360、iClock660、iClock2500、iClock2800等机型。
内容介绍本文档主要介绍了iClock Server 系列产品的使用说明，包括软件的安装与卸载，iClock Server的适用。
重要申明首先感谢您选择本系列产品。
在使用前，请您仔细阅读本产品的说明书。
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目录1. iClock Server安装与卸载 (1)1.1 软件的安装 (1)1.2 软件的卸载 (5)2. 登录iClock Server (6)2.1 iClock Server管理 (6)2.2 系统登录及注销 (7)2.3 语言选择 (8)2.4 密码修改 (8)3. iClock Server的使用 (10)3.1 快速使用 (10)3.2 设备管理 (10)3.2.1 设备维护与管理 (10)3.2.2 设备操作日志 (15)3.2.3 实时记录监控 (16)3.3 数据维护 (17)3.3.1 部门管理 (17)3.3.2 人员管理 (19)3.3.3 考勤记录 (24)3.4 系统日志 (27)3.4.1 设备上传数据日志 (27)3.4.2 服务器下发命令日志 (28)3.4.3 管理员操作日志 (30)3.4.4 系统管理员维护 (31)附录 (35)附录1 如何将终端设备连入网络 (35)附录2 常用操作 (37)1. iClock Server安装与卸载1.1 软件的安装1、将安装光盘放入光驱，安装程序会自动运行。
Clock时钟控件
事件相应：控件需要对鼠标点击做出响应，因此需要创建事件响应函数 这里是一个鼠标事件，每当点击一次，事件函数修改一次m_IfDigitShape值。
另外当用户关闭组件时，需要销毁该应用实例
当定义好属性值后，就可以绘制表盘。字符表盘是将当前的系统时间以字符 串现实出来，而图形表盘则是绘制一个圆形表盘，动画形式现实。 字符表盘实现：
Clock时钟控件
实现功能
时钟功能，两种表现方法，图形表盘， 字符表盘，通过点击控件区域是些两种模 式的切换。 通过创建一个容器实现调用该控件组件。
效果图
实现方法
首先要对控件初始化：在CClockCtrl::CClockCtrl() 构造函数中加入代码：
控件是一个动态时钟，因此画面需要重绘，数据也需要更新，因此要设置 WM_CREATE 和WM_TIMER两个消息，并在函数中加入代码：
编译调试后就可以生成一个.ocx文件，注册该组件后，就可以通过容器进行调用。
初始化中，需要设置自定义属性：UpdateInterval ,IfDigitShape,BackColor BackColor 背景颜色 UpdateInterval 负责处理事件间隔数据，该控件中，每秒更新以此画面，因此间 隔值为1000. IfDigitShape 是一个传递事件的BOOL值，当鼠标点击时，启动事件，修改 m_IfDigitShape值。 自定义属性的调用,定义。
图形表盘：
切换方式：
if(m_IfDigitShape) ｛ . . . . . . \\ 字符表盘代码 } else { . . . . . . \\图形表盘代码 ｝
初始化数据：
这些代码均在： void CClockCtrl::OnDraw(CDC* pdc, const CRect& rcBounds, const CRect& rcInvalid) 函数中定义，这个是绘图函数，绘制控件界面。
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目录第一章卡钟管理 (2)1. 添加设备 (2)2. 基本操作 (4)2.1、读取数据 (4)2.2、设置管理卡 (5)2.3、更改机号 (5)2.4 工作模式 (5)2.5、校正时间 (7)2.6、设置密码 (8)2.7、修改波特率 (8)2.8、实时监控 (8)2.9、取回时间 (9)2.10、机具状态 (10)2.11、清除数据 (10)2.12 在线检测 (11)3. 参数设置 (11)3.1 刷卡间隔 (11)4.显示控制 (12)4.1 自定义显示 (12)5.时段设置 (13)5.1 考勤时段设置 (13)5.2打铃时段设置 (14)6. 考勤名单管理 (14)7. 分组设置和IC卡操作 (16)第二章文件设置 (19)1. 定时间采集 (19)2. 定义文件格式 (19)第三章系统设置 (20)1. 界面风格设置 (20)2. 数据库接口定义 (20)第四章设机器密码 (21)第五章升级机具 (23)第六章IC卡加密 (26)第一章卡钟管理1. 添加设备在进入考勤管理界面后，让我们先看看考勤界面的设备列表中有哪些功能，在列表中右键就会弹出这些功能，都是对机具进行设置的，添加，修改，删除这些也就不用我不介绍了。
主要是看看下面的几项：1、读取参数，就是对机具原有的，或者是已经设置好的参数进行读取，主要读的参数是刷卡间隔时间，重复间隔，外接设备的点亮时间等。
2、下载字库，这项功能是为了适合所有客户的需求，专门下载繁体字库的。
我们的软件也同样配套有繁体版本。
3、参数初始化，是对机具的所有参数进行出厂值的恢复。
4、机具初始化是把机具进行所有设置的初始化，包括存储的纪录，名单等都会被变成“零”。
5、升级模式，是对机具进行升级的程序，可以点击升级模式进入升级界面对机具进行升级处理。
并且我们的软件还支持在线升级，所以在任何时候都可以对机具进行最新版本的轻松升级处理。
在这个操作的流程中要注意很多问题。
1、首先你要将考勤机连接到电脑上，就要选择用什么样的通讯方式？我们的软件提供了三种通讯方式：RS-232，RS-485，TCP/IP。
A、RS-232的特点是：安装布线简单，费用小，适合人少小型的办公区等工程使用，缺点：通讯距离很短，通讯速度满，一般在20M，不适合大型的工程安装。
B、RS-485的特点是：通讯距离远，适合人多流量大，门多的大型工程安装使用，通讯距离在1200M，通讯容量标准是30台机具同时通讯，最大可以连接400台机具，统一管理方便，培训简单，。
缺点：安装布线维护的难度大，所需费用较高。
C、TCP/IP除了集中以上所有的优点外，还有速度更快，安装更简单，联网数量更大，可以跨地域联网考勤，但是价格高，需要网络支持，同时要求使用这要懂基本的网络知识才行。
2、机号的填写，在填写的机号的时候一定要和考勤机上所显示的机号一致。
3、序列号的填写，每一个机具的后盖都有一个唯一的机具号码，所以在填写的时候必须按照后盖上的机具号填写。
4、机型的选择。
这是一个非常关键的选择，因为我们的考勤机机具分为三种系列：CO380，CT380，CU380。
其中CO380又分为：CO380C和CO380D两种机型，他们的区别就是所使用的卡的类型不一样，前者用的是IC卡，而后者用的是ID卡。
同样CT380也分IC和ID的两种卡类型。
CU就是U盘考勤机，可以不用和电脑连接，直接用U盘来存储考勤数据。
5、COM端口，什么是COM端口呢？就是通讯线和电脑连接的那个接口，就称为COM端口。
一般台式电脑有2~3个COM端口，从上到下依次是COM1，COM2…..。
你的通讯线接的是哪个端口就选择哪个端口。
6、波特率，就是通讯的速率。
RS-232的通讯速率在9600bps~~115200bps。
7、TCP/IP，因为在选择机具的时候，如果选择的机具是CT380系列的，我们就需要在这一行输入我们本机的IP地址这样才能使机具和电脑进行通讯。
如图以上每一个设置都会影响到设备和电脑是否能进行正常通讯，所以在选择的时候一定要保证设置正确。
如果设备和电脑进行正常通讯，那么检测设备在线的话。
就会出现绿色连接。
以下就是考勤管理的标准界面。
2. 基本操作在考勤设备的基本设置中包括了几个部分：读取数据，设置管理卡，更改机号，工作模式，校正时间，设置密码，修改波特率，实时监控，取回时间，机具状态，清楚数据，在线检测。
下面就一一介绍他们的功能以及注意事项。
2.1、读取数据就是在打卡考勤完了之后，对机具里面存储的数据读到电脑上来，进行部门和个人的上班考勤。
读取数据的方式是分页读取。
2.2、设置管理卡2.3、更改机号就是对现在在线的机具进行机号的更改。
因为初始化了的机具都是默认的1号机具。
所以在添加很多台机具的时候就需要更改机号才能添加。
2.4 工作模式2.4.1、应用模式应用模式是设备在读卡，纪录存储/名单检查，打卡响铃，外接设备的操作。
在应用模式中有功能用途类型，我们在选择用途类型的时候要知道我们的设备是做什么用的，是做为读卡器来发卡，还是做为考勤机来考勤用的。
实时监控模式的选择是选择打卡的时候是以什么方式来报告刷卡的结果。
选择刷卡处理结果报告查询就是在刷卡的时候显示是不是正常考勤，并且显示卡号和刷卡时间，机具号。
卡片的解析类型就是你要选择你用的卡片是什么类型的卡，如IC，ID的读的方式。
2.4.2 纪录存储/名单检查在工作模式中还有一项是很重要的就是纪录存储/名单检查，在这个界面中两个模块进行不同的设置，就会出现不同的结果，纪录存储模式中，可以同时纪录正常刷卡纪录和非法刷卡纪录，非允许时段刷卡操作时存储纪录等。
如果在前面打勾的话就选中，就会对所有的刷卡信息进行纪录。
在刷卡检查方式中，如果在前面打勾就会对用户的授权信息进行检查，如果不在授权范围内的话就不允许刷卡或者是无效卡。
2.4.3 操作响铃提示所以以上设置如果设置不同，就会出现不能打卡或者其他原因。
下面介绍操作响铃提示，就是你选择在什么情况下刷卡会响铃。
如：正常刷卡响铃，非法刷卡响铃，重复刷卡响铃等。
2.4.4外接设备设定外接设备设定，是除了考勤设备外还接有其他设备，如报警灯等就需要在这个界面中来设置。
如图：2.5、校正时间是对设备上显示的时间和电脑上的时间进行同步。
如果设备和电脑没有正常连接，就会出现校正时间失败，如图：2.6、设置密码就是对现在在线的设备进行密码的设置。
2.7、修改波特率前面已经提到我们的机具有几种波特率，前面已经很详细了，所以在这里就不多讲，就是对机具修改不同波特率进行通讯。
2.8、实时监控就是随时可以看见刷卡的信息，电脑和考勤机上的数据是同步的，监视的类型分为“刷卡结果处理报告查询”就是显示出刷卡的是否为正常刷卡，同时显示刷卡卡号，时间，机号，标识。
“监视刷卡卡号查询报告/允许PC端发送信息”就是只对卡号进行监视，确认卡是否是有效卡，如果是刷卡成功就会自动发送消息。
2.9、取回时间也是对通讯同步的检测，并且对机具的时间取出来进行显示。
2.10、机具状态是显示当前机具的存储状态。
可以看到石碑的序列号，允许存储的最大纪录数和已存储的打卡纪录数，允许存储的最大名单其中白名单数和黑名单数，门禁的通行名单数等。
这样在这里面就可以对机具的当前状态一目了然了。
2.11、清除数据就是只对机具上的打卡纪录进行清除，一般在打卡打满了已经采集完数据之后才进行数据的清除，如果在未采集数据就将数据清除是不能再恢复的，希望在操作时慎用这个功能。
2.12 在线检测是对设备是否与电脑正常连接，而进行的检测，可以检测到那些设备在线，如果检测成功就会出现100%。
并且连接显示绿色。
否则就会显示黄色。
3. 参数设置3.1 刷卡间隔刷卡间隔分为自由间隔和重复间隔。
自由间隔是指两次的刷卡时间之间的长短，我们可以设置的范围是：0~255，每个单位表示0.25秒。
我们通常都设置为“0”意思是不需要间隔，卡任何时候只要放在机具上就可以读取卡。
此外还有重复间隔，是为什么防止在一段时间，连续刷几次卡！外接设备的点亮时间，这个根据外接的设备来确定时间，一般是机具默认。
4.显示控制4.1 自定义显示显示控制分为自定义显示：就是可以根据客户的需要来显示开机信息，产品的型号，产品名称等都是可以由自己来设定。
如果空白就显示本公司的信息。
显示控制参数，可以对刷卡信息在机具上显示保留时间的长短设置，我们一般设置为3秒，卡号长度一般设置为8~10位。
在显示参数中，我们还增加了“高级设置”，可以选择使用的语言，时间显示的格式，日期，图标等；刷卡显示信息的控制，在进入页面后按照自己的需要设置就可以了。
设置简单易看懂，就不用一一介绍了。
5.时段设置5.1 考勤时段设置时段设置分为：考勤时段设置和打铃时段设置。
选择考勤时段，然后进行添加的，考勤时段的设置是设置在哪段时间范围内打卡才是有效的或者是才能打卡的，不在时段内是不能打卡的。
5.2打铃时段设置打铃时段的设置：比如设置在星期一到星期六下午17：30设置为下班打铃时段，持续时间10秒钟，就会设置的时间17：30开始打铃，提示下班时间。
6. 考勤名单管理考勤名单管理：是将所有考勤人员信息写入设备。
可以进行一个一个的添加名单，直接输入卡号确定，就会在列表中小时出现，然后再将名单写入到设备中，这样这个人的信息就存储在机具中了。
如图：为了节省时间和导入的数量，我们还增加了批量导入的方式。
直接先用文档建好名单，然后直接入到设备列表中去。
有人肯定要问了，那我怎么知道要什么样的格式才能导入进去呢？的确如果格式不对的话就不能导入成功，所以我们在建名单前，先用上面的添加名单，添加一个卡号和姓名到列表中去，然后再用软件上的导出功能将刚刚添加进去的名单导出来存储在指定的位置，这样不就有了格式了吗？我们可以进行白名单和黑名单的写入，在这里就只介绍白名单的导入，黑名单和白名单的导入操作都是一样的。
导入名单到列表中后不代表机具中有已经存在名单了，所以大家不要在这个时候就认为工作做完了，因为我们只是将名单导进列表，并没有写入设备，所以接来我们要将名单写入设备中去，如图：此外还增加了查询功能，就是查询某个员工的信息是否已经写入到设备中去了，输入卡号查询是否存在。
如果设备中已经有名单了，就会出现以下的提示，如图：“0001卡号机存在卡号=01，姓名=张三的白名单”。
7. 分组设置和IC卡操作IC卡存储区域：IC卡分为：16个存储扇区，密码存储在0扇区，其他扇区就可以对IC 卡的信息进行存储，这样选择扇区存储的好处在于一张卡可以同时在几中不同的机具上使用。
而每个机具又只会识别本机具存储进去的扇区信息，并且他们之间不会互相干扰，或者读取错误。
还可以对IC卡进行设置密码。
发卡方式，在这个接口软件中，我们软件也同样提供了两种发卡方式：单张和批量发卡。