DM74LS299WM中文资料

© 2000 Fairchild Semiconductor Corporation DS009827October 1988Revised March 2000DM74LS299 8-Input Universal Shift/Storage Register with Common Parallel I/O PinsDM74LS2998-Input Universal Shift/Storage Register with Common Parallel I/O PinsGeneral DescriptionThe DM74LS299 is an 8-bit universal shift/storage register with 3-STATE outputs. Four modes of operation are possi-ble: hold (store), shift left, shift right and load data. The par-allel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Separate outputs are provided for flip-flops Q0 and Q7 to allow easy cascad-ing. A separate active LOW Master Reset is used to reset the register.Featuress Common I/O for reduced pin counts Four operation modes: shift left, shift right, load and store s Separate shift right serial input and shift left serial input for easy cascading s 3-STATE outputs for bus oriented applicationsOrdering Code:Devices also available in T ape and Reel. Specify by appending the suffix letter “X” to the ordering code.Logic Symbol V CC = Pin 20GND = Pin 10Pin DescriptionsConnection DiagramOrder Number Package NumberPackage DescriptionDM74LS299WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74LS299NN20A20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 WidePin Names DescriptionCP Clock Pulse Input (Active Rising Edge)D S0Serial Data Input for Right Shift D S7Serial Data Input for Left Shift S0, S1Mode Select InputsMRAsynchronous Master Reset Input (Active LOW)OE1, OE23-STATE Output Enable Inputs (Active LOW)I/O0–I/O7Parallel Data Inputs or 3-STATE Parallel Outputs Q0–Q7Serial Outputs 2D M 74L S 299Functional DescriptionThe DM74LS299 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform syn-chronous shift left, shift right, parallel load and hold opera-tions. The type of operation is determined by the S0 and S1, as shown in the Mode Select Table. All flip-flop outputs are brought out through 3-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words.A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initi-ated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the rec-ommended setup and hold times, relative to the rising edge of CP, are observed.A HIGH signal on either OE1 or OE2 disables the 3-STATE buffers and puts the I/O pins in the high impedance state.In this condition the shift, hold, load and reset operations can still occur. The 3-STATE buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a paral-lel load operation.Mode Select TableH = HIGH Voltage Level L = LOW Voltage Level X = Immaterial= LOW-to-HIGH Clock (CP) TransitionLogic DiagramInputs ResponseMR S1S0CP L X X XAsynchronous Reset; Q0–Q7 = LOWH H H Parallel Load; I/O n →Q nH L H Shift Right; D S0→Q0, Q0→Q1, etc.H H L Shift Left; D S7→Q7, Q7→Q6, etc.HLLXHoldDM74LS299Absolute Maximum Ratings (Note 1)Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings.The “Recommended Operating Conditions” table will define the conditions for actual device operation.Recommended Operating ConditionsSupply Voltage 7V Input Voltage7VOperating Free Air Temperature Range 0°C to +70°C Storage Temperature Range−65°C to +150°CSymbol ParameterMin Nom Max Units V CC Supply Voltage4.7555.25V V IH HIGH Level Input Voltage 2V V IL LOW Level Input Voltage 0.8V I OH HIGH Level Output Current Q0, Q7−0.4mA I/O0–I/O7−2.6mA I OL LOW Level Output Current Q0, Q78mA I/O0–I/O724mA T A Free Air Operating Temperature 070°C t S (H)Setup Time HIGH or LOW 24ns t S (L)S0 or S1 to CP24t H (H)Hold Time HIGH or LOW 0ns t H (L)S0 or S1 to CP0t S (H)Setup Time HIGH or LOW 10ns t S (L)I/O n , D S0, D S7 to CP 10t H (H)Hold Time HIGH or LOW 0ns t H (L)I/O n , D S0, D S7 to CP0t W (H)CP Pulse Width HIGH or LOW15ns t W (L)15t W (L)MR Pulse Width LOW 15ns t RECRecovery Time 10nsMR to CP 4D M 74L S 299Electrical CharacteristicsOver recommended operating free air temperature range (unless otherwise noted)Note 2: All typicals are at V CC = 5V, T A = 25°C.Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.Switching CharacteristicsV CC = +5.0V, T A = +25°CSymbol ParameterConditionsMinTyp Max Units (Note 2)V I Input Clamp Voltage V CC = Min, I I = −18 mA −1.5V V OH HIGH Level V CC = Min, I OH = Max Q0, Q7 2.7 3.4VOutput Voltage V IL = Max I/O0–I/O72.4V OLLOW Level V CC = Min, I OL = Max0.350.5Output VoltageV IH = MinV I OL = 4 mA, V CC = Min 0.250.4I I Input Current @ Max V CC = Max Inputs 0.1mA Input Voltage V I = 7VSn 0.2mA I IH HIGH Level V CC = Max, V I = 2.7VSn 40µA Input CurrentInputs 20µA I IL LOW Level V CC = Max, V I = 0.4V Sn −0.8mA Input Current Inputs−0.4mA I OS Short Circuit V CC = Max Q 0, Q 7−20−100mA Output Current (Note 3)I/O 0–I/O 7−30−130I CC Supply Current V CC = Max, OE = 4.5V 60mA I OZH 3-STATE Output Off V CC = Max 40µA Current HIGH V O = 2.7V I OZL3-STATE Output Off V CC = Max −400µACurrent LowV O = 0.4VSymbol ParameterR L = 2 k ΩUnitsC L = 15 pFMinMaxf MAX Maximum Input Frequency 35MHz t PLH Propagation Delay 26ns t PHL CP to Q0 or Q728t PLH Propagation Delay 25ns t PHL CP to I/O n35t PHL Propagation Delay 28ns MR to Q0 or Q7t PHL Propagation Delay 35ns MR to I/O nt PZH Output Enable Time18ns t PZL 25t PHZ Output Disable Time15ns t PLZ20DM74LS299Physical Dimensions inches (millimeters) unless otherwise noted20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 WidePackage Number M20B6D M 74L S 299 8-I n p u t U n i v e r s a l S h i f t /S t o r a g e R e g i s t e r w i t h C o m m o n P a r a l l e l I /O P i n sPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 WidePackage Number N20AFairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。