DDS信号发生器电路设计
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1. 信号产生部分
1.1 频率控制字输入模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity ddsinput is
port(a,b,c,clk,clr:in std_logic;
q1,q2,q3,q4,q5:buffer unsigned(3 downto 0));
end ddsinput;
architecture a of ddsinput is
signal q:std_logic_vector(2 downto 0);
begin
q<=c&b&a;
process(cp,q,clr)
begin
if clr='1'then q1<="0000";q2<="0000";q3<="0000";q4<="0000";q5<="0000"; elsif clk 'event and clk='1'then
DDS信号信号发生器电路设计
case q is
when"001"=>q1<=q1+1;
when"010"=>q2<=q2+1;
when"011"=>q3<=q3+1;
when"100"=>q4<=q4+1;
when"101"=>q5<=q5+1;
when others=>NULL;
end case;
end if;
end process;
end a;
1.2 相位累加器模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity xiangwei is
port(m:in std_logic_vector(19 downto 0);
clk,clr:in std_logic;
data:out std_logic_vector(23 downto 0)); end xiangwei;
architecture a of xiangwei is
signal q:std_logic_vector(23 downto 0);
begin
process(clr,clk,m,q)
begin
if clr='1'then q<="000000000000000000000000"; elsif (clk'event and clk='1')then
q<=q+m;
end if;
data<=q;
end process;
end a;
向学壮201308354020
2. ROM数据存储器
3. 数码管显示部分
3.1 七段数码管显示模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY led7seg_1 IS
PORT ( A : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
LED7S : OUT STD_LOGIC_VECTOR(12 DOWNTO 0) ) ; END ;
DDS信号信号发生器电路设计
ARCHITECTURE one OF led7seg_1 IS
BEGIN
PROCESS( A )
BEGIN
CASE A IS
WHEN "00" => LED7S <= "0000000011111";
WHEN "01" => LED7S <= "0100100011111";
WHEN "10" => LED7S <= "1111001011111";
WHEN "11" => LED7S <= "0010010011111";
WHEN OTHERS => NULL ;
END CASE ;
END PROCESS ;
END ;
4. 总电路图
a,b,c是改变波形频率
key_1选择波形，有锯齿波、三角波、方波、正弦波。
向学壮201308354020 锯齿波
三角波
方波
DDS信号信号发生器电路设计正弦波