Mstart屏参配置

MStar方案屏参配置【屏类型结构体定义PanelType】文档位置：《apiPNL.h》 /// A panel struct type used to specify the panel attributes, and settings from Board l ayouttypedef struct{const char *m_pPanelName; ///< PanelName 屏的名称 //// Panel output //MS_U8 m_bPanelDither :1; ///< PANEL_DITHER, keep the setting//Sub BK VOP_36(不同芯片，此值可能不一样)，bPanelDither=1->0x2D05，bPanelDither=0->0x2D00APIPNL_LINK_TYPE m_ePanelLinkType :4; ///< PANEL_LINK//Sub BK VOP_44(不同芯片，此值可能不一样)，LVDS=0x11，RSDS=0x00/////////////////////////////////////////////////Board related setting///////////////////////////////////////////////MS_U8 m_bPanelDualPort :1; ///< VOP_21[8], MOD_4A[1], PANEL_DUAL_PORT, refer to m_ bPanelDoubleClkMS_U8 m_bPanelSwapPort :1; ///< MOD_4A[0], PANEL_SWAP_PORT, refer to "LVDS output a pp note" A/B channel swapMS_U8 m_bPanelSwapOdd_ML :1; ///< PANEL_SW AP_ODD_ML //蒙上灰MS_U8 m_bPanelSwapEven_ML :1; ///< PANEL_SW AP_EVEN_ML //蒙上灰MS_U8 m_bPanelSwapOdd_RB :1; ///< PANEL_SWAP_ODD_RB //缺色MS_U8 m_bPanelSwapEven_RB :1; ///< PANEL_SWAP_EVEN_RB //缺色MS_U8 m_bPanelSwapLVDS_POL :1; ///< MOD_40[5], PANEL_SWAP_LVDS_POL, for differe ntial P/N swap //正负极性切换MS_U8 m_bPanelSwapLVDS_CH :1; ///< MOD_40[6], PANEL_SWAP_LVDS_CH, for pair swa p//双通道切换MS_U8 m_bPanelPDP10BIT :1; ///< MOD_40[3], PANEL_PDP_10BIT ,for pair swapMS_U8 m_bPanelLVDS_TI_MODE :1; ///< MOD_40[2], PANEL_LVDS_TI_MODE, refer to "L VDS output app note"//说明当前的屏是不是TI mode///////////////////////////////////////////////// For TTL Only///////////////////////////////////////////////MS_U8 m_ucPanelDCLKDelay; ///< PANEL_DCLK_DELAYMS_U8 m_bPanelInvDCLK :1; ///< MOD_4A[4], PANEL_INV_DCLK MS_U8 m_bPanelInvDE :1; ///< MOD_4A[2], PANEL_INV_DEMS_U8 m_bPanelInvHSync :1; ///< MOD_4A[12], PANEL_INV_HSYNC MS_U8 m_bPanelInv VSync :1; ///< MOD_4A[3], PANEL_INV_VSYNC///////////////////////////////////////////////// Output driving current setting///////////////////////////////////////////////// driving current setting (0x00=4mA, 0x01=6mA, 0x02=8mA, 0x03=12mA)MS_U8 m_ucPanelDCKLCurrent; ///< define PANEL_DCLK_CURRENT //Sub VOP_？？[6:7](不同芯片，此值可能不一样)，MS_U8 m_ucPanelDECurrent; ///< define PANEL_DE_CURRENT //Sub VOP_？？[4:5](不同芯片，此值可能不一样)，MS_U8 m_ucPanelODDDataCurrent; ///< define PANEL_ODD_DA TA_CURRENT //Sub VOP_ [2:3](不同芯片，此值可能不一样)，MS_U8 m_ucPanelEvenDataCurrent; ///< define PANEL_EVEN_DATA_CURRENT //Sub VOP _？？[0:1](不同芯片，此值可能不一样)，///////////////////////////////////////////////// panel on/off timing///////////////////////////////////////////////MS_U16 m_wPanelOnTiming1; ///< time between panel & data while turn on powerMS_U16 m_wPanelOnTiming2; ///< time between data & back light while turn on powerMS_U16 m_wPanelOffTiming1; ///< time between back light & data while turn off powerMS_U16 m_wPanelOffTiming2; ///< time between data & panel while turn off power///////////////////////////////////////////////// panel timing spec.///////////////////////////////////////////////// sync relatedMS_U8 m_ucPanelHSyncWidth; ///< VOP_01[7:0], PANEL_HSYNC_WIDTHMS_U8 m_ucPanelHSyncBackPorch; ///< PANEL_HSYNC_BACK_PORCH, no register setting, provide value for query only,///< not support Manuel VSync Start/End now///< VOP_02[10:0] VSync start = Vtt - VBackPorch - VSyncWidth ///< VOP_03[10:0] VSync end = Vtt - VBackPorchMS_U8 m_ucPanelVSyncWidth; ///< define PANEL_VSYNC_WIDTH MS_U8 m_ucPanelVBac kPorch; ///< define PANEL_VSYNC_BACK_PORCH // DE relatedMS_U16 m_wPanelHStart; ///< VOP_04[11:0], PANEL_HSTART, DE H Start (PANEL_HSYNC _WIDTH + PANEL_HSYNC_BACK_PORCH)MS_U16 m_wPanelVStart; ///< VOP_06[11:0], PANEL_VSTART, DE V StartMS_U16 m_wPanelWidth; ///< PANEL_WIDTH, DE width (VOP_05[11:0] = HEnd = HStart + Width - 1)MS_U16 m_wPanelHeight; ///< PANEL_HEIGHT, DE height (VOP_07[11:0], = Vend = VStart + Height - 1) // DClk relatedMS_U16 m_wPanelMaxHTotal; ///< PANEL_MAX_HTOTAL. Reserved for future using. MS_U 16 m_wPanelHTotal; ///< VOP_0C[11:0], PANEL_HTOTALMS_U16 m_wPanelMinHTotal; ///< PANEL_MIN_HTOTAL. Reserved for future using. MS_U1 6 m_wPanelMaxVTotal; ///< PANEL_MAX_VTOTAL. Reserved for future using. MS_U16 m_w PanelVTotal; ///< VOP_0D[11:0], PANEL_VTOTALMS_U16 m_wPanelMinVTotal; ///< PANEL_MIN_VTOTAL. Reserved for future using. MS_U8 m_dwPanelMaxDCLK; ///< PANEL_MAX_DCLK. Reserved for future using. MS_U8 m_dwPan elDCLK; ///< LPLL_0F[23:0], PANEL_DCLK ,{0x3100_10[7:0], 0x3100_0F[15:0]}MS_U8 m_dwPanelMinDCLK; ///< PANEL_MIN_DCLK. Reserved for future using. ///< spread spectrumMS_U16 m_wSpreadSpectrumStep; ///< move to board define, no use now. MS_U16 m_wSpread SpectrumSpan; ///< move to board define, no use now. MS_U8 m_ucDimmingCtl; ///< Initial Dim ming Value MS_U8 m_ucMaxPWMVal; ///< Max Dimming Value MS_U8 m_ucMinPWMV al; /// < Min Dimming ValueMS_U8 m_bPanelDeinterMode :1; ///< define PANEL_DEINTER_MODE, no use nowE_PNL_ASPECT_RA TIO m_ucPanelAspectRatio; ///< Panel Aspect Ratio, provide information t o upper layer application for aspect ratio setting. /* ** Board related params ** If a board ( like BD_MST064C_D01A_S ) swap LVDS TX polarity * : This polarity swap value =* (LVDS_PN_SW AP_H<<8) | LVDS_PN_SW AP_L from board define, * Otherwise* : The value shall set to 0. */MS_U16 m_u16LVDSTxSwapValue;APIPNL_TIBITMODE m_ucTiBitMode; ///< MOD_4B[1:0], refer to "LVDS output app note" 当颜色不对的时候，就可以调整这个设定来试验APIPNL_OUTPUTFORMA T_BITMODE m_ucOutputFormatBitMode; //Define panel output for mat bit mode.The default value is 10bit,because 8bit panel can use 10bit config and 8bit config.Bu t 10bit panel(like PDP panel) can only use 10bit config.And some PDA panel is 6bit. MS_U8 m_b PanelSwapOdd_RG :1; ///< define PANEL_SWAP_ODD_RG MS_U8 m_bPanelSwapEven_RG : 1; ///< define PANEL_SWAP_EVEN_RGMS_U8 m_bPanelSwapOdd_GB :1; ///< define PANEL_SWAP_ODD_GB MS_U8 m_bPanelSwa pEven_GB :1; ///< define PANEL_SWAP_EVEN_GB//Sub MOD_??[2:5]，Odd_RG:bit3，Odd_GB:bit2，Even_RG:bit5，Even_GB:bit4 /** * Others */ MS_U8 m_bPanelDoubleClk :1; ///< LPLL_03[7], define Double Clock ,LVDS dual mode MS_U32 m_dwPanelMaxSET; ///< define PANEL_MAX_SET MS_U32 m_dwPanelMinSET; ///< define PANEL_MIN_SET //这个值会限定FPLL LOCK的范围，也就是LPLL_D5D6D7 //1.reg_frame_lpll_en:LPLL_18[3]=0//2.reg_lpll_set调整：手动调整SET(BK31_1E,1F,20)值，观察OSD是否异常找出Max/Min SET,写入代码需要除2.APIPNL_OUT_TIMING_MODE m_ucOutTimingMode; ///<Define which panel output timing ch ange mode is used to change VFreq for same panel 目前有三种选择:E_PNL_CHG_DCLK, E_PNL_CHG_HTOTAL, E_PNL_CHG_VTOTAL, 后面两者都是为了保持DCLK不变而修改HTOTAL/VTOTAL.MS_U8 m_bPanelNoiseDith :1; ///< PAFRC mixed with noise dither disable } PanelType;【名词解释】Port swap:只用在dual port (FHD在板子上有两组LVDS)，将两个LVDS互换 Channel swap:一个LVDS里面有很多channel, 6bit: CH0 CH1 CH2 CLK 8bit: CH0 CH1 CH2 CLK CH3 10bit: CH0 CH1 CH2 CLK CH3 CH4 以8bit为例，Channel swap enable后会有以下行为：CH0 <-> CH3、CH1 <-> CLK、CH2 <-> CH2 ，就是水平交换 Polarity swap:每个Channel 都有 Even(P)、Odd(M) 两个极性，Polarity swap就是将每个channel里的两个极性交换。