加州理工学院-计算系统导论 (38)

¢ Started to look at two implementation issues ¢ Issue 1: Page tables live in main memory
As much as 100ns away from the MMU! Caches would help with this, but page table entries
load programs, and to perform fast and easy IO ¢ Set permissions on memory pages to make some
pages read-only, or inaccessible by user code
LAST TIME: IMPLEMENTATION ISSUES
page table that the MMU uses ¢ Share memory regions between processes, such
as shared libraries, kernel code, working areas ¢ Memory-map disk files into virtual memory, to
Showed the processor using a single page table Real-world system doesn’t work that way!
¢ Given a 32-bit address space, and pages of 4KB:
Page offsets take 12 bits, page numbers are 20 bits
CPU
mov 307, %ebx
TLB
Virtual Address = 307
MMU
PTE
Physical Address = 7 Page Table
Main Memory 0123 4567 8 9 10 11
TRANSLATION LOOKASIDE BUFFER
¢ Translation lookaside buffer stores one page table entry per cache line
IMPLEMENTATION ISSUES (2)
¢ CPUs frequently use a Translation Lookaside Buffer (TLB) to cache page table entries Designed to be extremely fast Don’t even want to incur L1 or L2 penalty, if possible!
¢ Also added more details to page table entries
Entries have a valid (IA32: “present”) flag specifying if the page is in memory, and if not, where it resides
would still be 4-25ns away
CPU
mov 307, %ebx
Virtual Address = 307
MMU
Physical Address = 7 Page Table
Main Memory 0123 4567 8 9 10 11
¢ Can’t afford memory perf源自文库rmance being this bad!
CPU
TLB
mov 307, %ebx VPN
PTE
Virtual Address = 307
MMU
PTE
Physical Address = 7 Page Table
Main Memory 0123 4567 8 9 10 11
IMPLEMENTATION ISSUES (3)
¢ Issue 2: How large are page tables?
Operating system must handle situations where pages must be moved into and out of memory
CPU raises page fault and general protection fault exceptions when it requires the kernel’s intervention
Input is virtual page number, output is page table entry
¢ TLB typically has a high degree of associativity
Maximize chance that TLB contains needed page table entry!
Also permission flags, e.g. “read/write,” “supervisor”
¢ Requires both hardware and software support:
CPU performs address translation in hardware to make it as fast as possible
LAST TIME (2)
¢ Can now implement many useful features!
¢ Isolate address spaces of different processes ¢ Perform fast context-switches by changing the
CS24: INTRODUCTION TO COMPUTING SYSTEMS
Spring 2013 Lecture 24
LAST TIME
¢ Extended virtual memory concept to be a cache of memory stored on disk
DRAM becomes L4 cache of data stored on disk