Cyclone III资料

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EP3C10E144C8中文资料(Altera)中文数据手册「EasyDatasheet - 矽搜」

对于Cyclone III器件最大额定值.
表1-1 列出绝对
芯片中文手册,看全文,戳
1–2
第 1章： Cyclone III器件数据表
电气特性
1
超出所列条件
表1-1 对器件造成永久性损坏.
此外,在延长时间周期绝对最大额定值设备操作具有设备不利影响.
表 1-1. Cyclone III器件绝对最大额定值
(1)
符
参数
况
过冲持续时间为％高时间
VI = 3.95 V
100
VI = 4.0 V
95.67
VI = 4.05 V
55.24
VI = 4.10 V
31.97
VI = 4.15 V
18.52
VI = 4.20 V
10.74
Vi
交流输入电压
VI = 4.25 V VI = 4.30 V
6.23 3.62
Cyclone III器件.稳态电压和预期电流值
III器件中提供旋风
表1-3.
没有高原.
所有系统必须严格单调
表 1-3. Cyclone III器件推荐工作条件
(1), (2)
符
参数
条件
Min Typ Max Unit
VCCINT (3)
电源电压为内部逻辑
电源电压为输出缓冲器,3.3-V
手术
—
1.15 1.2 1.25
运行条件
当Cyclone III器件在一个系统中实现,它们是根据一组定义参数分级.为防护持 Cyclone III器件中最高性能和可靠性,系统设计人员必须考虑本文件中操作要求. Cyclone III器件提供商用,工业和汽车级版本.商业设备在-6（最快）,-7和-8速度等级提供.工业和汽车设备仅在-7速度年级课程.

cycione3_dataSheet

Note to Table 1–2:
(1) Figure 1–1 shows the methodology to determine the overshoot duration. In the example in Figure 1–1, overshoot voltage is shown in red and is present on the input pin of the Cyclone III device at over 4.1 V but below 4.2 V. From Table 1–1, for an overshoot of 4.1 V, the percentage of high time for the overshoot can be as high as 31.97% over a 10-year period. Percentage of high time is calculated as ([delta T]/T) × 100. This 10-year period assumes the device is always turned on with 100% I/O toggle rate and 50% duty cycle signal. For lower I/O toggle rates and situations in which the device is in an idle state, lifetimes are increased.
© June 2009 Altera Corporation
Chapter 1: Cyclone III Device Data Sheet Electrical Characteristics
1–3
Figure 1–1 shows the methodology to determine the overshoot duration.

Cyclone_III配置

Cyclone III 的配置全文翻译自Altera公司Cyclone III的器件手册。

所有表格与图标标号与手册原文一致，以便于查对。

出于个人需要，仅翻译了AS与JTAG配置两部分，且仅都配置一片FPGA芯片。

可以通过压缩数据的方法以节约存储空间，并节省程序load时间（page 220）；9通过Remote System Upgrade方式可以减少新产品面市的时间（page 221）；9AS Configuration（Serial Configuration Devices）¾表10-6显示的是对各种配置电平来说，MSELx管脚的接法¾单一器件配置四个接口管脚包含了串口时钟（DCLK），串行数据输出（DATA），AS 数据输入（ASDI），以及低电平有效的片选信号（nCS）。

注：1)上拉一个电阻，连接到该管脚所在的bank的VCCIO；2)Cyclone III器件通过DATA[1]-to-ASDI路径控制配置芯片；3)nCEO管脚浮空，或者当没有连接到另一个器件的nCE管脚时，可以当作通用IO使用；4)MSEL管脚的设置，用于选择不同的电平标准和不同的POR时间；参考表10-6，选择接法；5)这些是复用管脚。

FLASH_nCE管脚在AS配置电路图中当作nCSO功能使用，DATA[1]管脚当作ASDO功能使用；6)这些串接的电阻尽可能靠近配置芯片当连接一个配置芯片到Cyclone III器件时，DATA[0]管脚必须串一个电阻，并应接近配置芯片。

配置器件和Cyclone III芯片间连线的长度应符合表10-8所推荐的值。

当选择AS配置方式的时候，BAMK 1的IO电压必须是3.3，3.0或2.5。

上电以后，CIII器件有一个POR时间的延迟，在此期间，nSTATUS和CONF_DONE 会一直为低，所有的IO也都是三态输出。

芯片配置的三个阶段分别是复位，配置和初始化。

当nCONFIG或者nSTATUS为低，芯片处于复位状态，经过POR时间后，CIII释放nSTATUS，进入配置模式。

CycloneIII设计向导

CycloneIII设计向导CycloneIII设计向导第一篇：芯片选型1.考虑器件的资源，包括LE,ram资源，硬件乘法器，PLL，全局时钟网络等。

总体来说，对于FPGA设计，资源一定要留有余量，否则最后的时序收敛会比较困难。

我认为使用80%左右是比较合适的。

对于资源使用量在95%以上的设计，除了时序收敛，可能还会遇到一些你想不到的问题。

A. LE是5K到120K。

要对设计需要的资源做一个估算，120K，对于大部分的应用，应该是一个很大的数字了。

B.ram资源为400K-3888Kbit.注意ram块的大小都是9Kbit,有些模块，比如fifo，实际上用不到9K的资源。

但不管你用多少，都得占用一个ram（有些情况下占用0.5个ram)。

所以ram 的数量是否足够也得考虑。

C.乘法器的数量23-288个。

注意是18*18bit的乘法器。

实际使用时，要看应用需要的乘法器精度是多少。

D.PLL的数量为2-4个。

每个PLL可以输出5个时钟，一般的设计够用了。

如果设计中的时钟很多，就得仔细考虑了。

E.全局时钟网络为10-20个。

一般够用，如果设计中有很多时钟或者很多扇出(fan-out)很大的信号,比如复位信号，也得仔细考虑。

2.考虑引脚，封装和迁移A.引脚数量。

设计前，就要考虑需要多少普通IO(LVTTL），这个应该是比较好计算的。

电平有几种，因为一个bank只能1个IO电平。

需要多少LVDS管脚，一些小封装器件的LVDS管脚很少。

B.封装。

封装影响到引脚数量。

还影响到焊接的难度。

EQFP和PQFP当然好焊接也好拆卸，如果是BGA的，一般需要找专人焊接（需要专门的工具），价格也贵。

布线难度：用BGA，还得出注意ball pitch(焊接球的间距）。

1.0mm的当然比0.8mm的好布线。

F780比F484的外圈引脚数量多，当然也好布线一些。

体积：也就是芯片的大小了，比如用于移动和手持应用，就得考虑大小了。

Altera Cyclone III系列FPGA开发板简介

ETL-002 Altera Cyclone III系列FPGA开发板简介概述ETL-002 FPGA开发板是以Altera公司的最新系列Cyclone III中的3C10为主芯片，并提供了极为丰富的芯片外围接口资源以及下载线，数据线以及资料光盘等。

除了这些硬件外，我们还提供了十多个接口实验，并公开了电路原理图和实验的Verilog源代码，以便于大家对照学习，并可以在该开发板上进行二次开发。

单板描述主芯片EP3C10提供了10320个逻辑单元（LE），46块SRAM（每块9K bits）, 23个18*18的乘法器。

开发板自带USB供电电路：您只需将USB线插上您的USB端口，无需外接＋5V直流电源，开发板即可工作。

开发板同时支持AS模式下载和JTAG模式下载。

程序固化既可通过JTAG口也可直接对板上的FLASH进行编程。

丰富的外围接口可满足常用的外设的人机交互，我们还将剩下未用的40个用户I/O引脚全部引出，使得您可以通过这些信号对本开发板进行电路扩展。

这些接口主要包括：PS2鼠标接口：可以将PS2鼠标的任何移动的信息反应在数码管上PS2键盘接口：可以将PS2键盘上的任意按键以16进制的信息反应在数码管上VGA显示器接口：可以将FPGA产生的信息反映在VGA显示器上。

开发板自带了动态彩条显示的功能双串口接口：可以与任何的串口设备相接。

开发板自带的演示程序是将PC上的超级终端中输入的任何信息返回PC 4位数码管：可以实时显示任何的数字信息。

开发板自带的演示程序实时地显示分钟和秒钟的信息。

4位LED灯：用于指示状态。

开发板自带了跑马灯实验。

4位按键开关：可用于复位等作用。

4位拨码开关：可用于电路的选择作用教学实验除了开发板的丰富的硬件资源外，我们还提供了数十个学习实验。

通过这些实验，您可以学习FPGA芯片，Quartus II软件和设计仿真和下载等FPGA的设计流程，然后将试验中程序执行的信息通过数码管，LED 灯，串口等板上的硬件直观的显示出来。

在65nm Cyclone III FPGA中实现低功耗

在65nm Cyclone III FPGA中实现低功耗低功耗、低成本和高性能FPGA――CycloneIII系列，采用了TSMC的65nm工艺，含有5K至120K逻辑单元，288个DSP乘法器，存储器达到4Mb，比前一代产品逻辑单元成本降低20％，主要针对消费类、汽车、工业和无线通信等市场。

CycloneIII在单个器件中集成了SDR信号处理，静态功耗低于0.5W，可满足软件无线电的应用。

与前一代产品和竞争产品相比，CycloneIIIFPGA的低功耗、高密度和充足的DSP功能，使设计人员可以在无线应用中使用低成本系列产品，例如无线微基站的数字IF和基带功能等。

在视频系统I/O、视频压缩编码以及视频和图像处理应用中，客户能够以低于20美元的成本实现全H.264编码器，或低于5美元的成本实现高清晰缩放功能。

CycloneIII器件针对显示应用进行了优化，能够满足所有1080pHDTV性能需求。

采用专业显示I/O接口(mini-LVDS、低摆幅差分信号和点对点差分信号)来构建CycloneIII系列，与前一代产品相比，每个锁相环(PLL)有更多的输出，动态配置PLL支持可变刷新率。

客户可以针对多种显示尺寸和分辨率设计单一平台，成本只有4美元。

还可以结合现有的ASIc/ASSP器件来使用cycloneIII器件，以提高图像质量和功能。

工程师可以在QuartnsII设计软件7.0中开始CycloneIII 系列设计，该软件的订购版和免费的网络版支持所有的系列型号。

传统上，人们总是期望新一代FPGA具有更好的特性和性能。

然而，设计工程师必须将这些新特性和高性能集成在与上一代产品相同、甚至更小尺寸的芯片上，并要保持芯片功耗不变。

此外，某些应用还必须要满足一些特殊的功耗要求。

结果，功耗在设计工程师的FPGA选择标准中扮演了越来越重要的角色。

为了能够以最低的功耗来实现65nm工艺节点的低成本和高性能特性，Altera结合硅工艺优化和Quartus II PowerPlay 功耗分析及优化技术，生产了功耗非常低的65nm低成本FPGA――Cyclone III。

cyclone3引脚整理

当配置完成后，输出驱动为低。当多设备配置时，该引脚要接到后续设备的nCE 脚，通过外部10-K Ω 上拉电阻拉高至VCIO。单设备配置和多设备配置的最后一个设备时，引脚要
FLASH_nC E, nCSO
I/O, Output(A S, AP Note 13
DATA1, ASDO
PLL[1..4 ]_CLKOUT p Note 3
I/O, Output
Clock, Input
来自于 PLL [1..4]. 的可选 positive 正端外部时钟输出。该引脚如果被用作PLL输出，能被指定为单端或差分 I/O标准。
专用全局时钟输入引脚，用于差分全局时钟输入或用户输入引脚的 negative 负端输入。不支持编程弱上拉电阻。不使用时连接到 GND,注9.
MSEL[0.. 3]
Input
配置输入引脚，用来设置 Cyclone III 设备配置方案。一些较小的设备或包装选项不支持 AP注 13flash 编程，不使用 MSEL3引脚。
这些引脚内部连接 5-KΩ resistor to GND。当未被使用时，连接至GND, 不悬空。 Device Family Handbook ：配置，设计安全性， Cyclone III Devices 远程系统升级。如果使用 JTAG 配置，连到 GND.
nCE 应该接到模式，则 GND
CONF_DON E
Bidirect ional (opendrain)
专用配置状态引脚，随着状态输出，在配置前和配置期间， CONF_DON E pin drives low 当状态输入，所有数据被接收后， CONF_DON E变为高。然后设备初始化，进入用户使用模式。该引脚不可做I/O引脚，引脚应被拉高，通过上拉电阻被释放。 10-KΩ.

Cyclone III FPGA Starter Kit User Guide

101 Innovation DriveSan Jose, CA 95134Cyclone III FPGA Starter KitUser GuideDocument Version: 1.2Document Date: July 2010P25-36228-03© 2010 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at /common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of devicespecifications before relying on any published information and before placing orders for products or services.Part Number UG-01018-1.2ContentsChapter 1. Getting StartedIntroduction............................................................................................................................................1–1 Before You Begin...................................................................................................................................1–2 Further Information..............................................................................................................................1–2 Software Installation.............................................................................................................................1–2 Installing the Cyclone III FPGA Starter Kit..................................................................................1–2 Installing the Quartus II Web Edition Software..........................................................................1–4 Chapter 2. Development Board and Control Panel SetupDevelopment Board Setup...................................................................................................................2–1 Requirements....................................................................................................................................2–2 Powering Up the Development Board..........................................................................................2–2 Installing the USB-Blaster Driver........................................................................................................2–2 Control Panel Setup...............................................................................................................................2–3 Configuring the FPGA Using the Quartus II Programmer.............................................................2–3 Chapter 3. Using the Control PanelOverview.................................................................................................................................................3–1 Control Panel Start................................................................................................................................3–1 LEDs and Buttons..................................................................................................................................3–2 Illuminating LEDs............................................................................................................................3–2 Buttons Indicators............................................................................................................................3–3 DDR SDRAM/SSRAM/On-Chip Controller...............................................................................................................3–3 Read/Write Data..............................................................................................................................3–4 Read from a File................................................................................................................................3–5 Write to a File...................................................................................................................................3–5 Flash Memory Programmer.................................................................................................................3–5 Flash Memory Tab...........................................................................................................................3–6 CFI Query..........................................................................................................................................3–6 Read/Write Data..............................................................................................................................3–7ContentsChapter 4. Measuring Power on the Cyclone III Starter BoardIntroduction............................................................................................................................................4–1 Measuring Power...................................................................................................................................4–2 Changing the Example Design.......................................................................................................4–3 Appendix A. Programming the Configuration Flash DeviceOverview................................................................................................................................................A–1 Creating a Flash-Programmable POF File........................................................................................A–1 Programming the Flash Device..........................................................................................................A–5 Additional InformationRevision –i How to Contact –ii Typographic –ii1.Getting StartedIntroduction Welcome to the Altera® Cyclone®III FPGA Starter Kit, which includes afull-featured field-programmable gate array (FPGA) development board,hardware and software development tools, documentation, andaccessories needed to begin FPGA development.The development board includes an Altera Cyclone III FPGA and comespreconfigured with a hardware reference design stored in flash memory.You can use the development board as a platform to prototype a varietyof FPGA designs.The starter kit provides an integrated control environment that includesa software controller in a control panel application, a USB commandcontroller, a multi-port SRAM/DDR SDRAM/flash memory controller,and example designs specified in Verilog code. You can use this design asa starting point for test designs.This user guide addresses the following topics:■How to set up, power up, and verify correct operation of thedevelopment board.■How to install the Cyclone III FPGA Starter Kit.■How to install the Altera® Quartus II Web Edition software.■How to set up and use the control panel, a graphical user interface(GUI), to manipulate components on the board, implementapplications.■How to configure the Cyclone III FPGA.■How to set up and run example designs.f For complete details on the development board, refer to theCyclone III FPGA Starter Board Reference Manual.Before You BeginBefore You Begin Before proceeding, check the contents of the kit:■Cyclone III FPGA Starter Development Board ■12-V DC power supply■USB cablef For the most up-to-date information on this product, visit the Alterawebsite at /products/devkits/altera/kit-cyc3-starter.html.FurtherInformationFor other related information, refer to the following websites:Software Installation This section describes the following procedures:■“Installing the Cyclone III FPGA Starter Kit”■“Installing the Quartus II Web Edition Software” on page1–4 Installing the Cyclone III FPGA Starter KitThe license-free Cyclone III FPGA Starter Kit installer includes all the documentation and design examples for the kit.To install the Cyclone III FPGA Starter Kit, follow these steps:1.Download the Cyclone III FPGA Starter Kit installer from theCyclone III FPGA Starter Kit page of the Altera website.Alternatively, you can request a development kit DVD from theDevelopment Kits, Daughter Cards & Programming Hardware page of the Altera website.For More Information About Refer ToAdditional daughter cardsavailable for purchase/products/devkits/kit-daughter_boards.jspCyclone III handbook /literature/lit-cyc3.jspCyclone III reference designs /products/devkits/altera/kit-cyc3-starter.htmleStore if you want topurchase devices/buy/devices/buy-devices.htmlCyclone III Orcad symbols /support/software/download/pcb/pcbpcb_index.htmlNios® II 32-bit embeddedprocessor solutions/technology/embedded/emb-index.htmlGetting Started 2.Follow the on-screen instructions to complete the installationprocess.The installation program creates the Cyclone III FPGA Starter Kit directory structure shown in Figure1–1.Figure1–1.Cyclone III FPGA Starter Kit Default Installed Directory StructureTable1–1 lists the file directory names and a description of their contents.Table1–1.Installed Directory ContentsDirectory Name Description of Contentsboard_design_files Contains schematic, layout, assembly, and bill of materialboard design files. Use these files as a starting point for anew prototype board design.demos Contains demonstration projects that may or may notcontain up-to-date source code.documents Contains the development kit documentation.examples Contains the example design files for the Cyclone III FPGAStarter Kitfactory_recovery Contains programming files for returning board to factorydefault condition.Software InstallationInstalling the Quartus II Web Edition SoftwareThe Quartus II Web Edition software provides the necessary tools fordeveloping hardware and software for Altera FPGAs. Included in theQuartus II Web Edition software are the Quartus II software, the Nios IIEDS, and the MegaCore® IP Library. The Quartus II software (includingSOPC Builder) and the Nios II EDS are the primary FPGA developmenttools for creating the reference designs in this kit.To install the Quartus II Web Edition software, follow these steps:1.Download the Quartus II Web Edition software from the Quartus IIWeb Edition Software page of the Altera website. Alternatively, youcan request a DVD from the Altera IP and Software DVD RequestForm page of the Altera website.2.Follow the on-screen instructions to complete the installationprocess.f If you have difficulty installing the Quartus II software,refer to Quartus II Installation & Licensing for Windows andLinux Workstations.The Quartus II Web Edition software includes the following items:■Quartus II software—The Quartus II software, including the SOPCBuilder system development tool, provides a comprehensiveenvironment for system-on-a-programmable-chip (SOPC) design.The Quartus II software integrates into nearly any designenvironment and provides interfaces to industry-standard EDAtools.f To compare the Quartus II subscription and web editions,refer to Altera Quartus II Software—Subscription Edition vs.Web Edition. The kit also works with the subscriptionedition.■MegaCore IP Library—A library that contains Altera IP MegaCorefunctions. You can evaluate MegaCore functions with the OpenCorePlus feature to perform the following tasks:●Simulate behavior of a MegaCore function in your system●Verify functionality of your design, and quickly and easilyevaluate its size and speed●Generate time-limited device programming files for designs thatinclude MegaCore functions●Program a device and verify your design in hardwareGetting Started 1The OpenCore Plus hardware evaluation feature is anevaluation tool for prototyping only. You must purchase alicense to use a MegaCore function in production.f For more information about OpenCore Plus, refer toAN320: OpenCore Plus Evaluation of Megafunctions.■Nios® II Embedded Design Suite (EDS)—A full-featured tool set that allows you to develop embedded software for the Nios II processor which you can include in your Altera FPGA designs.Licensing ConsiderationsThe Quartus II Web Edition software is license-free and supports Cyclone III devices without any additional licensing requirement. This kit also works with the Quartus II Subscription Edition software, after you obtain the proper license file. To purchase a subscription, contact your Altera sales representative.Software Installation2.Development Board andControl Panel Setup DevelopmentBoard SetupThe development board is preloaded with an example design todemonstrate the Cyclone®III device and board features. At power-up,the preloaded design also enables you to quickly confirm that the boardis operating correctly.Figure2–1 shows the Cyclone III development board layout andcomponents.Figure2–1.Cyclone III Development Board Layout and Components1-Mbyte SSRAM (U5)DC PowerInput (J2)Power Switch (SW1)16-MbyteParallelFlash (U6)ConnectorFlash LEDUSBUART (U8)JT AG Header (J4)32-MbyteDDR SDRAM (U4)Reconfigureand ResetPush Buttons50-MHzSystem ClockUser LEDsUser Push Button SwitchesHSMCConnector (J1)Cyclone III Device (U1)Configuration Done LEDSense Resistor for FPGACore Power Measurement (JP6)Sense Resistorfor Shared I/OAltera Corporation 2–1Installing the USB-Blaster DriverRequirementsBefore you proceed, ensure that the follwing items are installed:■Altera® Quartus®II software on the host computer■Cyclone III FPGA Starter Kit■USB-Blaster™ driver software on the host computer. TheCyclone III FPGA starter development board includes an integratedUSB-Blaster circuitry for FPGA programming.Powering Up the Development BoardTo power-up the development board, follow these steps:1.Ensure that the ON/OFF switch (SW1) is in the OFF position (up).2.Connect the USB-Blaster cable from the host computer to theUSB-Blaster port on the development board.3.Connect the 12-V DC adapter to the development board and to apower source.w Only use the supplied 12-V power supply. Power regulationcircuitry on the board could be damaged by supplies greaterthan 12V.4.Press the power switch (SW1).5.Confirm that all four user LEDs are ON.Installing the USB-Blaster Driver The Cyclone III FPGA development board includes an integratedUSB-Blaster circuitry for FPGA programming. However, for the host computer and board to communicate, you must install the USB-Blaster driver on the host computer.Installation instructions for the USB-Blaster driver are available on the Altera website at /support/software/drivers/dri-index.html. On the “Altera Programming Cable Driver Information” page of the Altera website, locate the table entry for your configuration and click the link to access the instructions.2–2Altera CorporationDevelopment Board and Control Panel SetupControl Panel Setup Setting up the control panel involves the following:■Configuring the FPGA■Starting the control panel1Power up the board and ensure that is is operational.For more information about using the control panel, refer to the “Using the Control Panel” chapter.Configuring the FPGA Using the Quartus II Programmer You can use the Quartus II Programmer to configure the FPGA with a specific .sof. Before configuring the FPGA, ensure that the Quartus II Programmer and the USB-Blaster driver are installed on the host computer, the USB cable is connected to the development board, power to the board is on, and no other applications that use the JTAG chain are running.To configure the Cyclone III FPGA, follow these steps:1.Start the Quartus II Programmer.2.Click Add File and select the path to the desired .sof.3.Turn on the Program/Configure option for the added file.4.Click Start to configure the selected file to the FPGA. Configurationis complete when the progress bar reaches 100%.Altera Corporation 2–3Configuring the FPGA Using the Quartus II Programmer2–4Altera Corporationing the Control PanelOverview The control panel consists of the following:■The graphical user interface (GUI) application on the host computer■The standard Nios II hardware design running on the board'sCyclone III FPGA deviceAfter installing the Cyclone III FPGA Starter Kit, you can locate thecontrol panel for the hardware and software in the<kit path>\demos\control_panel directory.The design downloaded to the Cyclone III device implements acommand controller that processes board commands sent over theUSB-Blaster from the control panel. To perform the appropriate actions,the command controller communicates with the controller of the targetedboard I/O device.You can perform the following actions with the control panel:■Light up LEDs■Detect push button presses■Read from and write to the DDR SDRAM, SRAM, flash memory, andon-chip RAMThe following sections describe how to perform the above actions withthe control panel already open on the host computer. If not already open,launch the control panel as described in “Control Panel Start”.Control Panel Start The Cyclone III development board is shipped with an example design stored in the flash memory which configures the Cyclone III FPGA upon power-up with the standard Nios II design.1For an older version of the Cyclone III development board shipped with the Cyclone III FPGA Starter Kit v7.1.0, v7.2.0, or8.0.0 application, you must manually configure thecycloneIII_3c25_start_niosII_standard.sof into the FPGAbefore launching the control panel application.Altera Corporation 3–13–2Altera Corporation LEDs and ButtonsYou can locate the source for the example design in the <kitpath>\examples\cycloneIII_3c25_starter_board_standard directory. 1To launch the control panel user interface, run thecontrol_panel.exe program found in the <kitpath >\demos\control_panel directory (Figure 3–1).Figure 3–1.Control Panel WindowLEDs andButtons Illuminating LEDs To illuminate an LED, follow these steps:1.The LED & Buttons tab should be visible when the application runs.If it is not visible, click the LED & Buttons tab (Figure 3–2).2.Click on LEDs to individually turn on the LEDs.Using the Control PanelButtons Indicators1.Press the push-button switches on the board. Notice that buttons onthe GUI change accordingly.Figure3–2.Control Panel Window for LEDs and ButtonsDDR SDRAM/ SSRAM/On-Chip Controller You can perform the following types of memory read/write operations with the control panel:■Read from and write to the DDR SDRAM, SSRAM, or on-chip device ■Write entire contents of a file, to the DDR SDRAM, SSRAM, or on-chip device■Read contents of the DDR SDRAM, SSRAM, or on-chip device, to afileAltera Corporation 3–33–4Altera Corporation DDR SDRAM/ SSRAM/On-Chip ControllerThe following sections describe how to access the DDR SDRAM. You can use the same procedure to access the SSRAM.Read/Write DataTo read from and write to the DDR SDRAM, follow these steps:1.Click the DDR SDRAM tab (Figure 3–3). The Address columnindicates the hex address of the DDR SDRAM. The values inside the 0-3, 4-7, 8-B , and C-F columns are the DDR SDRAM contents in hex words format.Figure 3–3.Control Panel DDR SDRAM Tab2.To write a 32-bit word to the DDR SDRAM, click the desiredlocation, enter the desired value in hex format, and press Enter.Using the Control PanelRead from a FileTo read the contents of a file and load it to the DDR SDRAM, follow these steps:1.Click Load File.2.Browse to sample.txt located in the control_panel directory andclick Open. This step instantiates the DDR SDRAM controller and loads the text contents into the DDR SDRAM. Notice that the Data to Ascii-text column shows the DDR SDRAM contents in Asciivalue.Write to a FileTo write the contents of the DDR SDRAM to a file, follow these steps:1.Click Save File.2.Enter the start and end addresses of the DDR SDRAM.3.Choose a file name and click Save. This instantiates the controller toread the DDR SDRAM contents from the start address to the endaddress, and write the contents to a file.Flash Memory Programmer You can perform the following operations to read from and write to the board’s flash memory with the control panel:■Perform a CFI query of flash memory■Erase select blocks of flash memory■Write 32-bit hex word to flash memory■Write a binary file to flash memory■Load the contents of the flash memory into a filec Do not exit from the control panel while erasing the flashmemory.Altera Corporation 3–5Flash Memory ProgrammerFlash Memory TabTo use the flash memory functions, click the Flash Memory tab(Figure3–4).Figure3–4.Control Panel Flash Memory TabCFI QueryThe common flash interface (CFI) flash memory devices conform to basicflash commands. The most basic command is Query which switches thedevice into a ROM table mode so that features of the flash device aredetermined by reading values from the table.To perform a CFI query using the host application, click CFI Query.Notice that the memory table displays contents that correlate with thetable contents as described in the device datasheet.To put the flash device back in user mode, press Reset on the controlpanel.3–6Altera CorporationAltera Corporation 3–7Using the Control PanelRead/Write DataTo read from and write to the flash memory, follow these steps:Figure 3–5.Control Panel Flash Memory Tab1.Click Erase Block to perform a block erase of the flash memory. The Address column indicates the hex address of the flash memory. The values inside the 0-3, 4-7, 8-B , and C-F columns are the flash memory contents in hex words format.2.To write a 32-bit word to the flash memory, click the desired location, enter the desired value in hex format, and press Enter.Flash Memory Programmer3–8Altera Corporation4.Measuring Power on theCyclone III Starter BoardIntroduction One of the main features of the Cyclone®III device is its low powerconsumption. You can measure the power of the 3C25 device on theCyclone III starter board under various conditions with an exampledesign provided with the kit.The power example design allows you to control the amount of logicutilized in the FPGA, the clock frequency, the number of I/Os being used,and measure the effect on the power to the Cyclone III device. Because theCyclone III starter board has only four buttons and four LEDs, interactionwith the board is minimal as defined below.Table4–1 describes the functionality of the four input buttons that controlthe power example design.Tables4–2 and 4–3 describe how the LEDs indicate the example design’scurrent power state.Table4–1.Four Input Button FunctionalityButton FPGA Pin Type Description1F1Reset Resets the demo to the beginning, nodei_nrst.2F2Toggle Advances the example design to the next higherfrequency, node i_nfreq_next.3A10Toggle Advances the example design to the next higherresource utilization, node_i_nperc_next.4B10Press and Hold Enables the outputs to toggle, nodei_noutput_ena.Table4–2.LEDs Power State (Frequency)DisplaysLEDsStateClock Frequency(MHz)MSB LSBFrequency LED2 LED10000133106711100Altera Corporation 4–14–2Altera CorporationMeasuring PowerThe design used for power measurement is a replicated set of randomly filled ROMs that feed a multiplier block and a shift register that is fed by a signal that changes every clock cycle. Tables 4–2 and 4–3 show the power state which represent the percent of the full design used. As compiled, this full design uses:■Logic elements: 22,493/24,624 (91%)■Combinational functions: 1,961/24,624 (8%) ■Dedicated logic registers: 21,133/24,624 (86%) ■Total registers: 21,133 ■Total pins: 73/216 (34%)■Total memory bits: 524,288/608,256 (86%)■Embedded Multiplier 9-bit elements: 128/132 (97 %)■Total PLLs: 1/4 (25%)Measuring PowerThe example design is located in<kit install >\examples\cycloneIII_3c25_start_power_demo . Configure the FPGA with the .sof found in the directory. 1The input clock (i_clk PIN_B9) is the 50-MHz oscillator on the board, which generates the input clock for the reference design through a PLLfFor more information on configuring the FPGA, refer to “Configuring the FPGA Using the Quartus II Programmer” on page 2–3.Current sense resistors (0.010 ± 1%) are installed at locations JP6 (FPGA core power) and JP3 (FPGA I/O power + other device I/O power). With a digital multimeter set to mV measurement range, the resistor at location JP6 measures the core power. The resistor at location JP3 measures the I/O power. To measure the current being used in various configurations, use the following steps:Table 4–3.LEDs Power State (Resources)DisplaysLEDsState% of Design UsedMSBLSBResourcesLED4LED30025%0150%1075%11100%Measuring Power on the Cyclone III Starter Board1To obtain the power (P) in milliwatts, measure <MeasuredVoltage> (the voltage across the sense resistors at JP6 or JP3) inmV and calculate the nominal power using the equation:P = 100 x <Measured Voltage> x <Supply Voltage>where <Supply Voltage> is 1.2 V for JP6 and 2.5 V for JP3.You can use the four input buttons to advance through the various powerstate as outlined in Table4–2. Notice how current increases as frequencyand resource usage increase.You can also measure the I/O power consumed by measuring the voltageacross sense-resistor JP3 when Button 4 is pressed and held. Because this2.5-V power rail is shared with other devices, there is a nominal 100mWthat must be subtracted from the calculated I/O power to obtain theFPGA I/O power.The number of I/O pins used is controlled by the resource state (shownin Tables4–2 and 4–3). For each increment in resources, 16 additional I/Opins are added (refer to Table4–4).Table4–4.I/O Pin & Resource StateLED4/LED3Number of I/O Pins0016013210481164Similarly, the toggle-frequency of these I/O pins is set by the overalldesign frequency (refer to Table4–1).Changing the Example DesignThe source code for the Cyclone III power example design is alsoprovided so you can use it as a starting point for your own measurements.You can adjust the number of outputs by changing parameterNUM_OUTPUTS_PER_STAMP. The default is 16, which for four resourcepercentage steps equates to 16 x 4 = 64.The appropriate pins to be used as outputs are pre-assigned to the HSMCconnector (J1). If you would like to look at more than the 76 I/Os availableon J1, you need to make the appropriate pin assignments.Altera Corporation 4–3。

EP3C16F484C6中文资料(Altera)中文数据手册「EasyDatasheet - 矽搜」

芯片中文手册,看全文,戳
1–2
电气特性
1
超出所列条件
表1-1 对器件造成永久性损坏.
此外,在延长时间周期绝对最大额定值设备操作具有设备不利影响.
表 1-1. Cyclone III器件绝对最大额定值
符
参数
VCCINT VCCIO
VCCA
电源电压为内部逻辑
电源电压为输出缓冲器
电源电压（模拟）,用于锁相环（PLL）调节器
Min –0.5 –0.5 –0.5 –0.5 –0.5 –25 —
— –65 –40
最大允许过冲或冲电压
在转换过程中,输入信号可以过冲到中列出电压冲至-2.0 V电流小于100mA幅度和周期小于20纳秒短.
表1-2 列出所允许最大输入电压过冲和过冲电压作为在装置寿命百分比持续时间. 允许最大过冲持续时间被指定为高时间比设备寿命百分比.
运行条件
当Cyclone III器件在一个系统中实现,它们是根据一组定义参数分级.为防护持 Cyclone III器件中最高性能和可靠性,系统设计人员必须考虑本文件中操作要求. Cyclone III器件提供商用,工业和汽车级版本.商业设备在-6（最快）,-7和-8速度等级提供.工业和汽车设备仅在-7速度年级课程.
V
—
3.135出缓冲器,3.0-V
手术
—
2.85
3
3.15
V
VCCIO (3), (4)
电源电压为输出缓冲器,2.5-V
手术
电源电压为输出缓冲器,1.8-V
手术
电源电压为输出缓冲器,1.5-V
手术
—
2.375 2.5 2.625 V
—
1.71 1.8 1.89

EP3C25Q240C8N中文资料(Altera)中文数据手册「EasyDatasheet - 矽搜」

电源电压为输出缓冲器,3.3-V
手术
—
1.15 1.2 1.25
V
—
3.135 3.3 3.465 V
电源电压为输出缓冲器,3.0-V
手术
—
2.85
3
3.15
V
VCCIO (3), (4)
电源电压为输出缓冲器,2.5-V
手术
电源电压为输出缓冲器,1.8-V
手术
电源电压为输出缓冲器,1.5-V
手术
—
2.375 2.5 2.625 V
（4）所有输入缓冲器由在V驱动
供电.
（5）50-200毫秒之间POR时间标准POR范围.每个单独电源应达到在推荐工作范围 50毫秒.
3-9毫秒（6）POR时间,快速POR范围.每个单独电源应在3毫秒达到推荐工作范围内.
芯片中文手册,看全文,戳
第 1章： Cyclone III器件数据表
表1-2 列出所允许最大输入电压过冲和过冲电压作为在装置寿命百分比持续时间. 允许最大过冲持续时间被指定为高时间比设备寿命百分比.
Max
Unit
1.8
V
3.9
V
3.75
V
1.8
V
3.95
V
40
mA
±2000
V
±500
V
150
°C
125
°C
表1-2 and
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芯片中文手册,看全文,戳
July 2012 CIII52001-3.5
CIII52001-3.5
1.Cyclone III器件数据表
本章介绍电气特性,开关特性,以及I / O
对Cyclone时机

CycloneIII使用注意事项V1.0

© 2008 Cytech Technology Ltd – Confidential
Notice6:在使用增量编译时的告警
在使用增量编译的时候，如果在子工程中分配了管脚，在导出.QXP网表文件以及在定层导入网表的时候，QUARTUS会出现如下的警告，会造成用户的误解，导出网表时的警告：
Warning: Complex I/O atoms found during Design Partition Export Warning: Node GZ_DATA[0] is a non-trivial IO atom Warning: Node GZ_DATA[1] is a non-trivial IO atom Warning: Node GZ_DATA[2] is a non-trivial IO atom Warning: Node GZ_DATA[3] is a non-trivial IO atom Warning: Node GZ_DATA[4] is a non-trivial IO atom Warning: Node GZ_DATA[5] is a non-trivial IO atom Warning: Node GZ_DATA[6] is a non-trivial IO atom Warning: Node GZ_DATA[7] is a non-trivial IO atom Warning: Node flash_d[0] is a non-trivial IO atom Warning: Node flash_d[1] is a non-trivial IO atom Warning: Node flash_d[2] is a non-trivial IO atom Warning: Node flash_d[3] is a non-trivial IO atom Warning: Node flash_d[4] is a non-trivial IO atom Warning: Node flash_d[5] is a non-trivial IO atom Warning: Node flash_d[6] is a non-trivial IO atom Warning: Node flash_d[7] is a non-trivial IO atom

cyclone3的配置方式

cyclone3的配置方式ｃｙｃｌｏｎｅ３的配置方式ｃｙｃｌｏｎｅ３器件使用ＳＲＡＭ单元保存配置信息。

因为ＳＲＡＭ掉电易失的特性，ｆｐｇａ芯片上电的时候必须重新配置。

根据期间密度和封装选择，它有如下５中配置方案（红色部分为常用配置方案，并不是所有FPGA芯片都能使用所有配置方案，具体可查看cyclone3的器件手册）：1. Active serial (AS)主动串行配置2. Active parallel (AP)主动并行配置3. Passive serial (PS)被动串行配置4. Fast passive parallel (FPP)快速被动并行配置5. Joint Test Action Group (JTAG)AS和AP配置方案需要外部FLASH存储器存储配置信息。

其它3种配置方案需要外部的控制器或者下载电缆。

主动配置方案以及JTAG方案常用于单芯片系统设计。

下面重点介绍AS，AP和JTAG。

以AS配置为例介绍。

Cyclone3器件的配置芯片通常选择EPCS64,EPCS16以及EPCS4或者flash.这些芯片能够提供廉价，方便（引脚少）的解决方案。

因为FPGA芯片容量的限制，它对配置信息的大小也有所限制。

EP3C80系列器件可提供21MBITS的配置信息流容量。

MSEL【3：0】为FPGA器件的输入，用于确定配置方式。

AS模式下，它连接1101.AP模式下，它连接1011.注意要直接接 VCCA or GND，更不能悬空，避免无效配置。

查看手册可得到其它配置值。

在JTAG模式下，忽略MSEL配置，JTAG模式有优先权。

AS模式支持配置信息压缩，AP模式不支持。

压缩信息可以节约空间以及配置时间。

在Device & Pin Options――Configuration中可以选择压缩与否。

选择好器件后，参考下图连接。

POR――上电复位.复位时间由MSEL【3：0】决定。

复位结束后开始发送配置控制信号。

EP3C40F484C8中文资料(Altera)中文数据手册「EasyDatasheet - 矽搜」

—
1.71 1.8 1.89
V
—
1.425 1.5 1.575 V
电源电压为输出缓冲器,1.2-V
手术
—
1.14 1.2 1.26
V
VCCA (3)
VCCD_PLL (3) VI VO
供应（模拟）电压PLL
调节器
供应（数字）电压PLL
输入电压输出电压
TJ
工作结温
tRAMP IDiode
电源斜坡时间
芯片中文手册,看全文,戳
July 2012 CIII52001-3.5
CIII52001-3.5
1.Cyclone III器件数据表
本章介绍电气特性,开关特性,以及I / O
对Cyclone时机
® III器件.一个术语表还包括供您参考.
电气特性
以下各节提供有关绝对最大额定值详细信息, 推荐工作条件,直流特性,和其他规范 Cyclone III器件.
表1-2 列出所允许最大输入电压过冲和过冲电压作为在装置寿命百分比持续时间. 允许最大过冲持续时间被指定为高时间比设备寿命百分比.
Max
Unit
1.8
V
3.9
V
3.75
V
1.8
V
3.95
V
40
mA
±2000
V
±500
V
150
°C
125
°C
表1-2 and
芯片中文手册,看全文,戳
Typ Max Unit — 10 mA — 10 mA
总线防护持
总线防护持防护留源在最后一个有效逻辑状态,驾驶它要么进入高阻抗状态或者被删除 .每个I / O引脚有一个选项,以使总线防护持在用户模式.总线防护持始终在配置模式禁用.

CYCLONE III EPCS使用方法

一、只使用FPGA硬件资源，不使用NIOS的时候
需要将nCEO引脚设为用户引脚，注意：一般编译器是默认它为程序下载的引脚的
将nCEO设为用户IO，其它的保留原样
二、使用NIOS的时候
由于CD0板子上没有设计FLASH。

所以在使用NIOS的时候，需要把程序存在EPCS器件中。

CYCLONE III器件跟其它器件的EPCS使用方法不同。

将DEVICE AND PIN OPTIONS页全部置为USER IO
在SOPC中添加epcs_flash_controller
在FPGA工程的顶层模块中添加EPCS控值器的接口
在NIOS的FLASH PROGRAMMER中做如下设置
将FPGA的SOF文件用QUARTUS的通过JTAG下载到FPGA后，
在NIOS的FLASH PROGRAMMER中点这时，NIOS的FLASH
PROGRAMMER会把.SOF文件和NIOS生成的.ELF文件合在一起，生成另一个配置文件下载到板子上的EPCS芯片中
重新上电，FPGA就以正常运行NIOS+FPGA的程序了
注意：在使用NIOS的时候FPGA的PIN_22因为太靠近PIN_23：DCLK（FPGA提供给EPCS 芯片的时钟）而不能再使用（使用时QUARTUS编译器会报错）。

PIN_22对应了CD0板子上的GPIO1[13]，
所以在有NIOS的工程中都没有使用这一个引脚，对应的有NIOS的FPGA顶层也写成了如下：
跳过了…[12]这个引脚。

EP3C16Q240C8中文资料(Altera)中文数据手册「EasyDatasheet - 矽搜」

1–5
电气特性
直流特性
本节列出I / O漏电流,引脚电容,片上端接（OCT）耐受性,并为Cyclone III器件总线防护持规范.
电源电流
待机电流是流经器件电流在该装置没有配置输入或输出翻转,在该装置没有活动电流 .使用基于Excel早期功耗估算（EPE）来获取电源电流估计为您设计,因为这些电流变化在很大程度上与使用资源.
图1-1
示出方法来确定过冲持续时间.
图1-1,
Unit % % % % % % % % % % % % % %
超调
图 1-1. Cyclone III器件超调时间
4.2 V 4.1 V 3.3 V
T T
芯片中文手册,看全文,戳
1–4
第 1章： Cyclone III器件数据表
电气特性
电源电压为输出缓冲器,3.3-V
手术
—
1.15 1.2 1.25
V
—
3.135 3.3 3.465 V
电源电压为输出缓冲器,3.0-V
手术
—
2.85
3
3.15
V
VCCIO (3), (4)
电源电压为输出缓冲器,2.5-V
手术
电源电压为输出缓冲器,1.8-V
手术
电源电压为输出缓冲器,1.5-V
手术
—
2.375 2.5 2.625 V
TSTG TJ
储存温度工作结温
注意表 1-1：
（1）电源电压规格适用于电压器件引脚采取相对于地面,而不是在读电源.
(1)
Min –0.5 –0.5 –0.5 –0.5 –0.5 –25 —
— –65 –40
最大允许过冲或冲电压

Cyclone III FPGA系列

Cyclone III FPGA系列：一切皆有可能前所未有的同时实现了低功耗、高性能和低成本Cyclone® III FPGA系列前所未有的同时实现了低功耗、高性能和低成本，大大提高了您的竞争力。

其特性以及Cyclone III FPGA体系结构为您的大批量、低功耗、低成本应用提供了理想的解决方案。

为满足您独特的设计需求，这一FPGA系列包括：∙Cyclone III：功耗最低、成本最低的高性能FPGA∙Cyclone III LS：具有安全特性、功耗最低的FPGA Cyclone III LS器件具有200K逻辑单元、8 Mbits嵌入式存储器以及396个嵌入式乘法器，是高性能处理、低功耗应用的理想选择，包括：轻松达到您的功耗目标具有200K逻辑单元(LE)、8-Mbits存储器，而静态功耗不到1/4瓦，该系列设立了功耗标准。

采用台积电(TSMC)的低功耗(LP)工艺技术进行制造，无论是通信设备、手持式消费类产品，还是软件无线电设备，这些FPGA都能够轻松满足您的功耗预算。

设计安全性Cyclone III LS FPGA利用低功耗、高性能FPGA平台，在硬件、软件和知识产权(IP)层面上率先实现了一系列安全特性。

一系列安全特性保护了您的IP不被篡改、逆向剖析和克隆。

而且，这些器件还使您能够通过设计分离特性，在一个芯片中实现冗余功能，从而减小了实际应用的体积、重量和功耗。

全面的设计资源为确保流畅、成功的设计流程，帮助您更快的将构思变为收益，Altera 提供全面的Cyclone III FPGA设计环境，包括：∙Quartus® II开发软件∙成熟的IP库∙Nios® II，世界上最通用的嵌入式处理器∙低成本开发套件∙专用参考设计将您的设计从构思变为产品，更迅速推向市场。

采用Cyclone III FPGA，一切皆有可能。

相关链接∙观看划分FPGA设计，实现冗余和信息安全网播∙下载Cyclone III FPGA手册(PDF)∙观看Cyclone III FPGA视频Cyclone III 器件系列体系结构Cyclone® III FPGA前所未有地同时实现了低功耗、低成本和高性能。

CycloneIII EP3C25 引脚信息说明

41 42 43 44 45 46 47
L4 L3 M2 M1 M3 P2 P1 R2 R1 T2 T1 T3 DQS1L/CQ1L#, DPCLK1
DQ1L DQ1L DQS1L/CQ1L#, DPCLK1 DQ1L
DQ3L DQ3L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ3L
DQ1L DQ1L DQ1L
32 33 34
DQ3L
DQ1L
DIFFIO_L15p DIFFIO_L15n 35 36 37 DIFFIO_B1p 38 DIFFIO_B1n DIFFIO_B2p DIFFIO_B2n DIFFIO_B3p
40 41 42 43 44
PLL1_CLKOUTp PLL1_CLKOUTn DIFFIO_B4p DIFFIO_B4n
T2 R4 T4 N5 N6 M6
P6 U2 V2 N7 N8
DQS1B/CQ1B#, CDPCLK2
DQS1B/CQ1B#, CDPCLK2
DQS1B/CQ1B#, CDPCLK2
DQS1B/பைடு நூலகம்Q1B#, CDPCLK2
DQS1B/CQ1B#, CDPCLK2
DQS1B/CQ1B#, CDPCLK2
Bank Number B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 VREFB Group VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 Pin Name / Function IO GND IO IO IO IO IO VCCIO2 IO GND IO IO IO IO IO VCCINT IO GND IO IO IO VCCA1 GNDA1 VCCD_PLL1 IO VCCINT IO GND IO IO IO VCCIO3 GND IO IO IO IO IO IO VCCINT GND IO IO VCCIO3 IO GND IO IO IO Optional Function(s) DIFFIO_L10p DIFFIO_L10n DIFFIO_L11p DIFFIO_L11n VREFB2N0 DIFFIO_L12p DIFFIO_L12n DIFFIO_L13p DIFFIO_L13n RUP1 RDN1 DIFFIO_L14p DIFFIO_L14n 54 55 56 57 58 59 60 61 P3 39 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 R3 T3 V1 M6 N6 T4 DM3B/BWS#3B DQ3B DM5B1/BWS#5B2 DQ5B R1 P2 P1 L5 M5 N4 N3 M5 R5 R4 N5 P5 P4 U1 DQS3L/CQ3L#, CDPCLK1 DQ1L DQS3L/CQ3L#, CDPCLK1 DQ1L DM1L/BWS#1L DQS3L/CQ3L#, CDPCLK1 DQS3L/CQ3L#, CDPCLK1 DM3L/BWS#3L DQS3L/CQ3L#, CDPCLK1 DM1L1/BWS#1L2 48 49 50 51 52 53 R3 DQ3L DQ1L N2 N1 K5 L4 30 31 Configuration Function E144 (4) Q240 F256/ U256 K2 K1 L2 L1 L3 F324 DQS for x8/x9 in E144 DQS for x8/x9 in Q240 DQS for x8/x9 in F256/U256 DQS for x16/x18 in F256/U256 DQS for x8/x9 in F324 DQ3L DQ1L DQS1L/CQ1L#, DPCLK1 DQ1L DQS1L/CQ1L#, DPCLK1 DQ3L DQS1L/CQ1L#, DPCLK1 DQS for x16/x18 in F324 DQ1L DQ1L DQS1L/CQ1L#, DPCLK1

EP3C40F484C6中文资料(Altera)中文数据手册「EasyDatasheet - 矽搜」

第 1章： Cyclone III器件数据表
1–3
电气特性
1
DC信号是相当于100％占空比.例如,过冲,以4.2V信号只能是在4.2V用于在装置寿
命10.74％;为10年器件寿命,这相当于一年10.74/10ths.
表 1-2. Cyclone III器件最大允许过冲在转换过程中超过 10年
大体时间
1–5
电气特性
直流特性
本节列出I / O漏电流,引脚电容,片上端接（OCT）耐受性,并为Cyclone III器件总线防护持规范.
电源电流
待机电流是流经器件电流在该装置没有配置输入或输出翻转,在该装置没有活动电流 .使用基于Excel早期功耗估算（EPE）来获取电源电流估计为您设计,因为这些电流变化在很大程度上与使用资源.
电源电压为输出缓冲器,3.3-V
手术
—
1.15 1.2 1.25
V
—
3.135 3.3 3.465 V
电源电压为输出缓冲器,3.0-V
手术
—
2.85
3
3.15
V
VCCIO (3), (4)
电源电压为输出缓冲器,2.5-V
手术
电源电压为输出缓冲器,1.8-V
手术
电源电压为输出缓冲器,1.5-V
手术
—
2.375 2.5 2.625 V
表1-4 列出I / O引脚泄漏目前Cyclone III器件.
f
有关功耗估算工具更多信息,请参阅
估计用户指南
而
PowerPlay功耗分析
手册.
PowerPlay早期功耗
在本章
Quartus II
பைடு நூலகம்

Cyclone_III_EP3C25E144_外型尺寸-封装尺寸

June 2011
Altera Corporation
04R-00221-1.0
2
Altera Device Pacage Information
Package Outline
TOP VIEW
D D1
Pin 144
BOTTOM VIEW
D2
Pin 144
Pin 1
Pin 1 ID
Pin 1
E1
E2
Package Outline Dimension Table
Millimeters Symbol Min. A A1 A2 D D1 D2 E E1 E2 L L1 S b c e 0 0.20 0.17 0.09 6.55 0.45 6.55 1.45 0.05 1.30 Nom. 1.55 0.10 1.45 22.00 BSC 20.00 BSC 6.70 22.00 BSC 20.00 BSC 6.70 0.60 1.00 REF 0.22 0.50 BSC 3.5 7 0.27 0.20 6.85 0.75 6.85 Max. 1.65 0.15 1.60
Altera Corporation
04R-00221-1.0
E
Pin 36
Pin 36
A2 A1
A
See Detail A
Detail A
e
C Gage Plane
b
S L L1

0.25mm
04R-00221-1.0
June 2011
Altera Corporation
Altera Device Package Information
3
Document Revision History