DC培训教材2

dc_shell-t> analyze -f vhdl source/ALU.vhd dc_shell-t> analyze -f vhdl source/TOP.vhd dc_shell-t> elaborate TOP
Loading db file bob/DECODE.db Current design is now ‘TOP’
Synopsys 31833-000-S16 Synopsys Workshop
Unit Measurable Objectives
After completing this unit, you should be able to: Specify the target library Create the setup file for DC Differentiate between the design objects Find objects in DCSH mode and Tcl mode
Synopsys 31833-000-S16 Synopsys Workshop
Synthesis Review
Recall the 3 steps involved in synthesis:
Translation Optimization Mapping
2-4
When DC maps a circuit, how will it know which cell library you are using? How will it know the timing of your cells?
How do we tell DC to find DECODE.db in bob?
Setup, Libraries, and Objects
Synopsys 31833-000-S16 Synopsys Workshop
Set the search_path Variable
set target_library my_tech.db set link_library {* my_tech.db} lappend search_path {bob}
2-10
TOP.v module TOP (A,B,OUT1); input A, B; output [1:0] OUT1; ALU U1 (.AIN (A), . . DECODE U2 (.A (BUS0), . .
bob/
my_ech.db source/ TOP.v ALU.v
DECODE.db
Where do we specify the directory for the analyzed files?
Setup, Libraries, and Objects
Synopsys 31833-000-S16 Synopsys Workshop
Chapter Overview
2-12
Technology Libraries
Setup, Libraries, and Objects
Synopsys 31833-000-S16 Synopsys Workshop
Use of analyze / elaborate
set target_library my_tech.db set link_library {* my_tech.db} lappend search_path {bob}
design_vision (-tcl) Design Vision Tcl mode Design Compiler (DC) dc_shell-t
2-13
design_analyzer Design Analyzer dcsh mode dcsh mode
In release 2000.11
Synopsys 31833-000-S16
2-9
bob/
my_tech.db source/ TOP.v ALU.v
DECODE.db
dc_shell-t> read_verilog source/ALU.v dc_shell-t> read_verilog source/TOP.v dc_shell-t> link
Unable to resolve reference ‘DECODE’ in ‘TOP’
Setup, Libraries, and Objects
Synopsys 31833-000-S16 Synopsys Workshop
Example
set target_library my_tech.db set link_library {* my_tech.db}
ALU.v module ALU (A,B,OUT1); input A, B; output [1:0] OUT1; always @(A or B) begin . . .
Agenda: Day 1
DAY 1
2-1
Unit 1 2 3 4
Topic Introduction to Synthesis Setup, Libraries and Objects Partitioning for Synthesis Coding for Synthesis
Lab
Setup, Libraries, and Objects
2-11
TOP.v module TOP (A,B,OUT1); input A, B; output [1:0] OUT1; ALU U1 (.AIN (A), . . DECODE U2 (.A (BUS0), . .
bob/
my_tech.db source/ TOP.v ALU.v
DECODE.db
2-2
Setup, Libraries, and Objects
Synopsys 31833-000-S16 Synopsys Workshop
Chapter Overview
2-3
Technology Libraries
DC Setup File
Design Objects
Setup, Libraries, and Objects
Set it to point to the library file(s) provided by your silicon vendor
set target_library my_tech.db
Setup, Libraries, and Objects
Synopsys 31833-000-S16 Synopsys Workshop
Your ASIC vendor must provide a DC-compatible technology library for synthesis!
Setup, Libraries, and Objects
Synopsys 31833-000-S16 Synopsys Workshop
Technology Library
Synopsys 31833-000-S16
Synopsys Workshop
Target Library Variable
The Target Library is the library used by Design Compiler for building a circuit During mapping, DC will
dc_shell
Example of a cell description in .lib Format Cell name cell ( OR2_3 ) { area : 8.000 ; Cell Area pin ( Y ) { direction : output; timing ( ) { related_pin : "A" ; timing_sense : positive_unate ; rise_propagation (drive_3_table_1) { values ("0.2616, 0.2608, 0.2831,..) } rise_transition (drive_3_table_2) { values ("0.0223, 0.0254, ...) . . . . function : "(A | B)"; max_capacitance : 1.14810 ; min_capacitance : 0.00220 ; } pin ( A ) { direction : input; capacitance : 0.012000; . . . .
Link Library Variable
Used to resolve design references
2-7
set link_library {* my_tech.db}
DC Memory “*” Target Library
First DC searches the memory and then the library files specified in the link_library variable Second DC searches the all paths defined in the search_path variable
set target_library my_tech.db set link_library {* my_tech.db}
TOP.v module TOP (A,B,OUT1); input A, B; output [1:0] OUT1; ALU U1 (.AIN (A), . . DECODE U2 (.A (BUS0), . .
choose functionally-correct gates from this library calculate the timing of the circuit using vendor-supplied timing data for these gates
2-6
target_library is a reserved variable in DC
DC Setup File
Design Objects
Setup, Libraries, and Objects
Synopsys 31833-000-S16 Synopsys Workshop
Design Compiler Interfaces
Four ways to interface to Design Compiler (DC), the Synopsys synthesis engine:
dc_shell-t> read_verilog source/ALU.v dc_shell-t> read_verilog source/TOP.v dc_shell-t> link
Loading db file bob/DECODE.db
dc_shell-t> which DECODE.db
/server/my_project/bob/DECODE.db
t
2-5
A Y=A|B B Y
Pin A -> Pin Y nominal delays (look-up table)
Pin Y functionality Design Rules for Output Pin Electrical Characteristics of Input Pins
Setup, Libraries, and Objects
2-8
bob/
my_tech.db source/ TOP.v ALU.v
DECODE.db
UNIX% dc_shell-t dc_shell-t> read_verilog source/ALU.v
Loading Loading Loading Loading Current
Synopsys 31833-000-S16
db file standard.sldb db file gtech.db db file my_tech.db verilog file source/ALU.v design is now ALU
Setup, Libraries, and Objects
Synopsys Workshop
Use link to Resolve Design References