常见面试笔试题-verilog程序库

加减法module addsub( input [7:0] dataa,input [7:0] datab,input add_sub, // if this is 1, add; else subtractinput clk,output reg [8:0] result );always @ (posedge clk)beginif (add_sub) result <= dataa + datab; //or "assign {cout,sum}=dataa+datab;"else result <= dataa - datab;endendmodule四位的全加法器.module add4(cout,sum,a,b,cin)input[3:0]a,b; input cin;output [3:0] sum; output cout;assign {cout,sum}=a+b+cin;endmodule补码不仅可以执行正值和负值转换，其实补码存在的意义，就是避免计算机去做减法的操作。

1101 -3 补+ 1000 801015假设-3 + 8，只要将-3 转为补码形式，亦即0011 => 1101，然后和8，亦即1000 相加就会得到5，亦即0101。

至于溢出的最高位可以无视掉。

乘法器module mult(outcome,a,b);parameter SIZE=8;input[SIZE:1] a,b;output reg[2*SIZE:1] outcome;integer i;always @(a or b)begin outcome<=0;for(i=0,i<=SIZE;i=i+1)if(b[i]) outcome<=outcome+(a<<(i-1));endendmodule另一种乘法器。

在初始化之际，取乘数和被乘数的正负关系，然后取被乘数和乘数的正值。

输出结果根据正负关系取得。

else if( Start_Sig )case( i )0: beginisNeg <= Multiplicand[7] ^ Multiplier[7];Mcand <= Multiplicand[7] ? ( ~Multiplicand + 1'b1 ) : Multiplicand;Mer <= Multiplier[7] ? ( ~Multiplier + 1'b1 ) : Multiplier;Temp <= 16'd0;i <= i + 1'b1;end1: // Multiplingif( Mer == 0 ) i <= i + 1'b1;else begin Temp <= T emp + Mcand; Mer <= Mer - 1'b1; end2: begin isDone <= 1'b1; i <= i + 1'b1; end3: begin isDone <= 1'b0; i <= 2'd0; endendcaseassign Done_Sig = isDone;assign Product = isNeg ? ( ~Temp + 1'b1 ) : Temp;endmodulebooth乘法器module booth_multiplier_module(input CLK,input RSTn,input Start_Sig,input [7:0]A,input [7:0]B,output Done_Sig,output [15:0]Product,output [7:0]SQ_a,output [7:0]SQ_s,output [16:0]SQ_p);reg [3:0]i;reg [7:0]a; // result of Areg [7:0]s; // reverse result of Areg [16:0]p; // p空间，16+1位reg [3:0]X; //指示n次循环reg isDone;always @ ( posedge CLK or negedge RSTn )if( !RSTn )begini <= 4'd0;a <= 8'd0;s <= 8'd0;p <= 17'd0;X <= 4'd0;isDone <= 1'b0;endelse if( Start_Sig )case( i )0:begin a <= A; s <= ( ~A + 1'b1 ); p <= { 8'd0 , B , 1'b0 }; i <= i + 1'b1; end1:if( X == 8 ) begin X <= 4'd0; i <= i + 4'd2; endelse if( p[1:0] == 2'b01 ) begin p <= { p[16:9] + a , p[8:0] }; i <= i + 1'b1; endelse if( p[1:0] == 2'b10 ) begin p <= { p[16:9] + s , p[8:0] }; i <= i + 1'b1; endelse i <= i + 1'b1; //00和11，无操作2:begin p <= { p[16] , p[16:1] }; X <= X + 1'b1; i <= i - 1'b1; end //右移，最高位补0 or 1.3:begin isDone <= 1'b1; i <= i + 1'b1; end4:begin isDone <= 1'b0; i <= 4'd0; endendcaseassign Done_Sig = isDone;assign Product = p[16:1];endmodule除法器module divider_module(input CLK,input RSTn,input Start_Sig,input [7:0]Dividend,input [7:0]Divisor,output Done_Sig,output [7:0]Quotient,output [7:0]Reminder,);reg [3:0]i;reg [7:0]Dend;reg [7:0]Dsor;reg [7:0]Q;reg [7:0]R;reg isNeg;reg isDone;always @ ( posedge CLK or negedge RSTn )if( !RSTn )begini <= 4'd0;Dend <= 8'd0;Dsor <= 8'd0;Q <= 8'd0;isNeg <= 1'b0;isDone <= 1'b0;endelse if( Start_Sig )case( i )0:beginDend <= Dividend[7] ? ~Dividend + 1'b1 : Dividend;Dsor <= Divisor[7] ? Divisor : ( ~Divisor + 1'b1 );isNeg <= Dividend[7] ^ Divisor[7];i <= i + 1'b1;end1: if( Divisor > Dend )begin Q <= isNeg ? ( ~Q + 1'b1 ) : Q; i <= i + 1'b1; endelse begin Dend <= Dend + Dsor; Q <= Q + 1'b1; end2: begin isDone <= 1'b1; i <= i + 1'b1; end3: begin isDone <= 1'b0; i <= 4'd0; endendcaseassign Done_Sig = isDone;assign Quotient = Q;assign Reminder = Dend;endmodule除法器2module div(a,b,clk,result,yu)input[3:0]a,b;output reg[3:0] result,yu;input clk; reg[1:0] state;reg[3:0] m,n;parameter S0=2'b00,S1=2'b01,S2=2'b10;always@(posedge clk)begin case(state)S0: begin if(a>b) begin n<=a-b;m<=4'b0001; state<=S1; endelse begin m<=4'b0000;n<=a; state<=S2; endendS1: begin if(n>=b) begin m<=m+1;n<=n-b;state<=S1;endelse begin state<=S2;endendS2: begin result<=m;yu<=n;state<=S0;enddefule:state<=S0;endcaseend13、一个可预置初值的7进制循环计数器①verilogmodule count(clk,reset,load,date,out);input load,clk,reset;input[3:0] date;output reg[3:0] out;parameter WIDTH=4'd7;always@(clk or reset)beginif(reset) out<=4'd0;else if(load) out<=date;else if(out==WIDTH-1) out<=4'd0;else out<=out+1;endendmoduleJohnson计数器约翰逊(Johnson)计数器又称扭环计数器,是一种用n位触发器来表示2n个状态的计数器。