ICS954119时钟芯片

Integrated CircuitSystems, Inc.ICS954119Advance InformationPin ConfigurationRecommended Application:CK410 compliant clockOutput Features:• 2 - 0.7V current-mode differential CPU pairs • 1 - 0.7V current-mode differential SRC pair • 6 - PCI (33MHz)• 3 - PCICLK_F , (33MHz) free-running • 1 - USB, 48MHz • 1 - 24/48 MHz • 1 - DOT, 96MHz, 0.7V current differential pair • 2 - REF , 14.318MHz • 5 - PCI-Express 0.7V current differential pairs Key Specifications:•CPU/SRC outputs cycle-cycle jitter < 85ps •PCI outputs cycle-cycle jitter < 250ps •+/- 300ppm frequency accuracy on CPU & SRC clocks Programmable Timing Control Hub™ for Next Gen P 4™ processorFunctionalityFeatures/Benefits:•Programmable output frequencies •Programmable output skew.•Programmable spread percentage for EMI control.•Programmable watch dog safe frequency.•Supports tight ppm accuracy clocks for Serial-ATA •Supports spread spectrum modulation, 0 to -0.5%down spread, ±0.25% center spread, and ±0.3%center spread •Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning•Supports undriven differential CPU, SRC pair in PD#for power management.GND 156VDDPCI PCICLK3255PCICLK2PCICLK4354PCICLK1PCICLK5453PCICLK0GND 552Reset#VDDPCI 651REF0/FS L C PCICLK_F0750REF1FS L A/PCICLK_F1849GND FS L B/PCICLK_F2948X1VDD481047X2**SEL24_48#/24_48MHz1146VDDREF USB_48MHz1245SCLK GND1344SDATA DOTT_ 96MHz 1443CPUCLKT0DOTC_96MHz 1542CPUCLKC0Vtt_PwrGd#/PD1641VDDCPU PCIEXT01740CPUCLKT1PCIEXC01839CPUCLKC1VDDPCIEX1938GND GND 2037IREF PCIEXT12136GNDA PCIEXC12235VDDAPCIEXT22334VDDPCIEX PCIEXC22433PCIEXT4GND 2532PCIEXC4SRCCLKT 2631PCIEXT3SRCCLKC 2730PCIEXC3VDDSRC 2829GNDI C S 95411956-Pin SSOP* Internal Pull-Up ResistorPin DescriptionPin DescriptionGeneral DescriptionICS954119 follows Intel CK410 Y ellow Cover specification. This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets. ICS954119 is driven with a 14.318MHz crystal.Block DiagramVtt_PWRGD#/PDFSLAFSLBFSLCSel24/48General I2C serial interface information for the ICS954119How to Write:•Controller (host) sends a start bit.•Controller (host) sends the write address D2(H)•ICS clock will acknowledge•Controller (host) sends the begining byte location = N•ICS clock will acknowledge•Controller (host) sends the data byte count = X •ICS clock will acknowledge•Controller (host) starts sending Byte N through Byte N + X -1(see Note 2)•ICS clock will acknowledge each byte one at a time •Controller (host) sends a Stop bit How to Read:•Controller (host) will send start bit.•Controller (host) sends the write address D2(H)•ICS clock will acknowledge•Controller (host) sends the begining bytelocation = N•ICS clock will acknowledge•Controller (host) will send a separate start bit.•Controller (host) sends the read address D3(H)•ICS clock will acknowledge•ICS clock will send the data byte count = X•ICS clock sends Byte N + X -1•ICS clock sends Byte 0 through byte X (if X(H)was written to byte 8).•Controller (host) will need to acknowledge each byte •Controllor (host) will send a not acknowledge bit •Controller (host) will send a stop bit222I2C Table: Output Control Register222222222222222221Guaranteed by design and characterization, not 100% tested in production.2 Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.A DD L S ΩP Ω, ΙREF = 475Ω1Guaranteed by design and characterization, not 100% tested in production.2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 3I REF = V DD /(3xR R ). For R R = 475Ω (1%), I REF = 2.32mA. I OH = 6 x I REF and V OH = 0.7V @ Z O =50Ω.1Guaranteed by design and characterization, not 100% tested in production.A DD L S ΩP Ω, ΙREF = 475Ω1Guaranteed by design and characterization, not 100% tested in production.2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 3I REF = V DD /(3xR R ). For R R = 475Ω (1%), I REF = 2.32mA. I OH = 6 x I REF and V OH = 0.7V @ Z O =50Ω.AREAOrdering Information ICS954119y FLF-T Example:10-0034Reference Doc.: JEDEC Publication 95, MO-11856-Lead, 300 mil Body, 25 mil, SSOPDesignation for tape and reel packagingLead Free (Optional)Package TypeF = SSOPRevision Designator (will not correlate with datasheet revision)Device TypePrefixICS = Standard DeviceICS XXXX y F LF- T。