晶体管数据手册
沟绝缘栅双极晶体管数据手册说明书
JT015N065FED订 货 型 号 Order codes 印 记 Marking 封 装 Package 无 卤 素 Halogen Free 包 装 Packaging 器件重量 Device Weight JT015N065FED-O-F-N-BJT015N065FEDTO-220MF否 NO条管 Tube2.20 g(typ)主要参数 MAIN CHARACTERISTICSI C15 A V CES650V V cesat-typ（@V ge =15V） 1.6V用途● 逆变器 ● UPS 电源APPLICATIONS ● General purpose inverters ● UPS 产品特性 ● 低栅极电荷 ● T rench FS 技术, ● 通态压降, V CE (sat), typ = 1.6V @ I C =15A and TC = 25°C ● R oHS 产品 FEATURES● L ow gate charge● T rench FS Technology,● saturation voltage:V CE (sat), typ = 1.6V @ I C = 15A and TC = 25°C ● R oHS product绝对最大额定值 ABSOLUTE RATINGS (Tc=25℃)*连续集电极电流由最高结温限制*Collector current limited by maximum junction temperature项 目 Parameter符 号 Symbol 数 值Value 单 位 Unit JT015N065FED最高集电极－发射极直流电压 Collector-Emmiter Voltage V ces650 V *连续集电极电流Collector Current-continuous I C30 (T=25℃) A 15( T=100℃)A 最大脉冲集电极极电流（注1） Collector Current – pulse （note 1）I CM45A最高栅极发射极电压 Gate-Emmiter Voltage V GES ±20 V Turn-off safe area -60 A 耗散功率Power Dissipation P DT C =25℃ 31W最高结温及存储温度 Operating and Storage Temperature Range T J ，T STG-55～+150 ℃引线最高焊接温度 Maximum LeadTemperature for Soldering PurposesT L300 ℃电特性 ELECTRICAL CHARACTERISTICS项目Parameter符号Symbol测试条件Tests conditions最小Min典型Typ最大Max单位Units关态特性Off –Characteristics集电极－发射极击穿电压Collector-Emmiter VoltageBV CES I C=500μA, V GE=0V 650 - - V 击穿电压温度特性Breakdown Voltage TemperatureCoefficientΔBV CES/ΔT J I C=1mA, referenced to 25℃- 0.5 - V/℃零栅压下集电极漏电流Zero Gate Voltage Collector Current I CESV CE=650V, V GE=0V,T C=25℃- - 10 μA正向栅极体漏电流Gate-body leakage current,forwardI GESF V CE=0V, V GE =20V - - 200 nA反向栅极体漏电流Gate-body leakage current,reverseI GESR V CE=0V, V GE =-20V - - -200 nA 通态特性On-Characteristics阈值电压Gate Threshold VoltageV GE(th)V CE = V GE , I C=250μA 4.0 - 6.5 V 饱和压降Collector-Emmiter saturation Voltage V CESATV GE=15V I C=15ATc=25℃- 1.6 2.0 V动态特性Dynamic Characteristics输入电容Input capacitance C iesV CE=25V,V GE=0V,f=1.0MH Z- 880 - pF输出电容Output capacitanceC oes- TBD - pF 反向传输电容Reverse transfer capacitanceC res- TBD - pF栅极电荷总量Total Gate Charge Qg VCC=400V,I c=15A,R G=10ΩV GE=15 VT C=25℃- TBD-nC栅极-反射极Gate to emitter charge Qge - TBD-栅极-集电极Gate to collector charge Qgc - TBD-栅极电阻-Gate resistance Rg f=1 MHz, open collector- 1.75 - Ω短路电流-short current Isc V GE=15V V CE=360V - 75 - A电特性 ELECTRICAL CHARACTERISTICS 开关特性Switching Characteristics项目Parameter符号Symbol测试条件Tests conditions最小Min典型Typ最大Max单位Units开启延迟时间Turn-On delay time t d(on) V CC=400V,I c=15A,R G=60ΩV GE=15 VT C=25℃- TBD- ns上升时间Turn-On rise time t r- TBD- ns 关断延迟时间Turn-Off delay time t d(off) - TBD- ns 下降时间Turn-Off Fall time t f- TBD- ns 开通损耗Turn-On energy Eon - TBD- μJ 关断损耗Turn-off energy Eoff - TBD- μJ 总开关损耗Total switching energy Etot - TBD- μJ 反并联二极管特性及最大额定值Anti-Parallel Diode Characteristics and Maximum Ratings 正向压降Drain-Source Diode ForwardVoltageV F V GE=0V, I S=15A - 1.4 2.2 V反向恢复时间Diode Reverse recovery timet rrV GE=0V, V R=400V I F=15AdI F/dt=200A/μs (note 4) -TBD- ns反向恢复电荷Diode Reverse recovery charge Qrr -TBD- nC反向恢复电流Diode Reverse recovery Current I RRM-TBD- A项目Parameter符号Symbol典型Typ单位Unit JT05N065FED结到管壳的热阻Thermal Resistance, Junction to CaseR th(j-c) 4.8 ℃/W 结到环境的热阻Thermal Resistance, Junction to AmbientR th(j-A)62.5 ℃/W外形尺寸 PACKAGE MECHANICAL DATATO-220MF单位Unit ：mm。
晶体管参数大全
晶体管参数大全晶体管是一种能够对电流进行控制的电子器件，广泛应用于电子电路中。
根据其工作原理的不同，可以分为三极管和场效应管两种类型。
一、三极管参数1.最大允许电压（VCEO）：三极管的集电极-发射极间最大允许电压。
在正常工作中，电压不得超过该值，否则可能会损坏器件。
2.最大允许集电极电流（IC）：三极管的集电极电流的最大值。
在正常工作中，电流不得超过该值，否则可能会损坏器件。
3.最大功耗（Pd）：三极管透过的功率最大值。
在正常工作中，功率不得超过该值，否则可能会导致器件过热。
4.直流电流倍数（hFE）：表示三极管输入电流和输出电流之间的比例关系。
它决定了三极管的放大能力，一般越大越好，常见的值为几十到几百。
5. 饱和压降（VCEsat）：当三极管处于饱和区时，集电极与发射极之间的电压降。
6. 输入电阻（Rin）：三极管的输入电阻，表示输入信号导致的输入电压变化与输入电流变化之间的比例关系。
一般来说，输入电阻越大，对输入信号的影响越小。
7. 输出电阻（Rout）：三极管的输出电阻，表示输出电压变化与输出电流变化之间的比例关系。
一般来说，输出电阻越小，输出信号的失真越小。
8.动态电阻（rπ）：三极管的动态电阻，与输入电阻类似，表示输入信号导致的输入电压变化与输入电流变化之间的比例关系。
一般来说，动态电阻越小，对输入信号的影响越小。
9.最小输入电流（IB）：三极管正常工作所需要的最小基极电流。
二、场效应管参数1.最大允许栅源电压（VGS）：场效应管的栅源电压的最大值。
在正常工作中，电压不得超过该值，否则可能会损坏器件。
2.最大允许漏极电流（ID）：场效应管的漏极电流的最大值。
在正常工作中，电流不得超过该值，否则可能会损坏器件。
3.最大功耗（Pd）：场效应管透过的功率最大值。
在正常工作中，功率不得超过该值，否则可能会导致器件过热。
4. 转导（gm）：表示输入电压变化时输出电流变化的比例关系。
转导越大，场效应管的放大能力越强。
MMBT3906 40V PNP 小信号晶体管 SOT23 数据手册说明书
MMBT3906Features• Epitaxial Planar Die Construction• Ideal for Medium Power Amplification and Switching • Complementary NPN Type: MMBT3904• Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) • Halogen and Antimony Free. “Green” Device (Note 3) • Qualified to AEC-Q101 Standards for High Reliability • PPAP Capable (Note 4)Mechanical Data• Case: SOT23• Case Material: Molded Plastic, “Green” Molding Compound UL Flammability Classification Rating 94V-0 • Moisture Sensitivity: Level 1 per J-STD-020 • Terminals: Finish—Matte Tin Plated Leads, Solderable per MIL-STD-202, Method 208 •Weight: 0.008 grams (Approximate)Ordering Information (Notes 4 & 5)Product Status Compliance Marking Reel Size (inches)Tape Width (mm)Quantity per ReelMMBT3906-7-F Active AEC-Q101 K3N 7 8 3000 MMBT3906Q-7-F Active Automotive K3N 7 8 3000 MMBT3906Q-13-F Active Automotive K3N 13 8 10,000 MMBT3906-13-FActive AEC-Q101 K3N 13 8 10,000Notes:1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant.2. See https:///quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free.3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm antimony compounds.4. Automotive products are AEC-Q101 qualified and are PPAP capable. Refer to https:///quality/.5. For packaging details, go to our website at /products/packages.html.Marking InformationDate Code KeyYear 2015 2016 2017 2018 2019 2020 2021 2022 CodeC DE F G HI JTop ViewSOT23Device SymbolTop View Pin-OutK3NY MK3N = Product Type Marking Code YM = Date Code Marking Y or Y = Year (ex: E= 2017)M or M = Month (ex: 9 = September)Absolute Maximum Ratings(@T A = +25°C, unless otherwise specified.)Thermal Characteristics(@T A = +25°C, unless otherwise specified.)Characteristic Symbol Value UnitPower Dissipation (Note 6)P D310mW (Note 7) 350Thermal Resistance, Junction to Ambient (Note 6)RϴJA403°C/W (Note 7) 357Thermal Resistance, Junction to Leads (Note 8) RϴJL350 °C/W Operating and Storage Temperature Range T J,T STG-55 to +150 °CNotes: 6. For a device mounted on minimum recommended pad layout 1oz copper that is on a single-sided FR4 PCB; the device is measured under still air conditions while operating in a steady-state.7. Same as Note 6 except the device is mounted on 15 mm × 15mm 1oz copper.8. Thermal resistance from junction to solder-point (at the end of the leads).9. Refer to JEDEC specification JESD22-A114 and JESD22-A115.Thermal Characteristics and Derating InformationTransient Therm al Im pedancePulse Width (s)Pulse Power DissipationPulse Width (s)MElectrical Characteristics(@T A = +25°C, unless otherwise specified.)Note: 10. Measured under pulsed conditions. Pulse width ≤ 300µs. Duty cycle ≤ 2%.Typical Electrical Characteristics (@T A = +25°C, unless otherwise specified.)h , D C C U R R E N T G A I NF E I , COLLECTOR CURRENT (mA)Figure 1 Typical DC Current Gainvs. Collector CurrentC V , C O L L E C T O R -E M I T T E R S A T U R A T I O N V O L T A G E (V )C E (S A T )I , COLLECTOR CURRENT (mA)Figure 2 Typical Collector-Emitter Saturation Voltagevs. Collector CurrentC 0.1110V , B A S E -E M I T T E R (V )B E (S A T )S A T U R A T I O N V O L T A G E I , COLLECTOR CURRENT (mA)Figure 3 Typical Base-Emitter Saturation Voltagevs. Collector CurrentC 100C A P A C I T A N C E (p F )V , REVERSE VOLTAGE (V)Figure 4 Typical Capacitance Characteristics RPackage Outline DimensionsPlease see /package-outlines.html for the latest version.SOT23SOT23Dim Min Max Typ A 0.37 0.51 0.40 B 1.20 1.40 1.30 C 2.30 2.502.40 D 0.89 1.03 0.915 F 0.45 0.60 0.535 G 1.78 2.05 1.83 H 2.803.00 2.90 J 0.013 0.10 0.05 K 0.890 1.00 0.975 K1 0.903 1.10 1.025 L 0.45 0.61 0.55 L1 0.25 0.55 0.40 M 0.085 0.150 0.110 a 0° 8° -- All Dimensions in mmSuggested Pad LayoutPlease see /package-outlines.html for the latest version.SOT23。
2N3700HR中文资料(ST)中文数据手册「EasyDatasheet - 矽搜」
包
UB UB UB UB UB LCC-3 LCC-3 LCC-3 TO-18 TO-18 TO-18
辐射水平
100拉德HDR -
100拉德ESCC 100拉德SW -
芯片中文手册,看全文,戳
3
TO-18
1 2
LCC-3
在UB销4被连接到金属盖
1 2 3
3
4 1
2
UB
图 1.内部示意图
2N3700HR
高可靠性80 V,1 NPN晶体管
特征
数据表
- 生产数据
BVCEO
80 V
集成电路（MAX）
1A
HFE在10 V - 150毫安
100
密封包
食管鳞状细胞癌和JANS合格 高达100拉德（Si）低剂量率
[300]
20
0.5 V
IC =150毫安
IB =15毫安
- 1.1 V
IC =0.1毫安 IC =10毫安 IC =150毫安 IC =150毫安 Tamb = 150 °C IC =500毫安
VCE = 10 V 25
- 200
VCE = 10 V 45
-
VCE = 10 V 100
-
300
VCE = 10 V 40
2N3700UB0x SOC3700RHRx SOC3700SW SOC3700HRB 2N3700RHRx
2N3700SW 2N3700HR
资格 系统
JANSR JANS ESCC ESCC ESCC ESCC ESCC ESCC ESCC ESCC ESCC
维沙伊·西利康晶体管数据手册说明书
Dual N-Channel 100 V (D-S) MOSFETFEATURES•TrenchFET ® power MOSFET •100 % R g and UIS tested •Material categorization:for definitions of compliance please see /doc?99912APPLICATIONS•Primary side switching •Synchronous rectificationNotesa.Based on T C = 25 °Cb.Surface mounted on 1" x 1" FR4 boardc.t = 10 sd.See solder profile (/doc?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnectione.Rework conditions: Manual soldering with a soldering iron is not recommended for leadless componentsf.Maximum under steady state conditions is 85 °C/WPowerPAK ® S O-8 DualTop View16.15mm5.15m mBottom ViewG 241S 12G 13S 2D 18D 26D 17D 25ABSOLUTE MAXIMUM RATINGS (T A = 25 °C, unless otherwise noted)Parameter S ymbol Limit UnitDrain-source voltageV DS 100VGate-source voltageV GS± 20Continuous drain current (T J = 150 °C)T C = 25 °C I D36.7AT C = 85 °C29.2T A = 25 °C 10.1 b, c T A = 85 °C 8 b, cPulsed drain current (t = 300 μs)I DM 80Continuous source-drain diode current T C = 25 °C I S38T A = 25 °C 2.9 b, cSingle pulse avalanche current L = 0.1 mHI AS 20Single pulse avalanche energy E AS20mJMaximum power dissipation T C = 25 °C P D46WT C = 85 °C 29T A = 25 °C3.5 b, c T A = 85 °C 2.2 b, cOperating junction and storage temperature range T J , T stg -55 to +150°CSoldering recommendations (peak temperature) d, e 260THERMAL RESISTANCE RATINGSParameter S ymbol Typical Maximum UnitMaximum junction-to-ambient b, ft ≤ 10 s R thJA 2635°C/WMaximum junction-to-case (drain)Steady state R thJC 2.2 2.7Notesa.Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %b.Guaranteed by design, not subject to production testingStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.SPECIFICATIONS (T J = 25 °C, unless otherwise noted)Parameter S ymbol Test Conditions Min.Typ.Max.Unit StaticDrain-source breakdown voltage V DS V GS = 0 V, I D = 250 μA100--V V DS Temperature coefficient ∆V DS /T J I D = 250 μA -67-mV/°C V GS(th) Temperature coefficient ∆V GS(th)/T J --5.7-Gate-source threshold voltage V GS(th)V DS = V GS , I D = 250 μA 1.5- 3.5V Gate-source leakageI GSS V DS = 0 V, V GS = ± 20 V --± 100nA Zero gate voltage drain current I DSS V DS = 100 V, V GS = 0 V --1μA V DS = 100 V, V GS = 0 V, T J = 55 °C--10On-state drain current aI D(on) V DS ≥ 5 V, V GS = 10 V 30--ADrain-source on-state resistance a R DS(on)V GS = 10 V, I D = 15 A -0.0140.018ΩV GS = 7.5 V, I D = 12 A -0.0150.019V GS = 6 V, I D = 10 A -0.0160.021Forward transconductance a g fsV DS = 15 V, I D = 15 A-40-S Dynamic bInput capacitance C issV DS = 50 V, V GS = 0 V, f = 1 MHz -1170-pF Output capacitanceC oss -311-Reverse transfer capacitance C rss-33-Total gate charge Q gV DS = 50 V, V GS = 10 V, I D = 10 A-17.527nC V DS = 50 V, V GS = 7.5 V, I D = 10 A-13.420V DS = 50 V, V GS = 6 V, I D = 10 A -12.218.5Gate-source charge Q gs - 3.5-Gate-drain charge Q gd - 5.2-Out charge Q oss V DS = 50 V, V GS = 0 V-2741Gate resistance R g f = 1 MHz0.4 1.8 3.6ΩTurn-on delay time t d(on)V DD = 50 V, R L = 5 ΩI D ≅ 10 A, V GEN = 7.5 V, R g = 1 Ω-1224ns Rise timet r -1326Turn-off delay time t d(off) -1836Fall timet f -714Turn-on delay time t d(on)V DD = 50 V, R L = 5 ΩI D ≅ 10 A, V GEN = 10 V, R g = 1 Ω-816Rise timet r -1224Turn-off delay time t d(off) -2040Fall timet f-714Drain-Source Body Diode Characteristics Continuous source-drain diode current I S T C = 25 °C--38A Pulse diode forward current I SM --80Body diode voltageV SD I S = 5 A, V GS = 0 V-0.78 1.2V Body diode reverse recovery time t rr I F = 10 A, dI/dt = 100 A/μs, T J = 25 °C-3975ns Body diode reverse recovery charge Q rr -53100nC Reverse recovery fall time t a -26-nsReverse recovery rise timet b-13-TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)Output CharacteristicsOn-Resistance vs. Drain Current and Gate VoltageGate ChargeTransfer CharacteristicsCapacitanceOn-Resistance vs. Junction TemperatureTYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)Source-Drain Diode Forward Voltage Threshold Voltage On-Resistance vs. Gate-to-Source VoltageSingle Pulse Power (Junction-to-Ambient)Safe Operating Area, Junction-to-AmbientTYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)Current Derating a Power Junction to CasePower Junction to AmbientNotea.The power dissipation P D is based on T J max. = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below thepackage limit.TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)Normalized Thermal Transient Impedance, Junction-to-CaseVishay Silico nix maintains wo rldwide manufacturing capability. Pro ducts may be manufactured at o ne o f several qualified lo catio ns. Reliability data fo r Silico n Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?62634.Package Information Vishay SiliconixPowerPAK® SO-8, (Single/Dual)DIM.MILLIMETERS INCHESMIN.NOM.MAX.MIN.NOM.MAX.A0.97 1.04 1.120.0380.0410.044 A1-0.050-0.002 b0.330.410.510.0130.0160.020 c0.230.280.330.0090.0110.013D 5.05 5.15 5.260.1990.2030.207D1 4.80 4.90 5.000.1890.1930.197 D2 3.56 3.76 3.910.1400.1480.154 D3 1.32 1.50 1.680.0520.0590.066 D40.57 typ.0.0225 typ.D5 3.98 typ.0.157 typ.E 6.05 6.15 6.250.2380.2420.246E1 5.79 5.89 5.990.2280.2320.236 E2 3.48 3.66 3.840.1370.1440.151 E3 3.68 3.78 3.910.1450.1490.154 E40.75 typ.0.030 typ.e 1.27 BSC0.050 BSCK 1.27 typ.0.050 typ.K10.56--0.022--H0.510.610.710.0200.0240.028 L0.510.610.710.0200.0240.028 L10.060.130.200.0020.0050.008 0°-12°0°-12°W0.150.250.360.0060.0100.014 M0.125 typ.0.005 typ.ECN: S17-0173-Rev. L, 13-Feb-17DWG: 5881V I S H A Y S I L I C O N I XPower MOSFETsPowerPAK ® SO-8 Mounting and Thermal ConsiderationsA P P L I C A T I O N N O T by Wharton McDanielMOSFETs for switching applications are now available with die on resistances around 1 m and with the capability to handle 85 A. While these die capabilities represent a major advance over what was available just a few years ago, it is important for power MOSFET packaging technology to keep pace. t should be obvious that degradation of a high performance die by the package is undesirable. PowerPAK is a new package technology that addresses these issues.I n this application note, PowerPAK’s construction is described. Following this mounting information is presented including land patterns and soldering profiles for maximum reliability. Finally, thermal and electrical performance is discussed.THE PowerPAK PACKAGEThe PowerPAK package was developed around the SO-8package (figure 1). The PowerPAK SO-8 utilizes the same footprint and the same pin-outs as the standard SO-8. This allows PowerPAK to be substituted directly for a standard SO-8 package. Being a leadless package, PowerPAK SO-8utilizes the entire SO-8 footprint, freeing space normally occupied by the leads, and thus allowing it to hold a larger die than a standard SO-8. In fact, this larger die is slightly larger than a full sized DPAK die. The bottom of the die attach pad is exposed for the purpose of providing a direct,low resistance thermal path to the substrate the device is mounted on. Finally, the package height is lower than the standard SO-8, making it an excellent choice forapplications with space constraints.Fig. 1 PowerPAK 1212 DevicesPowerPAK SO-8 SINGLE MOUNTINGThe PowerPAK single is simple to use. The pin arrangement (drain, source, gate pins) and the pin dimensions are the same as standard SO-8 devices (see figure 2). Therefore, the PowerPAK connection pads match directly to those of theSO-8. The only difference is the extended drain connection area. To take immediate advantage of the PowerPAK SO-8single devices, they can be mounted to existing SO-8 land patterns.Fig. 2The minimum land pattern recommended to take full advantage of the PowerPAK thermal performance see Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs . Click on the PowerPAK SO-8 single in the index of this document.I n this figure, the drain land pattern is given to make full contact to the drain pad on the PowerPAK package.This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-to-ambient thermal resistance.Under specific conditions of board configuration, copper weight and layer stack, experiments have found that more than about 0.25 in 2 to 0.5 in 2 of additional copper (in addition to the drain land) will yield little improvement in thermal performance.Standard SO-8Po w erPAK SO-8PowerPAK ® SO-8 Mounting and Thermal ConsiderationsP P L I C A T I O N N O T EPowerPAK SO-8 DUALThe pin arrangement (drain, source, gate pins) and the pin dimensions of the PowerPAK SO-8 dual are the same as standard SO-8 dual devices. Therefore, the PowerPAK device connection pads match directly to those of the SO-8.As in the single-channel package, the only exception is the extended drain connection area. Manufacturers can likewise take immediate advantage of the PowerPAK SO-8 dual devices by mounting them to existing SO-8 dual land patterns.To take the advantage of the dual PowerPAK SO-8’s thermal performance, the minimum recommended land pattern can be found in Application Note 826,Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs . Click on the PowerPAK 1212-8 dual in the index of this document.The gap between the two drain pads is 24 mils. This matches the spacing of the two drain pads on the PowerPAK SO-8 dual package.REFLOW SOLDERINGVishay Siliconix surface-mount packages meet solder reflow reliability requirements. Devices are subjected to solder reflow as a test preconditioning and are then reliability-tested using temperature cycle, bias humidity,HAST, or pressure pot. The solder reflow temperature profile used, and the temperatures and time duration, are shown in figures 3 and 4.For the lead (Pb)-free solder profile, see /doc?73257.Fig. 3 Solder Reflow Temperature ProfileFig. 4 Solder Reflow Temperatures and Time DurationsRamp-Up Rate+ 3 °C /s max.Temperature at 150 - 200 °C120 s max.Temperature Above 217 °C 60 - 150 s Maximum Temperature 255 + 5/- 0 °CTime at Maximum Temperature 30 s Ramp-Down Rate+ 6 °C/s max.PowerPAK ® SO-8 Mounting and Thermal ConsiderationsP P L I C A T I O N N O T ETHERMAL PERFORMANCEIntroductionA basic measure of a device’s thermal performance is the junction-to-case thermal resistance, R thJC , or the junction-to-foot thermal resistance, R thJF This parameter is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device only, in other words, independent of the properties of the object to which the device is mounted. Table 1 shows a comparison of the DPAK, PowerPAK SO-8, and standard SO-8. The PowerPAK has thermal performance equivalent to the DPAK, while having an order of magnitude better thermal performance over the SO-8.Thermal Performance on Standard SO-8 Pad Pattern Because of the common footprint, a PowerPAK SO-8can be mounted on an existing standard SO-8 pad pattern.The question then arises as to the thermal performance of the PowerPAK device under these conditions. A characterization was made comparing a standard SO-8 and a PowerPAK device on a board with a trough cut out underneath the PowerPAK drain pad. This configuration restricted the heat flow to the SO-8 land pads. The results are shown in figure 5.Fig. 5 PowerPAK SO-8 and Standard SO-0 Land Pad ThermalPathBecause of the presence of the trough, this result suggests a minimum performance improvement of 10 °C/W by using a PowerPAK SO-8 in a standard SO-8 PC board mount. The only concern when mounting a PowerPAK on a standard SO-8 pad pattern is that there should be no traces running between the body of the MOSFET. Where the standard SO-8 body is spaced away from the pc board,allowing traces to run underneath, the PowerPAK sits directly on the pc board.Thermal Performance - Spreading CopperDesigners may add additional copper, spreading copper, to the drain pad to aid in conducting heat from a device. It is helpful to have some information about the thermal performance for a given area of spreading copper. Figure 6 shows the thermal resistance of a PowerPAK SO-8device mounted on a 2-in. 2-in., four-layer FR-4 PC board.The two internal layers and the backside layer are solid copper. The internal layers were chosen as solid copper to model the large power and ground planes common in many applications. The top layer was cut back to a smaller area and at each step junction-to-ambient thermal resistance measurements were taken. The results indicate that an area above 0.3 to 0.4 square inches of spreading copper gives no additional thermal performance improvement. A subsequent experiment was run where the copper on the back-side was reduced, first to 50 % in stripes to mimic circuit traces, and then totally removed. No significant effect was observed.Fig. 6 Spreading Copper Junction-to-Ambient PerformanceTABLE 1 - DPAK AND POWERPAK SO-8EQUIVALENT STEADY STATE PERFORMANCEDPAKPowerPAKSO-8 Standard SO-8 Thermal Resistance R thJC1.2 °C/W1 °C/W16 °C/WR th v s. Spreading Copper (0 %, 50 %, 100 % Back Copper)Spreading Copper (sq in))s t t a w /C ( e c n a d e p m I 0.0056514641360.250.500.751.001.251.501.752.000 %50 %100 %PowerPAK ® SO-8 Mounting and Thermal ConsiderationsA P P L I C A T I O N N O T EApplication Note AN821Vishay SiliconixRevision: 16-Mai-134Document Number: 71622For technical questions, contact: *********************************THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?91000SYSTEM AND ELECTRICAL IMPACT OF PowerPAK SO-8I n any design, one must take into account the change in MOSFET R DS(on) with temperature (figure 7).Fig. 7 MOSFET R DS(on) vs. TemperatureA MOSFET generates internal heat due to the currentpassing through the channel. This self-heating raises the junction temperature of the device above that of the PC board to which it is mounted, causing increased power dissipation in the device. A major source of this problem lies in the large values of the junction-to-foot thermal resistance of the SO-8 package.PowerPAK SO-8 minimizes the junction-to-board thermal resistance to where the MOSFET die temperature is very close to the temperature of the PC board. Consider two devices mounted on a PC board heated to 105 °C by other components on the board (figure 8).Fig. 8 Temperature of Devices on a PC BoardSuppose each device is dissipating 2.7 W. Using thejunction-to-foot thermal resistance characteristics of the PowerPAK SO-8 and the standard SO-8, the die temperature is determined to be 107 °C for the PowerPAK (and for DPAK) and 148 °C for the standard SO-8. This is a 2 °C rise above the board temperature for the PowerPAK and a 43 °C rise for the standard SO-8. Referring to figure 7,a 2 °C difference has minimal effect on R DS(on) whereas a 43 °C difference has a significant effect on R DS(on). Minimizing the thermal rise above the board temperature by using PowerPAK has not only eased the thermal design but it has allowed the device to run cooler, keep r DS(on) low, and permits the device to handle more current than the same MOSFET die in the standard SO-8 package.CONCLUSIONSPowerPAK SO-8 has been shown to have the same thermal performance as the DPAK package while having the same footprint as the standard SO-8 package. The PowerPAK SO-8 can hold larger die approximately equal in size to the maximum that the DPAK can accommodate implying no sacrifice in performance because of package limitations. Recommended PowerPAK SO-8 land patterns are provided to aid in PC board layout for designs using this new package.Thermal considerations have indicated that significant advantages can be gained by using PowerPAK SO-8devices in designs where the PC board was laid out for the standard SO-8. Applications experimental data gave thermal performance data showing minimum and typical thermal performance in a SO-8 environment, plus information on the optimum thermal performance obtainable including spreading copper. This further emphasized the DPAK equivalency.PowerPAK SO-8 therefore has the desired small size characteristics of the SO-8 combined with the attractive thermal characteristics of the DPAK package.Application Note 826Vishay Siliconix Document Number: 7260016Revision: 21-Jan-08A P P L I C A T I O N N O T ERECOMMENDED MINIMUM PADS FOR PowerPAK ® SO-8 DualLegal Disclaimer Notice VishayDisclaimerALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROV E RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.V ishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product.Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability.Statements regarding the suitability of products for certain types of applications are based on Vishay's knowledge of typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements about the suitability of products for a particular application. It is the customer's responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer's technical experts. Product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited to the warranty expressed therein.Hyperlinks included in this datasheet may direct users to third-party websites. These links are provided as a convenience and for informational purposes only. Inclusion of these hyperlinks does not constitute an endorsement or an approval by Vishay of any of the products, services or opinions of the corporation, organization or individual associated with the third-party website. Vishay disclaims any and all liability and bears no responsibility for the accuracy, legality or content of the third-party website or for that of subsequent links.Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.© 2021 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVEDRevision: 09-Jul-20211Document Number: 91000。
ao3400中文资料
O3400a数据手册规格AO3401A中文信息PDF）MOS晶体管-MOS管测试步骤：5：MOS晶体管的Gate AOS公司MOS管7407导线的连接使栅极电荷释放，内部电场消失，导电沟道消失，因此漏极和源极之间的电阻变得无限大。
此时，用一根导线连接被测管的栅极和源，万用表的指针将立即返回无穷大，如图5-6所示。
6：MOS晶体管源AOS半导体MOS晶体管74117：VDMOS，MOSFET，osmos晶体管MOS 7413（ao3400a数据手册规格AO3401A中文信息PDF）MOS晶体管8：MESFET如何工作AOS模拟开关MOS 74159：双栅极MOSFET AOSTVS二极管MOS晶体管7417如果去除了电阻，则探针将逐渐恢复为高电阻甚至无限大，因此应考虑被测管的栅极泄漏。
此时处于图5-4的状态；然后将连接的电阻移开，然后万用表的指针仍应为MOS晶体管导通指数保持不变，如图5-5所示。
尽管去除了电阻，但是由于由电阻充电至栅极的电荷不会消失，因此栅极电场继续保持，内部导电沟道保持不变，这是绝缘栅MOS晶体管的特性。
10：功率MOSFET有源模块MOS管740111：电子零件MOS管7405（ao3400a数据手册规格AO3401A中文信息PDF）MOS晶体管12：AOS公司的MOS FET参数MOS 780013：用于MOS FET的AOS半导体MOS晶体管7801此时，使用100k-200k电阻连接栅极和漏极，如图5-4所示。
此时，欧姆越小越好。
通常，它可以指示0欧姆。
此时，正电荷通过100k电阻为高功率MOS晶体管的栅极充电，以产生栅极电场。
随着电场的产生，导电通道导致漏极和源极连接，因此万用表指针会偏转并偏转角度。
高度（小欧姆指数）表示良好的放电性能。
14：MOSFET AOS代理MOS晶体管340015：什么是场效应管MOS晶体管3400a（ao3400a数据手册规格AO3401A中文信息PDF）MOS晶体管16：什么是MOS晶体管MOS晶体管340217：MOSFET的基础知识MOS晶体管3404将红色探针连接到MOS晶体管的源极，将黑色探针连接到MOS晶体管的漏极D。
SCI 高性能 NPN 双极性晶体管 2N4921G、2N4922G、2N4923G 数据手册说明书
2N4921G, 2N4922G,2N4923GMedium-Power PlasticNPN Silicon TransistorsThese high−performance plastic devices are designed for driver circuits, switching, and amplifier applications.Features•Low Saturation V oltage•Excellent Power Dissipation•Excellent Safe Operating Area•Complement to PNP 2N4920G•These Devices are Pb−Free and are RoHS Compliant** MAXIMUM RATINGSRating Symbol Value UnitCollector−Emitter Voltage 2N4921G2N4922G2N4923G V CEO406080VdcCollector−Emitter Voltage 2N4921G2N4922G2N4923G V CB406080VdcEmitter Base Voltage V EB 5.0VdcCollector Current − Continuous (Note 1)I C 1.0Adc Collector Current − Peak (Note 1)I CM 3.0Adc Base Current − Continuous I B 1.0AdcTotal Power Dissipation @ T C = 25_C Derate above 25_C PD300.24WmW/_COperating and Storage JunctionTemperature RangeT J, T stg–65 to +150_CStresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.1.The 1.0 A maximum I Cvalue is based upon JEDEC current gain requirements.The 3.0 A maximum value is based upon actual current handling capability of the device (see Figures 5 and 6).THERMAL CHARACTERISTICS (Note 2)Characteristic Symbol Max Unit Thermal Resistance, Junction−to−Case R q JC 4.16_C/W 2.Recommend use of thermal compound for lowest thermal resistance.*Indicates JEDEC Registered Data.*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.1.0 AMPEREGENERAL PURPOSEPOWER TRANSISTORS40−80 VOLTS, 30 WATTSMARKING DIAGRAMY=YearWW=Work Week2N492x=Device Codex = 1, 2, or 3G=Pb−Free PackageDevice Package Shipping ORDERING INFORMATION2N4921G TO−225(Pb−Free)500 Units / Box2N4922G TO−225(Pb−Free)500 Units / Box2N4923G TO−225(Pb−Free)500 Units / Box3EMITTERCOLLECTORTO−225CASE 77−09STYLE 13YWW2N492xGELECTRICAL CHARACTERISTICS (T C= 25_C unless otherwise noted)Characteristic Symbol Min Max Unit OFF CHARACTERISTICSCollector−Emitter Sustaining Voltage (Note 3) (I C = 0.1 Adc, I B = 0)2N4921G2N4922G2N4923G V CEO(sus)406080−−−VdcCollector Cutoff Current (V CE = 20 Vdc, I B = 0)2N4921G(V CE = 30 Vdc, I B = 0)2N4922G(V CE = 40 Vdc, I B = 0)2N4923G I CEO−−−0.50.50.5mAdcCollector Cutoff Current(V CE = Rated V CEO, V EB(off) = 1.5 Vdc)(V CE = Rated V CEO, V EB(off) = 1.5 Vdc, T C = 125_C I CEX−−0.10.5mAdcCollector Cutoff Current (V CB = Rated V CB, I E = 0)I CBO−0.1mAdcEmitter Cutoff Current (V EB = 5.0 Vdc, I C = 0)I EBO− 1.0mAdcON CHARACTERISTICSDC Current Gain (Note 3)(I C = 50 mAdc, V CE = 1.0 Vdc) (I C = 500 mAdc, V CE = 1.0 Vdc) (I C = 1.0 Adc, V CE = 1.0 Vdc)h FE403010−150−−Collector−Emitter Saturation Voltage (Note 3) (I C = 1.0 Adc, I B = 0.1 Adc)V CE(sat)−0.6VdcBase−Emitter Saturation Voltage (Note 3) (I C = 1.0 Adc, I B = 0.1 Adc)V BE(sat)− 1.3VdcBase−Emitter On Voltage (Note 3) (I C = 1.0 Adc, V CE = 1.0 Vdc)V BE(on)− 1.3VdcSMALL−SIGNAL CHARACTERISTICSCurrent−Gain − Bandwidth Product(I C = 250 mAdc, V CE = 10 Vdc, f = 1.0 MHz)f T3.0−MHzOutput Capacitance(V CB = 10 Vdc, I E = 0, f = 100 kHz)C ob−100pFSmall−Signal Current Gain(I C = 250 mAdc, V CE = 10 Vdc, f = 1.0 kHz)h fe25−−Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.3.Pulse Test: PW ≈ 300 m s, Duty Cycle ≈ 2.0%.40302010255075100125150Figure 1. Power DeratingT C , CASE TEMPERATURE (°C)P D , P O W E R D I S S I P A T I O N (W A T T S )Safe Area Curves are indicated by Figure 5. All limits are applicable and must be observed.Figure 2. Switching Time Equivalent Circuit5.0Figure 3. Turn −On TimeI C , COLLECTOR CURRENT (mA)t , T I M E ( s )μ 2.01.00.70.50.30.20.10.052.0%0.073.0V BE(off)V in V TURN-OFF PULSEobtain desired current levelsFigure 4. Thermal Responset, TIME (ms)1.00.010.70.50.30.20.10.070.050.030.02r (t ), T R A N S I E N T T H E R M A LR E S I S T A N C E (N O R M A L I Z E D )10Figure 5. Active −Region Safe Operating AreaV CE , COLLECTOR-EMITTER VOLTAGE (VOLTS)5.02.01.00.50.10.2I C , C O L L E C T O R C U R R E N T (A M P )7.03.00.70.3There are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. Safe operating area curves indicate I C − V CE operation i.e., the transistor must not be subjected to greater dissipation than the curves indicate.The data of Figure 5 is based on T J(pk) = 150_C; T C is variable depending on conditions. Second breakdown pulse limits are valid for duty cycles to 10% provided T J(pk) ≤ 150_C. At high case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdown.t μs , S T O R A G E T I M E ( s )′5.0Figure6. Storage Time I C , COLLECTOR CURRENT (mA)2.01.00.50.30.20.10.050.073.00.75.0Figure 7. Fall TimeI C , COLLECTOR CURRENT (mA)2.01.00.50.30.20.10.050.073.00.7t μf , F A L L T I M E ( s )V C E , C O L L E C T O R -E M I T T E R V O L T A G E (V O L T S )R B E , E X T E R N A L B A S E -E M I T T E R R E S I S T A N C E (O H M S )1000Figure 8. Current GainI C , COLLECTOR CURRENT (mA)1050020010070Figure 9. Collector Saturation Region1.0I B , BASE CURRENT (mA)0.80.60.40.2700300h F E , D C C U R R E N T G A I N503020108Figure 10. Effects of Base −Emitter Resistance T J , JUNCTION TEMPERATURE (°C)1071051041031061.5I C , COLLECTOR CURRENT (mA)1.20.90.60.3V O L T A G E (V O L T S )Figure 11. “On” Voltage104Figure 12. Collector Cut −Off Region V BE , BASE-EMITTER VOLTAGE (VOLTS)10310210-1, C O L L E C T O R C U R R E N T ( A )μI C + 2.5Figure 13. Temperature CoefficientsI C , COLLECTOR CURRENT (mA)T E M P E R A T U R E C O E F F I C I E N T S (m V /C )°+ 2.0+ 1.5+ 0.50- 0.5- 1.0- 1.5- 2.0- 2.5+ 1.010110010- 2TO −225CASE 77−09ISSUE ADDATE 25 MAR 2015STYLE 1:PIN 1.EMITTER 2., 4.COLLECTOR 3.BASE STYLE 6:PIN 1.CATHODE 2., 4.GATE 3.ANODESTYLE 2:PIN 1.CATHODE 2., 4.ANODE 3.GATE STYLE 3:PIN 1.BASE2., 4.COLLECTOR3.EMITTER STYLE 4:PIN 1.ANODE 12., 4.ANODE 23.GATE STYLE 5:PIN 1.MT 12., 4.MT 23.GATE STYLE 7:PIN 1.MT 12., 4.GATE 3.MT 2STYLE 8:PIN 1.SOURCE 2., 4.GATE 3.DRAINSTYLE 9:PIN 1.GATE 2., 4.DRAIN 3.SOURCESTYLE 10:PIN 1.SOURCE 2., 4.DRAIN 3.GATEYWW XXXXXXXGY = Year WW = Work Week XXXXX = Device Code G = Pb −Free Package*This information is generic. Please refer to device data sheet for actual part marking.Pb −Free indicator, “G” or microdot “ G ”,may or may not be present.GENERICMARKING DIAGRAM*SCALE 1:1DIM MIN MAX MILLIMETERS D 10.6011.10E 7.407.80A 2.40 3.00b 0.600.90P 2.90 3.30L1 1.27 2.54c 0.390.63L 14.5016.63b20.510.88Q3.804.20A1 1.00 1.50e 2.04 2.54NOTES:1.DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.2.CONTROLLING DIMENSION: MILLIMETERS.3.NUMBER AND SHAPE OF LUGS OPTIONAL.FRONT VIEWBACK VIEWFRONT VIEWSIDE VIEW31MECHANICAL CASE OUTLINEPACKAGE DIMENSIONSON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor theON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.PUBLICATION ORDERING INFORMATIONTECHNICAL SUPPORTNorth American Technical Support:Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 011 421 33 790 2910LITERATURE FULFILLMENT :Email Requests to:*******************ON Semiconductor Website: Europe, Middle East and Africa Technical Support:Phone: 00421 33 790 2910For additional information, please contact your local Sales Representative。
GS61008P底面冷却100V E模式GaN晶体管数据手册说明书
The thermal pad (pad 5) must be connected to Source, S (pad 4)Package OutlineFeatures• 100 V enhancement mode power transistor • Bottom-side cooled configuration • R DS(on) = 7 mΩ • I DS(max) = 90 A• Ultra-low FOM die• Low inductance GaN PX ® package• Simple gate drive requirements (0 V to 6 V) • Transient tolerant gate drive (-20 V / +10 V) • Very high switching frequency (> 10 MHz) • Fast and controllable fall and rise times • Reverse current capability • Zero reverse recovery loss• Small 7.6 x 4.6 mm 2 PCB footprint• Source Sense (SS) pin for optimized gate drive •RoHS 3 (6 + 4) compliantApplications• Energy Storage Systems• AC-DC Converters (secondary side) • Uninterruptable Power Supplies • Industrial Motor Drives • Fast Battery Charging • Class D Audio amplifiers • Traction Drive • Robotics•Wireless Power TransferDescriptionThe GS61008P is an enhancement mode GaN-on-silicon power transistor. The properties of GaN allow for high current, high voltage breakdown and high switching frequency. GaN Systems innovates with industry leading advancements such as patented Island Technology®andGaN PX®packaging .IslandTechnology® cell layout realizes high-current die and high yield. GaN PX® packaging enables low inductance & low thermal resistance in a small package. The GS61008P is a bottom-side cooled transistor that offers very low junction-to-case thermal resistance for demanding high power applications. These features combine to provide very high efficiency power switching.Circuit SymbolAbsolute Maximum Ratings (T case = 25 °C except as noted)Parameter Symbol Value Unit Operating Junction Temperature T J-55 to +150 °C Storage Temperature Range T S-55 to +150 °C Drain-to-Source Voltage V DS100 V Drain-to-Source Voltage - transient (Note 1) V DS(transient)120 V Gate-to-Source Voltage V GS-10 to +7 V Gate-to-Source Voltage - transient (Note 1) V GS(transient)-20 to +10 V Continuous Drain Current (T case = 25 °C) I DS90 A Continuous Drain Current (T case = 100 °C) I DS65 A Pulse Drain Current (Pulse width 50 µs, V GS = 6 V) (Note 2) I DS Pulse140 A(1) For < 1 µs(2) Defined by product design and characterization. Value is not tested to full current in production.Thermal Characteristics (Typical values unless otherwise noted)Parameter Symbol Value Units Thermal Resistance (junction-to-case) – bottom side RΘJC0.55 °C /W Thermal Resistance (junction-to-ambient) (Note 3) RΘJA23 °C /W Maximum Soldering Temperature (MSL3 rated) T SOLD260 °C (3) Device mounted on 1.6 mm PCB thickness FR4, 4-layer PCB with 2 oz. copper on each layer. Therecommendation for thermal vias under the thermal pad are 0.3 mm diameter (12 mil) with 0.635 mm pitch (25 mil). The copper layers under the thermal pad and drain pad are 25 x 25 mm2 each. The PCB is mounted in horizontal position without air stream cooling.Ordering InformationOrderingcode Package type Packingmethod QtyReelDiameterReelWidthGS61008P-TR GaN PX® bottom cooled Tape-and-Reel 3000 13” (330mm) 16mm GS61008P-MR GaN PX® bottom cooled Mini-Reel 250 7” (180mm) 16mmElectrical Characteristics (Typical values at T J = 25 °C, V GS = 6 V unless otherwise noted)ParametersSym.Min.Typ. Max. Units ConditionsDrain-to-Source Blocking Voltage V (BL)DSS 100 V V GS = 0 V, I DSS = 50 µA Drain-to-Source On Resistance R DS(on) 7 9.5 m Ω V GS = 6 V, T J = 25 °C I DS = 27 ADrain-to-Source On Resistance R DS(on) 17.5 m Ω V GS = 6 V, T J = 150 °C I DS = 27 AGate-to-Source Threshold V GS(th) 1.1 1.7 2.6 V V DS = V GS , I DS = 7 mA Gate-to-Source Current I GS 200 µA V GS = 6 V, V DS = 0 V Gate Plateau VoltageV plat 3.5 V V DS = 50 V, I DS = 90 A Drain-to-Source Leakage Current I DSS 0.5 50 µA V DS = 100 V, V GS = 0 V T J = 25 °CDrain-to-Source Leakage Current I DSS 100 µA V DS = 100 V, V GS = 0 V T J = 150 °CInternal Gate Resistance R G 0.8 Ω f = 5 MHz, open drain Input Capacitance C ISS 600 pF V DS = 50 V V GS = 0 V f = 100 kHzOutput Capacitance C OSS 250 pF Reverse Transfer Capacitance C RSS 12 pF Effective Output Capacitance, Energy Related (Note 4)C O(ER) 302 pF V GS = 0 VV DS = 0 to 50 VEffective Output Capacitance, Time Related (Note 5) C O(TR) 385 pF Total Gate Charge Q G 8 nC V GS = 0 to 6 V V DS = 50 V I DS = 90 AGate-to-Source Charge Q GS 3.5 nC Gate threshold charge Q G(th) 1.9 nC Gate switching charge Q G(sw) 3.3 nC Gate-to-Drain Charge Q GD 1.7 nC Output ChargeQ OSS 20 nC V GS = 0 V, V DS = 50 V Reverse Recovery ChargeQ RRnC(4) C O(ER) is the fixed capacitance that would give the same stored energy as C OSS while V DS is rising from 0 V to the stated V DS (5) C O(TR) is the fixed capacitance that would give the same charging time as C OSS while V DS is rising from 0 V to the stated V DS.(6) L P is the switching circuit parasitic inductance. (7) See Figure 16 for switching loss test circuit.Electrical Performance GraphsI DS vs. V DS Characteristic I DS vs. V DS CharacteristicFigure 1: Typical I DS vs. V DS @ T J = 25 ⁰C Figure 2: Typical I DS vs. V DS @ T J = 150 ⁰C R DS(on) vs. I DS Characteristic R DS(on) vs. I DS CharacteristicFigure 3: R DS(on) vs. I DS at T J = 25 ⁰C Figure 4: R DS(on) vs. I DS at T J = 150 ⁰CElectrical Performance GraphsI DS vs. V DS, T J dependence Gate Charge, Q G CharacteristicFigure 5: Typical I DS vs. V DS @ V GS = 6 V Figure 6: Typical V GS vs. Q G @ V DS = 50 V Capacitance Characteristics Stored Energy CharacteristicFigure 7: Typical C ISS, C OSS, C RSS vs. V DS Figure 8: Typical C OSS Stored EnergyElectrical Performance GraphsReverse Conduction Characteristics Reverse Conduction CharacteristicsFigure 9: Typical I SD vs. V SD at T J = 25 ⁰C Figure 10: Typical I SD vs. V SD at T J = 150 ⁰CI DS vs. V GS Characteristic R DS(on) Temperature DependenceFigure 11: Typical I DS vs. V GS Figure 12: Normalized R DS(on) as a function of T JThermal Performance GraphsI DS - V DS SOA Power Dissipation – Temperature DeratingFigure 13: Safe Operating Area @ T case = 25 °C Figure 14: Power Derating vs. T case Transient RθJCFigure 15: Transient Thermal Impedance1.00 = Nominal DC thermal impedanceTest CircuitsFigure 16: Switching Loss Test CircuitApplication InformationGate DriveThe recommended gate drive voltage range, V GS, is 0 V to + 6 V for optimal R DS(on) performance. Also, the repetitive gate to source voltage, maximum rating, V GS(AC), is +7 V to -10 V. The gate can survive non-repetitive transients up to +10 V and – 20 V for pulses up to 1 µs. These specifications allow designers to easily use 6.0 V or 6.5 V gate drive settings. At 6 V gate drive voltage, the enhancement mode high electron mobility transistor (E-HEMT) is fully enhanced and reaches its optimal efficiency point. A 5 V gate drive can be used but may result in lower operating efficiency. Inherently, GaN Systems E-HEMT do not require negative gate bias to turn off. Negative gate bias, typically V GS = -3 V, ensures safe operation against the voltage spike on the gate, however it may increase reverse conduction losses if not driven properly. For more details, please refer to the gate driver application note "GN001 How to Drive GaN Enhancement Mode Power Switching Transistors” atSimilar to a silicon MOSFET, the external gate resistor can be used to control the switching speed and slew rate. Adjusting the resistor to achieve the desired slew rate may be needed. Lower turn-off gate resistance, R G(OFF) is recommended for better immunity to cross conduction. Please see the gate driver application note (GN001) for more details.A standard MOSFET driver can be used as long as it supports 6V for gate drive and the UVLO is suitable for 6V operation. Gate drivers with low impedance and high peak current are recommended for fast switching speed. GaN Systems E-HEMTs have significantly lower Q G when compared to equally sized R DS(on) MOSFETs, so high speed can be reached with smaller and lower cost gate drivers.Many non-isolated half bridge MOSFET drivers are not compatible with 6 V gate drive for GaN enhancement mode HEMT due to their high under-voltage lockout threshold. Also, a simple bootstrap method for high side gate drive will not be able to provide tight tolerance on the gate voltage. Therefore, special care should be taken when you select and use the half bridge drivers. Alternatively, isolated drivers can be used for a high side device. Please see the gate driver application note (GN001) for more details.Parallel OperationDesign wide tracks or polygons on the PCB to distribute the gate drive signals to multiple devices. Keep the drive loop length to each device as short and equal length as possible.GaN enhancement mode HEMTs have a positive temperature coefficient on-state resistance which helps to balance the current. However, special care should be taken in the driver circuit and PCB layout since the device switches at very fast speed. It is recommended to have a symmetric PCB layout and equal gate drive loop length (star connection if possible) on all parallel devices to ensure balanced dynamic current sharing. Adding a small gate resistor (1-2 Ω) on each gate is strongly recommended to minimize the gate parasitic oscillation.Source SensingThe device has a dedicated source sense pin. The GaN PX® packaging utilizes no wire bonds so the source connection is very low inductance. The dedicated source sense pin will further enhance performance by eliminating the common source inductance if a dedicated gate drive signal kelvin connection is created. This can be achieved connecting the gate drive signal from the driver to the gate pad and returning from the source sense pad to the driver ground reference.ThermalThe substrate is internally connected to the thermal pad on the bottom-side of the package. The source pad must be electrically connected to the thermal pad for optimal performance. The transistor is designed to be cooled using the printed circuit board. The Drain pad is not as thermally conductive as the thermalpad. However, adding more copper under this pad will improve thermal performance by reducing the package temperature.Thermal ModelingRC thermal models are available to support detailed thermal simulation using SPICE. The thermal models are created using the Cauer model, an RC network model that reflects the real physical property and packaging structure of our devices. This thermal model can be extended to the system level by adding extra Rθ and Cθ to simulate the Thermal Interface Material (TIM) or Heatsink.RC thermal model:RC breakdown of R ΘJCR θ (°C/W) C θ (W∙s/°C) R θ1 = 0.017 C θ1 = 7.0E-05 R θ2 = 0.253 C θ2 = 6.7E-04 R θ3 = 0.264 C θ3 = 5.9E-03 R θ4 = 0.016C θ4 = 1.8E-03For more detail, please refer to Application Note GN007 “Modeling Thermal Behavior of GaN Systems’ GaN PX ® Using RC Thermal SPICE Models” available at Reverse ConductionGaN Systems enhancement mode HEMTs do not need an intrinsic body diode and there is zero reverse recovery charge. The devices are naturally capable of reverse conduction and exhibit different characteristics depending on the gate voltage. Anti-parallel diodes are not required for GaN Systems transistors as is the case for IGBTs to achieve reverse conduction performance.On-state condition (V GS = +6 V): The reverse conduction characteristics of a GaN Systems enhancement mode HEMT in the on-state is similar to that of a silicon MOSFET, with the I-V curve symmetrical about the origin and it exhibits a channel resistance, R DS(on), similar to forward conduction operation.Off-state condition (V GS ≤ 0 V): The reverse characteristics in the off-state are different from silicon MOSFETs as the GaN device has no body diode. In the reverse direction, the device starts to conduct when the gate voltage, with respect to the drain, V GD , exceeds the gate threshold voltage. At this point the device exhibits a channel resistance. This condition can be modeled as a “body diode” with slightly higher V F and no reverse recovery charge.If negative gate voltage is used in the off-state, the source-drain voltage must be higher than V GS(th)+V GS(off) in order to turn the device on. Therefore, a negative gate voltage will add to the reverse voltage drop “V F ” and hence increase the reverse conduction loss.Blocking VoltageThe blocking voltage rating, V (BL)DSS, is defined by the drain leakage current. The hard (unrecoverable) breakdown voltage is approximately 30 % higher than the rated V (BL)DSS,. As a general practice, the maximum drain voltage should be de-rated in a similar manner as IGBTs or silicon MOSFETs. All GaN E-HEMTs do not avalanche and thus do not have an avalanche breakdown rating. The maximum drain-to-source rating is 100 V and does not change with negative gate voltage. GaN Systems tests devices in production with a 120 V Drain-to-source voltage pulse to insure blocking voltage margin.Packaging and SolderingThe package material is high temperature epoxy-based PCB material which is similar to FR4 but has a higher temperature rating, thus allowing the device to be specified to 150 °C. The device can handle at least 3 reflow cycles.It is recommended to use the reflow profile in IPC/JEDEC J-STD-020 REV D.1 (March 2008)The basic temperature profiles for Pb-free (Sn-Ag-Cu) assembly are:•Preheat/Soak: 60 - 120 seconds. T min = 150 °C, T max = 200 °C.•Reflow: Ramp up rate 3 °C/sec, max. Peak temperature is 260 °C and time within 5 °C of peak temperature is 30 seconds.•Cool down: Ramp down rate 6 °C/sec max.Using “No-Clean” soldering paste and operating at high temperatures may cause a reactivation of the “Non-Clean” flux residues. In extreme conditions, unwanted conduction paths may be created. Therefore, when the product operates at greater than 100 °C it is recommended to also clean the “No-Clean” paste residues.Recommended PCB FootprintPackage DimensionsPart MarkingTape and Reel InformationTape and Reel Box DimensionsImportant Notice – Unless expressly approved in writing by an authorized representative of GaN Systems, GaN Systems components are not designed, authorized or warranted for use in lifesaving, life sustaining, military, aircraft, or space applications,nor in products or systems where failure or malfunction may result in personal injury, death, or property or environmental damage. The information given in this document shall not in any event be regarded as a guarantee of performance. GaN Systems herebydisclaims any or all warranties and liabilities of any kind, including but not limited to warranties of non-infringement of intellectual property rights. All other brand and product names are trademarks or registered trademarks of their respective owners. Information provided herein is intended as a guide only and is subject to change without notice. The information contained herein or any use of such information does not grant, explicitly, or implicitly, to any party any patent rights, licenses, or any other intellectual property rights. GaN Systems standard terms and conditions apply. All rights reserved.。
晶体管参数大全
晶体管参数大全晶体管是一种重要的电子元件，包括三极管和场效应管两种类型。
以下是关于晶体管参数的详细介绍。
1.三极管参数：(1)直流参数：- 静态放大倍数（hfe）：表示输入电流和输出电流之间的放大倍数；- 饱和电流（Isat）：在基极电流最大的情况下，由集电极和发射极之间的饱和电流；- 集电极-发射极饱和电压（Vce_sat）：集电极和发射极之间的饱和电压；- 输入电阻（Rin）：表示三极管的输入端电阻；- 输出电阻（Rout）：表示三极管的输出端电阻。
(2)动态参数：- 最大切换频率（ft）：表示三极管可以切换的最高频率；- 输入电容（Cin）：表示三极管的输入电容；- 输出电容（Cout）：表示三极管的输出电容；- 开关时间（ts/tf）：分别表示三极管的上升和下降时间。
2.场效应管参数：(1)直流参数：- 静态放大倍数（gm）：表示输出电流和输入电压之间的增益；- 饱和电流（Idss）：在栅压为零时，漏极电流最大的情况下，由源极和漏极之间的饱和电流；- 开启电压（Vgs_th）：栅极电压与源极电压之间的临界电压，开始导通的电压；- 漏极-源极饱和电压（Vds_sat）：漏极电压与源极电压之间的饱和电压；- 输入电阻（Rin）：表示场效应管的输入端电阻；- 输出电阻（Rout）：表示场效应管的输出端电阻。
(2)动态参数：- 最大切换频率（ft）：表示场效应管可以切换的最高频率；- 输入电容（Cin）：表示场效应管的输入电容；- 输出电容（Cout）：表示场效应管的输出电容；- 开关时间（ts/tf）：分别表示场效应管的上升和下降时间。
以上是晶体管参数的一些常见指标，不同型号的晶体管具体参数可能会有所不同。
在实际应用中，根据具体电路设计和需求，选择合适的晶体管参数非常重要。
同时，要注意不同厂家制造的晶体管参数可能存在差异，需要仔细查阅相关型号的数据手册。
2N5109中文资料(Central Semiconductor)中文数据手册「EasyDatasheet - 矽搜」
工作和存储结温
符号
VCBO VCEO VEBO
IC IB PD PD TJ, Tstg
电气特性： 符号
ICEV ICEV ICEO IEBO BVCBO BVCER BVCEO VCE(SAT) hFE hFE fT Cob NF GPE
测试条件
VCE=35V, VBE=1.5V
5.0
VCE=15V, IC=50mA, f=200MHz
1200
VCB=15V, IE=0, f=1.0MHz
VCE=15V, IC=10mA, f=200MHz
VCE=15V, IC=50mA, f=200MHz
11
40 20 3.0 400 400 1.0 2.5 -65到+200
TYP
MAX
5.0
5.0
20
100
0.5 210
3.5 3.0
UNITS V V V mA mA W W °C
UNITS mA mA μA μA V V V V
MHz pF dB dB
R4 (7-June 2109
硅
NPN晶体管 RF
TO-39 CASE - 机械外形
前导码：
1）发射 2）基 3）集电极
标记：全部型号
R4 (7-June 2011)
（TA = 25°C除非另有说明） MIN
VCE=15V, VBE=1.5V, TC=150°C
VCE=15V
VEB=3.0V
IC=0.1mA
40
IC=5.0mA, RBE=10Ω
40
IC=5.0mA
20
IC=100mA, IB=10mA
BLM3401 Pb Free 氧化钙晶体管数据手册说明书
P-Channel Enhancement Mode Power MOSFETNotes:1. Repetitive Rating: Pulse width limited by maximum junction temperature.2. Surface Mounted on FR4 Board, t ≤ 10 sec.3. Pulse Test: Pulse Width ≤ 300μs, Duty Cycle ≤ 2%.4. Guaranteed by design, not subject to productionTYPICAL ELECTRICAL AND THERMAL CHARACTERISTICSFigure 1:Switching Test CircuitT J -Junction Temperature(℃)Figure 3 Power DissipationVds Drain-Source Voltage (V)Figure 5 Output CHARACTERISTICSV INV tFigure 2:Switching WaveformsT J -Junction Temperature(℃)Figure 4 Drain CurrentI D - Drain Current (A)Figure 6 Drain-Source On-ResistanceP D P o w e r (W )I D - D r a i n C u r r e n t (A ）R d s o n O n -R e s i s t a n c e (m Ω)I D - D r a i n C u r r e n t (A )Vgs Gate-Source Voltage (V)Figure 7 Transfer CharacteristicsVgs Gate-Source Voltage (V)Figure 9 Rdson vs VgsQg Gate Charge (nC)Figure 11 Gate ChargeT J -Junction Temperature(℃)Figure 8 Drain-Source On-ResistanceVds Drain-Source Voltage (V)Figure 10 Capacitance vs VdsVsd Source-Drain Voltage (V)Figure 12 Source- Drain Diode ForwardI D - D r a i n C u r r e n t (A )R d s o n O n -R e s i s t a n c e (m Ω)V g s G a t e -S o u r c e V o l t a g e (V )N o r m a l i z e d O n -R e s i s t a n c eC C a p a c i t a n c e (p F )I s - R e v e r s e D r a i n C u r r e n t (A )Vds Drain-Source Voltage (V)Figure 13 Safe Operation AreaSquare Wave Pluse Duration(sec)Figure 14 Normalized Maximum Transient Thermal Impedancer (t ),N o r m a l i z e d E f f e c t i v e T r a n s i e n t T h e r m a l I m p e d a n c eI D - D r a i n C u r r e n t (A )SOT-23 PACKAGE INFORMATIONDimensions in Millimeters (UNIT:mm)NOTES1. All dimensions are in millimeters.2. Tolerance ±0.10mm (4 mil) unless otherwise specified3. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 5 mils.4. Dimension L is measured in gauge plane.5. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.。
2SC2983-O NPN 晶体管数据手册说明书
h —— I
1000
FE
C
COMMON EMITTER VCE= 5V
T a=100
T =25
100
a
10 1
300
β=10
100
10
10
100
COLLECTOR CURRENT I (mA) C
V
—— I
CEsat
C
1000 1500
T =100 a T =25 a
1
0.1
1
10
100
COLLECTOR CURREMT I (mA) C
x Low Collector Saturation Voltage x Execllent current-to-gain characteristics • Epoxy meets UL 94 V-0 flammability rating • Moisture Sensitivity Level 1 • Halogen free available upon request by adding suffix OF HFE (1)
Rank
Range
O 70-140
Y 120-240
2SC2983-O 2SC2983-Y
NPN Plastic-Encapsulate
Transistors
DPAK J H
C
1
O
2
4 FE
I
3
M
K
V
G
Q
A
L
B
D
PIN 1. BASE
PIN 2.4 COLLECTOR
Packing Tape&Reel: 2.5Kpcs/Reel
s9012中文资料_数据手册_参数
万联芯城专注电子元器件配单服务，只售原 装现货库存，万联芯城电子元器件全国供应，专为终端生产， 研发企业提供现货物料，价格优势明显，BOM配单整单采购可享 优惠价，提交BOM表报价，最快可当天发货，万联芯城电子 元器件配单业务，满足客户多种物料需求，点击进入万联芯城。
s9012硅外延平面晶体管9012文件编号：BL/SSSTC08特性高集电极电流。（IC=-500MA）无铅补充S9013。优良的HFE线性。应用高集 电极电流。SOT-23订购信息类型编号标记包代码90122T1SOT-23Ta=25℃时的最大额定值，除非另有规定，符号参数值、数值、电容 器基极电压-40VVvceoCollector-Emitter电压-25VveboEmitter-Base电压-5VicCollector电流-Continuous-500mapCollector耗散 300mwtj、TSTGjunction和存储温度
晶体管数据手册说明书
SURFACE MOUNT FAST SWITCHING DIODE REVERSE VOLTAGE – 100 Volts FORWARD CURRENT – 0.15 AmperesFEATURES• Fast switching speed• Ideally suited for automatic insertion• For general purpose switching applications MECHANICAL DATA • Case: SOD-123 plastic• Case Material: “Green” molding compound, UL flammability classification 94V-0, (No Br. Sb. Cl.), “Halogen-free”• Moisture sensitivity: Level 1 per J-STD-020D • Lead free in RoHS 2002/95/EC compliant •Marking Code : T4• Weight : 11.67m grams (Approximate)SOD-123MAXIMUM RATINGS AND ELECTRICAL CHARACTERISTICS Ratings at 25°C ambient temperature unless otherwise specified.ABSOLUTE RATINGSPARAMETERSYMBOL VALUE UNIT Non-repetitive peak reverse voltage V RM 100 V Repetitive peak reverse voltage Working peak reverse voltage DC blocking voltageV RRM V RWM V R 100 V Forward continuous current (Note 1) I FM 300 mA Average rectified output current (Note 1) I O 150 mA Non-repetitive peak forward current @ t =1.0 us @ t =1.0 sI FSM 2 1 A Repetitive peak forward current I FRM 300 mA Power dissipation (Note 1)P D 357 mW Operation and storage temperature rangeT J ,T STG-65 to +150 °C STATIC ELECTRICAL CHARACTERISTICSPARAMETERTEST CONDITIONSYMBOLMAX UNIT Forward voltageI F = 1 mA I F = 10 mA I F = 50 mA I F = 150 mA V F 715 855 1000 1250 mVReverse leakage current V R = 75 V V R = 20 V I R 2500 25 nA Typical junction capacitanceV R = 0 V, f= 1MH ZC D 2 pF THERMAL CHARACTERISTICSPARAMETERSYMBOL TYP. UNIT Typical thermal resistance (Note 1)RthJ A RthJ C290 200 °C/WDYNAMIC ELECTRICAL CHARACTERISTICSPARAMETERTEST CONDITIONSYMBOL TYP. UNIT Reverse recovery timeI F = I R = 10 mA,I rr = 0.1 x I R , R L = 100 ΩT RR4nsNote :(1) Valid provided that terminals are kept at ambient temperatureREV. 14,JUL.-2015 KSYR011N4148WRATING AND CHARACTERISTIC CURVES 1N4148WPackage Dimensions :SOD-123Soldering Pad Layout :INCHES MILLIMETERS Dim. Min. Max. Min. Max. A 0.037 0.053 0.94 1.35 A1 0.000 0.004 0.00 0.10 b 0.020 0.028 0.51 0.71 C -- 0.006 -- 0.15 D 0.055 0.071 1.40 1.80 E 0.100 0.112 2.54 2.84 H E0.140 0.152 3.56 3.86 L0.010--0.25--MECHANICAL INFORMATION 1N4148WNote:PIN 1. Cathode PIN 2. AnodeLEGAL DISCLAIMER NOTICEImportant Notice and DisclaimerLSC reserves the right to make changes to this document and its products and specifications at any time without notice. Customers should obtain and confirm the latest productinformation and specifications before final design, purchase or use.LSC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does LSC assume any liability for application assistance or customer product design. LSC does not warrant or accept any liability with products which are purchased or used for any unintended or unauthorized application.No license is granted by implication or otherwise under any intellectual property rights of LSC.LSC products are not authorized for use as critical components in life support devices or systems without express written approval of LSC.。
NXP BAP70-02 平面PIN晶体管数据手册说明书
BAP70-02Silicon PIN diodeRev. 8 — 11 December 2018Product data sheet1Product profile1.1General descriptionPlanar PIN diode in a SOD523 ultra small SMD plastic package.1.2Features and benefits•High voltage; current controlled RF resistor for attenuators •Low diode capacitance •Very low series inductance •AEC-Q101 qualified1.3Applications•RF attenuators •(SAT) TV •Car radio2Pinning information3Ordering informationSilicon PIN diode 4Marking[1]The marking bar indicates the cathode (see simplified outline graphic in Table 1)5Limiting valuesTable 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).6Thermal characteristics7CharacteristicsTable 6. CharacteristicsT= 25 °C unless otherwise specified.Silicon PIN diode8Graphical dataSilicon PIN diode 9Package outline10AbbreviationsSilicon PIN diode 11Revision historySilicon PIN diode 12Legal information12.1 Data sheet status[1]Please consult the most recently issued document before initiating or completing a design.[2]The term 'short data sheet' is explained in section "Definitions".[3]The product status of device(s) described in this document may have changed since this document was published and may differ in case of multipledevices. The latest product status information is available on the Internet at URL .12.2 DefinitionsDraft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors productis deemed to offer functions and qualities beyond those described in the Product data sheet.12.3 DisclaimersLimited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does notgive any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liabilityfor the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makesno representation or warranty that such applications will be suitablefor the specified use without further testing or modification. Customersare responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated withtheir applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is basedon any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above thosegiven in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at /profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance orthe grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expectedSilicon PIN diodeto result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.12.4 TrademarksNotice: All referenced brands, product names, service names and trademarks are the property of their respective owners.Silicon PIN diodePlease be aware that important notices concerning this document and the product(s)described herein, have been included in section 'Legal information'.Contents1Product profile ....................................................11.1General description ............................................11.2Features and benefits ........................................11.3Applications ........................................................12Pinning information ............................................13Ordering information ..........................................14Marking .................................................................25Limiting values ....................................................26Thermal characteristics ......................................27Characteristics ....................................................28Graphical data .....................................................39Package outline ...................................................410Abbreviations ......................................................411Revision history .. (512)Legal information (6)。
2N3904中文资料_数据手册_参数
2000年11月 - 修订版3 1出版订单编号： 2N3903 / D 2N3903,2N3904 2N3903是首选设备一般用途晶体管 NPN硅大额定值评分符 号值单元集电极 - 发射极电压 VCEO 40 VDC集电极 - 基极电压 VCBO 60 VDC发射极 - 基极电压 VEBO 6 VDC集电极电流 - 连 续我知道了 200 MADC器件总功耗 @ TA = 25°C减免25以上 C PD 625 5毫瓦毫瓦/ C器件总功耗 @ TC = 25°C减免25以上 C PD 1.5 12瓦毫瓦/ C操作和存储连接温度范围 TJ，TSTG -55到 +150 C 热特性 （注1）特性符号马克斯单元热阻，结到环境 [R θJA 200 °C / W热阻，交界处至凯斯 [R θJC 83.3 °C / W 1.除JEDEC要求外还指示数据.设备包运输订购信息 2N3903 TO-92 TO-92情况29风格1 5000个单位/箱 3 2 1首选设备是未来使用的推荐选择和好的整体价值. 2N3903RLRM TO-92 2000 / AMMO PACK集电极 3 2基础 1辐射源 2N3904 TO-92 5000个单位/箱 2N3904RLRA TO-92 2000 /卷带式 2N3904RLRE TO-92 2000 /卷带式 2N3904RLRM TO-92 2000 / AMMO PACK风格1 ? =年份 WW =工作周标记图 2N 3903 YWW 2N3904RLRP TO-92 2000 / AMMO PACK 2N 3904 YWW 2N3904RL1 TO-92 2000 /卷带式 2N3904ZL1 TO-92 2000 / AMMO PACK 3图1.延迟和上升时间等效测试电路图2.存储和下降时间等效测试电路 +3 V 275 10 K 1N916 CS <4 PF * +3 V 275 10 K CS <4 PF * <1NS -0.5V +10.9 V 300纳秒 DUTY CYCLE = 2％ <1NS +10.9 V DUTY CYCLE = 2％ T1 0 10 <T1 <500MS *测试夹具和连接器的总并联电容典型的瞬态特性图3.电容反向偏置电压（伏特） 2.0 3.0 5 7 10 1.0 0.1图4.收费数据 IC，集电极 电流（MA） 5000 1.0 VCC = 40V IC / IB = 10 3000 2000 1000 500 300 200 700 100 50 70 2.0 3.0 5.0 7.0 10 20 30 50
N-沟槽晶体管高性能汽车级TrenchMOS技术标准级FET数据手册说明书
BUK7Y07-30BN-channel TrenchMOS standard level FETRev. 03 — 7 April 2010Product data sheet 1.Product profile1.1General descriptionStandard level N-channel enhancement mode Field-Effect Transistor (FET) in a plasticpackage using NXP High-Performance Automotive (HPA) TrenchMOS technology. Thisproduct has been designed and qualified to the appropriate AEC standard for use inautomotive critical applications.1.2Features and benefitsLow conduction losses due to low on-state resistanceQ101 compliant Suitable for standard level gate drive sourcesSuitable for thermally demanding environments due to 175 °C rating1.3Applications12 V LoadsAutomotive systems General purpose power switch Motors, lamps and solenoids1.4Quick reference dataTable 1.Quick reference dataSymbol Parameter Conditions Min Typ Max UnitV DS drain-sourcevoltage T j≥25°C; T j≤175°C--30VI D drain current V GS=10V; T mb=25°C;see Figure 1; see Figure 4[1]--75AP tot total powerdissipationT mb=25°C; see Figure 2--105W Static characteristicsR DSon drain-sourceon-stateresistance V GS=10V; I D=25A;T j=25°C; see Figure 12;see Figure 13-57mΩAvalanche ruggednessE DS(AL)S non-repetitivedrain-sourceavalanche energy I D=75A; V sup≤30V;R GS=50Ω; V GS=10V;T j(init)=25°C; unclamped--198mJDynamic characteristicsQ GD gate-drain charge I D=25A; V DS=24V;V GS=10V; see Figure 14-10.7-nC[1]Continuous current is limited by package.2.Pinning information3.Ordering informationTable 2.Pinning information Pin Symbol Description Simplified outline Graphic symbol1S source SOT669 (LFPAK)2S source 3S source 4G gatembDmounting base; connected to drainmb1234Table 3.Ordering informationType numberPackage NameDescriptionVersionBUK7Y07-30BLFPAKplastic single-ended surface-mounted package (LFPAK); 4 leads SOT6694.Limiting values[1]Continuous current is limited by package.[2]Single-pulse avalanche rating limited by maximum junction temperature of 175 °C.[3]Repetitive avalanche rating limited by an average junction temperature of 170 °C.[4]Refer to application note AN10273 for further information.[5]Maximum value not quoted. Repetitive rating defined in avalanche rating figure.Table 4.Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).Symbol ParameterConditionsMin Typ Max Unit V DS drain-source voltage T j ≥25°C; T j ≤175°C --30V V DGR drain-gate voltage R GS =20k Ω--30V V GS gate-source voltage -20-20V I Ddrain currentT mb =25°C; V GS =10V; see Figure 1; see Figure 4[1]--75A T mb =100°C; V GS =10V; see Figure 1--63A I DM peak drain current T mb =25°C; t p ≤10µs; pulsed;see Figure 4--356A P tot total power dissipation T mb =25°C; see Figure 2--105W T stg storage temperature -55-175°C T j junction temperature -55-175°C Source-drain diodeI S source current T mb =25°C[1]--75A I SM peak source current t p ≤10µs; pulsed; T mb =25°C --356A Avalanche ruggednessE DS(AL)Snon-repetitive drain-sourceavalanche energyI D =75A; V sup ≤30V; R GS =50Ω; V GS =10V; T j(init)=25°C; unclamped--198mJE DS(AL)Rrepetitive drain-source avalanche energysee Figure 3[2][3][4][5]---J5.Thermal characteristicsTable 5.Thermal characteristicsSymbol Parameter Conditions Min Typ Max Unit R th(j-mb)thermal resistance from junction to mounting basesee Figure 5--1.42K/W6.CharacteristicsTable 6.CharacteristicsSymbol Parameter Conditions Min Typ Max Unit Static characteristicsV(BR)DSS drain-sourcebreakdown voltage I D=250µA; V GS=0V; T j=25°C30--V I D=250µA; V GS=0V; T j=-55°C27--VV GS(th)gate-source thresholdvoltage I D=1mA; V DS=V GS; T j=25°C;see Figure 10; see Figure 11234VI D=1mA; V DS=V GS; T j=-55°C;see Figure 10-- 4.4VI D=1mA; V DS=V GS; T j=175°C;see Figure 101--VI DSS drain leakage current V DS=30V;V GS=0V; T j=25°C-0.021µAV DS=30V;V GS=0V; T j=175°C--500µA I GSS gate leakage current V DS=0V; V GS=20V; T j=25°C-2100nAV DS=0V; V GS=-20V; T j=25°C-2100nAR DSon drain-source on-stateresistance V GS=10V; I D=25A; T j=175°C;see Figure 12; see Figure 13--13.4mΩV GS=10V; I D=25A; T j=25°C;see Figure 12; see Figure 13-57mΩDynamic characteristicsQ G(tot)total gate charge I D=25A; V DS=24V;V GS=10V;see Figure 14-31-nCQ GS gate-source charge-9.5-nC Q GD gate-drain charge-10.7-nCC iss input capacitance V GS=0V;V DS=25V; f=1MHz;T j=25°C;see Figure 15-13301773pFC oss output capacitance-495594pF C rss reverse transfercapacitance-206282pFt d(on)turn-on delay time V DS=25V;R L=1Ω; V GS=10V;R G(ext)=10Ω-17-nst r rise time-30-ns t d(off)turn-off delay time-40-ns t f fall time-28-ns Source-drain diodeV SD source-drain voltage I S=25A;V GS=0V; T j=25°C;see Figure 16-0.85 1.2Vt rr reverse recovery time I S=20A;dI S/dt=-100A/µs; V GS=0V;V DS=25V -39-nsQ r recovered charge-53-nC7.Package outlinePlastic single-ended surface-mounted package (LFPAK); 4 leads SOT669Fig 17.Package outline SOT669 (LFPAK)8.Revision historyTable 7.Revision historyDocument ID Release date Data sheet status Change notice Supersedes BUK7Y07-30B_320100407Product data sheet-BUK7Y07-30B_2 Modifications:•Status changed from objective to product.BUK7Y07-30B_220100215Objective data sheet-BUK7Y07-30B_19.Legal information9.1Data sheet status[1]Please consult the most recently issued document before initiating or completing a design.[2]The term 'short data sheet' is explained in section "Definitions".[3]The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest productstatus information is available on the Internet at URL .9.2DefinitionsDraft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give anyrepresentations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia salesoffice. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia andcustomer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product isdeemed to offer functions and qualities beyond those described in the Product data sheet.9.3DisclaimersLimited warranty and liability — Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.In no event shall Nexperia be liable for any indirect, incidental,punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia.Right to make changes — Nexperia reserves the right to makechanges to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.Suitability for use in automotive applications — This Nexperiaproduct has been qualified for use in automotiveapplications. The product is not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a Nexperiaproduct can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia accepts noliability for inclusion and/or use of Nexperia products in suchequipment or applications and therefore such inclusion and/or use is at the customer’s own risk.Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.Nexperia does not accept any liability related to any default,damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the Nexperia product issuitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. Nexperia does not accept any liability in this respect.Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.Terms and conditions of commercial sale — Nexperiaproducts are sold subject to the general terms and conditions of commercial sale, as published at /profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects toapplying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer.No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.Document status[1][2]Product status[3]DefinitionObjective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.Product [short] data sheet Production This document contains the product specification.Export control — This document as well as the item(s) described herein maybe subject to export control regulations. Export might require a priorauthorization from national authorities.10.Contact informationFor more information, please visit: For sales office addresses, please send an email to: salesaddresses@11.Contents1Product profile. . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.1General description . . . . . . . . . . . . . . . . . . . . . .1 1.2Features and benefits. . . . . . . . . . . . . . . . . . . . .1 1.3Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.4Quick reference data . . . . . . . . . . . . . . . . . . . . .1 2Pinning information. . . . . . . . . . . . . . . . . . . . . . .2 3Ordering information. . . . . . . . . . . . . . . . . . . . . .2 4Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3 5Thermal characteristics . . . . . . . . . . . . . . . . . . .5 6Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .6 7Package outline. . . . . . . . . . . . . . . . . . . . . . . . .10 8Revision history. . . . . . . . . . . . . . . . . . . . . . . . .11 9Legal information. . . . . . . . . . . . . . . . . . . . . . . .12 9.1Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12 9.2Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 9.3Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .12 9.4Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .13 10Contact information. . . . . . . . . . . . . . . . . . . . . .13© Nexperia B.V. 2017. All rights reservedFor more information, please visit: Forsalesofficeaddresses,pleasesendanemailto:*************************** Date of release:。
Silicon Carbide (SiC) 晶体管模块数据手册说明书
MSCSM120AM042CD3AGDatasheet Phase Leg SiC Power ModuleJanuary20201Revision History (1)Revision1.0 (1)Product Overview (2)2.1Features (3)2.2Benefits (3)2.3Applications (3)Electrical Specifications (4)3.1SiC MOSFET Characteristics(Per MOSFET) (4)3.2SiC Schottky Diode Ratings Characteristics(Per SiC Diode) (6)3.3Thermal Package Characteristics (6)3.4Typical SiC MOSFET Performance Curves (7)3.5Typical SiC Diode Performance Curves (10)Package Specifications (11)Table1•Absolute Maximum Ratings (4)Table2•Electrical Characteristics (4)Table3•Dynamic Characteristics (5)Table4•Body Diode Ratings and Characteristics (5)Table5•SiC Schottky Diode Ratings and Characteristics (6)Table6•Package Characteristics (6)Figure1•MSCSM120AM042CD3AG Electrical Schematic (2)Figure2•MSCSM120AM042CD3AG Pinout Location (2)Figure3•Maximum Thermal Impedance (7)Figure4•Output Characteristics,TJ=25°C (7)Figure5•Output Characteristics,TJ=175°C (7)Figure6•Normalized RDS(on)vs.Temperature (7)Figure7•Transfer Characteristics (7)Figure8•Switching Energy vs.Rg (8)Figure9•Switching Energy vs.Current (8)Figure10•Capacitance vs.Drain Source Voltage (8)Figure11•Gate Charge vs.Gate Source Voltage (8)Figure12•Body Diode Characteristics,TJ=25°C (8)Figure13•3rd Quadrant Characteristics,TJ=25°C (8)Figure14•Body Diode Characteristics,TJ=175°C (9)Figure15•3rd Quadrant Characteristics,TJ=175°C (9)Figure16•Operating Frequency vs.Drain Current (9)Figure17•Maximum Thermal Impedance (10)Figure18•Forward Characteristics (10)Figure19•Capacitance vs.Reverse Voltage (10)Figure20•Package Outline (11)1Revision HistoryThe revision history describes the changes that were implemented in the document.The changes are listed by revision,starting with the most current publication.1.1Revision 1.0Revision 1.0is the first publication of this document,published in January 2020.Revision HistoryThe MSCSM120AM042CD3AG is a phase leg1200V/495A silicon carbide power module.Figure1•MSCSM120AM042CD3AG Electrical SchematicFigure2•MSCSM120AM042CD3AG Pinout LocationAll ratings at T J=25°C unless otherwise specified.Caution:These devices are sensitive to electrostatic discharge.Proper handling procedures should befollowed.2.1FeaturesThe following are key features of the MSCSM120AM042CD3AG device:•SiC Power MOSFET◦Low RDS(on)◦High temperature performance•Silicon carbide(SiC)Schottky diode◦Zero reverse recovery◦Zero forward recovery◦Temperature-independent switching behavior◦Positive temperature coefficient on VF•Kelvin emitter for easy drive•High level of integration•Aluminum nitride(AlN)substrate for improved thermal performance•M6power connectors2.2BenefitsThe following are benefits of the MSCSM120AM042CD3AG device:•High efficiency converters•Stable temperature behavior•Direct mounting to heatsink(isolated package)•Low junction-to-case thermal resistance•RoHS Compliant2.3ApplicationsThe MSCSM120AM042CD3AG device is designed for the following applications:•Welding converters•Switched Mode Power Supplies•Uninterruptible Power Supplies•EV motor and traction drive3Electrical SpecificationsThis section shows the electrical specifications of the MSCSM120AM042CD3AG device.3.1SiC MOSFET Characteristics (Per MOSFET)This section describes the electrical characteristics of the MSCSM120AM042CD3AG device.Table 1•Absolute Maximum RatingsUnit Maximum Ratings ParameterSymbol V 1200Drain-source voltage V DSS A4951T C =25°C Continuous drain currentI D3951T C =80°C990Pulsed drain current I DM V –10/25Gate-source voltage V GS mΩ5.2Drain-source ON resistance R DSon W 2031T C =25°CPower dissipationP DNote:1.Specification of SiC MOSFET device but output current must be limited due to the size of power connectors.Table 2•Electrical CharacteristicsUnitMaxTypMinTest ConditionsCharacteristicSym-bol μA 60060V GS =0V;V DS =1200V Zero gate voltage drain current I DSS mΩ5.24.2T J =25°C V GS =20V I D =240ADrain–source on resistanceR DSon6.7T J =175°CV2.81.8V GS =V DS ,I D =6mA Gate threshold voltage V GS(th)nA600V GS =20V,V DS =0VGate–source leakage currentI GSSTable 3•Dynamic CharacteristicsUnit MaxTyp MinTest Conditions Characteristic Symbol pF18.1V GS =0V V DS =1000V f =1MHzInput capacitance C iss 1.6Output capacitance C oss 0.15Reverse transfer capacitance C rss nC1392V GS =–5/20V V Bus =800V Total gate charge Q g 246Gate–source charge Q gs I D =240A 300Gate–drain charge Q gd ns 56V GS =–5/20V V Bus =600V Turn-on delay time T d(on)55Rise time T r I D =300A166Turn-off delay time T d(off)R Gon =1.3Ω;R Goff =0.8ΩTJ =150°C 67Fall time T f mJ 6.1T J =150°CInductive Switching V GS =–5/20V Turn on energy E on mJ5.5T J =150°CTurn off energyE offV Bus =600V I D =300A R Gon =1.3ΩR Goff =0.8ΩΩ1Internal gate resistanceR Gint °C/W0.074Junction-to-case thermal resistanceR thJCTable 4•Body Diode Ratings and CharacteristicsUnit MaxTyp MinTest Conditions Characteristic Symbol V4V GS =0V;I SD =240A Diode forward voltageV SD4.2V GS =–5V;I SD =240Ans 90I SD =240A;V GS =–5V;V R =800V;diF/dt =6000A/μsReverse recovery time t rr nC 3300Reverse recovery charge Q rr A81Reverse recovery currentI rr3.2SiC Schottky Diode Ratings Characteristics (Per SiC Diode)This section shows the SiC Schottky diode ratings and characteristics of the device.Table 5•SiC Schottky Diode Ratings and CharacteristicsUnitMaxTypMinTest ConditionsCharacteristicSym-bol V 1200Peak repetitive reverse voltage V RRM μA120060T J =25°C V R =1200VReverse leakage currentI RRM900T J =175°CA180T C =100°CForward currentI FV1.81.5T J =25°C I F =180ADiode forward voltage V F2.1T J =175°CnC 780V R =600VTotal capacitive charge Q C pF846f =1MHz,V R =400V Total capacitanceC630f =1MHz,V R =800V°C/W0.175Junction-to-case thermal resistance R thJC3.3Thermal Package CharacteristicsThis section shows the thermal and package characteristics of the device.Table 6•Package CharacteristicsUnit MaxMin CharacteristicSymbol V 4000RMS isolation voltage,any terminal to case t =1min,50/60Hz V ISOL °C 175–40Operating junction temperature rangeT J °C T Jmax –25–40Recommended junction temperature under switching conditions T JOP °C 125–40Storage temperature range T STG °C 125–40Operating case temperature T C N.m53M6For terminals Mounting torqueTorque53M6To heatsinkg350Package weightWt3.4Typical SiC MOSFET Performance CurvesThis section shows the typical performance curves of the MSCSM120AM042CD3AG SiC MOSFET.Figure3•Maximum Thermal ImpedanceFigure4•Output Characteristics,T J=25°CFigure6•Normalized RDS(on)vs.TemperatureFigure8•Switching Energy vs.Rg Figure9•Switching Energy vs.CurrentFigure10•Capacitance vs.Drain Source VoltageFigure12•Body Diode Characteristics,T J=25°C°CFigure16•Operating Frequency vs.Drain Current3.5Typical SiC Diode Performance CurvesThis section shows the typical performance curves of the MSCSM120AM042CD3AG SiC diode.Figure17•Maximum Thermal ImpedanceFigure18•Forward CharacteristicsThis section shows the package outline of the MSCSM120AM042CD3AG device.All dimensions are inmillimeters.Figure20•Package OutlineSee application note1908-Mounting instructions for D3and D4power modules on Microsemi's product warranty is set forth in Microsemi's Sales Order Terms and rmation contained in this publication is provided for the sole purpose of designing with and using Microsemi rmation regarding device applications and the like is provided only for your convenience and may be superseded by updates.Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi.It is your responsibility to ensure that your application meets with your specifications.THIS INFORMATION IS PROVIDED "AS IS."MICROSEMI MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,WRITTEN OR ORAL,STATUTORY OR OTHERWISE,RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY ,PERFORMANCE,NON-INFRINGEMENT,MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.IN NO EVENT WILL MICROSEMI BE LIABLE FOR ANY INDIRECT,SPECIAL,PUNITIVE,INCIDENTAL OR CONSEQUENTIAL LOSS,DAMAGE,COST OR EXPENSE WHATSOEVER RELATED TO THIS INFORMATION OR ITS USE,HOWEVER CAUSED,EVEN IF MICROSEMI HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.TO THE FULLEST EXTENT ALLOWED BY LAW,MICROSEMI’S TOTAL LIABILITY ON ALL CLAIMS IN RELATED TO THIS INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES,IF ANY ,YOU PAID DIRECTLY TO MICROSEMI FOR THIS e of Microsemi devices in life support,mission-critical equipment or applications,and/or safety applications is entirely at the buyer’s risk,and the buyer agrees to defend and indemnify Microsemi from any and all damages,claims,suits,or expenses resulting from such use.No licenses are conveyed,implicitly or otherwise,under any Microsemi intellectual property rights unless otherwisestated.Microsemi2355W.Chandler Blvd.Chandler,AZ 85224USAWithin the USA:+1(480)792-7200Fax:+1(480)792-7277 ©2020Microsemi andits corporate affiliates.All rights reserved.Microsemi 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2SA1242 SI-P 35V 5A 1W 170MHz
2SA1249 SI-P 180V 1.5A 10W 120MHz
2SA1262 SI-P 60V 4A 30W 15MHz
2SA1265N SI-P 140V 10A 100W 30MHz
2SA1624 SI-P 300V 0.1A 0.5W 70MHz
2SA1626 SI-P 400V 2A 1W 0.5/2.7us
2SA1643 SI-P 50V 7A 25W 75MHz
2SA1668 SI-P 200V 2A 25W 20MHz
2SA1671 SI-P 120/120V 8A 75W 20MHz
晶体管数据手册.txt每天早上起床都要看一遍“福布斯”富翁排行榜，如果上面没有我的名字，我就去上班。谈钱不伤感情，谈感情最他妈伤钱。我诅咒你一辈子买方便面没有调料包。Transistor Caracteristicas Transistor Caracteristicas
2N1305 GE-P 30V 0.3A 0.15W 5MHz
2N3904 SI-N 60V 0.2A .35W 300MHz
2N3963 SI-P 80V 0.2A 0.36W >40MHz
2N4001 SI-N 100V 1A 15W 40MHz
2N4036 SI-P 90V 1A 1W 60MHz
2N4236 SI-P 80V 3A 1W >3MHz
2SA1112 SI-P 180V 1A 20W 200MHz
2Sห้องสมุดไป่ตู้1124 SI-P 150V 50mA 1W 200MHz
2SA1141 SI-P 115V 10A 100W 90MHz
2SA1145 SI-P 150V 50mA 0.8W 200MHz
2SA1156 SI-P 400V 0.5A 10W POWER
2SA1315 SI-P 80V 2A 0.9W 0.2us
2SA1317 SI-P 60V 0.2A 0.3W 200MHz
2SA1319 SI-P 180V 0.7A 0.7W 120MHz
2SA1328 SI-P 60V 12A 40W 0.3us
2SA1345 SI-N 50V 0.1A 0.3W 250MHz
2N5589 SI-N 36V 0.6A 3W 175MHz
2N5672 SI-N 150V 30A 140W 0.5us
2N5682 SI-N 120V 1A 1W >30MHz
2N5686 SI-N 80V 50A 300W >2MHz
2N5771 SI-P 15V 50mA 625mW >850MHz
2SA1441 SI-P 100V 5A 25W <300ns
2SA1450 SI-P 100V 0.5A 0.6W 120MHz
2SA1460 SI-P 60V 1A 1W <40NS
2SA1475 SI-P 120V 0.4A 15W 500MHz
2SA1477 SI-P 180V 0.14A 10W 150MHz
2N4906 SI-P 80V 5A 87.5W >4MHz
2N5090 SI-N 55V 0.4A 4W 5mA
2N5116 P-FET 30V 5mA 150E Up<4V
2N5179 SI-N 20V 50mA 0.2W >1GHz
2N5240 SI-N 375V 5A 100W >2MHz
2N5308 N-DARL 40V 0.3A 0.4W B>7K
2N5322 SI-P 100V 2A 10W AFSWITCH
2N5416 SI-P 350V 1A 10W 15MHz
2N5460 P-FET 40V 5mA Up<6V GEN.P
2N5462 P-FET 40V 16mA Up<9V GEN.
2SA1930 SI-P 180V 2A 20W 200MHz
2SA473 SI-P 30V 3A 10W 100MHz
2SA493 SI-P 50V 0.05A 0.2W 80MHz
2SA562 SI-P 30V 0.5A 0.5W 200MHz
2SA608 SI-N 40V 0.1A 0.1W 180MHz
2SA1048 SI-P 50V 0.15A 0.2W 80MHz
2SA1061 SI-P 100V 6A 70W 15MHz
2SA1065 SI-P 150V 10A 120W 50MHz
2SA1103 SI-P 100V 7A 70W 20MHz
2SA1110 SI-P 120V 0.5A 5W 250MHz
2SA1013 SI-P 160V 1A 0.9W 50MHz
2SA1016 SI-P 100V 0.05A 0.4W 110MHz
2SA1018 SI-P 250V 70mA 0.75W >50MHz
2SA1027 SI-P 50V 0.2A 0.25W 100MHz
2SA1034 SI-P 35V 50mA 0.2W 200MHz
2N3571 SI-N 30V 0.05A 0.2W 1.4GHz
2N3632 SI-N 40V 0.25A 23W 400MHz
2N3700 SI-N 140V 1A 0.5W 200MHz
2N3708 SI-N 30V 0.03A 0.36W 80MHz
2N3725 SI-N 80V 0.5A 1W 35/60ns
2SA1489 SI-P 80V 6A 60W 20MHz
2SA1491 SI-P 140V 10A 100W 20MHz
2SA1507 SI-P 180V 1.5A 10W 120MHz
2SA1516 SI-P 180V 12A 130W 25MHz
2SA1535A SI-P 180V 1A 40W 200MHz
2N5878 SI-N 80V 10A 150W >4MHz
2N5884 SI-P 80V 25A 200W AFPOWSW
2N6031 SI-P 140V 16A 200W 1MHz
2N6098 SI-N 70V 10A 75W AFPOWSWITCH
2N6109 SI-P 60V 7A 40W 10MHz
2N3055H SI-N 100V 15A 115W 800kHz
2N3375 SI-N 40V 0.5A 11.6W 500MHz
2N3440 SI-N 300V 1A 10W 15MHz
2N3442 SI-N 160V 10A 117W 0.8MHz
2N3502 SI-P 45V 0.6A 0.7W 200MHz
2N2894 SI-P 12V 0.2A 1.2W 60/90ns
2N2906A SI-P 60V 0.6A 0.4W 45/100
2N2955 GE-P 40V 0.1A 0.15W 200MHz
2N3053 SI-N 60V 0.7A 5W 100MHz
2N3055 SI-N 100V 15A 115W 800kHz
2SA1352 SI-P 200V 0.1A 5W 70MHz
2SA1358 SI-P 120V 1A 10W 120MHz
2SA1360 SI-P 150V 50mA 5W 200MHz
2SA1370 SI-P 200V 0.1A 1W 150MHz
2SA1376 SI-P 200V 0.1A 0.75W 120MHz
2SA1539 SI-P 120V 0.3A 8W 400MHz
2SA1541 SI-P 200V 0.2A 7W 300MHz
2SA1566 SI-N 120V 0.1A 0.15W 130MHz
2SA1593 SI-P 120V 2A 15W 120MHz
2SA1606 SI-P 180V 1.5A 15W 100MHz
2SA1296 SI-P 20V 2A 0.75W 120MHz
2SA1300 SI-P 10V 2A 0.75W 140MHz
2SA1303 SI-P 150V 14A 125W 50MHz
2SA1306A SI-P 180V 1.5A 20W 100MHz
2SA1309 SI-P 30V 0.1A 0.3W 80MHz
2SA1268 SI-N 120V 0.1A 0.3W 100MHz
2SA1271 SI-P 30V 0.8A 0.6W 120MHz
2SA1282 SI-P 20V 2A 0.9W 80MHz
2SA1286 SI-P 30V 1.5A 0.9W 90MHz
2SA1292 SI-P 80V 15A 70W 100MHz
2N428 GE-P 30V 0.4A 0.15W B>60
2N4287 SI-N 45V 0.1A 0.25W 40MHz
2N4348 SI-N 140V 10A 120W >0.2MHz
2N4391 N-FET 40V 50mA 30E Up<10V
2N4393 N-FET 40V 5mA 100E Up<3V
2N6211 SI-P 275V 2A 20W 20MHz
2N6248 SI-P 110V 15A 125W >6MHz
2N6356 N-DARL 50V 20A 150W B>150