1用VHDL设计的一位二进制全加器的示例程序

1用VHDL设计的一位二进制全加器的示例程序library ieee;

use ieee.std_logic_1164.all;

entity adder is port(a, b,ci : in bit;

sum : out bit);

end adder;

architecture a of adder is

begin

sum<=a xor b xor ci;

co<=((a or b) and ci) or ( a and b);

end a;

2用vhdl语言实现一个脉冲信号的十分频ibrary ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity div is

generic (duty : integer := 5);

port (clk : in std_logic;

Q : out std_logic）；

end div ;

architecture divlo of div is

constart period : integer := 10;

signal count : integer range 0 to period-1;

begin

process (clk)

begin

if rising_edge ( clk ) then

if count < duty then

Q <= …0? ;

count <= count+1;

else if count < period-1 then

Q <= …1? ;

count <= count+1 ;

else count <= …0? ;

end if ;

end if ;

end process ;

end divlo ;

3用vhdl 语言if 语句来实现2选1数据选择器ibrary ieee;

use ieee.std_logic_1164.all;

entity choose is

port (d0;d1,sel : in std_logic;

y : out std_logic );

end choose ;

architecture arc of choose is

begin process(d0,d1,sel)

begin

if (sel <= …1?) then

y <= d1;

else y <= d0 ;

end if ;

end process ;

end arc;

4用VHDL实现3-8译码器

ibrary ieee;

use ieee.std_logic_1164.all;

entity encoder is

port ( a : in std_logic_vector ( 2 downto 0 );

b : out std_logic_vector ( 7 downto 0));

end encoder ;

architecture behav of encoder is

signal indata : std_logic_vector ( 2 downto 0 ); begin

process (a)

begin

indata <= a(2)&a(1)&a(0);

case indata is

when “000”=>b<=”00000001”;

when “001”=>b<=”00000010”;

when “010”=>b<=”00000100”;

when “011”=>b<=”00001000”;

when “100”=>b<=”00010000”;

when “101”=>b<=”00100000”;

when “110”=>b<=”01000000”;

when “111”=>b<=”10000000”;

when others =>b<=”XXXXXXXX”;

end case ;

end process ;

end behav ;